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Getting to Work with OpenPiton Princeton University OpenPit http://openpiton.org

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Page 1: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Getting to Work with OpenPiton

Princeton University

OpenPit

http://openpiton.org

http://openpiton.org/
Page 2: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Prototyping

2

Page 3: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Supported Development Boards

Boards supported by toolchain:

Xilinx VC707

Digilent Genesys2

Digilent NexysVideoDigilent Nexys4DDR** doesn’t have DDR controller and FPU

3

Page 4: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Comparison of Supported Boards

Development Board,FPGA name,

Part

Core Clock(1 core)

Max# of Cores

DDR Type,Size,

Data Width

Price (nonacademic/

academic)

Xilinx VC707Virtex-7

XC7VX485T-2FFG1761C67 MHz 4

DDR31 GB

64 bits$3,495

Digilent Genesys2Kintex-7

XC7K325T-2FFG900C50 MHz 2

DDR31GB

32 bits

$1,299/$600

Digilent NexysVideoArtix-7

XC7A200T-1SBG484C29 MHz 1

DDR3512MB16 bits

$490/$250

Digilent Nexys 4 DDRArtix-7

XC7A100T-ACSG324C29MHz 1

DDR2128MiB16 bits

$320/$160

4

Page 5: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Prototype Architecture

OpenPitonCore

DRAM

SD Master

UART

Switches, LEDs

ETH IO_C

TRL_

TOP

Digilent Genesys2

5

Page 6: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

I/O Interfaces

Wishbone SD Master*:• Up to 2GB SD (microSD) cards• Storage for HV/OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write)

DDR controller*:• Xilinx’s MIG 7 IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

6

Page 7: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

I/O Interfaces

Wishbone SD Master*:• Up to 2GB SD (microSD) cards• Storage for HV/OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write)

DDR controller*:• Xilinx’s MIG 7 IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

DRAM

6

Page 8: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

I/O Interfaces

Wishbone SD Master*:• Up to 2GB SD (microSD) cards• Storage for HV/OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write)

DDR controller*:• Xilinx’s MIG 7 IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

SD

DRAM

6

Page 9: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

I/O Interfaces

Wishbone SD Master*:• Up to 2GB SD (microSD) cards• Storage for HV/OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write)

DDR controller*:• Xilinx’s MIG 7 IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

UART

SD

DRAM

6

Page 10: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

I/O Interfaces

Wishbone SD Master*:• Up to 2GB SD (microSD) cards• Storage for HV/OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write)

DDR controller*:• Xilinx’s MIG 7 IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

UART

SD

DRAM

6

Page 11: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

I/O Interfaces

Wishbone SD Master*:• Up to 2GB SD (microSD) cards• Storage for HV/OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write)

DDR controller*:• Xilinx’s MIG 7 IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

UART

SD

DRAM

ETH

6

Page 12: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

I/O Interfaces

Wishbone SD Master*:• Up to 2GB SD (microSD) cards• Storage for HV/OS/tests

UART:• Terminal I/O• Loading of assembly test(DMW - Direct Memory Write)

DDR controller*:• Xilinx’s MIG 7 IP core• Configurable data width• Used as main memory

*optional

Ethernet controller*:• Xilinx’s Ethernet Lite MAC IP Core• Driver from Linux kernel• 100 Mb/s

To/From OpenPiton core

7

Page 13: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Demo

8

Page 14: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setup for Hands-on with FPGA

9

Page 15: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setting up Your FPGA Board

10

Page 16: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setting up Your FPGA Board

10

Page 17: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setting up Your FPGA Board

10

Page 18: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setting up Your FPGA Board

10

Page 19: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setting up Your FPGA Board

10

Page 20: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setting up Your FPGA Board

10

Page 21: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Setting up Your FPGA Board

GO!

10

Page 22: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Booting Linux

11

Page 23: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Booting Linux

11

Page 24: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Linux Boot

12

Page 25: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Linux Boot

After ~4 min

12

Page 26: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Coffee Break

13

Page 27: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Linux Boot

14

Page 28: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Hands on: Login to the System

15

Page 29: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Hands on: Login to the System

15

Page 30: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Suggested Configurations

BRAM_TEST SD with OS + Eth

UART DMWto DDR

BRAM with hardwired test

DRAM memory controller

SD card controller

UART 16550

Ethernet Lite MAC

UART support fortest streaming

16

Page 31: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Suggested Configurations

BRAM_TEST SD with OS + Eth

UART DMWto DDR

BRAM with hardwired test

DRAM memory controller

SD card controller

UART 16550

Ethernet Lite MAC

UART support fortest streaming

16

Page 32: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Tools

• protosyn

All encompassing tool for creation of FPGA project and generating programming file

• pitonstream

Tool for running assembly tests on FPGA

Sources are located at piton/tools/src/proto/

pitonstreamboard type, asm test list .ustr

protosynboard type, design, config opt.xpr

.bit

17

Page 33: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

protosyn Flow

bram test?

*.v.pyv -> *tmp.v

sims build

sims run

RTL

mapping test to BRAM

create project?

mem.imagesims.log

test_proto.coe

project creation .xpr

synthesis

mapping, placing, routing, bitstream generation, STA

NO

YES

implement?

YES

NO

IP cfg (.xci),constraints (.cdc),defines

YES

NO

.xpr

.bit,

.ltx

LegendControl FlowData Flowpyv preprocessorSims scriptVivadoinput/output filesflow step conditions

18

Page 34: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

19

Page 35: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

Put a MAC from your board!

19

Page 36: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

Put a MAC from your board!

19

Page 37: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

Put a MAC from your board!

19

Page 38: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Running protosyn

…more options are in FPGA manual

20

Page 39: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Running protosyn

…more options are in FPGA manual

20

Page 40: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Running protosyn

…more options are in FPGA manual

20

Page 41: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Running protosyn

…more options are in FPGA manual

20

Page 42: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example protosyn run

21

Page 43: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example protosyn run

21

Page 44: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example protosyn run

21

Page 45: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example protosyn run

21

Page 46: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example protosyn run

21

Page 47: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example protosyn run

21

Page 48: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example protosyn run

21

Page 49: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Runtimes

• System including DDR controller

– ~1.5 hour including IP generation

– ~40 mins excluding IP generation

22

Page 50: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 51: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 52: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 53: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 54: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 55: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 56: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 57: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

23

Page 58: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

24

Page 59: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

24

Page 60: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

24

Page 61: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

24

Page 62: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

25

Page 63: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

25

Page 64: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

25

Page 65: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

FPGA Flow Outputs

25

Page 66: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

26

Page 67: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

Put a MAC from your board!

26

Page 68: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

Put a MAC from your board!

26

Page 69: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Bringing up Network

Put a MAC from your board!

26

Page 70: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example pitonstream Run

27

Page 71: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example pitonstream Run

27

Page 72: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example pitonstream Run

27

Page 73: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Example pitonstream Run

27

Page 74: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Writing OS Image to SD Card

28

Page 75: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Writing OS Image to SD Card

28

Page 76: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Writing OS Image to SD Card

29

Page 77: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Writing OS Image to SD Card

30

Page 78: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Writing OS Image to SD Card

30

Page 79: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Hands-on with FPGA

31

Page 80: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Running Tetris on OpenPiton

32

Page 81: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Running Tetris on OpenPiton

32

Page 82: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Browsing OpenPiton web page onOpenPiton

33

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Browsing OpenPiton web page onOpenPiton

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Page 84: FPGA Prototyping - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton-hpca17-fpga.pdfFPGA name, Part Core Clock (1 core) Max # of Cores DDR Type,

Browsing OpenPiton web page onOpenPiton

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OpenPiton Synthesis and Back-end Manual

OpenPiton+Arianein Action - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/wosh19/... · 2019-06-18 · BRAM_TEST SD with OS + Eth UART DMW to DDR BRAM with

OpenPiton+Arianein Action - Princeton Universityparallel.princeton.edu/openpiton/tutorial_slides/... · •PyHPis a python preprocessorused in OpenPitonfor generating complex RTL

Extension Using NoCsparallel.princeton.edu/openpiton/tutorial_slides/asplos18/openpiton... · Cache Coherence Protocol Directory-based MESI coherence Protocol - Four-hop message communication

OpenPiton with RISC-V Cores A Hands-On Tutorial with the ... · *L1 cache goes to 2-ways at smallest size 3 Component Configurability Options Cores (per chip) Up to 65,536 Cores (per

Dynamic GPGPU Power Management Using Adaptive Model ...albonesi/research/papers/hpca17.pdf · C. GPGPU Kernel Characterization GPGPU kernels show sensitivity to hardware configurations

OpenPit - Princeton Parallel Computing Groupparallel.princeton.edu/openpiton/docs/synbck_man.pdf · OpenPit OpenPiton Synthesis ... infrastructure, including static timing analysis

OpenPit - Princeton University · with private L1 and L1.5 caches and a distributed, shared L2 cache. Each tile in OpenPiton contains an instance of the L1 cache, L1.5 cache, and

OpenPiton with RISC-V Cores A Hands-On Tutorial …...A Hands-On Tutorial with the Open Source Manycore Processor Operating System and System Software 2 Privileged Specification 1.11

OpenPiton+Ariane: The RISC-V Hardware Research Platformparallel.princeton.edu/.../2-openpitonariane-intro.pdf · 2019. 7. 13. · OpenPiton+Ariane: The RISC-V Hardware Research Platform

OpenPiton+Ariane Tutorial, HiPEAC 2019 · 0.2 - 1.7 GHz (0.5 V –1.15 V) Kosmodrom: RV64GCXsmallFloat Transprecision / Vector FPU Ariane HP 8T library, 0.8V, 1.3 GHz 55 mW @ 1 GHz

OpenPiton: An Open-Source Framework for EDA Tool Development€¦ · 5V VDD BF R sense 2.5V VIO Config 1.2V BF R sense VIO Chip AF R sense 1.2V AF R sense 3.3V 12V VIO Gateway FPGA

OpenPiton: An Open Source Manycore Research Frameworkparallel.princeton.edu/papers/openpiton-asplos16.pdf · OpenPiton: An Open Source Manycore Research Framework Jonathan Balkind

GraphPIM: Enabling Instruction-Level PIM Offloading in ...jaewoong.org/pubs/hpca17-graphpim.pdf · GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

Cooper: Task Colocation with Cooperative Gamessmzahedi/pub/hpca17.pdfCooper: Task Colocation with Cooperative Games Qiuyun Llull, Songchun Fan, Seyed Majid Zahedi, Benjamin C. Lee

OpenPiton with RISC-V Cores A Hands-On Tutorial with the Open Source Manycore Processorparallel.princeton.edu/openpiton/tutorial_slides/micro19/... · 2019. 10. 28. · •10 PhD

OpenPiton: An Open-Source Framework for EDA Tool Development · OpenPiton: The world’s first open source, general purpose, multithreaded manycore processor ... – Good support

OpenPiton+Arianein Action - Princeton UniversityPrototype Architecture Ariane Core DRAM UART SDHC Switches, LEDs Ethernet DigilentGenesys2 5 Wishbone SD Master*: •Up to 32GB SD/SDHC

OpenPiton+Ariane Tutorial, HiPEAC 2019parallel.princeton.edu/openpiton/tutorial_slides/... · 15:00 –15:30 Michael Schaffner –Ariane + OpenPiton (intro) ... JTAG interface OpenOCD

OpenPiton+Ariane: The RISC-V Hardware Research Platformparallel.princeton.edu/.../7-openpitonariane-fpga.pdf · Ariane Core DRAM UART SDHC Switches, LEDs Ethernet DigilentGenesys2

Simulating OpenPiton RTL - Princeton University · Anatomy of a Simulation •Simulation model –Design under test (DUT) RTL –Top-level test bench –Simulator compiler arguments

OpenPiton+Ariane: The RISC-V Hardware Research Platformparallel.princeton.edu/openpiton/tutorial_slides/... · OpenPiton+Ariane: The RISC-V Hardware Research Platform Princeton University

OpenPiton with RISC-V Cores A Hands-On Tutorial with the ... · A Hands-On Tutorial with the Open Source Manycore Processor. Simulating OpenPitonRTL 2. Anatomy of a Simulation •Simulation

OpenPiton+Ariane: The RISC-V Hardware Research Platform...Red Hat 6.6, 7 SimulatorSynopsys VCS vcs_mx_L-2016.06 Mentor ModelSim 10.6b Verilator 4.014 FPGA Xilinx Vivado 2018.2 ASIC

OpenPit - Princeton Universityparallel.princeton.edu/openpiton/docs/sim_man.pdf2.1 04/03/16 WPRG Third version 2.2 10/21/16 MM Updates for new release 2.3 09/21/17 JB Updates for new

OpenPiton in Action O pe nP it

OpenPiton+Ariane: The RISC-V Hardware Research Platformparallel.princeton.edu/openpiton/tutorial_slides/...–Use a commercial processor (licensing, collaboration issues) –Use what

OpenPiton with RISC-V Cores A Hands-On Tutorial

Getting to Work with OpenPiton · Ld. Coherence Transaction Example (2) 11 Core 1 E → I Core 2 I→ M E → M Memory L1.5 L1.5 L2 Store Downgrade DG Ack Data Ack Core 1 Core2 Ld

OpenPiton with RISC-V Cores A Hands-On Tutorial with the

OpenPiton: An Open Source Manycore Research Framework · Jonathan Balkind Michael McKeown Yaosheng Fu Tri Nguyen Yanqi Zhou Alexey Lavrov Mohammad Shahrad Adi Fuchs Samuel Payne Xiaohua

Getting to Work with OpenPiton O pe nP itparallel.princeton.edu/openpiton/tutorial_slides/hpca17/openpiton... · Whats in the Box? • Synthesis –Synopsys Design Compiler • Static

DOI:10.1145/3366343 OpenPiton: An Open Source Hardware ... · OpenPiton, an open source framework for building scal-able architecture research prototypes from one core to 500 million

OpenPit - Princeton University2.2.5 Place and Route OpenPiton uses Synopsys IC Compiler (ICC) for place and route (PAR). The OpenPiton PAR scripts have been tested with the following

OpenPiton in Action O pe nP it - Princeton University