from transistors to digital logiccomputer-architecture.org/lectures/computer-architecture... ·...
TRANSCRIPT
![Page 1: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/1.jpg)
A
GND
VDD
Y
Computer ArchitecturePaul Mellies
From transistors to digital logic
![Page 2: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/2.jpg)
1 0
1
1
0 0
0 0 1
1 1
1
0
0
0 0
000 1 1
1 1
0
The digital abstraction
Every light bulb is either ON or OFF
![Page 3: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/3.jpg)
The digital abstraction
Every light bulb is either ON or OFF
1 0 1 0 0 1 0 0
1 0 0 1 10 1 1
1 0000 1 1 0
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Additional idea : transistors are switches !
drain
source
gate
gate = 0 gate = 1
drain
source
gateNMOS
PMOS
source
drain
source
drain
source
drain
source
drain
ON
ON
OFF
OFF
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Additional idea : transistors are switches !
drain
source
gate
gate = 0 gate = 1
drain
source
gateNMOS
PMOS
source
drain
source
drain
source
drain
source
drain
ON
ON
OFF
OFF
good for 0’sbad for 1’s
good for 1’sbad for 0’s
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Additional idea : transistors are switches !
drain
source
gate
gate = 0 gate = 1
drain
source
gateNMOS
PMOS
source
drain
source
drain
source
drain
source
drain
ON
ON
OFF
OFF
good for 0’sbad for 1’s
good for 1’sbad for 0’s
Fine, but what does that mean exactly ?
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gate
source of electrons
drain of electrons
gate
source of holes
drain of holes
N-channel MOSFETenhancement mode
P-channel MOSFETenhancement mode
dire
ctio
n of
the c
urre
nt �
ow
Enhancement-mode MOSFET transistors
The device is OFF at rest.A positive voltage must then be applied to the gate
wrt. the source in order to switch the device ON.
The device is OFF at rest.A negative voltage must be applied to the gatewrt. the source in order to switch the device ON.
![Page 8: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/8.jpg)
gate
source of electrons
drain of electrons
gate
source of holes
drain of holes
N-channel MOSFETenhancement mode
P-channel MOSFETenhancement mode
dire
ctio
n of
the c
urre
nt �
ow
Enhancement-mode MOSFET transistors
The device is OFF at rest.A positive voltage must then be applied to the gate
wrt. the source in order to switch the device ON.
The device is OFF at rest.A negative voltage must be applied to the gatewrt. the source in order to switch the device ON.
body body
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A 3D picture of an NMOS transistor
Picture reproduced from the excellent book by Jaeger and Blalock : Microelectronic -- Circuit Design ( Mac Graw Hill, fourth edition )
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The three operation modesof a NMOS transistor
= 0DI
VTN
CUT-OFF
≤
GSV+
_
DSV+
_
ID
drain
source
gateGSV
TNwhere V denotes the threshold voltage
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Here, Kn denotes the transductance parameter of the NMOS transistor
The three operation modesof a NMOS transistor
VTN
LINEAR OR TRIODE
≥ ≥ GSV+
_
DSV+
_
ID
drain
source
gate
DSVGSV
TNwhere V denotes the threshold voltage
0-
VTNVGS 2DSV
nK DSV--D = I
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The linear or triode operation mode
GSV+
_
DSV+
_
ID
Drain-source voltage ( V )
drain
source
gate
Drain
-sour
ce cu
rrent
( μA )
800
600
400
200
00 0.2
GSV = 5 V
GSV = 4 V
GSV = 3 V
GSV = 2 V
0.4 0.6 0.8
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Exercise :
For this speci�c NMOS transistor, can you give for each Gate-Source Voltage :
2 V 3 V 4 V 5 V
an approximation of the Drain-Source resistance at the origin ?
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pMOS transistors work in just the opposite fashion, as might be guessedfrom the bubble on their symbol shown in Figure 1.31. The substrate is tiedtoVDD. When the gate is also atVDD, the pMOS transistor is OFF.When thegate is at GND, the channel inverts to p-type and the pMOS transistor is ON.
Unfortunately, MOSFETs are not perfect switches. In particular,nMOS transistors pass 0’s well but pass 1’s poorly. Specifically, whenthe gate of an nMOS transistor is at VDD, the drain will only swingbetween 0 and VDD−Vt. Similarly, pMOS transistors pass 1’s well but0’s poorly. However, we will see that it is possible to build logic gates thatuse transistors only in their good mode.
nMOS transistors need a p-type substrate, and pMOS transistorsneed an n-type substrate. To build both flavors of transistors on the samechip, manufacturing processes typically start with a p-type wafer, thenimplant n-type regions called wells where the pMOS transistors shouldgo. These processes that provide both flavors of transistors are calledComplementary MOS or CMOS. CMOS processes are used to build thevast majority of all transistors fabricated today.
In summary, CMOS processes give us two types of electricallycontrolled switches, as shown in Figure 1.31. The voltage at the gate (g)regulates the flow of current between the source (s) and drain (d). nMOStransistors are OFF when the gate is 0 and ON when the gate is 1. pMOS
n
p
gatesource drain
substrate
n
(a)GND
GND
n
p
gatesource drain
substrate
n
(b)
VDD
GND
- - - - - - -
channel
+++++++
Figure 1.30 nMOS transistor operation
Gordon Moore, 1929–. Born in SanFrancisco. Received a B.S. inchemistry from UC Berkeley anda Ph.D. in chemistry and physicsfrom Caltech. Cofounded Intelin 1968 with Robert Noyce.Observed in 1965 that thenumber of transistors on acomputer chip doubles everyyear. This trend has becomeknown as Moore’s Law. Since1975, transistor counts havedoubled every two years.
A corollary of Moore’sLaw is that microprocessorperformance doubles every 18to 24 months. Semiconductorsales have also increasedexponentially. Unfortunately,power consumption hasincreased exponentially as well(© 2006, Intel Corporation.Reproduced by permission).
g
s
d
g
d
s
nMOS
pMOS
g = 0
s
d
d
s
OFF
ON
g = 1
s
d
d
s
ON
OFF
Figure 1.31 Switch models ofMOSFETs
30 CHAPTER ONE From Zero to OneThe two switching positions of an NMOS transistor
switched OFF switched ON
Threshold voltage : voltage required to turn on a transistor
Note : the MOS terminal which is acting as the drain is determined by the potentials.
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Here, just as before, Kn denotes the transductance parameter of the NMOS transistor
GSV+
_
DSV+
_
ID
drain
source
gate
VTN ≥ ≥ DSV GSV 0-
The three operation modesof a NMOS transistors
SATURATION
TNwhere V denotes the threshold voltage
VTNVGS2nK
-D = I2
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VoltageGate-Source
VoltageDrain-Source
Summary :the three modes of an NMOS transistor
V -GS
VTN
VTN
cut-o� saturation
linear
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VoltageGate-Source
VoltageDrain-Source
Summary :the three modes of an NMOS transistor
V -GS
VTN
VTN
cut-o� saturation
linear
VTNVGS2nK
-D = I2
VTNVGS 2DSV
nK DSV--D = I
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Summary :the three modes of an NMOS transistor
V + DS
VTN
V TN
VoltageGate-Source
VoltageDrain-Source
cut-o�
saturation
linear
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Summary :the three modes of an NMOS transistor
V + DS
VTN
V TN
VoltageGate-Source
VoltageDrain-Source
cut-o�
saturation
linear
VTNVGS2nK
-D = I
VTNVGS 2DSV
nK DSV--D = I
2
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Summary :the three modes of an NMOS transistor
V + DS
VTN
V TN
VoltageGate-Source
VoltageDrain-Source
cut-o�
saturation
linear
VTNVGS 2DSV
nK DSV--D = I
VTNVGS2nK
-D = I2
VDS2nK
D = I 2
![Page 21: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/21.jpg)
Characteristics of the NMOS transistor
GSV+
_
DSV+
_
ID
drain
source
gate
Drain-source voltage ( V )
Drain
-sour
ce cu
rrent
( μA )
LinearRegion
0
20406080
100120140160180200220
0 2 4 6 8 10 12
GSV = 5 V
Linear region
Pinch-o� locus
Saturation region
GSV = 4 V
GSV = 3 V
GSV = 2 V
GSV ≤ 1 V
![Page 22: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/22.jpg)
Three-dimensional representationof the characteristic curves
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Three-dimensional representationof the characteristic curves
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Voltage of A
VDD
VDDV /2DD
Voltage of Y
Exercise :Using a transistor and an NMOS resistor
can you construct a circuit with the following ( idealized ) transfer curve ?
Inverter
A Y
Note : such a circuit is called an inverter
![Page 25: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/25.jpg)
An NMOS inverter with resistor-load
A
Y
VDD
GND
pull-up resistor
NMOS transistor
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Voltage of A
VDD
VDDV /2DD
Voltage of Y
Ideal characteristic transfer curve
VOL
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Voltage of A
VDD
VDD
Voltage of Y
Real characteristic transfer curve
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Voltage of A
VDD
VDD
Voltage of Y
Exercise :
VTN
Describe in which mode the NMOS transistoroperates at each position of the curve
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Voltage of A
VDD
VDD
Voltage of Y
Solution
V -GS
VTN
VTNcut-o�saturation
linear
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Voltage of A
VDD
VDD
Voltage of Y
Solution
V -GS
VTN
VTNcut-o�saturation
linear
transition point
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Drain-source voltage ( V )
Drain
-sour
ce cu
rrent
( μA )
0
20406080
100120140160180200220
0 1 2 3 4 V = 5 V
GSV = 5 V
GSV = 4 V
GSV = 3 V
GSV = 2 V
VDD
R
How to compute the transition point ?
load line
transition point
DD
X
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Exercise
Y
VDD
GND
resistor R
resistor r
Give an explicit formula for the voltage V with parameters V and the values of the two resistors R and r in the schematics below/
DDDS
Explain why the resistor R should be as high as possiblecompared to the resistance r of the NMOS transistorat linear mode with gate-source voltage V equal to V .GS DD
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Exercise
A
Y
VDD
GND
resistor R
More generally, how would you compare the characteristictransfer curves of two inverters with resistor load constructed with the same NMOS transistorbut with pull-up resistors R and R of di�erent values ?1 2
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V =IL VIH
Voltage of A
VDD
VDDV /2DD
Voltage of Y
Ideal characteristic transfer curve
VOL
V =OH
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VIL VIH
Voltage of A
VDD
VDD
Voltage of Y
VOL
VOH
Unity Gain Pointwith slope = -1
Unity Gain Pointwith slope = -1
Real characteristic transfer curve
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Logic levels and noise margins
ForbiddenZone
NM
NML
H
Logic HighOutput Range
Logic LowOutput Range
Logic HighInput Range
Logic LowInput Range
V IL
V IH
VOL
VOH
GND
VDDOutput characteristics Input characteristics
Driver Receiver
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Exercise
Driver Receiver
Can you draw a ( qualitative ) picture of the characteristic transfer curveof the following circuit, constructed by composing two inverters:
What can this circuit be useful for ?
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Logic levels of 5 V and 3.3 V logic families
TTL = Transistor - Transistor Logic
LVTTL = Low Voltage TTL Logic LVCMOS = Low Voltage CMOS Logic
CMOS = Complementary Metal - Oxide Semiconductor
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An NMOS inverter with resistor-load
A
Y
VDD
GND
such a resistor would be far too largeto implement on an integrated circuit
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The NMOS saturated inverter
A
Y
VDD
GND
pull-up transistoreither in cut-o� orin saturation mode
enhancement-mode load=DSV GSV
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A
Y
VDD
GND
pull-up transistoralways in cut-o� orin saturation mode
enhancement-mode load=DSV GSV
The NMOS saturated inverter
GND
GND
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Drain-source voltage ( V )
Drain
-sour
ce cu
rrent
( μA )
0
20406080
100120140160180200220
0 1 2 3 4 V = 5 V
GSV = 5 V
GSV = 4 V
GSV = 3 V
GSV = 2 V
Resistor vs. enhancement vs. depletion loads
load line
DD
X
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gate
source of electrons
drain of electrons
gate
source of holes
drain of holes
N-channel MOSFETdepletion mode
P-channel MOSFETdepletion mode
dire
ctio
n of
the c
urre
nt �
ow
Depletion-mode MOSFET transistors
The device is ON at rest.A negative voltage must then be applied to the gate
wrt. the source in order to switch the device OFF.
The device is ON at rest.A positive voltage must then be applied to the gate
wrt. the source in order to switch the device OFF.
![Page 44: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/44.jpg)
Characteristics of an NMOS transistorin depletion-mode
GSV+
_
DSV+
_
ID
drain
source
gate
Drain-source voltage ( V )
Drain
-sour
ce cu
rrent
( μA )
LinearRegion
0
20406080
100120140160180200220
0 2 4 6 8 10 12
GSV = 5 V
Linear region
Pinch-o� locus
Saturation region
GSV = 2 V
GSV = 0 V
GSV = -1 V
GSV ≤ -2 V
![Page 45: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/45.jpg)
A depletion-load NMOS inverter
A
Y
VDD
GND
depletion-mode loadpull-up transistoralways switched on
at gate-source voltageequal to zero
Further reading : Toshiaki Masuhara’s PhD thesis ( Sept. 1976 )
![Page 46: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/46.jpg)
A depletion-load NMOS inverter
A
Y
VDD
GND
depletion-mode loadGND
Further reading : Toshiaki Masuhara’s PhD thesis ( Sept. 1976 )
GND
pull-up transistoralways switched on
at gate-source voltageequal to zero
![Page 47: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/47.jpg)
Drain-source voltage ( V )
Drain
-sour
ce cu
rrent
( μA )
0
20406080
100120140160180200220
0 1 2 3 4 V = 5 V
GSV = 5 V
GSV = 4 V
GSV = 3 V
GSV = 2 V
Depletion load inverter
load line
DD
X
![Page 48: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/48.jpg)
Drain-source voltage ( V )
Drain
-sour
ce cu
rrent
( A )
0 1 2 3 4 V = 5 V
Resistor-load vs. enhancement-load vs. depletion-load
depletion
DD
resistor
enhancement
On the other hand, the output fall time 1 0 is almost independent of the pullup device
The output rise time 0 1 depends on the pullup deviceDepletion-load is faster than enhancement-load because of the weaker resistance of the pullup device
X
![Page 49: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/49.jpg)
A
Y
VDD
GND
B
An NMOS NAND gate with resistor load
a resistor would be far too largeto implement on an integrated circuit
![Page 50: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/50.jpg)
A saturated NMOS NAND gate
A
Y
VDD
GND
B
enhancement-mode loadpull-up transistoreither in cut-o� orin saturation mode
![Page 51: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/51.jpg)
A depletion-load NMOS NAND gate
A
Y
VDD
GND
B
pull-up transistoralways switched onwith voltage gate-sourceequal to zero
depletion-mode load
![Page 52: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/52.jpg)
PMOS = NMOSthrough the looking glass
![Page 53: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/53.jpg)
Characteristics of the PMOS transistor
GSV+
_
DSV
+
_ID
Drain-source voltage ( V )
Drain
-sour
ce cu
rrent
( μA )
drain
source
gate
Drain-source voltage ( V )
Sour
ce-d
rain
curre
nt ( μ
A )
250
200
150
100
50
0
- 50+2 0 - 2 - 4 - 6 - 8 - 10 - 12
GSV = - 5 V
GSV = - 4 V
GSV = - 3 V
GSV = - 2 V
GSV ≥ - 1 V
![Page 54: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/54.jpg)
Voltage of A
VDD
VDDV /2DD
Voltage of Y
Exercise :Using a PMOS transistor and a resistor
can you construct a circuit with the following ( idealized ) transfer curve ?
Inverter
A Y
Trick : use symmetry !!!
![Page 55: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/55.jpg)
Solution : PMOS inverter with resistor-load
A
Y
VDD
GND
pull-down resistor
PMOS transistor
![Page 56: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/56.jpg)
Order of apparition in history
PMOS
NMOSenhancement-load
NMOSdepletion-load
CMOS
• 1971 : Intel 4004 ≈ 2250 PMOS transistors• 1972 : Intel 8008 ≈ 3500 PMOS transistors• 1975 : Rockwell PPS-8
• 1973 : NEC μCOM 4 ≈ 2500 NMOS transistors• 1974 : Intel 8080 ≈ 6000 NMOS transistors• 1974 : Toshiba TLCS-12• 1974 : Motorola 6800 ≈ 4100 NMOS transistors
• 1975 : Zilog Z80 ≈ 8500 NMOS transistors• 1975 : MOS Technology 6502 ≈ 3510 NMOS transistors• 1977 : Intel 8085 ≈ 6500 NMOS transistors• 1978 : Intel 8086 ≈ 29000 NMOS transistors
• 1963 : invented by Frank Wanlass at Fairchild Semiconductor• 1975 : Intersil 6100 ≈ 4000 NMOS transistors• 1976 : RCA 1802 or COSMAC• 1981 : Hitachi HD6301 CMOS version of the Motorola 6801• 1982 : Western Design 65C02 which is a CMOS version of the 6502
![Page 57: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/57.jpg)
A CMOS inverter
A Y
VDD
GND
NMOS transistor
PMOS transistor
![Page 58: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/58.jpg)
The �ve modes of the CMOS inverter
Unity Gain Pointwith slope = -1
Unity Gain Pointwith slope = -1
2.5 V
2.0 V
1.5 V
1.0 V
0.5 V
0 V
0 V 0.5 V 1.0 V 1.5 VVoltage of A
Voltage of Y
2.0 V 2.5 V
NMOS saturatedPMOS saturated
NMOS saturatedPMOS linear
NMOS linearPMOS saturated
NMOS o�
PMOS o�
![Page 59: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/59.jpg)
The �ve modes of the CMOS inverter
Unity Gain Pointwith slope = -1
Unity Gain Pointwith slope = -1
2.5 V
2.0 V
1.5 V
1.0 V
0.5 V
0 V
0 V 0.5 V 1.0 V 1.5 VVoltage of A
Voltage of Y
2.0 V 2.5 V
NMOS saturatedPMOS saturated
NMOS saturatedPMOS linear
NMOS linearPMOS saturated
NMOS o�
PMOS o�
![Page 60: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/60.jpg)
A Y
VDD
GND
NMOS transistor
PMOS transistor
cuto�
The �ve modes of the CMOS inverter
linear
![Page 61: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/61.jpg)
The �ve modes of the CMOS inverter
Unity Gain Pointwith slope = -1
Unity Gain Pointwith slope = -1
2.5 V
2.0 V
1.5 V
1.0 V
0.5 V
0 V
0 V 0.5 V 1.0 V 1.5 VVoltage of A
Voltage of Y
2.0 V 2.5 V
NMOS saturatedPMOS saturated
NMOS saturatedPMOS linear
NMOS linearPMOS saturated
NMOS o�
PMOS o�
![Page 62: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/62.jpg)
A Y
VDD
GND
NMOS transistor
PMOS transistor
saturated
linear
The �ve modes of the CMOS inverter
![Page 63: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/63.jpg)
The �ve modes of the CMOS inverter
Unity Gain Pointwith slope = -1
Unity Gain Pointwith slope = -1
2.5 V
2.0 V
1.5 V
1.0 V
0.5 V
0 V
0 V 0.5 V 1.0 V 1.5 VVoltage of A
Voltage of Y
2.0 V 2.5 V
NMOS saturatedPMOS saturated
NMOS saturatedPMOS linear
NMOS linearPMOS saturated
NMOS o�
PMOS o�
![Page 64: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/64.jpg)
A Y
VDD
GND
NMOS transistor
PMOS transistor
saturated
saturated
The �ve modes of the CMOS inverter
![Page 65: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/65.jpg)
The �ve modes of the CMOS inverter
Unity Gain Pointwith slope = -1
Unity Gain Pointwith slope = -1
2.5 V
2.0 V
1.5 V
1.0 V
0.5 V
0 V
0 V 0.5 V 1.0 V 1.5 VVoltage of A
Voltage of Y
2.0 V 2.5 V
NMOS saturatedPMOS saturated
NMOS saturatedPMOS linear
NMOS linearPMOS saturated
NMOS o�
PMOS o�
![Page 66: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/66.jpg)
A Y
VDD
GND
NMOS transistor
PMOS transistor
linear
saturated
The �ve modes of the CMOS inverter
![Page 67: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/67.jpg)
The �ve modes of the CMOS inverter
Unity Gain Pointwith slope = -1
Unity Gain Pointwith slope = -1
2.5 V
2.0 V
1.5 V
1.0 V
0.5 V
0 V
0 V 0.5 V 1.0 V 1.5 VVoltage of A
Voltage of Y
2.0 V 2.5 V
NMOS saturatedPMOS saturated
NMOS saturatedPMOS linear
NMOS linearPMOS saturated
NMOS o�
PMOS o�
![Page 68: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/68.jpg)
The �ve modes of the CMOS inverter
A Y
VDD
GND
NMOS transistor
PMOS transistor
cut-o�
linear
![Page 69: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/69.jpg)
A
GND
B
Y
VDD
CMOS NAND gate
![Page 70: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/70.jpg)
A
GND
B
Y
VDD
GND
VDD
A
B
Y
CMOS NOR gate
![Page 71: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/71.jpg)
Gate
Source
Drain
Insulator
Latest technology : the FinFet transistors
![Page 72: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/72.jpg)
Latest technology : Through-Silicon Via ( TSV )
![Page 73: From transistors to digital logiccomputer-architecture.org/Lectures/Computer-Architecture... · 2018-02-06 · Complementary MOS or CMOS. CMOS processes are used to build the](https://reader030.vdocument.in/reader030/viewer/2022041208/5e8ec3ac16ce61468369d8b5/html5/thumbnails/73.jpg)
Readings
Exercices
Harris and Harris, Chapter 1.
Harris and Harris : 1.86, 1.87, 1.88, 1.89, 1.90. Build the corresponding schematics in CircuitLab and test them.
Do the exercises in Recitation 2.
Instruction Set ArchitectureStudy the instruction set which you were assigned between
• LC-3 • MIPS • x86