front-end electronics for future linear collider calorimeters c. de la taille in2p3/lal orsay on...

Front-End electronics for Future Linear

Collider calorimeters C. de La Taille

IN2P3/LAL Orsay

On behalf of the CALICE collaboration http::/www.lal.in2p3.fr/technique/se/flc

http://www.in2p3.fr/

20 may 2006 C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia 2

« Imaging calorimetry » at ILC

Particle flow algorithm Reconstruct each particle individually Bring jet resolution down to 30%/√E Measure charged particles in tracker Measure photons in ECAL Measure hadrons in ECAL and HCAL Minimize confusion term

Calorimeter design High granularity : typ < 1 cm2

High segmentation : ~30 layers Moderate energy resolution (10%/√E) ECAL : Silicon-Tungsten HCAL : analog vs digital

CALICE collaboration « a high granularity calorimeter

optimized for particle flow algorithm 190 phys./eng., 9 countries, 3

regions

©J.C Brient (LLR)F. Sefkow (DESY)


ILC Challenges for electronics

Requirements for electronics Large dynamic range (15 bits) Auto-trigger on ½ MIP On chip zero suppress Front-end embedded in detector Ultra-low power : ( « 100µW/ch) 108 channels Compactness

« Tracker electronics with calorimetric performance »

ATLAS LAr FEB 128ch 400*500mm 1 W/chFLC_PHY3 18ch 10*10mm 5mW/ch ILC : 100µW/ch

W layer

Si pads

ASIC

Ultra-low POWERis the

KEY issue


CALICE physics prototype(s)

1 m3 prototype for physics tests Goal : study particle flow algorithm Check modelization of hadronic

showers

3 calorimeters to go to testbeam ECAL : W-Si 24X0 20x20 cm2

AHCAL : Tiles + fibers + SiPMs DHCAL : RPCs or GEMS Already 104 to 4 105 channels ! Run at DESY (05), CERN (06), FNAL

(07)


14 layers, 2.1 mm thick70 boards made in Korea

ECAL W-Si prototype

ECAL prototype 1 cm2 Si PADS, 550 µm 1 MIP = 40 000 e- 216 channels/slab 10 000 channels total

Readout electronics FLC_PHY3 ASIC [LAL] Calibration ASIC [LAL] CRC DAQ boards [UK]


FLCPHY3 front-end ASIC

AmpOPA

OPA

G1

G10

1 channel Chip architecture 18 Channels/chip Low noise charge preamp optimized

for Cd=70pF. Variable gain (Cf = 0.2 -> 3 pF) ENC = 1000e- + 40 e-/pF @ tp=200ns series noise : en = 1.6nV/√Hz @ 600 µA poor 1/f noise : 25 e-/pF

Dual gain shaper (G1-G10) tp = 200 ns splits 15bit dynamic range in 2 x 12 bits

Differential shaper and Track&Hold => better pedestal stability and dispersion : pedestal dispersion : 5 mV rms

Multiplexed output : 5 MHz

Power dissipation : 6mW/channel Technology : AMS 0.8µm BiCMOS 2000 chips produced in 2003, yield :

86%

Synoptic of 1 channel of FLCPHY3

©J. Fleury (LAL)


FLC_PHY3 : performance

Measured on all preamp gains Cf = 0.2, 0.4, 0.8, 1.6, 3 pF Well within ± 0.2 %

Dynamic range (G1, Cf=1.6pF) Max output : 3 V linear (0.1%) range : 2.5V

= 500 MIPS @ Cf = 1.6 pF

Noise : • 200 µV (Cd = 0)• 410 µV (Cd = 68pF)

• = 0.1 MIP @ Cd = 68 pF

Dynamic range : > 12 bits• 13 000 (14 bits) @ Cd = 0• 6500 (12 bits) @ Cd = 68 pF

Can be extended to 13-14 bits by using the bi-gain outputs


Results with detector

Testbeam at DESY (jan 05) Calorimeter partially equipped

(7 X0, 3000 channels) MIP/noise = 8 => clean cut at ½

MIP Calibration done with cosmics Just now completed to 24X0 !

Noise, MIP

2 adjacent 2 GeV electrons

©G. Gayken (LLR)

20 may 2006 C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia

9

AHCAL testbeam prototype

• 1 cubic metre, • 38 layers, 2cm steel plates• 8000 tiles with SiPMs• Electronics based on ECAL design

Mechanics and front end boards: DESYFront end ASICs: LAL

©F. Sefkow (DESY)


10

SiPMs for calorimetry

• Multipixel Geiger Mode APDs– Gain 106, bias ~ 50 V, size 1 mm2

– Insensitive to magnetic fields

3x3 cm scintillator tile with WLS fibre

ITEP

1156 pixels with individual quenching resistor on common substrate

MEPHI / PULSAR

Auto-calibratingbut non-linear

New era for scintillator–based

detectors:High granularity at relatively low cost


0 20 40 60 80 100-1,2

-0,8

-0,4

0,0

A,

mV

time, ns

Variable Gain Charge Preamplifier

Variable Shaper CR-RC²

in

8bit DAC

out

SiPM readout ASIC

Readout AHCAL (DESY) SiPM detector (MEPHI ) >3000 channels : first large scale use G ~ 106 e ~10% HV ~ 50 V

FLC_SiPM readout ASIC 18 channel variable gain preamp and

shaper Dynamic range : 13 bits (2 gains) 8 bit DAC for SiPM gain adjustment 1000 chips produced in 2004

One pixel signal © E. Popova

Single photoelectron spectrum © E. Popova

©L. Raux (LAL)


Digital HCAL physics prototype

GEM based DHCAL RPC based DHCAL

Signal PadMylar sheet

Mylar sheet Aluminum foil

1.1mm Glass sheet

1.1mm Glass sheet

Resistive paint

Resistive paint

1.2mm gas gap

-HV

GND

Charged particles

©A. White (U. Arlington)J. Repond (ANL)


DHCAL front-end electronics ©J. Hoff, A. Mekaoui (FNAL)

DCAL chip 64 inputs with gain choice

GEM/RPC Triggerless or triggered operation Output hit pattern & time stamp Prototyped in 0.25µm in march

2005


DCAL chip performance

DCAL chip performance All digital functions operationnal Excellent efficiency curves Threshold adjustable between 2-8 fC

DCAL2 chip Submission foreseen july 06 Reduced preamp gain Threshold RPC ~ 100 fC Threshold GEMS ~10 fC


Technological prototype : “EUDET module”

Front-end ASICs embedded in detector Very high level of integration Ultra-low power with pulsed mode FLC_TECH1 ASIC prototype in 0.35 µm SiGe

All communications via edge 4,000 ch/slab, minimal room, access, power small data volume (~ few 100 kbyte/s/slab)

« Stitchable motherboards »

Elementary motherboard ‘stitchable’ 24*24 cm ~500 ch. ~8 FE ASICS


EUDET module FEE : main issues

Mixed signal issues Digital activity with sensistive

analog front-end

Pulsed power issues Electronics stability Thermal effects To be tested in beam a.s.a.p.

No external components Reduce PCB thickness to <

800µm Internal supplies decoupling

FE chip (1mm)Wafer (400µm)PCB (600µm)

Tungsten (1 mm)


ECAL Front-End ASIC

PowerCycling

Auto-trigger on ½ MIP

Internal ADC

Readout integration is the key element of compact detector Keep small Moliere radius for good shower separation Many features have never been used before e.g. power cycling (ON 2ms OFF

200 ms)


Present status on noise & power cycling

FLC_TECH1 : moving into SiGe 0.35µ 30 µW in pulsed mode ENC = 1000 e- @ Cd=27pF (MIP=40 000e-) NOISE WELL BELOW MIP First demonstration of power cycling : Target power of 100 µW/channel

appears within reach : to be validated in testbeam in 2006 with FLC PHY4 ASIC

FLC shaping

Detector capacitance

Autotrigger

ON

signal

Ready for pulse

RFCF

20 µs

POWER CYCLING MEASUREMENTNOISE MEASUREMENT


EUDET ECAL ASIC

72 channels Scales with the 4 factor reduction in pad size and is compatible with

physics prototype

Detector DC coupling Prepares the case the on-detector MMIC HV capacitance is not

affordable Provides leakage current monitoring, up to 1 µA/Ch

Auto-trigger If one channel is hit during a bunch crossing, then the whole chip is

recorded with a time tag (BCID) The auto trigger activates the T&H

Analogue pipeline, ADC & digital registers 8-depth analog pipeline to store « in bunch » events Wilkinson 12 bit 100MHz ADC On chip storage, inter-bunch data outputting

Digital data output Daisy chained with redundancy : one output for 40 ASICs Common architecture for ECAL and HCAL


Front-end

Derived from existing FLC_PHY4 chip

I N P U T A m p lif ie r

C f 0

C f 1

C f 2

C f 3

SW 0

SW 1

SW 2

SW 3

R f

o p . a m p .-

+ Ga in 1

o p . a m p .-

+ Ga in 1 0

Vr e f _ ss

Vr e f _ ss

T r a c k & H o ld

T r a c k & H o ld

T o Ga in 1 M U X

T o Ga in 1 0 M U X

C A L I B R A T I O N

To ADC – leakage current meas.

SCA

SCA

Bipolar Fast shaper

Monostable

Threshold

TriggerTimewalk-free

Vref_fs


ADC

Channel 0

Channel 1

Channel 71

Rampgenerator

Register 0

Register 71

Graycounter

Wilkinson architecture, developped by Clermont group 100 MHz clock frequency : 4 µs digitization time for 12 bits

©G. Bohner (LPCC)


Digital part Store all channels and BCID for every hit. Depth ~8 bits Event size : 8(depth)*[16bit*72ch+16bit(bcid)] = 9344 bits Sequential readout : 9344*10ns = 100 µs : LVDS level

Register 16bits

OR

16 bit counter BCID

Register 16bits

DiscriCH 0

DiscriCH 71

Register 16*16 bit BCID


EUDET ECAL ASIC

Will be submitted in AMS 0.35µm SiGe in sept 06 Area : 3 x 7 mm

36 Analog

Channels+ ADC

36 inputs

36 inputs

Digital memory

and controls

36 Analog

Channels+ ADC

Control signals and power supplies

Control signals and power supplies


EUDET DHCAL RPC ASIC

Move towards ILC specs Power pulsing Data internally saved during bunch train Data transferred to DAQ during inter-bunch

Chip based on MAROC will be submitted in sep 06

Close

to M

AROC chip

64 chan

nels f

or m

ulti-a

node

PM

C h a n n e l 0

C h a n n e l 1

C h a n n e l 2

C h a n n e l 3

C h a n n e l 6 2

C h a n n e l 6 3

T h r e sh o ld 0

T h r e sh o ld 1

T h r e sh o ld 2

T h r e sh o ld 3

T h r e sh o ld 6 2

T h r e sh o ld 6 3

>

B unc h c ro s s ing ID

Dig

ital m

emor

y[ 6

4 bi t s

(da

t a)

+ 12

bi ts

(B

CID

)]*d

e pht

mem

ory write

D a ta o u t

an a lo g u e f r o n t- en d


MAROC : 64 ch MAPMT chip for ATLAS lumi

Characteristics 64 PMT channels input (50-100 Ω) Variable gain current conveyor (0-2)

6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16

64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron

(50fC). Counting rate up to 2 MHz Common threshold loaded by internal

10bit DAC 1 multiplexed charge output with variable

shaping 20-200ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC) Crosstalk < 1%

Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm2

Dissipation 130 mW @ VDD=3.5V

Can be accomodated to DHCAL Adding power pulsing and digital readout

Synoptic diagramm of MAROC1

Hold signal

Variable

GainPream

p.

VariableSlow

Shaper

S&H

BipolarFast Shaper

64 Trigger outputs

Gain correction6 bits/channel

discriminator

threshold10 bits DAC

Multiplexed charge output

64 PM inputs

10 bit DAC

©N. Seguin (LAL)


« super common base » Preamplifier

Current conveyor « Super common-base » configuration Low input impedance : 50 – 100 Ω

• Rin = 1/gm1gm2RC=VT2/IC1IC2RC + 50 Ω protection

• Can be varied by adjusting IC1

• Low “Inductive term”(50 nH) with careful dimensioning

Large output impedance : ~500 kΩ Unity current gain

Q2

Q1

Rc

Iin

Iout


MAROC Efficiency curves


Prospective for A-HCAL SiPM Chip

Similar developments for AHCAL Chip fully dedicated to SiPMs developped after ECAL chip Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing

T&Hx1

Variable gain Preamplifier

Discri

TDC

12-bit ADC

8 bit DAC (0-5V)

in

Fast Shaper

Shaper tp~30-40ns

Auto-trigger

12-bit DAC

Threshold

Capacitance for AC

coupling

…

Analogue Memory

Charge Ouput

Time Ouput


Conclusion

Several large dynamic range ASICs developped for CALICE physics prototypes ECAL W-Si calorimeter : FLC_PHY3 = 104

channels in beam, dynamic range 0.1-600 MIPS

AHCAL Tile-SiPM calorimeter : FLC_SiPM = 103 channels installed, beam in summer 06

DHCAL GEM/RPC

ASICs for technological prototypes now in development Power pulsing Zero-suppress Auto-trigger

System aspects not to be forgotten Power supplies ! Mechanics Reliability…


Backup slides


SLAC-Oregon-UC Davis-BNL Si-W ECal R&D

David Strom

Effective 4 x 4 mm2


SLAC-Oregon-UC Davis-BNL Si-W ECal R&D

KPix Cell 1 of 1024

M.Breidenbach

Tungsten

Tungsten

Si Detector

KPix

Kapton

Bump BondsMetallization on detector from KPix to cable

Thermal conduction adhesive

Kapton Data Cable

Heat Flow


FLC_TECH1 : noise performance

FLC_TECH1 : 0.35µm Series : en = 1.4 nV/√Hz

CPA = 7 pF 1/f noise : 12 e-/pF Parallel : in = 40 fA/√Hz

Target noise of ENC < MIP/10 = 4000 e- is (more than) achieved

FLC_PHY3 : 0.8µm Series : en = 1.6nV/√Hz

CPA = 10pF + 15pF test board

1/f noise : 25e-/pF Parallel : in = 40 fA/√Hz

ENC vs shaping time FLC_PHY3 0.8µ

ENC vs shaping time FLC_TECH1 0.35µ

FLC shaping

Detector capacitance

Autotrigger

C. de La Taille front-end electronics for ILC calorimeters FEE2006 Perugia

EUDET : ECAL emodule

Electromagnetic calorimeter Prototype of a (~ 1/6) module 0 :

one line & one column 150 cm long, 12 cm wide 30

layers 1800 + 10800 channels Test full scale mechanics + PCB Can go in test beam Test full integration + edge

communications Similar in #channels as physics

prototype

©M. Anduze (LLR)


Digital part Store all channels and BCID for every hit. Depth ~16 bits Data format : 16(depth)*[1bit*128ch+16bit(bcid)] = 2 kbits Sequential readout @ 100 MHz : 2000 * 10 ns = 20 µs

Register 16bits

OR

16 bit counter BCID

Register 16bits

DiscriCH 0

DiscriCH 127

Register 16*16 bit BCID

Moreprobably a RAM


FLCPHY4

Ch.1 1

10

Ch.2

Ch.18

Digital Output

Mu

ltip

lexi

ng

Gain

10

Mu

ltip

lexi

ng

Gain

1Idle

DigitalOutput

Integrating 12 bit ADC [collab LPNHE Paris] and full power cycling Submitted in july 05, to be validated in testbeam 06 at CERN

12 bit ADC ( AMS IP)

PowerCyclin

g


37

HCAL architecture

Typical layer2m2

2000 tiles

38 layers80000 tiles

FEE: 32 ASICs (64-fold)

4 readout lines / layer

Layer dataConcentrator

(control, clock and read FEE)

Module data concentrator

Instrument one tower (e.m. shower size)

+ 1 layer (few 1000 tiles)

To DAQ

EUDET: Mechanical structure, electronics integration:

DESY and Hamburg U


Towards module0 ASIC : FLC_TECH

No PowerCycling

No Auto-trigger on ½ MIP

No Internal ADC

What is missing in FLC_PHY3 :

AmpOPA

OPA

MUX out Gain=1

MUX out Gain=10

1 channel

Dynamic range <1000 MIPS


Signal uniformity (G1)

Signal (Gain 1, Cf=1.6pF) Amplitude = 696 mV/pC ± 18 mV

= 4.66 mV/ MIP ± 2.5% rms Peaking time = 189 ns ± 2 ns rms Pedestals = -3.7 V ± 4.8 mV rms

Noise Cd = 0 pF : Vn = 200 µV Cd = 68pF : Vn = 410 µV

Crosstalk : < 0.1%

Gain 1 uniformity vs channel number

Peaking time uniformity Pedestal uniformity


Signal uniformity (G10)

Signal (Gain 10, Cf=1.6pF) Amplitude = 6294 mV/pC ± 188 Peaking time = 174 ns ± 2 ns Pedestals = -3.74 V ± 8.3 mV rms

Noise Cd = 0 pF : Vn = 500 µV Cd = 68pF : Vn = 1.6 mV

Crosstalk < 0.2%

Pedestal uniformity Peaking time uniformity

Gain 10 uniformity vs channel number


41

<T50> as function of input charge

Error bars = RMS of distributions

Nice linear dependence!

2nd Iteration of ASIC Prototype

- Decrease of input sensitivity by x 100

Currently upper threshold corresponds to 7.6 fC Smallest RPC signals ~ 100 fC Noise from digital lines ~ 20 fC (preliminary)

- Decouple of output clock and chip clock

- Submission on July 22nd (highest priority of FNAL design group)

Redesign will start in late May

- Will be used in slice test of Digital Hadron Calorimeter with RPCs (January 2007 at MT6)

More Results…

c) Linearity with injected charge

d) Tests of pipeline

e) Measurements of noise rate

f) Tests of time stamp counter

All successful!!!

front-end electronics for future linear collider calorimeters c. de la taille in2p3/lal orsay on...

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