CMPE 480 ADVANCED DIGITAL LOGIC DESIGN Department of Electrical and Computer Engineering University of Alberta Winter 2010

Finite State Machines

Lab

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Finite State Machines

Finite state machines (FSM) are the classic method of describing the behaviour of a sequential system. In this lab you will gain experience in the design, implementation and debugging of FSMs. You will design a hardware implementation of a one-dimensional variant of Conways game of life. This variant will require a Rule 90 cellular automaton. Your design will be implemented on the Digilab D2 and the Digilab D2IO FPGA boards. The logic analyzer will be used to debug and verify your design.

Lab Overview In this lab you will learn:

How to turn a sequential circuit description into a formal Finite State Machine. How to model a Finite State Machine using behavioural-level VHDL. How to implement your design in an FPGA. How to use the logic analyzer for debugging and verification purposes.

Pre-lab 1. Read the Background section of this handout and do the following:

a. Draw a state diagram for a single cell of a Rule 90 cellular automaton. Include a mechanism to load an initial state into the cell. Define the cells entity and create a block symbol for it.

b. Draw a block diagram interconnecting 4 cells to form a cellular automaton

with wrap-around.

c. Calculate the first 12 generations of a 14-cell Rule 90 cellular automaton. Assume that the initial state is: 00 0001 0000 0000 (0100H). Present your answers in 12 binary step values and the final hexadecimal value.

2. Read the Digilab 2 reference manual. Map the IO ports CA_CLOCK, CA_ITER and

CA_STATE (in the supplementary toplevel.vhd file) to the appropriate XC2S200 FPGA pin numbers so that these signals can be observed through the expansion connector C of the Digilab D2 FPGA board.

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Use the following pin assignment in the expansion connector C:

a. CA_CLOCK : Pin 4.

b. CA_ITER : Pin 7 to 20 (map the LSB to the lower numbered pin).

c. CA_STATE: Pin 23 to 36 (map the LSB to the lower numbered pin).

Submit a copy of your FPGA pin assignments.

3. Read the logic analyzer tutorial. Although you will not be able to complete the tutorial exercise before the lab, you need to read it.

4. Prepare and type in all VHDL code you will use for this lab, prior to the lab (not necessarily the optional bonus part). You can save your VHDL code in your ECE computer account. Compiling and correcting syntax errors prior to the lab is optional but would be a good idea nonetheless. When the pre-lab is marked, present your VHDL code on the screen of your computer.

5. Prepare test case for a single cell and explain.

Background Game of Life The game of life was invented by the mathematician John Conway. This is not a game in the conventional sense since there are no players: it is a cellular automaton. It consists of a collection of cells which, based on a few mathematical rules, can live, die or multiply. Depending on the initial conditions, the cells form various patterns throughout the course of the game.

Background on Cellular Automata A cellular automaton (CA) is a state machine composed of an array of cells, each of which is a finite state machine. The cells are updated synchronously in discrete time steps according to an identical interaction rule. The state that a given cell will have in the next generation is based on the current state of the cell and the current state of its surrounding neighbourhood. The transitions are usually specified in the form of a rule table that defines the cell's next state for each possible neighbourhood configuration. The cellular array is highly parallel, locally connected and uses simple elemental units.

The simplest case of a cellular automaton is a one-dimensional automaton, where the next state of a cell will depend only on its current state and the current state of its left and right neighbours. Notice that there are 23 = 8 possible neighbourhood

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configurations; thus, there are 28 = 256 different possible rules (a rule is applied to each set of 8 neighbourhood configurations).

CA Rule 110 As the CA evolves, each cell checks the state of itself and the cells directly to the left and right of it, and then changes its state according to Rule 110:

In the above figure, the 8 different 3-cell neighbourhood configurations (e.g., 000, 001, . . . , 111) are illustrated. The name "Rule 110" comes from the decimal value of the truth table entries interpreted as one 8-bit binary number. Thus the "Rule 90" is defined by a truth table whose entries correspond to the binary number equal to decimal 90. In the figure, the eight possible values of the three neighbouring cells are shown in the top row of each panel, and the resulting value the central cell takes in the next generation is shown below in the center. In the figure the white blocks represent the DEAD state (binary value 0) and gray blocks represent the ALIVE state (value 1). The following diagram shows the evolution of the CA for some different rules after several generations. The starting generation is at the top, and every row represents a new generation.

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Reference: Math World web site

http://mathworld.wolfram.com/ElementaryCellularAutomaton.html

Lab Procedure

Section A The cell. 1. Design a single CA cell implementing CA Rule 90. Use the state diagram that you

designed in the pre-lab.

2. Synthesize and implement your design.

3. Perform a behavioural and a post-place-and-route simulation to verify your design.

4. Open the FPGA Editor and investigate how the FSM was implemented in the FPGA. In particular, how many Look Up Tables (LUTs) were used in the synthesized implementation of your design.

Section B The Automaton 1. Using the following entity, design a parameterizable N-cell CA. You can use as a

reference the interconnection diagram of the 4-cell automaton that you prepared in your pre-lab.

entity CA is

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Generic ( width : integer := 14 ); Port (CLK : in std_logic; LOAD_STATE : in std_logic; INI_STATE : in std_logic_vector(width-1 downto 0); STATE : out std_logic_vector(width-1 downto 0); ITERATION : out std_logic_vector(13 downto 0)); end CA;

The two inputs LOAD_STATE and INI_STATE set the initial state of the automaton. The output STATE presents the current state. The output ITERATION presents the number of the current generation of the CA. Note that a reset signal is not present, but the bonus section will offer you the chance of adding a synchronous reset.

2. Synthesize and implement a 14-cell CA.

3. Perform a behavioural and a post place and route simulation to verify your design.

Section C FPGA Implementation You are required to connect the provided components as illustrated in the SYSTEM_DIAGRAM.JPG file on the course website (pictured below). Once this is done correctly, you will implement the design on the Digilab D2 and Digilab D2IO FPGA boards. Hook the ITERATION to LEDs and STATE to 7-segment display.

Calculate the value for the generic parameters of the clock divider, so that the CA evolves at approximately one generation per 750 milliseconds. Find how to calculate these values in the header of file clock_divider.vhd. Set these values when you instantiate the clock divider in the toplevel struture.

If everything is hooked up properly, you will see every generation of the CA in the 7- Segment displays and and the generation number displayed on the 16 LEDs. You will be able to set an initial CA state through the bank of 8 switches (only the leftmost eight cells of the CA can be initialized, the state of the six rightmost cells will be set to DEAD). The LOAD_STATE signal of your CA is connected to the push-button PB0.

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The design is provided to you as individual modules. You are provided with a toplevel.vhd file, which contains an empty architecture. Use this to start your work. Create the system pictured above at the structural level (instantiated components connected using Port map statements.) within the top-level entity architecture. All of the required connections are detailed in the system diagram. Ports that are not included in the system diagram (unused) must still be connected to something when port mapping the component in question in order to appease the synthesizer. You can simply connect these ports to unused signals in order to get around any related error messages. This is analogous to the process that takes place in traditional digital design.

14-Cell CAR

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When connecting an IC in a digital system, it is standard practice to terminate any unused input terminals so they dont pick up and amplified electrical noise.

Remember that you will need internal signals to connect ports of internal components to other internal component ports. You do not need internal signals to connect ports of internal components to ports of the entity whose architecture you are defining. For example, you will need an internal signal to connect CLK_OUT of the clock divider to CLK of the CA; however, you do not need a signal to connect CS of the D2IO_driver to CS of toplevel.

With the toplevel.vhd source file selected in the ISE source window, expand the User Constraints process and click on Assign Package Pins. Use the PACE editor to complete the pin assignments (refer to Lab 0 for details). The correct pin assignment for CA_CLOCK, CA_ITER and CA_STATE was determined in the pre-lab section.

Once the pin numbers have been assigned to the logical ports, create the toplevel.bit (the bit file will always have the same filename as the entity you are implementing) file and download it to the Digilab D2 board. Before you generate the programming bit file, select the toplevel source file and right click the Generate Programming File process. Select Properties. Select the Startup Options tab. For FPGA Start-Up Clock, use the pull-down box to select JTAG Clock.

Verification With a working implementation of your design in the Digilab D2 and Digilab D2IO FPGA boards, you could visually verify your design. However, you will notice that this task is very difficult because you need to evaluate all the cells in less than one second, and remember the previous state so you can verify that the CA is evolving properly. A Logic Analyzer (LA) will help us perform this task.

Demonstrate your design to the TA or Lab Instructor, and then change the generic parameters of the clock divider in the toplevel (the one connected to the CA) so that it now divides the IO_CLOCK by 16.

We do this in order to better use the limited memory of the Logic Analyzer (if the frequency is too low, then the memory of the LA will be full before a state transition occurs in the CA).

The Digilab D2IO board uses an addressing scheme to multiplex all of the available hardware onto the 8 data lines. Each hardware resource has an address. The D2IO driver simply polls the hardware, updating its registers in a continuous loop.

Although you will never need to worry about the details of reading or writing to the Digilab D2IO board (because its done for you in the D2IO driver), it is still beneficial

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to understand the system you will be using for the remainder of the term. Take a look at the VHDL code in the D2IO_driver.vhd file.

Having read the LA tutorial, you are already familiar with the theory behind this piece of equipment. So lets get right to the goods.

We will use the two input channels of the LA because each channel can capture up to 16 signals and we need to capture 28 (14 for CA_ITER and 14 for CA_STATE). One extra probe exists to connect the clock signal to the channel.

Hook up the Logic Analyzer as described below:

Logic Analyzer Connection Scheme FPGA Board Port C

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16

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D E S C R I P T I O N C

A_I

ter (

13)

CA

_Ite

r (12

) C

A_I

ter (

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CA

_Ite

r (10

) C

A_I

ter (

9)

CA

_Ite

r (8)

C

A_I

ter (

7)

CA

_Ite

r (6)

C

A_I

ter (

5)

CA

_Ite

r (4)

C

A_I

ter (

3)

CA

_Ite

r (2)

C

A_I

ter (

1)

CA

_Ite

r (0)

C

A_C

LK

GN

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LA Channel 1 probe 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0 clk

g n d

Logic Analyzer Connection Scheme FPGA Board Port C

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D E S C R I P T I O N C

A_s

tate

(13)

C

A_s

tate

(12)

C

A_s

tate

(11)

C

A_s

tate

(10)

C

A_s

tate

(9)

CA

_sta

te (8

) C

A_s

tate

(7)

CA

_sta

te (6

) C

A_s

tate

(5)

CA

_sta

te (4

) C

A_s

tate

(3)

CA

_sta

te (2

) C

A_s

tate

(1)

CA

_sta

te (0

)

GN

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LA Channel 2 probe 15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

g n d

Make sure that the GND probe of both channels is connected to pin 1 of connector C. You will be provided with a special probe connector to share the ground pin between the two channels.

The following table describes the pin numbers of the header as though you were looking at the connector.

FPGA board Physical Connector Locations (connect all highlighted pins)

F P G A B O A R D 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

Port (A to F) 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

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Once the LA is hooked properly, perform experiments to answer the following questions. Set the initial state of the CA as 0100H = 00 0001 0000 0000. This will be the generation #0.

Questions

1. With the LA, capture the first twelve generations of the CA after the initial state and compare them with the manually calculated evolution of your pre-lab. In your design summary, include annotated LA printouts.

2. What is the state in the 512th generation? Set the trigger condition of the LA such that it captures the 512th iteration. Verify that the state is correct. In your design summary, include annotated LA printouts.

3. Identify the first generation at which the 14-cell CA shows the following state pattern: (D700)H. You may need to use an appropriate trigger condition and the search capabilities of the LA to locate and capture this state.

4. What is the maximum operating frequency of the CA cell and the 14-cell CA?

5. What is the critical path for both the CA cell and the 14-cell CA?

Demonstration You are required to demonstrate the complete design functioning in hardware with the CA evolving approximately once per 750 ms (~1.33 Hz).

Bonus (20%) You can do the following modifications to the CA in order to get up to 20% bonus:

Create a new entity for the CA. Add a synchronous reset that, when asserted, sets the initial 14-cell CA

generation to 00 0001 0000 0000. Map this reset to a push-button. The initial condition is no longer input through the switches.

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The user should be able to use the bank of 8 switches to set the rule for the CA.

Try rules 30 and 110. Why are rules 30, 90 and 110 particularly interesting?

Documentation You are required to submit a design summary for this lab. Consult the course website for details of what is required.

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