November 21, 2014

KAIST, Korea

Hiroshi Iwai

Frontier Research Center, Tokyo Institute of Technology

1

Future of Logic Nano CMOS

Technology

My background

Toshiba Corporation 26 years1973 - 1999

Tokyo Institute of Technology 16 years1999 – now (2014)

CMOS. Bipolar, BiCMOS

DRAM, SRAM, RF

Development/Manufacturing

Process/Device/Design/CAD/Reliability

Tokyo Institute of Technology (東京工業大学）

Suzukakedai Campus （鈴懸台校庭）

Interdisciplinary Gradate School of Science and Engineering

（大学院総合理工学研究科）

Department of Electronics and Applied Physics

（物理電子系統創造専攻）

Frontier Research Center （先端研究機構）

Department of Electronics and Applied Physics

（集積機能素子分野）

Research Project: Creation of Green Nanoelectronic Devices

（環境保全極微電子素子創生事業）

Suzukakedai Campus

Interdisciplinary

Gradate School

of Science and

Engineering

Frontier Research Center

Members of Iwai & Kakushima Laboratory November, 2014

SecretaryBachelor

Students

M. NishizawaA. Matsumoto

L. PuchengM. Okamoto X. H. Tan Y. Nakamura H. Hasegawa S. Munekiyo M. MotokiH. Imamura

Y. Lei J. Jin

T. Shoji

M. Yoon T. Ohashi T. Katou M. Sugiura H. Hori A. Miyawaki

K. Ohga K. MatsuuraT. Suzuki

T. Baba R. Fukui R. Miyazawa

Prof.

K. Natori

Prof.

H. Iwai

A. Prof.

K. Kakushima

Prof.

N. Sugii

Prof.

K. Tsutsui

Prof.

S. M. Sze

Prof.

A. Nishiyama

Prof.

Y. Kataoka

Prof.

H. Wakabayashi

Prof.

H. Ohashi

Master

Students

Researcher

T. Kawanago

Doctor

Students

M. Koyama S. YamaguchiW. Li C. J. Ning A. SasakiH. Yabuhara

6

研究風景

Research Project: Creation of Green Nanoelectronic Devices

（環境保全極微電子素子創生事業）

Information Technology

Renewable Energy

Power Saving Technology

Integrated Circuit Technology

Si nanowire-FET, High-k gate stack, silicide S/D

InGaAs/Ge-FET, T-FET, RRAM

CMOS Image sensor, X ray sensor

Photovoltaic devices: Si-nanowire, BaSi/FeSi

Si-IGBT, GaN, SiC Power devices

Brain: Integrated Circuits

Hands, Legs：Power device

Stomach：PV device

Ear, Eye：Sensor

Mouth：RF/Opto device

8

Various semiconductor devices

Brain is very important

Yearly budget 5.5 USD

NEDO (Founding Agency under Ministry of Economy)

0.25M USD

Industry

5.0M USD Si IGBT Project GaN Wafer Project

Si photovoltaic Project

Toshiba, Toshiba Material, Sumitomo Chemical

JST (Founding Agency under Ministry of Education)

0.16M USD

International Collaboration

Leti (France), NCTU (Taiwan), IIT-Bombay (India), CUHK (Hong Kong)

Exchange of students/faculty, Research collaboration

University

0.1 USD

High performance power devicesElectronic devices

for integrated-circuits

◎Interface controlling

◎High mobility

Solar cells

RRAM

◎High speed ◎Rewritable

BaSi2

◎High efficiency ◎Low cost

High performance & Low energy consumption

Si nanowires

b-FeSi2

InGaAs devices

MIPSW TiN/W

Kav ~ 8 Kav ~ 12 Kav ~ 16

Si 2nm2nm2nm

HK

MG200

150

100

50

0

Ele

ctr

on M

obili

ty [

cm

2/V

sec]

1.510.50

Eeff [MV/cm]

L / W = 10 / 10m

Nsub = 3 x 1016

cm-3

T = 300K

La-silicate (EOT=0.62nm)

Si

Si Devices

Ge devices

100 nm

Source

Drain

Gate

ナノワイヤ

Gate dielectric

Gate Voltage (V)

Cap

acit

ance

(µ

F/c

m2 )

Gate Voltage (V)

0.0

0.2

0.4

0.6

0.8

1.2

Cap

acit

ance

(µ

F/c

m2 )

PMA 370 oC (FG) PMA 370 oC (FG)

W/La2O3(10 nm)/InGaAs TiN/W/La2O3(10 nm)/InGaAs

5kHz

10kHz

100kHz

1MHz

5kHz

10kHz

100kHz

1MHz

5kHz

10kHz

100kHz

1MHz

5 kHz

10kHz

100kHz

1MHz

5 kHz

10kHz

100kHz

1MHz

5 kHz

10kHz

100kHz

1MHzforwardreverse

reverseforward

1.0

0.0

0.2

0.4

0.6

0.8

1.2

1.0

Nanowires

0

0.0002

0.0004

0.0006

0.0008

0.001

0.0012

0 0.5 1 1.5 2

Drain voltage (V)

Dra

in c

urr

ent

(A)

Vth+0.5V

Vth+1.0V

Vth+1.5V

Vg=Vth+2.0V

GaN

AlGaN

2DEG

Buffer

G

S D

Si(111) Substrate

dielectric

GaN

AlGaN

2DEG

Buffer

G

S D

Si(111) Substrate

dielectric

AlGaN/GaN

on Si wafer

(6 inch)

660V

Co

ns

um

er

us

eIn

fra

str

uctu

re

AlGaN/GaN

Diamond

◎High withstand voltage

◎Low loss

◎Long term reliable

10kV

-4

-3

-2

-1

0

-10-8-6-4-20

-4

-3

-2

-1

0

-10-8-6-4-200 -6-4 -10

VD (V)

-2 -8

VG =

-5 V

7 V

V

G=

2 V

I D(

A)

0

-1

-2

p-diamond

L = 12 m-3

-4

0

1

2

3

4

0 2 4 6 8 10

0

1

2

3

4

0 2 4 6 8 10

0 -6-4 -10

VD (V)

-2 -8

VG =

0 V

7 V V

G=

1 V

n-Si

L = 170 m

I D(

A)

0

-1

-2

-3

-4

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+02 1.E+03 1.E+04 1.E+05

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+02 1.E+03 1.E+04 1.E+05

100 100k10k

Blocking voltage (V)

1k

Sp

ecific

On

-Re

sis

tan

ce

Ro

nA

(-c

m2)

0.01

0.1

1

10

100

n-Si

p-diamond

Research Themes

Cu

rren

t D

ensi

ty (

mA

/cm

2)

Under AM1.5PowerDark

Voltage (V)

hnw = 22 nmwnw = 44 nmlnw = 1.5 µmFF = 0.47

Pow

er (

pW

)

-0.2 0 0.2 0.4 0.6-40

0

40

80

120

160

200

240

0

0.2

0.4

0.6

0.8

1

10nm

CeO2

W

NiSi2

界面SiO2

スイッチング回数

抵抗

()

0 100 200 300

108

107

106

105

104

103

102

set 4V

0V100msec

-4V

0V

100msecreset

Operation cycle

Resis

tan

ce

(

)

Green Nanoelectronics

11

(1970) 10 μm 8 μm 6 μm 4 μm 3 μm 2 μm 1.2 μm

0.8 μm 0.5 μm 0.35 μm 0.25 μm 180 nm 130 nm

90 nm 65 nm 45 nm 32 nm (28 nm ) 22 nm(2012)

Feature Size / Technology Node

From 1970 to 2013 (Last year)

18 generations

Line width: 1/450

Area: 1/200,000

43 years 1 generation

2.5 years

Line width: 1/1.43 = 0.70

Area: 1/2 = 0.5

14 nm (2014)

Toshiba Corporation

1970’s

1k SRAM

2 inch wafer

1974

64k DRAM

4 inch wafer

1980

64k DRAM

3 inch wafer

1979

100%

50

0

1974 Jan. 1975 Feb. 1975 Dec.

Wafer Yield

1k bit NMOS SRAM

2015 2017 2019 20252021 2023 20272013

10 7 5 1.83.5 2.5 1.314

32 25.3 20 1015.9 12.6 840

19 16 13.3 7.711.1 9.3 6.423

16.8 14.0 11.7 6.79.7 8.1 5.620.2(10) (8) (6) (5)(13)

0.73 0.67 0.61 0.470.56 0.51 0.430.80(0.60) (0.55) (0.50) (0.50)(0.60)

0.83 0.80 0.77 0.680.74 0.71 0.650.86(0.80) (0.70) (0.70) (0.65)(0.90)

6.1 5.1 4.3 2.53.6 3.0 2.07.4(6.0) (4.5) (3.8) (3.2)(6.0)

Year

Lg (nm)

Metal half pitch (HP) (nm)

(Lg for ITRS 2007)

Commercial name (nm)

Lg for low stand by power (nm)

Vdd (V) (Vdd (V) for ITRS 2007)

EOT (nm) (EOT (nm) for ITRS 2007)

TSi (nm) (TSi (nm) for ITRS 2007)

(4.5 in 2022)

(3.0 in 2022)

(0.50 in 2022)

(0.65 in 2022)

ITRS 2013 (Just published in April 2014)

Now, HP: X 0.80 / 2 years, Lg: X 0.83 / 2 years

Thus, now more generations and more years until reaching limit

Before, HP: X 0.70 / 2 years, Lg: X 0.70 / 2 years

15

ITRS 2013 (Just published in April 2014)

Lg (nm)

Metal half pitch (nm)

Commercial name (nm)

Vdd (V)

EOT (nm)

TSi (nm)

X 0.70 / 2 years

X 0.80 / 2 years

X 0.83 / 2 years

X 0.96 / 2 years

X 0.91 / 2 years

X 0.84 / 2 years

Only the commercial names decreases X0.7/ 2 years

Year 2027

1.3 (nm)

8 (nm)

5.6 (nm)

0.43 (nm)

0.65 (V)

2.0 (nm)

Year 2013

14 (nm)

40 (nm)

20.2 (nm)

0.80 (nm)

0.86 (V)

7.4 (nm)

Difference between the commercial name and

physical parameters becomes larger

1.3 nm technology!

but HP = 8nm

Lg = 5.6 nm

Recently, companies become not to disclose Lg values at conferences

16

More Moore to More More Moore

65nm 45nm 32nm

Technology node

M. Bohr, pp.1, IEDM2011 (Intel)

P. Packan, pp.659, IEDM2009 (Intel)

C. Auth et al., pp.131, VLSI2012 (Intel)

T. B. Hook, pp.115, IEDM2011 (IBM)

S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)

Lg 35nm Lg 30nm

Main stream

(Fin,Tri, Nanowire)

22nm14nm 10nm, 7nm, 5nm, 3.5nm

Alternative

Alternative (III-V/Ge)

Channel FinFET

Emerging

Devices

Tri-Gate

Now Future

Si channel

Si

Others

(FDSOI)

Planar

Si is still main stream for future !! FD: Fully Depleted

17

-gate Si Nanowire (TIT)S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)

19 nm

12 nm

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

10-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urr

en

t (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

10-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urr

en

t (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

0 0.5 1 1.5 2ION (mA/m)

Lg=65nm

0 0.5 1 1.5 2ION (mA/m)

Lg=65nm

Lg=65nm

Poly-Si

SiO2

SiNSiN

SiO2

NW

・Conventional CMOS process

・High drive current

(1.32 mA/m @ IOFF=117 nA/m)

・DIBL of 62mV/V and SS of 70mV/dec

for nFET18

High-k gate dielectrics

Continued research

and development

SiO2 IL (Interfacial Layer)

is used at Si interface to

realize good mobility

Technology for direct contact of

high-k and Si is necessary

Remote SiO2-IL

scavenging

HfO2 (IBM)

EOT=0.52 nm

Si

La-silicate

MG

Direct contact with La-silicate (Tokyo.Tech)

T. Ando, et al., p.423, IEDM2009, (IBM)

T. Kawanago, et al., T-ED, vol. 59, no.

2, p. 269, 2012 (Tokyo Tech.)

K. Mistry, et al., p.247, IEDM 2007, (Intel)

TiN

HfO2

Si

SiO2

EOT=0.9nm

HfO2/SiO2

(IBM)

T.C. Chen, et al., p.8, VLSI 2009, (IBM)

Hf-based oxides

45nm

EOT:1nm

32nm

EOT:0.95nm

22nm

EOT:0.9nm

10nm, 7nm, 5nm, 3.5nm,

K. Kakushima, et al., p.8, IWDTF 2008,

(Tokyo Tech.)

EOT=0.37nm EOT=0.40nm EOT=0.48nm

0.48 → 0.37nm Increase of Id at 30%

14nm

EOT:0.?nm

19

Cluster Chambers for HKMG Gate Stack

Flash Lamp

Anneal

EB Deposition: HK

Sputter: MG

ALD: HK

Robot

RTA

Entrance

20

La-Silicate Reaction at La2O3/Si

La2O3

La-silicate

W

500 oC, 30 min

1 nm

k=8~14

k=23

1837184018431846

Binding energy (eV)

Inte

nsit

y (

a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC

1837184018431846

Binding energy (eV)

Inte

nsit

y (

a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC

La2O3 + Si + nO2

→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.

La2O3 can achieve direct contact of high-k/Si

XPS Si1s spectraTEM image

Direct contact high-k/Si is possible

21

0 0.2 0.4 0.6 0.8 1.0

Drain Voltage (V)

0.2

0.4

0.6

0.8

1.0

Dra

in C

urr

en

t (m

A)

Vg= 0.4V

Vg= 0.6V

Vg= 0.8V

Vg= 1.0V

Vg= 0.2V

Vg= 0 V

L/W = 5/20m

T = 300K

Nsub = 3×1016cm-3

0

20

40

60

80

100

120

140

0 0.5 1 1.5 2 2.5

EOT = 0.40nm

L/W = 5/20m

T = 300K

Nsub = 3×1016cm-3

Eeff [MV/cm]

Ele

ctr

on

Mo

bilit

y [

cm

2/V

sec]

EOT=0.40nm

Our Work at TIT: High-k

22

Our result at TIT

23

4. Gate leakage current

Probably OK using high-k, until EOT=0.4 nm

See Appendix 2

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

0.3 0.4 0.5 0.6 0.7 0.8

ITRS requirement

Jg

at 1

V (

A/c

m2)

EOT (nm)

Gate Leakage current

H. Iwai, SBMicro 2013

La silicate

Gate dielectrics

Thank you very much

for your attention