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Future of Nano-CMOS Technology

June 4, 2007

Tokyo Institute of Technology, JapanHiroshi IWAI

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• Electronics is theMost important invention in the 20th century

• Electronics: Electronic Circuits or IC• Electronic Circuits in 100 years

Vacuum tube ULSILast year was 100 year anniversary

1906

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1900 1950 1960 1970 2000

VacuumTube

Transistor IC LSI ULSI

10 cm cm mm 10 µm 100 nm

In 100 years, the feature size reduced by one million times.We have never experienced such a tremendous reduction in human history.

10-1m 10-2m 10-3m 10-5m 10-7m

Downsizing of the components has been the driving force for circuit evolution

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Downsizing1. Reduce Capacitance

Reduce switching time of MOSFETsReduce power consumption

2. Increase number of TransistorsIncrease functionalityParallel processing

Increase circuit operation speed

Thus, downsizing of Si devices is the most important and critical issue.

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Nano-CMOS:

What would be the downsizing limit?

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Late 1970’s 1µm: SCEEarly 1980’s 0.5µm: S/D resistanceEarly 1980’s 0.25µm: Direct-tunneling of gate SiO2

Late 1980’s 0.1µm: ‘0.1µm brick wall’(various)

2000 50nm: ‘Red brick wall’ (various)

2000 10nm: Fundamental?

Period Expected Cause limit(size)

Many people wanted to say about the limit. Past predictions were not correct!!

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Historically, many predictions of the limit of downsizing.VLSI text book written 1979 predict that 0.25 micro-meter would be the limit because of direct-tunneling current through the very thin-gate oxide.

8Qi Xinag, ECS 2004, AMD

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Gate Oxd

Channel

Electronwavelength

10 nm

Channel length?Downsizing limit?

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5 nm gate length CMOS

H. Wakabayashi et.al, NEC

IEDM, 2003

Length of 18 Si atoms

Is a Real Nano Device!!

5 nm

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Gate Oxd

Channel

Electronwavelength

10 nm

Tunnelingdistance

3 nm

Atomdistance

0.3 nm

Channel lengthGate oxide thickness

Downsizing limit!

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Electronwavelength

10 nm

Tunnelingdistance

3 nm

Atomdistance

0.3 nm

MOSFET operation

Lg = 2 ~ 1.5 nm?

But, no one knows future!

Prediction now!

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Electronwavelength

10 nm

Tunnelingdistance

3 nm

Atomdistance

0.3 nm

Prediction at present

Practical limitbecause of off-leakagebetween S and D?

Lg = 5 nm?

MOSFET operation

Lg = 2 ~ 1.5 nm?

But, no one knows future!

Gate length Prediction now!

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Ultimate limitation

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050

MPU LgJunction depthGate oxide thickness

Direct-tunneling

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(µm

), V

olta

ge(V

)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

However,Gate oxide thickness2 orders magnitude smallerClose to limitation!!

Lg: Gate length downsizing will continue to another 10-15 years

15By Robert Chau, IWGI 2003

0.8 nm Gate Oxide Thickness MOSFETs operates!!

0.8 nm: Distance of 3 Si atoms!!

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There is a solution!To use high-k dielectrics

Thin gate SiO2Thick gate high-k dielectrics

Almost the same electric characteristics

However, very difficult and big challenge!Remember MOSFET had not been realized without Si/SiO2!

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New material research will give us many future possibilities and the most importantfor Nano-CMOS!

New material for Metal gate electrodeNew material for High-k gate dielectric

New materialFor Metal S/D

New channel material

Not only for high-k!

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New materials are important for Not only nano-CMOS logic MOSFETs,But also for new memories!

Limit of high-density memories, such as flash, DRAM will be solved by new materials.Flash: floating gate gate insulator charge trap

like SONOS, MNOSDRAM New high-k insulator

New memory PRAM, RRAMFlash DRAM PRAM, RRAM

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PMOS 1kbit DRAM Toshiba(1974)

NMOS 1k bit SRAM Toshiba (1974)

1970s: 10 years after single MOSFETs,

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magnification

6 µm NMOS LSI in 1974

5. S/D

Layers

3. Gate oxide

1. Si substrate2. Field oxide

4. Poly Si

6. Interlayer7. Aluminum 8. Passivation

Si substrate

Field SiO2

ILD (InterlayerDielectrics)

Al interconnects

Passivation (PSG)

(SiO2 + BPSG)Si substrate

Field SiO2

ILD (InterlayerDielectrics)

Al interconnects

Passivation (PSG)

(SiO2 + BPSG)

Poly Si gate electrode

Gate SiO2

Source / Drain

Poly Si gate electrode

Gate SiO2

Source / Drain

Materials1. Si

3. BPSG

5. PSG4. Al

2. SiO2

Atoms

1. Si

4. B

(H, N, Cl)

2. O

3. P

5. Al

21Y. Nishi, Si Nano Workshop, 2006,

(S. Sze, Based on invited talk at Stanford Univ., Aug. 1999)

Al

SiO2

Si

Poly Si

Si3N4

Air

HSQ

Polymer

TiN

TaN

Cu

Low-kdielectrics

Metals

La2O3

Ta2O5

HfO2

ZrO2

ZrSixOy

RuO2

Pt

IrO2

Y1

PZT

BST

High-kdielectrics

Electrode materials

Ferroelectrics

PtSi2WSi2CoSi2TiSi2MoSi2TaSi2

Silicides

W

1970 1980 1990 20001950 2010

Al

SiO2

Si

Ge SemiconductorsIII-V

Just examples!Many other candidatesNew materials

NiSi silicide

SiGe Semiconductor

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32 Gb and 16Gb NAND, SAMSUNG

Now: After 45 Years from the 1st single MOSFETs

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Capacity Node Announcement Product

512Mbit 120nm 2000 2001

1Gbit 100nm 2001 2002

2Gbit 90nm 2002 2003

4Gbit 70nm 2003 2004

8Gbit 60nm 2004 2005

16Gbit 50nm 2005 2006

32Gbit 40nm 2006 2007?

256Gbit 20nm 2010 2011?

Even Tbit is possible!

Samsung’s NAND flash trend

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Already 32 Gbit: larger than that of world populationcomparable for the numbers of neuronsin human brain

Samsung announced 256 Gbit will be produced in 2010.Only 4 years from now.256Gbit: larger than those of # of stars in galaxies

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What will be the roadmap after 2020?

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Moore’s Law & More

More Moore and More than Moore

http://strj-jeita.elisasp.net/pdf_ws_2005nendo/9A_WS2005IRC_Ishiuchi.pdf

ITRS 2005 EditionQuestion what is the other side of the cloud?

27http://www.rcns.hiroshima-u.ac.jp/21coe/pdf/5th_WS/2-4-2_Hiramoto.pdf

Question: Will CMOS end in 2020?

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New Concept for Roadmap

Evolution of Extended CMOS

Existing technologies

New technologies

Extended C

MO

S

Year

Beyond CMOS

More Than Moore Elements

More Than Moore

Beyond CMOS Elements

More Moore Top-downBottom-up

Evolution of Extended CMOS Continues!!

Existing technologies

New technologies

Extended C

MO

S

Year

Beyond CMOS

More Than Moore Elements

More Than Moore

Beyond CMOS Elements

More Moore Top-downBottom-up

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45

What comesNext?

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Scaling proceeds

Size(Gate length etc）

Saturation of Downsizing

2020？

5 nm？

New Materials, New Process, New Structure（Logic, Memory)

Hybrid integration of different functional Chip Increase of SOC functionality

3D integration of memory cell3D integration of logic devices

Low cost for LSI processRevolution for ＣＲ，Equipment, Wafer

Miniaturization of Interconnects on ＰＣＢ(Printed Circuit Board)

Introduction of algorithmof bio-systemBrain of insects, human

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After 2020

There is no decrease in gate length around at 5 nm due to subthreshold leakage.

It is not useful to reduce the gate length any more for increasing the drain current, because the conduction is already semi-ballistic.

What is important for keeping Moore Law, then?

Increase drain current drive under low drain voltagein order to reduce the power consumption.

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Selection of MOSFET structureFor suppression of Ioff, the structure will be Fin-FET type

High-conduction at low voltage１．1D conduction Nano-wire, Nano-tube FET２．Increase number of quantum channel

Band engineering、CNT( Carbon Nano-tube Tnansistor)３．Increase the number of wire or tube

3D integration of wires and tubes

High-integration, low cost production, no-small-geometry lithography CNT

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1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)

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2015 2020 2025 2030 20352015 2020 2025 2030 2035

Cloud

Beyond the horizon

2010

?More Moore

ITRS Beyond CMOS

? ? ?? ? ? More Moore ??

ITRS

PJT(2007~2012)

2007

Horizon

Extended CMOS: More Moore + CMOS logic

Ribbon

Tube

Extended CMOS

Si Fin, Tri-gate

Si Nano wire

III-V及びGe Nano wire

製品段階

開発段階

研究段階

Production

Research

Development

Natural direction of downsizing

Diameter = 2nm

Si Channel

Nanowire

Tube, Ribbon

Selection

-

Problem：Mechanical Stress, Roughness

1D - High conduction

More perfect crystal

CNT

Graphene

Diameter = 10nm Problem：Hiigh-k gate oxides, etching of III-V wire

Further higher conductionBy multi quantum channel Selection

Our new roadmap

High conductionBy 1D conduction

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2015 2020 2025 2030 20352015 2020 2025 2030 2035

我々が提案する今後30年のExtended CMOSの開発のロードマップ

2010

経産ナノエレPJT(2007~2012)

2007

Ribbon

Tube

Si Nano wire

III-V及びGeNano wire

製品段階

開発段階

研究段階

製品段階

開発段階

研究段階

製品段階

開発段階

研究段階

CNT

Graphene

径の制御、断面形状制御

FETの構造・組み立て検討

Plasma dopingのS/D形成への導入歪の制御、バリシティシティの制御

High-k/Metal gateの導入Metal S/Dの導入

歪の制御、バリシティシティの制御

High-k材料の選択基板の結晶性

ワイヤのエッチング技術

MESFETゲート電極の選択

CNTの水平成長技術

CNTの欠陥制御 CNTカイラリティ制御ゲート絶縁膜の選択 CNT表面の安定化

歪の制御、バリシティシティの制御

バンド構造の制御（半導体化）

表面の安定化ゲート絶縁膜の選択

ソース・ドレインメタルの選択

ソース・ドレインメタルの選択

歪の制御、バリシティシティの制御

しきい値の制御

NMOSの高性能化

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1D conduction per one quantum channel:G = 2e2/h = 80 µS/wire or tuberegardless of gate length and channel material

But this value has not been obtained yet,due to reflection of carriers from drain, surface roughness

and mechanical stress

Abortion to drain

Optical PhononBallistic scattering

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SiSiGe

SiSiGe

...

Selective EtchingDry EtchingSi/SiGe multistacked wafer

H2 Annealing

SiSiGeSi

(c) Selective Etching

(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer

(d) H2 Annealing

(e) Gate Oxide (f) Gate, S/D Formation

SiSiGeSi

(c) Selective Etching

(b) Dry Etching(a) Si/SiGe/Siepitaxial wafer

(d) H2 Annealing

(e) Gate Oxide (f) Gate, S/D Formation

Increase the number of wires

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Lateral growth of CNT

Nano dot catalyst

( )

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Thank you for your attention!