Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials, Yokohama, 1994, pp' 334-336

Dynamic Characteristics of Inverter Circuits Using Single Electron Transistors

Nobuyuki Yoshikawa, Hiroshi Ishibashi and Masanori Sugahara

Faculty of Engineering, Yokohama National UniversityTokiwadai 156, Hodo9aya, Yokohama,240, Japan

We have investigated basic characteristics of capacitively and resistively coupled SET inverters as

a digitat logic circuit. Input-output transfer characteristics and dynamic characteristics have be,en

calculated based on the semi-classical model by the Monte Carlo method. Although a voltage gainlarger than unity is found even in a cascade connection, they reveal some disadvantages such as

small voltage gain, poor input-oulput separation, small logic level difference, instability ofoperating point and oscillational output voltages. The switching delay time is estimated to be ofthe order of l00RC, where R and C is a resistance and a capacitance of a tunnlel junctionrespectively.

l.IntroductionRecently, single electron digital circuits are

attracting many researchers attentions because of ttreirpotential perforrnance with very low power consumptionand high switching speed. Basic operating mechanismof these circuits are based on the single electron

tunneling (SET) effectl) in very small tunnel junctions.There have been proposed many types of SET devices,

such as a capacitively coupled transistorl), a resistivelycoupled transistorl), a complementary logic circuit2), aturnstile device3), and a pump device4), etc., and theirbasic characteristics have been verified experimentally.In this report, we represent numerical calculationsconcerning basic characteristics of the capacitivelycoupled (C-) and the resistively coupled (R-) SETinverters which are loaded by resistance, and examinedtheir transfer characteristics and dynamic properties as adigital logic circuit.

2.Basic Cell and Simulation MethodFigure 1 shows basic cells of C-SET and R-SET

inverters. The C-SET inverter (Fig. 1(a)) consists of a

C-SET transistor (which is composed of two small

tunnel junctions with capacitance Ct, C2 and resistance

Rl, R2, and an input capacitance G'), a load resistance

Rq and a output capacitance Cout, where Gut includes aparasitic capacitance of the electrode B and an inputcapacitance of a next stage inverter. The basic cell isdriven by a voltage source H-. The R-SET inverter (Fig.1(b)) is a revised version of the C-SET inverter, where

Gn and Gur aro replaced by a input resistance Rin and an

output resistance Rout, respectively. In this case, a

output capacitance Cout is added parallel to Rour as aparasitic capacitance of a elecuode B.

PA-2-1

All calculations in this study are based on the

semi-classical modell), where electron tunneling eventsin individual nrnnel junctions are stochastic process and

determined by free energy difference benveen before and

after ttre tunneling event. Using a junction voltage V and

a temperature T, an electron tunneling rate per unit timeis given by the following equation

f(y)=+ leV-E"ezR, 1- exP[(+ eV + E') | lcT] , (1)

where Rt is a resistance of the tunnel junction and

Ec=eZ\CE is a charging energy nequired in the single

electron tunneling. Cl is a total capacitance including thejunction capacitance and a parasitic capacitance of the

external circuits connected in parallel with the junction.Considering that a total charge in the isolated elecrode

changes only by an elementary charge e in each

tunneling evont, we can calculate the time evolution ofthe electrode charge and hence the junction voltage bydetermining whether an elecEon tunnels or not during a

(a) O)Fig. 1 The inverter circuits using (a) capacitively and (b)

resistively coupled SET transistors.

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short time period according to the electron tunneling rateeq.(11s). In calculations, we ignore the co-tunnelingprocess and the quantum fluctuation which have to beconsidered when the resistance of the tunnel junction isnot so large comparing with the critical resistance Rc.

3.Static Characteristics of the SET InvertersFigure 2 shows voltage transfer characteristics of

the c-sET and the R-SET inverters for various values ofthe bias voltage Vv at very low temperatue kTl(ezl2Cr)=0.001 where the thermal fluctuation can be neglected.As can be seen in the figure, the both inverters havevoltage gain larger than unity atVi"/(e/ZCr)=0.16 for ttreC-SET inverrer and at Vi"/(e/ZCr)=0.55 for the R-SETinverter. Although the R-sET inverter has larger voltagegain than the C-SET inverter, an output voltagedifference AVout which is a difference between logiclevel "1" and "0" is very small in the R-SET inverter.

By the calculation of the Vr- dependence of ttremaximum voltage gain Cr-ax and AVout, we find thatGnax and AVour are optimized when Vr;0.g-0 .9Vtt,where vr.t is the bias voltage of the inverrers which givesthe threshold whether the sET transistor is in aconduction state or in a coulomb blockade stare.Throughout the following calculations, we use thecondition Vt;O.9Vt-t.

Figure 3 shows the dependence of Gnax of the C-SET inverter on the input capacitance Gn and the outputcapacitance coul one can see that cnnax increases withdecreasing G,'t and increasing Gn, in the range 2-6. Anelementary estimation about the voltage gain givesGnax=-G"lCt, which is slightly larger than thesimulation results. The discrepancy is arising from thenon ideal current biasing. Smalt Gnax value atcou/ct-2and Gn/Ct=2O is due to the thermal fluctuation which isnot negligible when G" is large.

In Fig. 4(a) is shown the dependence of Cnnax ofthe R-sET inverter on the output resistance Rout. It isseen from the figure that the gain of the inverter goesdown with decreasing Rout (or increasing output load).The reduction of the gain will be serious problems indesigning the logic circuits using this injection rypedevice, because it restricts fan-out number. Figure 4(-b)shows the dependence of Gna* on the input resistanceRin. There is a maximum crmax in the Clnux-Rin relation.The decrease in crmax for larger Rin is due to ttrereduction of the rate of charge injection through Rin tothe center electrode (electrode A in Fig. l(b)) whichtriggers and breaks the coulomb blockade srate of thelower tunnel junction. on the other hand, too small RinexEacts excess charges on the electrode A, resulting insuppression of the space-correlated tunneling betweenthe two tunnel junctions.

(b)iii A.iE tir-"--"

::d-. i7 i U-.:*---i-;:.=-

VL/(e/2Cr )-1.4

- - - vL/(er2cl )-1 .8 i i-'

-vL/(el2c)-2.2

" ft -R-Rr-/30-&130-Rdr/30'"""V1/(8l2Cr)-2.6 Cily's-q-q---..--. vl/(€/2cr )-3.0 (€?2C1 ykT-1 0oo

i

ool; o.2

!

0.1

?o(\l!0'65J

0.3

1.2v,n/@laci

Fig. 2 The voltage transfer characteristics of (a) the C-SETinverter and O) ttre R-SET inverter for various values

of the bias voltage Vr".

R1=&=RL/10

(e2l2c1)/kT=1ooo

t a*lroa' 1oo

Fig. 3 The @ndence of the maximum voltage gain G-.*of the C-SET inverter on the input capacitance Cin

and on the output capacitance Cout.

We also calculated the dependence of theoperation point with the maximum voltage gain onparameters of external circuit elements. The results showthat the operating point varies considerably depending onGn and Cout in the case of C-SET inverter, whereas theR-SET inverter exhibits only slight change.

4.Dynamic Characteristics of the SET InvertersFigure 5 shows switching waveforms of the

input and output node voltages of the C-SET and the R-sET inverters. It can be seen in the figure that the oueurwaveforms are oscillating function of time connected

-5.0

-4.0tEo -g.o

-1.0

0.0

Y5t(e l?Ql

335

(a)

R1 =R2 =RL / 30 = Rir /30Cout /5 =Cr =Q(e l2q )/kT= 1000

40

fuut /Rr

(b) R1=R2=Rr-/30=Rir/30Csa/5= Cr =Q(ezlZea)/kT=1000

'- o 20 40 60 80 100Rir /R r

Fig. 4 The dependence of the maximum voltage gain Gmax

of the R-SET inverter (a) on the ouput resistanceRoutand (b) on the input resisEDce Rin.

with the stochastic tunneling events of single elecffons.By taking an ensemble average of the output waveforrn,we can derive a delay time of the inverters. In the case ofthe C-SET inverter, a pull-up time constant is estimated

to be trcrJ-Rr0out which is a re-charging time of thecharge on Gut through Rr4 and a pull-down time

constant tcD-RdGut where Ra is a dynamic resistance ofthe SET transistor which depends on the input voltageVin. For the R-SET inverter, a pull-up time constant isrepresented as tRU-(RUlRout)Cout. A pull-down delayTRD=TRDI*TRDr consists of two pa_rt: one is turn-ondelay TRDr-RinC2 and the other is rising time constant

TRDr-RaCout. Using the circuit parameters in Fig.5, wedetermine a switching time ts which is a time when ttreoulput voltage variation reaches gOVo of the logic leveldifference AVout. For the C-SET inverter, we obtainTscu-25ORrCr and TscD-lOORrCr, and for the R-SETinverter TsRU-200R r Cr and Gno-150R r Cr.

As noted above, the output voltage is veryoscillational, which seems to cause some problems instability of the logic operation. A larger outpur capacit-ance can stabilize the voltage oscillation, but it lowers thevoltage gain and reduces the operating speed. Thecalculation on transfer characteristics of two cascadedSET invefters indicates that voltage gains larger thanunity are obtained in the both inverters, but that input-output separation of the voltage signal is not enough dueto the low voltage gain in the case of C-SET inverter.

& =fie=RL/10 (ezl2Ql RT=lI =Q =C;n/5=Cour/10 Vl/(e/2Cr)= 0.3

\h

Vort

(a)

-0.50 1000 1500

t /RrCr

Rt=R2=B!EO=Ri,, 130=Ror1/OO (ezl2CllkT =,1 C

q4246u1/5 V/(el2Q)=2.0

(b)

_o.gr ..._r-_. . I I .. ^ too s@ looo 15oo zoo6

t /R1C1

Fig. 5 Swirching waveforms of the input and outpur node voltagesof (a) the C-SET inverrer and (b) the R-SET inverrer.

5.ConclusionsWe made simulation study on basic character-

istics of the capacitively and the resistively coupled SETinverters in digital logic operation. The calculation ofinput-output transfer characteristics and dynamiccharacteristics is made using the semi-classical model bythe Monte Carlo method. Although a voltage gain largerthan unity is found even in a cascade connection, somedisadvantages are revealed such as small voltage gain,poor input-output separation, small logic leveldifference, instability of operating point depending onthe external circuit parameters, and oscillational outputvoltages, are revealed.

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5) K. Mullen, E. Ben-Jacob, R. C. Jaklevic and,Z.Schuss, Phys. Rev. 837 (1988) 98.

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