gheorghe m. Ştefan - 2014 -
TRANSCRIPT
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Gheorghe M. Ştefan http://arh.pub.ro/gstefan/
- 2014 -
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Tristate buffers enable = 0, out = hi-z
enable = 1, out = in’
Interconnecting two systems:
en1=1, en2=0 : System 1 sends, System 2 receives
en1=0, en2=1 : System 2 sends, System 1 receives
en1=0, en2=0 : System 1 receives, System 2 receives
en1=1, en2=1 : forbidden
2014 Digital Integrated Circuits - week three 2
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Inverting & non-inverting tristate buffer
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Transmission gate
en = 1 => out = in
en = 0 => out = hi-z
Main limitation: RON is serially connected to CL
Main advantage: no connection to VDD and ground
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Elementary inverting multiplexor
Low power, small area, but low speed
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Memory circuits
Data latches revisited
Delay flip-flop (DF-F)
Reset-able DF-F
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Data latches
0 : active level of CK 1 : active level of CK
CK = 1 : loop closed CK = 1 : transparent CK = 0 : transparent CK = 0 : loop closed
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The master-slave structure of DF-F
What is the active edge of clock?How can the active edge be changed?
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master-latch is transparent, slave-latch latches
master-latch latches, slave-latch is transparent
the overall structure is anytime non-transparent
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Reset-able DF-F
The free inverter is substituted by an appropriate gate
Both, master-latch and slave–latch must be “forced” asynchronously
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Growing – Speeding - Featuring
Size vs. Complexity Time restrictions in digital systems
Growing the size by composition Speeding by pipelining Featuring by closing new loops The taxonomy of digital systems
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Size vs. ComplexitySize: the dimension of physical resources –
Sdigital_system
Gate size: the number of CMOS pairsArea size: silicon areaDepth: number of logic levels
Complexity (algorithmic complexity): ~ the dimension of the shortest description Cdigital_system
Simple circuit: Csimple_system << Ssimple_system
Complex circuit: Ccomplex_system ~ Scomplex_system
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Size vs. Complexity (examples)
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Complex circuit:
Simple circuit:
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Time restrictions in digital systems
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tin_reg : minimum input arrival time before clocktreg_reg : minimum period of clock = Tclock_min = 1/fclock_max
tin_out : maximum combinational delay pathtreg_out : maximum required time after clock
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Example
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tin_reg = tp(adder) + tp (selector) + tsu(register) = (550+85+35)ps
treg_reg = Tclock_min = 1/fmax= tp(register) + tp(adder) + tp(selector) + tsu(register) = (150+550+85+35)ps fmax= 1.21 GHz
tin_out = tp(comparator) = 300ps
treg_out = tp(register) + tp(comparator) = (150+300)ps
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Pipelined connections
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Blocking – Non-Blocking assignment
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Blocking assignment: “=“ for combinational circuitsNon-blocking assignment: “<=“ for edge triggered transitions
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Fully buffered connection
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tin_reg = tsu(regsiter)
treg_reg = tp(regsiter) + tp(comb) + tsu(regsiter) = 1/fclock_max
tin_out : not defined
treg_out = tp(regsiter)
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Growing by composing
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f(x) = g(h1(x), h2(x), … hm(x) )
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Serial & Parallel Composition
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Example: inner product
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Example: inner product (cont.)
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Speeding by pipeliningWith no pipeline:fclock = 1/(treg+tf+tsu) =
1/(treg+th_1+tg+tsu)
Latency: λ = 2
With pipeline:fclock =
1/(treg+ max(th_1+tg)+tsu)
Latency: λ = 3
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Example: pipelined inner product
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tp(mult) = 2 nstp(add) = 1nstsu(reg) = 20pstp(reg) = 50ps
No pipeline:fck = 0.325 GHz
With pipeline:fck = 0.483 GHz
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Home work 3 Problem 1: design at the gate level an asynchronously reset-
able (RST) and preset-able (SET) DF-F.
Problem 2: design a synchronously reset-able DF-F.
Problem 3: design the test module for the pipelined version of the inner product circuit represented in Figure 3.6 and described in Example 3.7. Use it to simulate the inner product circuit.
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