goepel presentation for electronics next 2010

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Delhi, 24.-26.02.2010GOEPEL electronics ASIA Limited 2010

2ElectronicsNext 2010New Delhi, India

20 years of standard IEEE1149.1

IntroductionRalph DresslerApplication EngineerR&D Manager JTAG / Boundary Scan

GOEPEL electronics Asia Ltd.高普電子亞洲有限公司

Unit 223A, 2/F, Core Building 2HONG KONG SCIENCE PARK

Shatin, N.T., Hong Kong

Mobil: +852-6418-9562Fax: +852-2810-4494

[email protected]



Overview

• Introduction• Electrical Test of PCBA - the test problem• Limitation of Functional Test• Limitation of In Circuit Test• Idea of JTAG / Boundary Scan• 20 years IEEE1149.1• JTAG / Boundary Scan Test Solutions in

Practice• Conclusion



Electrical test of PCBA (PCBA - printed circuit board assembly)

v

v

combinatorial logic (and, or, nand, ...)

sequential logic (flip flop)

I1

I2

I3

Ix

x number of inputs

y number of flip flops

FF1

FF2

FFy



Electrical test of PCBA - the test problem

v

I1

I2

I3

Ix

x number of inputs

y number of flip flops

FF1

FF2

FFy

V = 2V number of test vectors

(x+y)V = 2 = 65536

(8+8)



Test time (Limitation of Functional Test)• Calculation if we apply every 1 micro second a new test vector

x y V (Number of test vectors) time

5 5 over 1.000 about 1 ms

10 10 over 1.000.000 about 1 sec

15 15 over 1.000.000.000 about 18 min

20 20 over 1.000.000.000.000 about 2 years

25 25 over 1.000.000.000.000.000 about 2.000 years

How complex is your board?



Partitioning

v

I1

I2

I3

Ix

FF1

FF2

FFy

➡Fixture for functional test➡Long Test development time➡Detailed knowledge of the board is needed

additional test access points

Expansive

Test!



In Circuit Test (ICT)

v

I1

I2

I3

Ix

FF1

FF2

FFy

➡Bed of nails

test point on every net



Limitation of In-Circuit-Test (ICT)

?➡Placing of the test points➡Expansive Fixture➡No models for highly integrated devices

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ElectronicsNext 2010New Delhi, India


Idea of JTAG / Boundary Scan

Replace the physical nails by silicon nails (Boundary Scan Cells)

Physical nailsof the fixture

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Boundary Scan Devices

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Normal Function after Power UP

13



Boundary Scan Test Mode (EXTEST)

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• 1985: Joint European Test Action Group (JETAG)• 1986: Joint Test Action Group• 1990 (February): The IEEE Testability Bus Standard

Commitee accepted the proposal of the JTAG group:

• IEEE 1149.1 Standard Test Access Board and Boundary-Scan Architecture was approved

• 1999: IEEE 1149.4 Standard for a Mixed-Signal Test Bus (Analog)

• 2003: IEEE 1149.6 Standard for Boundary-Scan Testing of Advanced Digital Networks (AC Coupled)

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JTAG / Boundary Scan (IEEE 1149.1)

• JTAG/Boundary Scan is possibly the most resourceful test access technique around.

Similar to In-Circuit Test (ICT), but without physical bed of-nail adapters, it detects structural fault locations by utilizing thousands of test points - with only four test bus lines.

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Typically devices on a digital board

Boundary Scan

RAMFLASH

Logic Cluster

Interfaces

Testbus Interface

DisplayClock LEDs

Power Supply

Transparent Logic

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Access by JTAG / Boundary Scan

91

Testbus Interface Boundary Scan Power Supply

Logic Cluster

RAMFLASH

Interfaces

DisplayClock LEDs

Transparent Logic

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Scan Booster/USB

Scan Booster/PCI

Scan Booster/PEC

Scan Booster/USB-FXT

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Testcoverage

• Power OK?

PLD

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK

• Infrastructure test

• Interconnection test

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Testcoverage

• Power OK?

PLD

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK



• Memory test

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Testcoverage

• Power OK?

PLD

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK



• Memory test

• Flash test

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Testcoverage

• Power OK?

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK



• Memory test

• Flash test

• Flash programming

• PLD programming

PLD• Cluster test

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Testcoverage

• Power OK?

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK



• Memory test

• Flash test

• Flash programming

• PLD programming

PLD• Cluster test

• Interface test

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Extended JTAG / Boundary Scan

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK

PLD

CION

CION

A

D

RS232

IEEE1149.1

CION

TDI

TDI

TDI

TDO

TDO

TDO

Customer adapteror GÖPEL I/O module(s)

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Interface test (Interconnection test)

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK

PLD

CION

CION

A

D

RS232

IEEE1149.1

CION

TDI

TDI

TDI

TDO

TDO

TDO


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Interface test (Cluster test)

TDI

TDO

TDI

TDO

µP

UUT

POWER IEEE1149.1

RAM 1...4

FLASH 1...2

A

D

C

A

D

C

C (FLASH)

A

D

C (RAM)

CLK

DISPLAY(LED / LCD)

version?

CLUSTER

RS232

D

ACLK

PLD

CION

CION

A

D

RS232

IEEE1149.1

CION

TDI

TDI

TDI

TDO

TDO

TDO


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Boundary Scan Controller

SFX/USL 1149-X

SFX/PCI 1149-X

SFX/PCIe 1149-X

SFX/PXI 1149-X

SFX/ASL 1149-X

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SFX-TAP4/FXT

SFX-TAP7SFX-TAP2

SFX-TAP6

TAP Transceiver

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ANALOG I/ODIGITAL I/O

I/O Module

DIFFERENTIAL I/O

Bus Access Cables (BACs)

•RS232, RS422, RS485•10/100-Mbit-LAN•CAN, LIN•USB 2.0 Master/Slave•Bluetooth

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CION Module

FXT ModulePCIe

PCIDIMM

SO-DIMM

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33



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34



Get the total Coverage

• SCANFLEX I/O MODULE• CION MODULE• JULIET (JTAG Unlimited Tester)• Integration in AOI/AXI• Integration in Functional Tester• Integration in Flying Probe Tester• Integration in ICT Tester

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Conclusion

• JTAG / Boundary Scan is the key technology for testing of todays digital boards!

• To Get the total Coverage! you can• use Extended JTAG / Boundary Scan test solutions• use the JULIET tester• integrate in your existing test environment (like ICT,

Flying Probe, Functional test equipment)

• JTAG / Boundary Scan can be used in the whole life cycle of a product (development, production and service)

• JTAG / Boundary Scan is a cost effective test method!

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Thank you for your

attention!

goepel presentation for electronics next 2010

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