grid power quality analyis of 3-phase and 1-phase … · of 50hz and sort out related issues in...

GRID POWER QUALITY ANALYIS OF 3-PHASE

AND 1-PHASE SYSTEMS

A PROJECT REPORT

SUBMITTED IN PARTIAL FULFILMENT OF THE

REQUIREMENTS FOR THE DEGREE OF

Master of Engineering

IN

ELECTRICAL ENGINEERING

by

V SRAVAN

Department of Electrical Engineering

Indian Institute of Science

Bangalore – 560 012

June 2008

Acknowledgements

I express deep gratitude to Dr. Vinod John, Department of Electrical Engineering, for

providing me a chance to in work Power Electronic Group and for always being a

source of inspiration. I am deeply indebted to him for the invaluable guidance and

advice I have received from him throughout the work.

I wish to express my gratitude to Prof. V. Ramnarayanan, prof. V. T. Ranganathan,

Prof. P. S. Nagender Rao, Prof. D.Thukaram and Dr. G. Narayanan for their courses

and for their constant encouragement.

I acknowledge the MHRD, Govt. of India for the Financial support. I would like

to thank IISc administration for a nice accommodation and mess facility during my

memorable two years.

I thank Mrs. Silvi Jose for the support extended in procuring components. I also

extend my thanks to Mr D. M. Channe Gowda and his colleagues for their assistance

and cooperation.

I sincerely acknowledge the support of Siva Kumar, Siva Prasad, Debmalya Benerje,

Amit Jain, Kamalesh, Dipankar, Dinesh Gopinath and Anirban Goshal for their in-

valuable advice.

i

ii

Thanks to all IISc friends and members of Electrical Department including Suneel,

Bharath, Anand, Naresh, Dharmesh, Tripati, Rajkoti, Parikshit and Karupu Swamy

for giving me a nice company during the two years.

Finally, I express my gratitude to my family members for their moral support and

generosity.

Abstract

The aim of this project is to design and develop a power qualitymonitoring system for

1-phase, 3-phase (3-wire and 4-wire) power system operating at a nominal frequency

of 50Hz and sort out related issues in sensing, measurement,calculation of different

important electrical quantities, serial communication and displaying the monitoring

quantities.

The main objectives of the project are :

1. To acquire voltage and current signals from the grid.

2. To track the frequency of the acquired signals and calculate themagnitude,phase,

harmonics, total harmonic distortion,active power, reactive power and power

factor of voltage and current signals on a fast, low-cost Digital Signal Processor

(DSP).

3. Communicate to the PC via RS-232 and display it on the screen using Graphical

User Interface (GUI) built in Visual Basic (VB).

Today power quality monitoring has become an essential service for industrial and

commercial customers because the reliability, efficiency and liability of their devices

very much rely on the quality of the electric supply. Not only can amonitoring system

provide information about the quality of the power and the causes of power system

disturbances, but it can identify problem conditions throughout the system before

they cause equipment malfunctions,and even equipment failures.

iii

iv

Today most of the algorithms for controlling electrical systems are implemented in

DSP’s. These DSP’s are low cost low power and high performance processing ca-

pability and also have separate program and data memory. The memory and time

required for implementing power quality quantities is very less the additional com-

puting power and memory available is used for implementing the algorithms to con-

trol the system. The advantage of this system is we can have continuous monitoring

of the system without the need for additional devices. We can also program it to dis-

play an error message if there is a fault in the system.

The data acquired from calculation of electrical quantities in DSP, are transmitted to

Personal Computer (PC) via RS-232 cable and displayed on PC screen using GUI built

in VB.

Contents

Acknowledgements i

Abstract iii

1 Introduction 1

2 Measurement of electrical quantities 32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 Measurement of frequency and harmonic quantities . . . . . . . . . . . 3

2.2.1 Calculation of controller Gains . . . . . . . . . . . . . . . . . . . 52.2.2 Calculation of Harmonics . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Magnitude and Phase Calculations . . . . . . . . . . . . . . . . . . . . . 72.4 Real and Reactive Power Calculations . . . . . . . . . . . . . . . . . . . 8

2.4.1 Power Factor Calculation . . . . . . . . . . . . . . . . . . . . . . 9

3 Implementation and Results 103.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 MATLAB Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3 DSP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . 153.3.2 Implementation of PLL on DSP . . . . . . . . . . . . . . . . . . . 16

3.4 Hardware Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.4.1 Voltage sensing card . . . . . . . . . . . . . . . . . . . . . . . . . 203.4.2 Current sensing card . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Communication between DSP and PC and GUI 274.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.2 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . 27

4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.2.2 Synchronous Serial Communication . . . . . . . . . . . . . . . . 284.2.3 Asynchronous Serial Communication . . . . . . . . . . . . . . . 28

4.3 Serial Communication Interface (SCI) Module in DSP . . . . . . . . . . 294.3.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . 304.3.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

v

CONTENTS vi

4.3.3 Programmable Data Format . . . . . . . . . . . . . . . . . . . . . 324.3.4 Communications Modes . . . . . . . . . . . . . . . . . . . . . . 324.3.5 Multiprocessor Communication . . . . . . . . . . . . . . . . . . 334.3.6 Communication Format . . . . . . . . . . . . . . . . . . . . . . . 344.3.7 Baud Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4 Design of Graphical User Interface . . . . . . . . . . . . . . . . . . . . . 354.4.1 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . 354.4.2 Selection of Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . 374.4.3 Selection of Data Display Refresh Rate on PC Screen . . . . . . 38

5 Conclusions 40

Bibliography 41

List of Tables

3.1 Computation time for different subroutines . . . . . . . . . . . . . . . . 223.2 Per unit quantities & finite word length representation of an analog

quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

vii

List of Figures

2.1 3-phase to 2-phase transformation . . . . . . . . . . . . . . . . . . . . . 42.2 Block diagram representation of PLL . . . . . . . . . . . . . . . . . . . 62.3 Butterfly structure of FFT algorithm . . . . . . . . . . . . . . . . . . . . 7

3.1 Matlab simulation of PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Increase in magnitude of R-phase and decrease in magnitude of B-

phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3 Change in Frequency from 50Hz to 55 Hz . . . . . . . . . . . . . . . . . 123.4 Vd and Vq under balanced condition . . . . . . . . . . . . . . . . . . . 123.5 Harmonic spectrum of a sinewave. Scale X-axis 50Hz/div Y-axis 0.5V/div

123.6 Harmonic spectrum of a square wave. Scale X-axis 50Hz/div Y-axis

0.5V/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.7 Unbalance sine wave. Scale X-axis 100ms/div Y-axis 5V/div . . . . . . 143.8 When there is a increase in R-phase voltage and decrease in Y-phase

voltage. Scale X-axis 500ms/div Y-axis 2V/div . . . . . . . . . . . . . . 143.9 When there is a increase in VR andVB is constant. Scale X-axis 500ms/div

Y-axis 2V/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.10 Block Diagram of implementation of PLL . . . . . . . . . . . . . . . . . 153.11 3-phase to 2-phase transformation. Scale X-axis 10ms/div Y-axis 2V/div 163.12 Magnitude of Vd and Vqwhen tested with a three phase sine generated

in another DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.13 Magnitude of VR and VY . . . . . . . . . . . . . . . . . . . . . . . . . . 173.14 Phase angle of VR and VY . . . . . . . . . . . . . . . . . . . . . . . . . . 183.15 Magnitude of VR and VB . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.16 Phase angle of VR and VB . . . . . . . . . . . . . . . . . . . . . . . . . . 193.17 Scaled downVoltages(VR,VY)obtained fromGrid. Scale X-axis 5ms/div

Y-axis 2V/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.18 Scaled downVoltages(VR,VB)obtained fromGrid. Scale X-axis 5ms/div

Y-axis 2V/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.19 3-phase to 2-phase transformation of Grid Voltages. Scale X-axis 5ms/div

Y-axis 2V/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.20 Magnitude of Vd and Vq obtained from Grid voltages . . . . . . . . . . 233.21 Harmonic spectrum of a square wave implemented in DSP . . . . . . . 24

viii

LIST OF FIGURES ix

3.22 Sampled Signal of VR and VY . . . . . . . . . . . . . . . . . . . . . . . . 243.23 Block diagram of voltage sensing card . . . . . . . . . . . . . . . . . . . 253.24 Duty cycle of an Flyback Transformer . . . . . . . . . . . . . . . . . . . 253.25 input voltage Vs output voltage . . . . . . . . . . . . . . . . . . . . . . . 263.26 Magnitude Vs Frequency response plot . . . . . . . . . . . . . . . . . . 26

4.1 Power Quality monitoring system built in VB . . . . . . . . . . . . . . 39

Chapter 1

Introduction

The aim of this project is to develop a power quality monitoring system. This is to

measure and calculate variables like magnitude, phase angle of voltages and currents,

active and reactive power, power factor, harmonics, total harmonic distortion,which

has to be carried out in Digital Signal Processor (DSP). The TMS320LF2407 DSP pro-

cessor, which is low cost, low power and high-performance processing capability.

The project is sub divided in to three parts.

1. Acquiring voltages and currents from the grid.

2. Processing through the DSP.

3. Display it on a PC

The voltages and currents from the grid are of high magnitudes, the DSP cannot han-

dle these signals so we need to scale down the signals appropriately,which can be

done by using voltage and current sensing cards.

The signals acquired from the sensors are given to the Analog to Digital converter

(ADC) of Digital Signal Processor.The ADC of DSP takes signals in the range of±10V .

The TMS320LF 2407 DSP module is developed by Texas Instruments, which has 40

1

Chapter 1. Introduction 2

MIPS operating speed at maximum with 25ns cycle time and is a 16 bit Fixed-point

processor. It is a modified Harvard Architecture DSP.

The calculated data is transmitted from the processor to PC via RS-232 serial com-

munication, the data can be send at different Baud rates by programming the baud

select register of the processor. The data acquired from the serial link is displayed on

PC screen using Graphical User Interface (GUI) built in Visual Basic (VB).

Chapter 2

Measurement of electrical quantities

2.1 Introduction

In this chapter the theoretical explanation for calculation of electrical quantities are

explained. This chapter is sub divided as

1. Measurement of frequency and harmonic quantities.

2. Measurement of magnitude and phase quantities.

3. Measurement of active power, reactive power and power factor

2.2 Measurement of frequency and harmonic quantities

Measurement of fundamental quantities such as phase and frequency is carried out

using Phase Locked Loop (PLL).The basic configuration of the PLL system is shown

in fig 2.2. The phase voltages Va, Vb, Vc are obtained from sampled line to line volt-

ages. These Three phase voltages are then transformed toVα, Vβ using 3-phase to 2-

phase transformation.These stationary reference frame voltages are then transformed

3

Chapter 2. Measurement of electrical quantities 4

to voltagesVd, Vq frame of reference synchronized to the utility frequency. The Trans-

formations are shown below. Three Phase Voltages from th Grid are shown as

Va = Vm cos (θ) (2.1)

Vb = Vm cos (θ − 120) (2.2)

Vc = Vm cos (θ − 240) (2.3)

where θ = (ωt + θ0).

Transformation from 3-Phase to 2-Phase and transformation from stationary to rotat-

ing frame are carried out as

V

V

α

β

Va

Vb

Vc

Vd

qV

Figure 2.1: 3-phase to 2-phase transformation

Vα = Va (2.4)

= Vm cos (θ) (2.5)


Vβ =(Vc − Vb)√

3(2.6)

= −Vm sin (θ) (2.7)

Which is then transformed to synchronous frame (Vd, Vq) given by

Vq

Vd

=

cos (θ∗) − sin (θ∗)

sin (θ∗) cos (θ∗)

Vα

Vβ

(2.8)

substituting for Vα and Vβ we get

Vq

Vd

= Vm

cos (θ∗ − θ)

sin (θ∗ − θ)

= Vm

cos (∆θ)

sin (∆θ)

(2.9)

The angle θ∗ used in these transformations is obtained by integrating a frequency

command ω∗. If the frequency command ω∗ is identical to the utility frequency, the

voltages Vd, Vq appear as dc values depending on the angle θ∗.

If the error ∆θ between the utility angle θ and the PLL output θ∗ is set to zero,Vq = Vm

and Vd = 0.This offers immediate possibility to lock onto the utility voltage by regu-

lation of Vd to zero. No information is needed about the magnitude Vm of the utility

voltage.

For small values of ∆θ, the term sin (∆θ) behaves linearly i.e. , sin (∆θ) ≈ ∆θ. The PLL

can thus be treated as a linear control systemwith the utility magnitude Vm appearing

as a gain in the forward path, the plant being a simple integrator.

2.2.1 Calculation of controller Gains

The transfer function of the plant, taking sampling delay in to account is given as

Hplant =[

VmS

] [

11+sTs

]

(2.10)


3−phase to Va

Vb

Vc2−phase(α, β)Transformation

Tranformation

α, β to d, q Vq

Vd

V *d

Kp1 + STp

pST

++

ωff

1

S

ω∗

=0

θ*

1 + STs

1

Figure 2.2: Block diagram representation of PLL

The open loop transfer function with the controller is given by

Hopenloop =[

VmS

] [

11+sTs

] [

Kpll1+sTpll

sTpll

]

(2.11)

Where Kpll and Tpll are the gains of PI regulator. The method of symmetric optimum

is used for calculation of gains. According to this method the regulator gains Kpll and

Tpll are selected such that the gain and the phase plot ofHopenloop are symmetrical about

the crossover frequency ωc. Given normalizing factor α ,the frequency ωc, Kpll, Tpll are

related as following.

ωc = (1/αTs) (2.12)

Tpll = α2Ts (2.13)

Kpll = (1/α) (1/VmTs) (2.14)

2.2.2 Calculation of Harmonics

Harmonic analysis is carried out using Fourier Transforms. The Discrete Fourier

Transform (DFT) of a finite-length sequence x [n] of length N is

X [k] =

N−1∑

i=0

x [n] ωknN k = 0, 1, . . . , N − 1 (2.15)


Where ωN = e−j(2π/N) and X [k] ∗ 2/N gives magnitude of the kth harmonic. If we ex-

ploit both symmetry and the periodicity of the complex exponential ωN = e−j(2π/N) we

can decompose the computation into successively smaller DFT computations which

known as Fast Fourier Transform (FFT). the butterfly structure of 8-point radix-2 dec-

imation in time algorithm is shown in Fig 2.3. The Total Harmonic Distortion(THD)

x[2]

x[4]

x[0] X[0]

X[3]

X[6]

X[7]

X[5]

X[4]

X[2]

X[1]

x[6]

x[1]

x[5]

x[3]

x[7]

ωN0

ωN0

ωN0

ωN0

ωN0

ωN0

ωN2

ωN2

ωN0

ωN2

ωN1

ωN3

Figure 2.3: Butterfly structure of FFT algorithm

is given as

VTHD =√

ΣV 2k /V1 (2.16)

ITHD =√

Σi2k/i1 Where k = 0, 1, 2 . . . , N/2 (2.17)

2.3 Magnitude and Phase Calculations

Magnitude calculations are carried out by multiplying the Utility voltages with unit

sine and cosine and low pass-filtering , the mathematical equations for obtainingmag-

nitudes are given as The Utility voltages are given in equations 2.2, 2.3 and 2.3.

Multiplying Va by unit sin (θ∗) and cos (θ∗), where θ∗ = (ω∗t + θ∗0) we get

Va1 = Va ∗ sin (ω∗t + θ∗0) (2.18)

Va2 = Va ∗ cos (ω∗t + θ∗0) (2.19)


solving the above equations we get

Va1 = Vm/2 ∗ [sin (2ωt + (θ0 − θ∗0)) + sin (θ0 − θ∗0)] (2.20)

Va2 = Vm/2 ∗ [cos (2ωt + (θ0 − θ∗0)) + cos (θ0 − θ∗0)] (2.21)

By low pass filtering, the 100Hz component is eliminated, and the output become as

given

Vs1 = Vm/2 sin (θ0 − θ∗0) (2.22)

Vc1 = Vm/2 cos (θ0 − θ∗0) (2.23)

The magnitude and phase angle are given as

V1 = 2√

V 2s1 + V2c1 (2.24)

θ1 = arctan (Vs1/Vc1) (2.25)

The other two phase voltages and currents can be calculated similarly.

2.4 Real and Reactive Power Calculations

The active and reactive power are calculated using the fundamental quantities of the

voltage and currents evaluated using equations 2.24,2.25 is given by The active power

per phase

P1 = V1I1 cos (θ1 − θi1) (2.26)

P2 = V2I2 cos (θ2 − θi2) (2.27)

P3 = V3I3 cos (θ3 − θi3) (2.28)


where θ1, θi1 are phase angles of R-phase voltage and current respectively.

Total real power is the sum of the three phase power

P = P1 + P2 + P3 (2.29)

Reactive power per phase

Q1 = V1I1 sin (θ1 − θi1) (2.30)

Q2 = V2I2 sin (θ2 − θi2) (2.31)

Q3 = V3I3 sin (θ3 − θi3) (2.32)

Total reactive power is

Q = Q1 + Q2 + Q3 (2.33)

2.4.1 Power Factor Calculation

The complex power(S) is expressed as

S̄ = P + jQ (2.34)

from power triangle, power factor can be calculated as

cos (θ) =P

√

P 2 + Q2(2.35)

The type of loads determines the power factor. These can be resistive (unity power

factor), inductive (zero power factor lagging), capacitive (zero power factor leading).

Chapter 3

Implementation and Results

3.1 Introduction

In this chapter the approach to the problem , software and hardware details are ex-

plained.

3.2 MATLAB Simulation

Calculation of frequency is the starting point of the work, to calculate frequency PLL

system is required which is implemented in MATLAB (SIMULINK) software, the

block diagram of the PLL system is shown in fig 3.1. The PLL is tested for different

unbalanced conditions (i.e,change in frequency,magnitude and phase ) and the sim-

ulation results are shown below. The DFT and FFT algorithms are implemented in

MATLAB software and the harmonics analysis is carried out on different signals(sine

wave, square wave etc).Algorithms are also verified by injecting different harmon-

ics to the sinusoial signals. Following figures shows the harmonic spectrum under

different conditions.

10

Chapter 3. Implementation and Results 11

Figure 3.1: Matlab simulation of PLL

Figure 3.2: Increase in magnitude of R-phase and decrease in magnitude of B-phase


Figure 3.3: Change in Frequency from 50Hz to 55 Hz

Figure 3.4: Vd and Vq under balanced condition

0 100 200 300 400 500 600 700 8000

0.5

1

1.5

2

2.5

3

Figure 3.5: Harmonic spectrum of a sine wave. Scale X-axis 50Hz/div Y-axis 0.5V/div


0 100 200 300 400 500 600 700 8000

0.5

1

1.5

2

2.5

3

3.5

Figure 3.6: Harmonic spectrum of a square wave. Scale X-axis 50Hz/div Y-axis0.5V/div

3.3 DSP Implementation

The implementation of DSP algorithms are carried out first in signal level i.e. instead

of taking voltage and current signals from the Grid these signals are generated locally,

Two DSP Processors are required for this purpose one to generate the required signals

(DSP#1) , DACS software is used to develop the code for DSP#1, serial link(RS-232)

is used to connect the DSP#1 and PC.Code Composer Studio(CCS) software is used

to develop code in other DSP(DSP#2),XDS - 510PP emulator is used to connect the

DSP#2 and PC. DSP #2 is used for implementing algorithms required for developing

the power quality analyzer.

The utility grid may contain unbalance in magnitude, phase and frequency the per-

formance of the PLL should not get affected, for this purpose DSP #1 is used as signal

generator that can provide signal inputs with controllable magnitude, phase and fre-

quency. The algorithms are tested for different unbalanced conditions. The Fig 3.7

shows the unbalanced sine wave and Fig 3.8,Fig 3.9 shows corresponding change in

magnitudes.


Figure 3.7: Unbalance sine wave. Scale X-axis 100ms/div Y-axis 5V/div

Figure 3.8: When there is a increase in R-phase voltage and decrease in Y-phase volt-age. Scale X-axis 500ms/div Y-axis 2V/div


Figure 3.9: When there is a increase in VR and VB is constant. Scale X-axis 500ms/divY-axis 2V/div

3.3.1 Phase Locked Loop (PLL)

The phase transformation , proportional plus integrator(PI), magnitude and phase

calculations are done on DSP. The following Fig 3.10 shows the implementation of

PLL on DSP.

1/sqrt(3) Kpll(1+STpll)*Vm

STpll

1

1 +Ts

1

S

Vq

Vd

Wff

LOOK UP

TABLE

Theta*

Feed Forwardgain

3−phase to 2−phase

Transformation

FROM VOLTAGE

SENSING CARD OR

DSP #1 Vd*=0

alpha,beta to d ,q

Transformation

Figure 3.10: Block Diagram of implementation of PLL


3.3.2 Implementation of PLL on DSP

The transfer function of PI regulator is

[

Kpll1+sTpll

sTpll

]

(3.1)

which is simplified as

Kpll

[

1 +1

sTpll

]

(3.2)

Which is further simplified as

Kpll +

[

Kpll1s

]

Where Kkpll1 = Kpll/Tpll (3.3)

Then the controller is simply an integrator with gain.

The following Fig 3.11 shows the transformation from 3-phase to 2-phase and Fig

3.12 shows the d,q transformation. The magnitude and phase angles are shown be-

Figure 3.11: 3-phase to 2-phase transformation. Scale X-axis 10ms/div Y-axis 2V/div

low. The following figures fig 3.17,fig 3.18 shows the three phase voltges from the

grid. 3-phase to 2-phase and d,q transformation of grid voltages are shown in fig


Figure 3.12: Magnitude of Vd and Vq when tested with a three phase sine generatedin another DSP

Figure 3.13: Magnitude of VR and VY


Figure 3.14: Phase angle of VR and VY

Figure 3.15: Magnitude of VR and VB


Figure 3.16: Phase angle of VR and VB

Figure 3.17: Scaled down Voltages(VR,VY)obtained from Grid. Scale X-axis 5ms/divY-axis 2V/div


Figure 3.18: Scaled down Voltages(VR,VB)obtained from Grid. Scale X-axis 5ms/divY-axis 2V/div

below.

3.4 Hardware Details

Voltage and current sensing cards are needed to sense the grid voltages and currents,

the details of the sensors and interface cards used are explained.

3.4.1 Voltage sensing card

Voltage sensing card is used to scale down the voltage and to provide isolation be-

tween the Grid and control side. The specifications of a voltage sensing card used are

given below.

• Range of input voltage is ± 700V.

• Range of output voltage is ± 10V.

• 20kHz Bandwidth.


Figure 3.19: 3-phase to 2-phase transformation of Grid Voltages. Scale X-axis 5ms/divY-axis 2V/div

• Isolation between input voltage to output voltage

Block diagram of the voltage sensing card is shown in Fig above.The input and output

signals are isolated from each other by an optical amplifier HP7800. HP7800 requires

two isolated power supply of magnitude of 5V.The 5V power supplies are obtained

from two linear regulators( LM 7805 ).One of the regulator gets its input from the con-

trol power supply (+15V ) and other from a fly back converter. Switching frequency

of the converter is chosen to be 50kHz.The input voltage to HP7800 is divided by us-

ing the voltage divider circuit to a range within± 200mVwhich is the linear range for

HP7800.Typical gain of HP7800 is 8 with a tolerance of ± 5 %.Output of the HP7800

is connected to a differential amplifier.The gain of the amplifier is chosen to be 6.5.

Linearity Test:

The voltage sensing card is tested for different DC voltages,the plot of input voltage

Vs voltage is shown below.

Bandwidth is calculated by obtaining the gain at different frequencies. The Magni-

tude VS frequency response plot is as shown.


3.4.2 Current sensing card

Features:

• It can sense two line currents by two Hall Sensor in the board.

• Low non-linearity and high Bandwidth.

• Measures currents in the range of ± 50A maximum.

• Uses low profile Hall effect current transformer HTP50.

Specifications:

• power supply : +15V, 0, -15V.

• Primary current amplitude : ± 50A maximum.

• Output signal amplitude : ± 10V maximum.

• Bandwidth : 100 kHz.

• Non-linearity : 0.2% maximum.

The following table shows the computation time required for different subrou-

tines. The following table gives per unit quantities and finite word length Represen-

Table 3.1: Computation time for different subroutinesS.No Subroutine time in µsec1 Analog to digital conversion for 16 channels 11.3002 PLL Program 18.0003 Magnitude and Theta calculation for all 6 signals 40.0004 Power calculation 4.0005 FFT FFT algorithm for one signal 96.0006 3-phase to 2-phase transformation 0.7407 Digital to Analog Conversion 2.1208 Data transmission of 24 signals at 9600 baud rate 25000.000

tation of an analog quantity.


Table 3.2: Per unit quantities & finite word length representation of an analog quantity

S.No Units Analog representation Finite word length representation P.U1 Voltage -10V 08000h -2

−5V 0BFFFh -15V 03FFFh 110V 07FFFh 20V 0000h, FFFFh 0

2 Time 20ms 03FFFh 140ms 07FFFh 2

3 Frequency 314.16rad/s 03FFFh 14 Theta 2πrad 03FFFh 1

πrad 01FFFh 0.5

Figure 3.20: Magnitude of Vd and Vq obtained from Grid voltages


0 100 200 300 400 500 600 7000

0.5

1

1.5

2

2.5

3

3.5

Figure 3.21: Harmonic spectrum of a square wave implemented in DSP

Figure 3.22: Sampled Signal of VR and VY


LM 7805 Fly Back

Converter

LM 7805

Differential

Amplifier

Voltage

Divider

+15V

+15V

+5V

+5V

HP 7800

Output

Input

Figure 3.23: Block diagram of voltage sensing card

Figure 3.24: Duty cycle of an Flyback Transformer


−600 −400 −200 0 200 400 600−8

−6

−4

−2

0

2

4

6

8

Input Voltage

Otp

ut V

olta

ge

Figure 3.25: input voltage Vs output voltage

100

101

102

103

104

105

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency in Hz

Abs

olut

e M

agni

tude

Figure 3.26: Magnitude Vs Frequency response plot

Chapter 4

Communication between DSP and PC

and GUI

4.1 Introduction

This chapter illustrates the serial communication between DSP and PC.The commu-

nication interface and the Graphical User Interface (GUI) in the Visual Basic platform

is also outlined in this chapter.

4.2 Serial Communication Interface (SCI)

4.2.1 Introduction

Serial link RS-232 is used to communicate between DSP and PC. In a serial link, the

transmitter, sends one bit at a time in sequence.A link with just two devices may

have a dedicated path for each direction or it may have a single path shared by

both,with the transmitters taking turns.The transmitter and receiver use a clock to

decide when to send and read bit.Two types of serial-data formats are synchronous

and asynchronous, and each uses clocks in different ways.

27

Chapter 4. Communication between DSP and PC and GUI 28

• USART: Universal Synchronous-Asynchronous Receiver/Transmitter

• UART: Universal Asynchronous Receiver/Transmitter

4.2.2 Synchronous Serial Communication

Synchronous serial transmission requires that the sender and the receiver share a

clock with one another, or that the sender provides a strobe or other timing signal so

that the receiver knows when to ”read” the next bit of the data. in most forms of serial

synchronous communication, if there is no data available at a given instant to trans-

mit, a fill character must be sent instead so that data is always uninterruptedly being

transmitted. Synchronous communication is usually more efficient because only data

bits are transmitted between sender and receiver, and it is costly communication if

extra wiring for sharing same clock is required between sender and receiver.

4.2.3 Asynchronous Serial Communication

Asynchronous serial transmission allows data to be transmitted without the sender

having to send a clock signal to the receiver. Instead, the sender and receiver must

agree on the timing parameters in advance and special bits are added to each word,

which are used to synchronize the sending and receiving units.

When a word is given to the UART for asynchronous transmission, a bit called the

”Start-bit” is added to the beginning of each word that is to be transmitted. The start

bit is used to alert the receiver that a word is about to come and to force the clock in

the receiver into synchronization with the clock in the transmitter. Those two clocks

must be accurate enough not to have the frequency drift more than 10 during trans-

mission of the remaining bits of the word.

After the start bit, the individual bits of the word is sent, with the least significant

bit(LSB) being sent first, each bit in the transmission is transmitted for exactly the


same amount of time as all the other bits, and the receiver ”looks” at the wire approx-

imately halfway through the period assigned to each bit to determine if the bit is ”0”

or ”1”.The sender does not also know when the receiver has ”looked” at the value of

the bit. The sender only knows when the clock says to begin transmitting the next bit

of the word.

The transmitter may add a parity bit to the data being sent. It may be used by the

receiver to perform simple error checking. then at least one stop bit is sent by the

transmitter to indicate the end of data. When the receiver has received all of the bits

in the data word, it may check for the parity bits (both sender and receiver must agree

on weather a parity bit is to be used), and the receiver looks for stop bit. if the stop

bit does not appear when it is supposed to, the UART considers the entire word to be

garbled it will report a ”Framing Error” to the host processor when the data word is

read. The usual cause of a framing error is that the sender and receiver clocks were

not running at same speed, or that the signal was interrupted.

Regardless of whether the data was received correctly or not, the UART automati-

cally discards the ”Start”, ”Parity” and ”Stop” bits. If the sender and the receiver is

configured identically, these bits are not passed to the host. If another word is ready

for transmission, the ”Start” bit for the word can be sent as soon as possible as the

”Stop” bit for the previous word has been sent. Because data is ”self-synchronizing”,

if there is a new data to transmit, the transmission line could be idle.

4.3 Serial Communication Interface (SCI)Module inDSP

This chapter describes the architecture, functions, and programming of the Serial

communication interface (SCI) module in the DSP. The programmable SCI module


supports digital communications between the CPU and other asynchronous periph-

erals like other CPU or any PC that use the standard NRZ (non return-to-zero) for-

mat.The SCI transmits and receives serial data, one bit at a time, at a programmable

bit rate. The SCI receiver and transmitter are double buffered, and each has its own

separate enable and interrupt bits. Both may be operated independently or simulta-

neously in the full-duplex mode. To ensure data integrity, the SCI checks data that

has been received for break detection, parity, overrun, and framing errors. The speed

of the bit rate (baud) is programmable to over 64000 different speeds through a 16-bit

baud-select register.

4.3.1 Physical Description

The SCI module contains the following key features:

• Two I/O pins:

1. SCITXD (SCI transmit data output).

2. SCIRXD (SCI receive data input).

• Programmable bit rates to over 64K different speeds the registers16-bit baud

select register.

1. Range at 10-MHz SYSCLK: 19.07 bps to 625.0 kbps.

2. Number of bit rates: 64K.

• Programmable data-word length from one to eight bits.

• Programmable stop-bits of either one or two bits in length.

• Internally generated serial clock.

• Four error detection flags:

1. Parity error.


2. Overrun error.

3. Framing error.

4. Break detect.

• Two wake-up multiprocessor modes that can be used with either communica-

tion format:

1. Idle-line wake-up.

2. Address-bit wake-up.

• Half- or full-duplex operation.

• Double-buffered receive and transmit functions.

• A transmitter and receiver operation that can be operated through interrupts or

through polled operation.

• NRZ (non-return-to-zero) format.

4.3.2 Architecture

The major elements used in the full duplex operation are:

• A transmitter (TX) and its major registers:

1. SCITXBUF: transmitter data buffer register. Contains data (loaded by the

CPU) to be transmitted.

2. TXSHF:transmitter shift register. Loads data from SCITXBUF and shifts

data onto the SCITXD pin, one bit at a time.

• A receiver (RX) and its major registers:

1. RXSHF receiver shift register. Shifts data in from SCIRXD pin, one bit at a

time.


2. SCIRXBUF receiver data buffer register. Contains data to be read by the

CPU.Data from a remote processor is loaded into RXSHF and then into

SCIRXBUF and SCIRXEMU

• A programmable baud generator.

• Data memory-mapped control and status registers.

The SCI receiver and transmitter can operate independently or simultaneously.

4.3.3 Programmable Data Format

The basic unit of data is called a character and is one to eight bits in length. Each

character of data is formatted with a start bit, one or two stop bits, and optional parity

and address bits. A character of data with its formatting information is called a frame.

4.3.4 Communications Modes

The SCI has two multiprocessor protocols, the idle-line multiprocessor mode and the

address-bit multiprocessor mode. These protocols allow efficient data transfer be-

tweenmultiple processors. The SCI offers the universal asynchronous receiver/transmitter

(UART) communications mode for interfacing with many popular peripherals. The

asynchronous mode requires two lines to interface with many standard devices such

as terminals and printers that use RS-232-C formats. Data transmission characteristics

include:

• One start bit.

• One to eight data bits.

• An even/odd parity bit or no parity bit.

• One or two stop bits.


4.3.5 Multiprocessor Communication

The multiprocessor communication format allows one processor to efficiently send

blocks of data to other processors on the same serial link. On one serial line, there can

be only one transfer (or transmitter) at a time. The first byte of a block of information

that the transmitter sends contains an address byte, that is read by all receivers. Only

receivers with the correct address can be interrupted by the data bytes that follow the

address byte. The receivers with an incorrect address remain uninterrupted until the

next address byte. A processor recognizes an address byte according to the multipro-

cessor mode.

Idle-Line Multiprocessor Mode:The idle-line mode leaves a quiet space before the ad-

dress byte. This mode does not have an extra address/data bit and is more efficient

than the address-bit mode for handling blocks that contain more than ten bytes of

data. The idle-line mode should be used for typical non-multiprocessor SCI commu-

nication. In the Idle-line multiprocessor protocol (ADDR/IDLE MODE bit = 0), the

blocks are separated by a longer idle time between blocks than between frames in the

blocks. An idle time of ten or more high-level bits after a frame indicates the start of a

new block the time of a single bit is calculated directly from the baud value (bits per

second).

Address-Bit Multiprocessor Mode:The address-bit mode adds an extra bit (address

bit) into every byte to distinguish addresses from data. This mode is more efficient in

handling many small blocks of data because, unlike the idle mode, it does not have

to wait between blocks of data. However, at high transmit speeds, the program is

not fast enough to avoid a 10-bit idle in the transmission stream. In the address-bit

protocol (ADDR/IDLEMODE bit = 1), frames have an extra bit, called an address bit,

that immediately follows the last data bit. The address bit is set to 1 in the first frame

of the block and to 0 in all other frames. The idle period timing is irrelevant.


4.3.6 Communication Format

The SCI asynchronous communication format uses either single-line (one-way) or

two-line (two-way) communications. In this mode, the frame consists of a start bit,

one to eight data bits, an optional even/odd parity bit, and one or two stop bits. There

are 8 SCI clock (SCICLK) periods per data bit. The receiver begins operation on receipt

of a valid start bit.A valid start bit is identified by four consecutive internal SCICLK

periods of 0 bits. If any bit is not 0, then the processor starts over and begins looking

for another start bit.

For the bits following the start bit, the processor determines the bit value by mak-

ing three samples in the middle of the bits. These samples occur on the fourth, fifth,

and sixth SCICLK periods, and bit-value determination is on a majority (two out of

three) basis. Since the receiver synchronizes itself to frames, the external transmitting

and receiving devices do not have to use a synchronized serial clock; the clock can be

generated locally.

4.3.7 Baud Rate Calculation

The internally-generated serial clock is determined by the system clock (SYSCLK)

frequency and the baud-select registers. The SCI uses the 16-bit value of the baud-

select registers to select one of the 64K different serial clock rates. The SCI baud rate

for the different communication modes is determined in the following ways:

SCIAsynchronousbaud =CLCKOUT

(BRR + 1) × 8(4.1)

Alternatively,

BRR =CLKOUT

(SCIAsynchronousbaud) × 8− 1 (4.2)


4.4 Design of Graphical User Interface

The GUI is built in the VB environment which is done just by dragging all components

like labels and text boxes from object browser and drop in the ”Form” in VB window.

The project is built using a ”standard.exe” type project.The RS-232 is used to transfer

the data from the DSP to the PC.

4.4.1 Communication Protocol

There are several ways to access the serial port in the VB environment as follows

• MS Comm.

• Calling API (Applications Programmer’s Interface) Functions.

• Using a DLL (Dynamic Link Library) programming.

• Other driver that enables reading and writing directly to the port registers

MS Comm:MS Comm is VB’s custom control module for serial communication. This

helps to communicate with the help of protocol defined for both the VB program and

external CPU (in this case DSP). The data comes continuously and are read by the

receive buffer, which can be of 2048 in size at the maximum case. Receive buffer size

is defined in the initialization subroutine of the port. Whenever the receive buffer is

full, it generates an ”Communication Event”. In that event one function is called for

data conversions to make the hex data to meaningful physical variable and to store

those data in one array. One timer is there to control the data display refresh rate.

Steps for data conversion in DSP:

1. Store and update the data in a memory block with known starting address in

the code in DSP.


2. Access the memory block with a count value initialized to zero stored in an

Auxiliary register.

3. Read the 16 bit data to be sent.

4. Split it into two 8 bit data.

5. Send the low byte first.

6. Send higher byte.

7. Increase count.

8. Check the count is exceeded the defined no of bytes to be sent.

9. If count is not zero then go to step 3 after increasing the indirect memory address

by

10. otherwise go to step 1.

Steps for data conversion in VB Code:

1. Read continuous data bytes.

2. Store in variant in binary data mode.

3. Store in array of bytes.

4. Read Low and High Bytes.

5. Calculate: Number = HighByte × 256 + LowByte.

6. Calculate:DisplayQuantity = Number × scalefactortoconverttophysicalvalues.


4.4.2 Selection of Baud Rate

A link’s bit rate is the number of bits transmitted or received per unit of time, usually

it is expressed in bits per second (bps). Baud rate is the number of possible events,

or data transitions per second. These two values are often identical because in most

of the links each transmission period represents a new bit. Over phone lines, high

speed modems use phase shifters and other tricks to encode multiple bits in each data

period, so the baud rate actually much lower than the bit rate.

All of the bits required to transmit a value from start to stop bit form ”word”. The

data bit in the ”word” form a ”character”. In some links, the ”characters” actually do

represent text characters (letters or numbers), while in others the characters are binary

values that have nothing to do with the text.

Adding one ”start” and one ”stop” bit to each byte, the transmission time increases by

25% (because of 10 bits instead of 8). So for 9600 bits/sec link will transfer 960 bytes

in one second.

Baud Rate Limitations:

1. DSP side:

Maximum baud rate =SCICLK16

.

Where,SCICLK = SCImoduleclockfrequency.

System clock of DSP (SY SCLK) = 40MHz.

SCICLK(max) = SY SCLK.

So, maximum baudrate = 2.5Mbps.

2. PC side:

The UART usually uses a receive clock that is 16 times of the bit rate.

In PC, the standard UART clock frequency = 1.18432MHz.

So, the maximum baud rate = 115.2kbps.


4.4.3 Selection of Data Display Refresh Rate on PC Screen

1. Total Number of display data = 19.

2. Each data is of 16 bit.

3. Each data is divided into two 8-bit data.

4. Each byte is added with start and stop bits.

5. So, each split ed-data has 10 bits.

6. Current baud rate = 9600 baud per second (bps).

7. Calculate: Total time to send those data from DSP =Tsend

Tsend = 2 × 19 × 101

9600seconds. (4.3)

= 39.58msec. (4.4)

8. Human eye sensitivity: 100mSec i.e. in one second ten changes in display could

be recognized at the maximum case.

9. The Refresh rate on the PC screen should bemore than 100mSec because nobody

will understand the display if it is less than or equal 100mSec.

The refresh rate is controlled by the timer event in the VB code. Whenever the event

comes(after each count reaches the initialized value) the data is refreshed. The refresh

rate is selected as 500mSec.


the following figure shows the power quality monitoring system built in VB envi-

ronment.

Figure 4.1: Power Quality monitoring system built in VB

Chapter 5

Conclusions

In this work the algorithms required for implementing power quality algorithms are

developed and tested both in signal and power level. Back to Back test is conducted

on two 10KVA FECs, to get the required voltage and current signals.Harmonic anal-

ysis is verified with MATLAB program. Serial communication from DSP to PC is

addressed.GUI has been developed in VB environment.

Scope for future work:

1. In present work the harmonics of the order 0to16th are calculated and it can be

extended to higher order harmonics.

2. The harmonic analysis of particular signal can be displayed on the PC screen by

transmitting a signal from visual basic(VB).

3. The data displayed can be stored in memory for diagnostic purpose.

4. The VB code can be sofisticated for logging the error message.

40

Bibliography

1. Albert So, Norman Tse,W. L. Chan and L. L. Lai, ”A Low-Cost Power QualityMeter

for Utility and Consumer Assements,”International Conference on Electric Utility

Deregulation and Restructuring and Power Technologies 2000, City University,

London, 4-7 April 2000.

2. V. Kaura and V. Blasko, “ Operation of a phase locked loop system under distorted

utility conditions ,” in IEEE Transactions on Industry Applications, Volume 33,

Issue 1, Jan.-Feb. 1997 Page(s):58 - 63.

3. Anirban Goshal and Vinod John, “ A Method To Improve PLL Performance Under

Abnormal Grid Conditions,” National Power Electronic Conference-2007, Banga-

lore.

4. V.T. Ranganathan “Course notes on electrical drives,” Dept of Electrical engg.,Indian

Institute of Science, Bangalore,India.

5. Alan V. Oppenheim and Ronald W. Schafer, “ Discrete Time Signal Processing,”

Prentice Hall signal processing series,1989, New Jersey.

6. Jan Axelson, “Serial Port Complete,” Penaram International,1998,Mumbai.

7. L Cristaldi and A Ferro ” A method and related digital instruments for the measure-

ment of electrical power,” in IEEE Transactions on power delivery, Volume 10 3rd

July 1985.

41

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