hardware basic & verilog introduction

Hardware Basic & Verilog Introduction

Speaker :劉承曄(Cheng-Yeh LIOU)

Date : 2018/07/16

Graduate Institute of Electronics Engineering

National Taiwan University

HDL vs Software Language

Verilog

System Verilog

VHDL

Hardware Description Language

C/C++

Python

Java

Software Language

HDL vs Software Language

Hardware Software

Every part functions at

the same time.

Line by line.

Circuit Abstraction

Levels of Abstraction

RTL

Gate Level

Cell-Based IC Design

Specifications

RTL Coding

Synthesis

DFT Insertion

Place and Route

Tape Out

ATPG

DRC LVS

Front-End

Back-End

Test Patterns

Layout

RTL code

Gate-level netlist

GDS Layout

RTL vs Gate-Level

RTL

Gate Level

a2

a1

n1

o1

in2

in1

sel

out

a2_o

a1_oiv_sel

1

0

in2

in1

out

sel

Flip-Flop and Latch

Flip-Flop

Latch

D Q

clk

register

Combinational & Sequential

1

0

sel

in2

clk

in1

clk

clk

Combinational PartSequential Part Sequential Part

Memory-less

Always running

Memory

Clock-triggered

out

Critical Path

Critical path is the path that has longest delay between reg or

in/out in the whole circuit.

Delay: 5ns

clk clk

Delay: 3ns

clk

Setup time & Hold time

Setup time(Tsu) : the minimum amount of time the data signal

should be held steady before the clock.

Hold time (Th) : the minimum amount of time the data signal

should be held steady after the clock

Overview

Module Declaration

Basic format

Vector port is valid

– But array is invalid

• Use SystemVerilog

Example

module <module name> ( <port list> );

input <signal A> ;

output <signal B> ;inout <signal C> ;

….

endmodule

down

counter

clk

rst num4

Parameters are constant.

Usually for states, width, height, etc.

Parameter

Data type

Frequently used data type are “wire” and “reg”

Basic format

Example

wire [vector length] < variable name> [array size] ;

reg [vector length] < variable name> [array size] ;

Data type

The datatype isn’t equal to the real circuit.

– reg doesn’t mean a register. It depends on how you use these

variables.

The selection of data type depends on the style of

assignment

– wire

• for continuous assignment (assign)

– reg

• for procedural assignment (within always block)

• Flip-Flop must be the data type of “reg”

Numeric System

Number representation:

– 4’d9 : means 4 bits decimal 9 (4’b1001 in binary)

– 10’b01: means 10 bits binary 00_0000_0001

– 8’h10 : means 8 bits hexadecimal 10 (8’b0001_0000 in binary)

– default value is decimal if there is no specific radix type and 32 bits.

Verilog support bitwise assignment:

<number of bits>’ <radix type> <value>

<signal A> = f( < signal B> [N:M] ) ; // only used some bits

<signal A> [ N:M] = <function value> // only assign some bits

A = 8’d12; A:

B = 8’h34;

A[7:4] = B[3:0]; B:

0 0 0 0 1 1 0 0

0 0 1 1 0 1 0 0

0 1 0 0 1 1 0 0

Value can include z and x

Unsigned and signed number

Unsigned Signed

3’b000 0 0

3’b001 1 1

3’b010 2 2

3’b011 3 3

3’b100 4 -4

3’b101 5 -3

3’b110 6 -2

3’b111 7 -1

Unsigned and signed number

In verilog, unsigned number is default.

If any of the input is unsigned, the operation is unsigned

To use signed number

Naming Rule

Consistent naming convention for the design

Lowercase letters for signal names: reset, adder_tmp

Uppercase letters for constants: LOAD, STORE

clk sub-string for clocks: clk_blk1, clk_blk2, blk3_clk

rst sub-string for resets: rst_uart, ip_rst,

Suffix

– _n for active-low, _z for tri-state, _a for async , …

state for current state, n_state for next state

Identical(similar) names for connected signals and ports

Consistency within group, division and corporation

Assignment

Describing the combinational circuit has two style:

– Continuous assignment( assign)

– Procedural assignment( always block)

Continuous assignment

– Signal at left hand side(LHS) must be wire data type

– Signal/ function value at RHS can be wire or reg data type

Combinational circuits are memory-less

assign <signal A> = <function value> ;

Always Block

Procedural assignment

– Signal at LHS must be reg datatype

– Signal at RHS can be reg or wire

– If there are 2 or more statements in always block, remember to add

“begin” and “end”

– All signal in RHS must include in sensitivity list. (or use ”＊”)

always @ (sensitivity list)

<signal A> = <function value>;

+

+

inA

inB

C

1’b1

D

Assignment vs always block

Assignment Always Block

LHS should be wire LHS should be reg

RHS can be wire or reg RHS can be wire or reg

Begin & end are not allowed Begin & end are used for multiple statements

Always running Triggered by sensitivity lists

Combinational only Could be sequential or combinational

Only 1-line conditional statement

is allowed

1-line, if-else and case conditional statements

are allowed.

Conditional Statement


– For continuous assignment

– You can’t use if-else or case statement in continuous assignment

statement.

assign signal A = ( condition) ? (True Signal) : (False Signal) ;

X



– For procedural assignment

if ( condition1 )

statement1 ;

else if ( condition2 )

statement2 ;

else

statement3 ;

case ( target )

condition1: statement1 ;

condition2: statement2 ;

…

default: statement N;

endcase

※ Remember write all

possible case or use

default.

※ The incomplete case

will cause a Latch after

synthesis.

※Remember that “If

“must accompany with

a “else”; otherwise, it

cause a Latch too.

Value logic system

0

- zero, false, low

1

- one, true, high

Z

- high impedance, float

X

- unknown

Operators

Common used operators

– red word means has a limited synthesis support

– Orange word means not recommended

Type Operators Examples

Arithmetic +, -, *, /, % A = B+C; 1001 = 0111+0010

Bitwise ~, &, |, ^, ~^ A = B^C; 0101 = 0111^ 0010

Reduction &, ~&, |, ~|, ^, ~^ &A 0 = &(0111)

Logical !=, ==, &&, ||, ===, !== A == B 0 = (0111 == 0101)

Relational >, >=, <, <= A>B 1 = (0111 > 0101)

Shift >>, << A= B << 1; 1110 = 0111 << 1

Conditional (condition) ? s1: s2; A = (B)? C: D; 0 = (0)? 1: 0;

Concatenation { } A = {B, C} 0110 = {01, 10}

Note : {b,3{a,b}} = {b, a, b, a, b, a, b}

For loop

Auto unroll, can only use in always block

Different with C/C++

Provide a convenient way of writing a series of statement

Loop index variables must be integer

Example

integer k;

always@(*) begin

out[0] = a[0]&b[0];

out[1] = a[1]&b[1];

out[2] = a[2]&b[2];

end

integer k;

always@(*) begin

for (k=0;k<=2;k=k+1)

begin

out[k] = a[k]&b[k];

end

end

Generate For

For continuous assignment / instance duplication

In Verilog-2001

Use genvar instead of integer

Block name is essential

Example:

Sequential Part

Verilog uses always block to generate flip-flop circuit.

Sequential Part

Describe the behavior of sequential circuit

always @ ( <sensitivity edge > <clock> [or <sensitivity edge> < reset >] )

if ( reset ) … ; // reset mode

else … ; // normal mode

Asynchronous reset Synchronous reset

D Q

rst

clk

countnext_count

Syn & Asyn Reset

Difference between asynchronous reset and synchronous reset

Asyn

reset

Syn

reset

Syn

reset

reset at the posedge of reset signal

reset at the posedge of clock signal

no reset occurs

Blocking and Non blocking Assignment

Use non blocking assignments in sequential always block.

always@(posedge clk) begin

x <= a;

y <= x;

z <= y;

end

always@(posedge clk) begin

x = a;

y = x;

z = y;

end

Usually as you expect

May not as you expect

Blocking and Non blocking Assignment

Use blocking assignments in combinational always block.

always@(*) begin

x = a & b;

y = x | b;

x = a;

end

always@(*) begin

x <= a & b;

y <= x | b;

x <= a;

end

Usually as you expect

May not as you expect

Sequential Part

The circuit must have a reset signal. Otherwise, the initial

value of Flip-Flop will be unknown.

Asynchronous or synchronous reset type depends on the

circuit’s spec.

non-blocking assignment “ <=“ for sequential circuit.

– Update value at the end of the always block

blocking assignment “=“ for combinational circuit. blocking assignment

non-blocking assignment

Two Different Coding Style

Split into 2 parts Merge into 1 part

Writing Next Logic

Naming rule: XXX_next, XXX_n, n_XXX, next_XXX

Datatype: could be reg or wire.

– wire

– reg

Remember to have default value for conditional statement

Completeness of condition statement

You should assign all conditions clearly.

reg [1:0]n_c,c;

always@(posedge clk)

begin

c <= n_c;

end

always@(*) begin

if (XXX)

begin

if(XXX)

n_c = 2’b00;

else

n_c = 2’b11;

end

end

reg [1:0]n_c,c;


begin

c <= n_c;

end

always@(*) begin

if (XXX)

begin

if(xxx)

n_c = 2’b00;

else

n_c = 2’b11;

end

else

n_c = c;

end

Wrong! Correct!

Latch!!!

Completeness of condition statement

Convenient way to save coding times.

To assign value for register in the beginning.

reg [1:0]n_c,c;


begin

c <= n_c;

end

always@(*) begin

n_c = c;

if (XXX)

begin

if(XXX)

n_c = 2’b00;

else

n_c = 2’b11;

end

end

Common issues

Data type “reg” is NOT definitely to be a register. Instead, the synthesis

result depends on the described behavior of RTL.

Multiple Driven Signals issue

– The variable of data type “wire” can NOT be repeatedly assigned.

– The variable of data type “reg” can only be assigned in single always

block.

x x

Common issues

Avoid appearance of Latch during synthesis.

– Latch is too advanced for beginner of digital circuit.

– Latch is due to incomplete assignment in combinational part.

– Incomplete assignment implies that circuit will hold the previous value.

Usage of positive & negative clock simultaneously is NOT recommended.

– Timing issue will cause the poor performance if not design properly.

– Complicated clock tree for skew issue during place and route.

Good Verilog Code

Clear Control

Readability

Maintainability

Performance

Clear Control

Controlling Unit Processing Unit

Circuit

Finite State Machine (FSM)

Model of computation consisting of

- A set (of finite number) of states

- An initial state

- Input symbols

- Transition function that maps input symbols and current

states to a next state

FSM

State parameter

parameter <MACRO> = <replaced number> ;

IDLE

DOWN ZERO

down =1

count=0

Readability

Naming rule is important.

– Try to give a specific name rather than a,b,c…

Indent

Maintainability

Make identical code to have single source

Single source coding Multi source coding

Performance

Depending on the spec, different evaluation method may be

used.

– Area

– Speed

• Number of cycles

• Frequency

– Power

Design tip -- pipeline

Delay: 4ns

clk

Delay: 4ns

clk

Delay: 4ns

clk clk

Delay: 4ns

clk

Non-pipelined, critical delay: 8ns

Pipelined, critical delay: 4ns

Design tip -- parallel

a

b c

a2

b2 c2

a1

b1 c1

Non-parallel100 data, 100 cycles

Parallel 100 data, 50 cycles

Design tip -- hardware reuse

in1

in2

in3

in4

1

0

state

STATE1

n_num

Design tip -- hardware reuse

n_num

state

STATE1

1

0

in1

in3

1

0

in2

in4

Design tip – input buffer

Input Delay

4nsDelay: 4ns

clk

Input Delay

4nsDelay: 4ns

clkclk

Design tip – input buffer

No input buffer Input buffer

Example of Design (1/3)

A count down counter.

– The circuit has three input port: clk, rst, and down.

– The circuit has one output port: num.

– The circuit is synchronous to posedge clk

– The circuit has asynchronous active high reset

– If down=1, the circuit begin count from 10 to 0.

– If the counter count to 0, it will stay at zero 2 clock cycle

and back to 10.


Step 1: plot the state diagram to

describe the circuit behavior.

Step 2: Estimate the essential

sequential element.

Step 3: Construct the FSM for control

signals based on state diagram.

Step 4: Construct the combinational

circuit based on control signals

IDLE

DOWN ZERO

down =1

count=0


IDLE

DOWN ZERO

down =1

count=0Next state logic

Output logic

Editors

SystemVerilog Introduction

Speaker :林裕盛 (Yu-Sheng Lin)

Date : 2018/07/16

Graduate Institute of Electronics Engineering

National Taiwan University

SystemVerilog What and Why

Improved version of Verilog

– Verilog 1995, 2001(most popular), 2005

– SystemVerilog 2005, 2009, 2012

What’s new?

– Some handy features for simplifying RTL coding

– Many many features for verification

EDA tool support?

– Good supports from commercial tools

I will use ☆ 1~5 to indicate the usefulness of each feature.

Handy Features of SystemVerilog (for RTL)

logic data type

clog2

Multi-dimension signals

Simpler for loop

Improved always block

Not introduced

– unique and priority case

– Improved macros

– enum for finite state machine

The New Logic Data Type (☆☆☆☆☆)

Reason: The datatype isn’t equal to the real circuit.

– reg doesn’t mean a register. It depends on how you use these

variables.

So, in SystemVerilog, a new type “logic” is introduced to

replace both of them.

– wire

• for continuous assignment (assign)

– reg

• for procedural assignment (within always block)

• Flip-Flop must be the data type of “reg”

The New Logic Data Type (☆☆☆☆☆)

Since logic is useful, you can do this:

module MyModule(input a,output reg b,input c,output wire d,

module MyModule(input logic a,output logic b,input logic c,output logic d,

The New Built-In Functions (☆☆☆☆☆)

I only introduce one: $clog2() – ceil(log2(x)).

Someday you write:

– parameter MAX_NUM = 6;parameter BIT_NEED = 3; // 6 requires 3 bitslogic [BIT_NEED-1:0] counter;

The second day:

– parameter MAX_NUM = 100; // Advisor says that...parameter BIT_NEED = 3; // You forget it

The SystemVerilog version:

– parameter BIT_NEED = $clog2(MAX_NUM);

Multi-Dimension Improvements 1 (☆☆☆☆)

The Verilog style array is:

– logic [31:0] signal [0:5][0:12];

The SyetemVerilog style array is:

– logic [31:0] signal [6][13];

Looks like most languages

Much cleaner

Multi-Dimension Improvements 2 (☆☆☆☆☆)

What’s wrong with this?

– module AddFourNumber(input [31:0] a [0:3],input [31:0] b [0:3],output [31:0] c [0:3]

);assign c[0] = a[0]+b[0];assign c[1] = a[1]+b[1];assign c[2] = a[2]+b[2];assign c[3] = a[3]+b[3];

endmodule

Looks like most languages

Much cleaner

Multi-Dimension Improvements 2 (☆☆☆☆☆)

Verilog ports is 1D

– module AddFourNumber(input [127:0] a,input [127:0] b,output [127:0] c

);assign c[127-:32] = a[127-:32]+b[127-:32];assign c[ 95-:32] = a[ 95-:32]+b[ 95-:32];assign c[ 63-:32] = a[ 63-:32]+b[ 63-:32];assign c[ 31-:32] = a[ 31-:32]+b[ 31-:32];

endmodule

Trust me, this pretty sucks.

Improved Always Combinational Blocks (☆☆☆)

Replace all always@* by always_comb

If you are lucky, you can know this earlier!

However, there are dedicated tools for finding out this, so this

is less useful.

– Spyglass, nLint

Improved Always Sequential Blocks (☆☆)

Sequential flip-flop

– always_ff

– It’s paired with always_comb

Simpler For-Loop (☆☆☆☆)

Don’t need to declare a global indices

– integer i;for (i=0; i<10; i=i+1)

The SystemVerilog Version is:

– for (int i=0; i<10; i++) Looks like C

A little cleaner

Assignment vs always block

Assignment Always Block

LHS should be wire LHS should be reg

RHS can be wire or reg RHS can be wire or reg

Everything is logic! Everything is logic!

Begin & end are not allowed Begin & end are used for multiple statements

Always running Triggered by sensitivity lists

But you don’t need to write them

Combinational only Could be sequential or combinational

Combinational only always_comb for combinational

always_ff for sequential (flip-flop)

EDA tool can do some checks for you

Only 1-line conditional statement

is allowed

1-line, if-else and case conditional statements

are allowed.

Why SystemVerilog in Short

Why?

– People make much efforts to:

• preventing you from making something stupid and

• letting you write less codes and write faster.

– Why not?

• Legacy reasons:

– Old codes/flows work perfectly and you don’t want to ruin that.

• You are smart and you write correct codes at all times.

Creator of the Slide

Some slides are modified from slides of CVSD lecture .

1st Edition:

2nd Edition:

3rd Edition: Chiang Ching-Fan

4th Edition: Liou Cheng-Yeh

SystemVerilog part: Lin Yu-Sheng

hardware basic & verilog introduction

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