Unit 2

Note: Explanation to this block diagram - take some important points of each module from topic “on chip peripherals” which is included in this document.

Address space

On chip peripherals

http://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/msp/peripherals.page#hw

FRAM TechnologyFerroelectric Random Access Memory (FRAM) is a memory technology that combines the best features of Flash and SRAM. It is non-volatile like Flash, but offers fast and low power writes, write endurance of 10^15 cycles and unmatched flexibility. While new to microcontrollers, FRAM has been used in the industry for over a decade.

Features: Non-volatile memory

100x faster writes than Flash

250x lower energy writes than Flash

High endurance - 10^15 write cycles

Resistance to electric/magnetic fields and radiation

Unified memory – flexible code and data partitioning

Benefits: Extend battery life

Backup data on power fail and quicken restart time

Reduce system cost by replacing external EEPROM

No data loss caused by soft-errors

Secure data with instantaneous and near infinite refresh of security keys

Hardware MultiplierThe MSP low-power microcontroller portfolio offers 16-bit and 32-bit multiplication modules on select devices. These peripherals can be used while the microcontroller is in low-power modes. Combined with optimized fixed and floating-point math libraries, MSP MCU performance can be increased dramatically.

Features: 16-bit or 32-bit available

Independent of the CPU

Supports signed and unsigned multiply and multiply accumulate

Benefits: Increase device capabilities with faster math operations

Extend battery life with low-power operation

Flexible design enables support for many applications

SecurityThe MSP low-power, advanced microcontroller portfolio provides embedded security systems that allow our customers to prevent, detect and respond to unintended or malicious behavior , including MCU reverse engineering. These secure microcontroller features include Advanced Encryption Standard (AES) hardware accelerators, IP encapsulation memory protection, anti-tampering, the FRAM advantage, among other features listed below

Feature Benefit MSP Families Learn more

FRAM Fast writes log data quickly, and generate PRNG keys faster for cryptography. Also resistant to glitch-attacks

MSP430FR57x/59x/69x Closing the security gap with TI’s MSP430™ FRAM-based microcontrollers

Debug Lockout

Prevent unauthorized access to the device through the debug interface. JTAG security fuse or FRAM password

All MSP families MSP430™ Programming Via the JTAG Interface User's Guide

Feature Benefit MSP Families Learn more

BSL Password Protection

Use a BSL password to prohibit every command that potentially allows unauthorized direct or indirect data access

All MSP families MSP430 Programming Via the Bootstrap Loader (BSL) User's Guide 

Configuring BSL and Security Features on MSP432 Microcontrollers, MSP432P401R Bootstrap Loader (BSL) User's Guide

Crypto-Bootloader

Counter the most important threats to in-field update mechanisms with authentication and encryption of firmware updates

MSP430FR59x,MSP430FR69x

Crypto-Bootloader – Secure in-field firmware updates for ultra-low-power MCUs

IP Encapsulation

Safely segregate your IPs from the rest of the application

MSP430FR59x/69x MSP430FRxx User’s Guide (See 7.2.2 IP Encapsulation Segment)

IP Protection

Regional security to enable multiple parties with software IP protection needs to be involved in product development

MSP432P4x Software IP Protection on MSP432P4xx Microcontrollers

256-bit AES Hardware Accelerator

Secure data transfers via the integrated hardware security accelerator while saving power by drastically reducing

MSP430F5x/F6x, CC430, MSP430FR59x/69x, MSP432P4x

MSP430F5xx/6xx, CC430, andMSP430FRxx User’s Guide (See AES Accelerator Chapter) MSP432P401x Technical Reference Manual (See AES

Feature Benefit MSP Families Learn more

the cycles required for serial encryption/decryption

Accelerator Chapter)

True Random Number seed

Generate random AES keys, and do so more often with FRAM-based devices

MSP430FR59x/69x MSP430FRxx User’s Guide (See 1.14.3.4 Random Number Seed)

Tamper Detection

Two pins can be used as an event or tamper detection input of an external switch (mechanical or electronic), with an RTC time stamp

MSP430F677x MSP430F5xx/6xx User’s Guide (see 24.3.2 Real-Time Clock Event/Tamper Detection With Time Stamp)

Voltage MonitoringThe power management module (PMM) manages all functions related to the power supply and its supervision for the device. Its primary functions are first to generate a supply voltage for the core logic, and second, provide several mechanisms for the supervision and monitoring of both the voltage applied to the device (DVCC) and the voltage generated for the core (VCORE). The PMM uses an integrated low-dropout voltage regulator (LDO) to produce a secondary core voltage (VCORE) from the primary one applied to the device (DVCC).In general, VCORE supplies the CPU, memories (flash and RAM), and the digital modules, while DVCC supplies the I/Os and all analog modules (including the oscillators). The VCORE output is maintained using a dedicated voltage reference.VCORE is programmable up to four steps, to provide only as much power as is needed for the speed that has been selected for the CPU. This enhances power efficiency of the system. The input or primary side of the regulator is referred to as its high side. The output or secondary side is referred to as its low side.

Features Wide supply voltage (DVCC) range

Generation of voltage for the device core (VCORE) with up to four programmable levels

Supply voltage supervisor (SVS) and supply voltage monitor (SVM) for DVCC and VCORE with programmable threshold levels

Brownout reset (BOR)

Software accessible power-fail indicators

I/O protection during power-fail condition

Benefits Simplifies system power sequencing requirements

Safety concepts supported by built-in diagnostic features

Eases safety-critical concept development and rational

CapTIvate™ touch microcontrollerMSP MCUs with FRAM and CapTIvate™ technology are the most noise immune capacitive touch MCUs, with IEC61000-4-6 certified solutions and the most configurable combination of capacitive buttons, sliders, wheels, and proximity sensors, all at the world's lowest power.

10-bit and 12-bit SAR ADCsThe ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core with sample select control, reference generator, window comparator and data transfer controller (DTC). The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention. The module can be configured with user software to support a variety of applications. The ADC also has a built in temperature sensor and supports a conversion rate of greater than 200ksps. 

The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, window comparator and data transfer controller (DTC). The DTC allows ADC12 samples to be converted and stored anywhere in memory without CPU intervention. The module can be configured with user software to support a variety of applications. 

The ADC also has a built in temperature sensor and supports a conversion rate of greater than 200ksps.

Features 10-bit & 12-bit ADCs at the rate of 200ksps, 14-bit ADCs at 1Msps

Autoscan

Single, Sequence, Repeat-single, Repeat-sequence

Timer triggers

Data Transfer Controller (DTC)

DMA Enabled

Differential input mode

Conversion window comparator

Benefits Fast sample/conversions for greater accuracy

Ultra-Low Power operation:

o Sample data autonomously in Low Power modes – without the CPU!

o Transfer samples to anywhere in memory using the DTC and DMA – all while in Low Power modes!

16- and 24-bit Sigma-Delta ConvertersThe CTSD16 module consists of up to seven independent sigma-delta analog-to-digital converters, referred to as channels. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb-type filters with selectable oversampling ratios of up to 256. Additional filtering can be done in software. The SD24 module consists of up to eight independent sigma-delta analog-to-digital converters. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to 1024. Additional filtering can be done in software.

Features Dedicated 32-bit result registers

Modulation frequency up to 2 MHz

Supports bit stream out/input modes

Auto power-down mode

Flexible clock divider selections

64 and 128 PGA gains

External trigger options available

Can trigger the ADC10 conversions

Benefits Differential inputs - good for AC measurements and eliminates need for level shifting

Simultaneous conversions - no inherent delay between voltage and current samples means SW compensation not required

Built-in PGA - when shunt resistors or Rogowski coils are used, complete dynamic range can be used with any external gain amplifiers

12-bit Digital-to-Analog Converter (DAC)The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be configured in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.

Features 12-bit monotonic

8/12-bit voltage output

Programmable settling time versus power

Int/ext reference

Binary or 2’s compliment

Self-calibration

Group sync load

DMA enabled

Benefits Configurable balance between performance and power

Allows synchronous update operations when multiple modules are available

Output waves while in Low Power standby modes to minimize current consumption!

Analog ComparatorThe Comparator module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals.

Features of the Comparator includes: inverting and non-inverting terminal input multiplexer, software selectable RC- filter for the comparator output, output provided to Timer capture input, software control of the port input buffer, interrupt capability, selectable reference voltage generator, comparator and reference generator can be powered down.

Features Low Power operation

Hysteresis generator (B)

Input multiplexer

Programmable reference generator

Low-pass filter

Interrupt source

Timer_A capture

Programmable performance/power modes to meet high performance requirements, or enable ultra-low power operations

Multiplexer short for sample-and-hold

Benefits Ultra-Low Power operation extends battery life

Enables monitoring of external analog signals

Supports precision slope Analog to Digital Conversions

Analog Pool (A-POOL)Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are complex analog functions that consists of analog and digital components, some types use compensation methods and auto-zero (AZ) mechanisms to eliminate error sources. Modern converters provide automatic range control and other advanced features. A-POOL has none of those complex functions as ready modules; instead, it provides analog and analog-oriented digital elementary functions that can be

used to build complex analog functions like DACs, ADCs, and SVMs of different kinds when combined through software.

Features Software-configurable peripheral that can implement a complete signal chain with the following

building blocks Comparator

8-bit elementary DAC

8-bit ADC

Supply Voltage Monitor

Temperature Sensor

Ultra –low-voltage (256 mV) reference

Benefits Enable flexible and diverse designs

Reduce board size

Form a complete signal chain using one peripheral

Transimpedance Amplifier (TIA)A transimpedance amplifier (TIA) is a high-performance and low-power amplifier with rail-to-rail output. It has programmable power modes to suit different application needs. MSP430FR231x MCUs support a dedicated low-leakage pad for TIA negative input to reduce system current consumption.

Features Current-to-voltage conversion

Half-rail input

Rail-to-rail output

Low-leakage negative input down to 50 pA

Multiple input selection

Configurable high-power and low-power modes

Benefits Reduced bill of materials

Reduced system physical footprint

Direct connectivity to other integratedperipherals for improved signal chain performance

Operational AmplifierThe operational amplifiers (OA) support front-end analog signal conditioning prior to analog-to-digital conversion. The OA is a configurable low-current rail-to-rail operational amplifier. It can be configured as an inverting amplifier or a non-inverting amplifier, or it can be combined with other OA

modules to form differential amplifiers. The output slew rate of the OA can be configured for optimized settling time vs power consumption.

Features Single supply, low-current operation

Rail-to-rail output

Software selectable rail-to-rail input

Programmable settling time vs. power consumption

Software selectable configurations

Software selectable feedback resistor ladder for PGA implementations

Low-impedance ground switches individually software selectable

Benefits Reduced bill of materials

Reduced system physical footprint

Direct connectivity to other integratedperipherals for improved signal chain performance

LCD DriversThe MSP low-power microcontroller portfolio features a broad set of devices with integrated segmented Liquid Crystal Display (LCD) controllers. These controllers include a proven core that has been optimized for low power. Combined with code examples and collateral, these MCUs are ideal for developers new to segmented displays as well as experienced engineers.

Features: Up to 320 Segments

Static upto 8-mux

Individual blinking segment control

Integrated charge pump and resistor ladder to provide multiple voltage levels

Software configuration of pins

Benefits: Extend battery life and reduce Bill of Materials

Maintain contrast in low-power modes

Minimize system size with flexible hardware layout

Inputs / OutputsThe integrated general purpose I/O pins are designed to support a variety of needs dependent upon specific applications or pin configuration settings.

I/O pins may be multiplexed with multiple peripherals providing layout and peripheral flexibility to the

system designer. These features could include serial port, analog input channels or touch-sensitive pin oscillation functionality.

While these microcontrollers typically operate with a core voltage between 1.8-3.6V depending on device, some MCUs have special features to enable an independent DVIO voltage supply to enable direct connection to true 1.8V (+/-10%) or 5V systems. Special I/O pins also support programmable drive strength up to 20mA.

Features Multiple voltage options available for I/O control

1.8V I/Os : directly interface to same voltage I/O logic and sensors

5V I/Os : tolerant push/pull I/Os with up to 20mA drive strength for interfacing to same voltage IC, driving logic level MOSFETs or white LEDs

Capacitive touch I/Os: Each touch sense-enabled I/O has an individually programmable pin oscillator enable bit to enable low-cost touch applications

Programmable glitch-filter for selected pins to improve ESD immunity for interrupt capable pins

Benefits Eliminates level translation circuits, reduced BOM cost

Lower power consumption in overall system such as for sensor hub applications

USBThe MSP Low Power + Performance MCU portfolio offers a broad portfolio of devices with integrated Universal Serial Bus (USB) and up to 512 KB of Flash memory. Development is made easy with the USB Developer’s Package and tools like the MSP430F5529 LaunchPad. TI also offers aUSB Vendor ID sharing program   to help jumpstart development.

Features: Full speed (12 Mbps)

Supports all transfer types except isochronous Multiple endpoints (8 IN and 8 OUT)

USB PHY (transceiver) is fully integrated

Powered by 5V VBUS, through an integrated LDO

As part of USB certification, all MSP430’s have passed all electrical tests.

See this application report for complete list of all MSP430 USB Test ID’s proving certification, or contact the USB-IF

The application report contains a complete hardware reference design

Benefits: Reduce BOM and enable longer battery life

Suited for 99% of USB applications

Enables more USB interfaces in a composite USB device

Perfect for new and experienced USB developers

Wireless Connectivity and Embedded RFMSP’s broad portfolio of microcontrollers allows our customers to innovate and create designs across a wide range of Internet of Things (IoT) applications, whether high performance or ultra low-power. These microcontrollers include system-on- chip solutions as well as software for simple pairing with external radio frequency (RF) transceivers. Software and TI Designs enable the combination of MSP MCUs and RF in complete system solutions. In addition, LaunchPad and BoosterPack hardware modules, development environments and white papers are available to help get your IoT design underway!

Integrated RF: CC430 and RF430 microcontrollers offer the industry’s lowest power, single-chip RF portfolio. These series of devices combine low power with tight integration between the MCU core,peripherals and RF interface.

External RF: TI offers radios including sub-1GHz, 6LoWPAN, Bluetooth® Smart, Wi-Fi®, NFC™   that pair with TI Low-power MCUs.

The Ultra-low-power MSP MCUs, which integrate a power-management system with interrupt handling and FRAM/SRAM for real-time data capture make these devices extremely efficient in IoT applications.

TheLow-Power + Performance MSP MCUs combine 25-MHz 16-bit CPUs or 48-MHz 32-bit ARM® Cortex®-M4 CPUs with high performance analog and the low-power MSP DNA to support consumer, industrial and HealthTechIoT applications with advanced computing requirements.

Register SetsThe width of the memory address bus (MAB) is increased to 20 bits in the MSP430X to address the extended memory but the memory data bus (MDB) remains 16 bits wide. Most of the registers in the CPU of the MSP430X can be used for either data or addresses and have therefore been enlarged to 20 bits as well. The exception is the status register (SR).

Only 9 of its 16 bits are used in the MSP430 but the unused bits are exploited in theMSP430X, as we shall see.

The registers in the CPU of the MSP430X are shown in Figure . Both the programcounter and stack pointer are used only as addresses and are therefore always treated as20-bit registers. In contrast, the status register has only 16 bits. The constant generator andgeneral-purpose registers can handle 8, 16, or 20-bit numbers. This raises a problem withthe terminology. A “word” usually means 16 bits, which remains applicable for data,but an “address word” now contains 20 bits

The general functions of the registers are unchanged from the MSP430. For example, thestack pointer should be initialized to the top of RAM before any functions are called.However, some details of their usage change to accommodate 20-bit values. For example,the current value in the program counter must be stacked when a subroutine is called, This requires a single 16-bit word in the MSP430 following the call instruction, as shown inFigure 11.3(a). The 20-bit PC in the MSP430X requires two words of the stack to hold it,although 12 bits of one 16-bit word are wasted, as shown in Figure 11.3(b). A differentinstruction, calla, must therefore be used unless the whole program fits in the lowest64KB. (In this case you could probably save money with a smaller device.) There is acorresponding return instruction, reta, that retrieves a 20-bit address from the stack ratherthan 16 bits.

Figure 11.3(b) shows that two 16-bit words are needed to store a 20-bit address on thestack and the same is true for main memory: Address words require 4 bytes of storage,12 bits of which are unused. This wastes memory and reduces the effective speed of theprocessor because two cycles are needed to fetch a complete 20-bit address from memory.

In most cases these addresses are parts of instructions and the extended instruction set isdesigned to reduce these overheads.Interrupts are handled in a slightly different way from subroutines. Both the status registerand program counter are stacked in this case, as shown in Figure 6.5 for the MSP430. Theupper 7 bits of the status register are not used and the MSP430X therefore takes over thespace for the top 4 of them to hold the extra 4 bits of the program counter. Figure 11.4shows this. It saves both memory and time, which is particularly important for interrupts.The reti instruction has been updated to match. An interrupt service routine must be situated in the lowest 64KB of the address space because vectors hold only 16-bit addresses but the full 20-bit address is stacked to ensure that execution can resume at any address after the interrupt.

Pull‒Up and Pull‒Down ResistorWhy do we need them?

The pull up and pull down resistors are used for preventing a node from floating. Consider following images.

Fig 1: An Example of Floating node Fig 2: Another Example of Floating Node

So lets consider Fig 1. When the switch is pressed, voltage at input pin will be equal to VCC. But when switch is open (Notpressed), state of input pin is undefined. We can’t be sure about the voltage level of the Input Pin. So we can write the statesof Input Pin based on switch state as:

Similarly for Fig 2 we can write the table as

So we can see that, if we use the Switch as input device to a microcontroller in these configuration, the device is going to facesome undefined states (Floating State). So it may lead to ambiguous readings from the switch. Everyone connecting a switchto a microcontroller must avoid theseconfiguration for their switches.

Pull Down Resistor:

Pull down resistor will pull a floating node to logic level low i.e. 0. So after connecting to a Pull down resistor the Fig 1 will looklike as follow:

So now we connected a very High value resistor from the floating node to Ground. Lets see how its going to help us.

Switch ̲State Input ̲Pin ̲StateOpen(Not Pressed) UndefinedClosed (Pressed) High (Equal to

Switch ̲State Input ̲Pin ̲StateOpen(Not Pressed) UndefinedClosed (Pressed) Low (Equal to

Switch ̲State Input ̲Pin ̲StateOpen(Not Pressed) LowClosed (Pressed) High (Equal to VCC)

When the switch is in Open state the resistor will try to pull down the node to Ground level. Hence it is named as Pull DownResistor.

Pull Up Resistor:

By now you must have guessed the use of pull up resistor. The pull up resistor pulls up the floating node to a High logic value

Here the resistor R1 will serve the purpose of pulling the Input Pin high when the switch is not pressed. But now the Voltageat Input Pin will be slightly less than VCC based on your R1 value. But as you are using it as input to a Microcontroller, so it isnot going to cost you in terms of errors as for Digital Devices there is a threshold between High and Low level. Every othervariation is not of much use. So the table for switch with pull up resistor will be

Can I eliminate Resistor?

No you can’t. If you are thinking of providing two different state by directly connecting the two pins of Switch to two differentlogic levels then believe me you are going to do a blunder. Yes, your guess is right, the Input Pin will not be in a Floating Statenow when the switch is not pressed. But as soon as you are going to press the switch, the VCC node will be shorted to Groundand you circuit will go down.

So what is difference in using either of them?

Not much. As you might have observed in their truth table that both configurations are opposite in Logic Level. So for Switchconfiguration with Pull Up resistor you have to read logic low to know

Switch ̲State Input ̲Pin ̲StateOpen(Not Pressed) HighClosed (Pressed) Low (Equal to GND)

when the switch is pressed. Opposite is the case withthe Pull Down Configuration. In this case you have to read High logic level to know when the switch is pressed

GPIO Philosophy

The MSP430 uses a limited number of GPIO hardware pins that are assignable to several functions depending on your specific model and your program's needs. Our version, the MSP430G2231, can have the Port_1 pins act as digital output, digital input, or ADC input. The pins are organized into ports, with each port usually one byte (8 bits/pins) wide. On larger versions of the processor (different format chips with physically many more pins...) you can encounter several ports, but in this lab you will only be using Port_1 and Port_2 You can set each pin's function independently (input or output) by modifying some memory mapped I/O registers. Since we want to do both, we will divide P1 into half inputs and half outputs as needed.UsageThe I/O ports are memory mapped into the top of the MSP430 address space. There are several registers associated with each port. For now, you only need to worry about four (P1IN, P1OUT, P1DIR, and P1REN).

P1IN

The P1IN register is located at address 0x0020 in memory, which you can also refer to using the C symbol &P1IN The register holds the values the MSP430 sees at each pin, regardless of the pin direction setting. To read the register, it is good practice to use a mov.b instruction to avoid accidentally reading adjacent registers

Tip: If you are looking to test or read just the pins set to input, you will have to mask the P1IN register to zero out the other unwanted/output pins. Reading P1IN reads the entire port, regardless of pin direction.

P1OUT

The P1OUT register is located at address 0x0021 in memory, which you can also refer to using the C symbol &P1OUT If their direction bits in P1DIR are set to output/ "1", the corresponding pins will output the values set in P1OUT. If a pin's direction bits are set to input in P1DIR and its resistors are enabled in P1REN, P1OUT controls the pin's connection to the pull-up resistor. Setting P1OUT to "1" enables the pull-up, while setting it to "0" leaves the input to float in a high impedance state. To set P1OUT, use a mov.b instruction to set several pins at once. To set individual bits to "1", you can use an or.b instruction with a "1" in the positions you want to set. To clear individual bits/ set them to zero, use an and.b instruction with mostly "1"s except for a "0" for the bits you want to clear.

P1DIR

The P1DIR register is located at address 0x0022 in memory, which you can also refer to using the C symbol &P1DIR The value of the bits in P1DIR determines whether the MSP430 hardware leaves the pin in a high impedance state where it responds to external voltage changes (which you can read at P1IN), or in a low impedance state where the MSP430 drives the output voltage to a certain value determined by P1OUT. To set the bit directions all at once, use a mov.b instruction,

but to change individual bits regardless of the others, use an and.b or a or.b Set the corresponding bits to "0" to set pins to input mode, or to "1" to set them to output mode.

P1REN

The P1REN register is located at address 0x0027 in memory, which you can also refer to using the C symbol &P1REN P1REN controls whether the MSP430 Launchpad enables the integrated pull-up resistor for a given pin. The pull-up resistors allow the use of single pole switches. They prevent the input signals from floating randomly while the switches are open by loosely tying the inputs to Vcc. When the switch is closed though, the much stronger connection to ground wins out, pulling the inputs down to GND. Set the corresponding bits to "1" to enable a pin's pull-up resistor, or to "0" to disable it (disabled by default).

Outputs

Setting up the outputs is easy-- simply set the upper four bits (bits 4-7) of &P1DIR to "1", and then write the output to the upper four bits of &P1OUT. That means you'll have to shift your data left 4 positions before output, but you should already know a simple technique to do so!

Aside: You'll notice that when you change the output, the corresponding input bits also change. This happens because the input hardware always reads the status of the line, regardless if it is set to input our output. Changing the &P1DIR values only connects or disconnects the driving circuitry built into the MSP430. In advanced applications this can be used to analyze potential faults in the circuitry outside the chip.

Inputs

Inputs are also "easy," but there are a few hardware concepts you'll need before you understand how they work!

A Little Bit About Wires:- binary digital logic has two valid states, plus one third mystery state. That third state, "The High Impedance State," (High-Z) just means that the wire isn't connected to anything.

Aside: Impedance is a generalized form of the classical Resistance concept. Impedances can be real or complex valued, and apply too signals expressed in complex exponential form (whether constant or variable!).

In order to read useful input from your switches, you need them to be "0" in one state, and "1" in the other. Yet knowing what you know about the third state, the switch shown above will actually give a "0"/"1" (depending on what you connect it to) when closed and "High-Z" when open. Because there's nothing else driving the sensor input besides our switch, the input value will be random when the switch is open. In digital logic this is called floating, and it is a very very bad thing. One simple solution is the Pull-Up (or Pull-Down) Resistor. Connecting the floating side of the switch to a logic level through a large resistor will tie down the floating input when the switch is open, but won't effect the read value much when the switch is closed.

Pull-Ups in the MSP430For better or for worse, the MSP430 actually has pull up resistors already built into the chip's hardware. Configuring them takes several steps, but once setup they provide all the functionality above without the extra external connections.

* Set the Pin Direction for P1.0-P1.3 to input. (Set bits 0-3 of &P1DIR to "0")

* Enable the resistors themselves. (Set bits 0-3 of &P1REN to "1")

* Configure the resistors to be pull-up. (Set bits 0-3 of &P1OUT to "1")

Important: The most confusing part of the whole process is the double function of P1OUT. Because of the hardware implementation on the MSP430, &P1OUT controls the outputs as well as the connections to the pull up resistors. You will need to ensure that every time you output a value, you KEEP the lower four bits "1". The easiest way to do this is just by ORing your raw output with the constant #0Fh before you write to P1OUT. The MSP430 does not have a specific "or" instruction by name, but bis does the same thing. For more info on bis and its inverse bic

Polling

Philosophy - A traditional single threaded polling scheme consists of a main loop that runs continuously. Within that loop, the processor periodically checks for changes, and if there are none, continues looping. Once a change is detected, the program moves to a new section of code or calls a new subroutine to deal with the changes.

Polling has advantages and disadvantages-- it keeps program execution linear and is very easy to code and implement, but it also is not incredibly responsive. Since polling only checks values at

certain points in the main run loop, if the loop is long or changes occur quickly, a polling scheme can miss input data. For now though it will suffice.

GPIO program to blink LED(P1.0) when button(P1.1) is pressed#include <msp430.h>

int main(void) {

WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

P1DIR |= 0x01; //set button pin(P1.1) to output

P1REN |= 0x02; //enable pull up resistance for button(P1.1)

while(1){ //infinite loop

if(P1IN & BIT1){ //if button is not pressed

P1OUT &= ~BIT0; //turn off LED

}else{

P1OUT |= BIT0; //turn on LED

}

}

return 0;}

Interrupts and Interrupt programmingInterruptsThey are like functions but with the critical distinction that they are requested by hardware at unpredictable times rather than called by software in an orderly manner. (Well, a periodic interrupt should be highly predictable in real time, but this is not apparent to the CPU.) Interrupts are commonly used for a range of applications:Urgent tasks that must be executed promptly at higher priority than the main code. However, it is even faster to execute a task directly by hardware if this is possible.Infrequent tasks, such as handling slow input from humans. This saves the overhead of regular polling.Waking the CPU from sleep. This is particularly important in the MSP430, which typically spends much of its time in a low-power mode and can be awakened only by an interrupt.Calls to an operating system. These are often processed through a trap or software interrupt instruction but the MSP430 does not have one. A substitute is for software to set an unused interrupt flag for one of the peripherals, such as port P1 or P2.The code to handle an interrupt is called an interrupt handler or interrupt service routine (ISR). It looks superficially like a function but there are a few crucial modifications. The feature that interrupts arise at unpredictable times means that an ISR must carry out its action and clean up thoroughly so that the main code can be resumed without error—it should not be able to tell that an interrupt occurred. Interrupts can be requested by most peripheral modules and some in the core of the MCU,such as the clock generator. Each interrupt has a flag, which is raised (set) when the condition for the interrupt occurs. For example, Timer_A sets the TAIFG flag in the TACTL register when the counter TAR returns to 0.We polled this flag to pace the loop in the section “Automatic Control: Flashing a Light by Polling Timer_A” on page 105. Each flag has a corresponding enable bit, TAIE in this case. Setting this bit allows the module to request interrupts.

Most interrupts are maskable, which means that they are effective only if the general interrupt enable (GIE) bit is set in the status register (SR). They are ignored if GIE is clear. Therefore both the enable bit in the module and GIE must be set for interrupts to be generated. The (non)maskable interrupts cannot be suppressed by clearing GIE. The reason for the parentheses around (non) is that these interrupts also require bits to be set in special function or peripheral registers to enable them. Thus even the (non) maskable interrupts can be disabled and indeed all are disabled by default. I drop the parenthesesaround non for clarity.

The MSP430 uses vectored interrupts, which means that the address of each ISR—its vector—is stored in a vector table at a defined address in memory. In most cases each vector is associated with a unique interrupt but some sources share a vector. The ISR itself must locate the source of interrupts that share vectors. For example,

TAIFG shares a vector with the capture/compare interrupts for all channels of Timer_A other than 0. Channel 0 has its own interrupt flag TACCR0 CCIFG and separate vector.

Interrupts must be handled in such a way that the code that was interrupted can be resumed without error. This means in particular that the values in the CPU registers must be restored. The hardware can take two extreme approaches to this:Copies of all the registers are saved on the stack automatically as part of the process for entering an interrupt. This is done in the Freescale HCS08, for example, which is a CISC and has only a few registers. The disadvantage is the time required, which means that the response to an interrupt is delayed. An alternative is to switch to a second set of registers, which is done in the Z80 and descendants.The opposite approach is for the hardware to save only the absolute minimum, which is the return address in the PC as in a subroutine. This is much faster but it is up to the user to save and restore values of the critical registers, notably the status register. The Microchip PIC16 takes this approach, consistent with its minimalist philosophy.

What Happens when an Interrupt Is Requested?1. Any currently executing instruction is completed if the CPU was active when the interrupt was requested. MCLK is started if the CPU was off.2. The PC, which points to the next instruction, is pushed onto the stack.3. The SR is pushed onto the stack.4. The interrupt with the highest priority is selected if multiple interrupts are waiting for service.5. The interrupt request flag is cleared automatically for vectors that have a single source. Flags remain set for servicing by software if the vector has multiple sources, which applies to the example of TAIFG.6. The SR is cleared, which has two effects. First, further maskable interrupts are disabled because the GIE bit is cleared; nonmaskable interrupts remain active. Second, it terminates any low-power mode.7. The interrupt vector is loaded into the PC and the CPU starts to execute the interrupt service routine at that address.This sequence takes six clock cycles in the MSP430 before the ISR commences. The stack at this point is shown in Figure 6.5. The position of SR on the stack is important if the low-power mode of operation needs to be changed.

Interrupt programming:1.Example port1 interrupt

#include <msp430x20x3.h>

void main(void)

{

WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

P1DIR |= 0x01; // Set P1.0 to output direction

P1IE |= 0x10; // P1.4 interrupt enabled

P1IES |= 0x10; // P1.4 Hi/lo edge

P1IFG &= ~0x10; // P1.4 IFG cleared

_BIS_SR(LPM4_bits + GIE); // Enter LPM4 w/interrupt

}

// Port 1 interrupt service routine

#pragma vector=PORT1_VECTOR

__interrupt void Port_1(void)

{

P1OUT ^= 0x01; // P1.0 = toggle

P1IFG &= ~0x10; // P1.4 IFG cleared

}

2. Example timer interrupt

#include <msp430x20x3.h>

void main(void)

{

WDTCTL = WDTPW + WDTHOLD; // Stop WDT

P1DIR |= 0x01; // P1.0 output

TACTL = TASSEL_2 + MC_2 + TAIE; // SMCLK, contmode, interrupt

_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt

}

// Timer_A3 Interrupt Vector (TAIV) handler

#pragma vector=TIMERA1_VECTOR

__interrupt void Timer_A(void)

{

switch( TAIV )

{

case 2: break; // CCR1 not used

case 4: break; // CCR2 not used

case 10: P1OUT ^= 0x01; // overflow

break;

}

}

Watchdog Timer: Ref. John H Davis text bookWDT can be used in two modes:

Supervision mode• Ensure correct working of software program• Perform PUC• Generate interrupt when counter overflows

Interval timerIndependent timer generates standard interrupt when counter overflows periodicallyWDTCNT is not directly accessible to the userWDT controlled by WDTCTL register

The main purpose of the watchdog timer is to protect the system against failure of the software, such as the program becoming trapped in an unintended, infinite loop. Left to itself, the watchdog counts up and resets the MSP430 when it reaches its limit. The code must therefore keep clearing the counter before the limit is reached to prevent a reset.

The operation of the watchdog is controlled by the 16-bit register WDTCTL. It is guarded against accidental writes by requiring the password WDTPW = 0x5A in the upper byte. A reset will occur if a value with an incorrect password is written to WDTCTL. This can be done deliberately if you need to reset the chip from software. Reading WDTCTL returns 0x69 in the upper byte, so reading WDTCTL and writing the value back violates the password and causes a reset.The lower byte of WDTCTL contains the bits that control the operation of the watchdog timer, shown in Figure 8.1. The RST/NMI pin is also configured using this register, which you must not forget when servicing the watchdog—we see why shortly. Most bits are reset to 0 after a power-on reset (POR) but are unaffected by a power-up clear (PUC). This distinction is important in handling resets caused by the watchdog. The exception is the WDTCNTCL bit, labeled r0(w). This means that the bit always reads as 0 but a 1 can be written to stimulate some action, clearing the counter in this case.

The watchdog counter is a 16-bit register WDTCNT, which is not visible to the user. It is clocked from either SMCLK (default) or ACLK, according to the WDTSSEL bit. The reset output can be selected from bits 6, 9, 13, or 15 of the counter. Thus the period is 26 = 64, 512, 8192, or 32,768 (default) times the period of the clock. This is controlled by the WDTISx bits in WDTCTL. The intervals are roughly 2, 16, 250, and 1000 ms if the watchdog runs from ACLK at 32 KHz. The watchdog is always active after the MSP430 has been reset. By default the clock is SMCLK, which is in turn derived from the DCO at about 1 MHz. The default period of the watchdog is the maximum value of 32,768 counts, which is therefore around 32 ms. You must clear, stop, or reconfigure the watchdog before this time has elapsed. In almost all programs in this book, I take the simplest approach of stopping the watchdog, which means setting the WDTHOLD bit. This goes back to the first program to light LEDs, Listing 4.2. If the watchdog is left running, the counter must be repeatedly cleared to prevent it counting up as far as its limit. This is done by setting the WDTCNTCL bit in WDTCTL. The task is often called petting, feeding, or kicking the dog, depending on your attitude toward canines. The bit automatically clears again after WDTCNT has been reset. The MSP430 is reset if the watchdog counter reaches its limit. The watchdog causes a power-up clear, which is the less drastic form. Most registers are reset to default values but some retain their contents, which is vital so that the source of the reset can be determined. The watchdog timer sets the WDTIFG flag in the special function register IFG1. This is cleared by a power-on reset but its value is preserved during a PUC. Thus a program can check this bit to find out whether a reset arose from the watchdog. Listing 8.1 shows a trivial program to demonstrate the watchdog. I selected the clock from ACLK (WDTSSEL = 1) and the longest period (WDTISx = 00), which gives 1s with a 32 KHz crystal for ACLK. It is wise to restart any timer whenever its configuration is changed so I also cleared the counter by setting the WDTCNTCL bit. LED1 shows the state of button B1 and LED2 shows WDTIFG. The watchdog is serviced by rewriting the configuration value in a loop while button B1 is held down. If the button is left up for

more than 1s the watchdog times out, raises the flag WDTIFG, and resets the device with a PUC. This is shown by LED2 lighting.

Program wdtest1.c to demonstrate the watchdog timer.// ----------------------------------------------------------------------#include <io430x11x1.h> // Specific device// Pins for LEDs and button#define LED1 P2OUT_bit.P2OUT_3#define LED2 P2OUT_bit.P2OUT_4#define B1 P2IN_bit.P2IN_1// Watchdog config: active , ACLK /32768 -> 1s interval; clear counter#define WDTCONFIG (WDTCNTCL|WDTSSEL)// Include settings for _RST/NMI pin here as wellvoid main (void){WDTCTL = WDTPW | WDTCONFIG; // Configure and clear watchdogP2DIR = BIT3 | BIT4; // Set pins with LEDs to outputP2OUT = BIT3 | BIT4; // LEDs off (active low)for (;;) { // Loop foreverLED2 = ˜IFG1_bit.WDTIFG; // LED2 shows state of WDTIFGif (B1 == 1) { // Button upLED1 = 1; // LED1 off} else { // Button downWDTCTL = WDTPW | WDTCONFIG; // Feed/pet/kick/clear watchdogLED1 = 0; // LED1 on}}}

System clocks:All microcontrollers contain a clock module to drive the CPU and peripherals. The conflicting requirements for clocks in high-performance, low-power microcontrollers were described in the section “Clock Generator” on page 33. Figure 5.8 shows a simplified diagram of the Basic Clock Module+ (BCM+) for the MSP430F2xx family. I concentrate on this because it is the most recent design; I mention the extra features of the MSP430x4xx later. The details vary between devices, even in the same family, and the second crystal oscillator XT2 is often omitted. Recall that the clock module provides three outputs:Master clock, MCLK is used by the CPU and a few peripherals.Sub-system master clock, SMCLK is distributed to peripherals.Auxiliary clock, ACLK is also distributed to peripherals.

Most peripherals can choose either SMCLK, which is often the same as MCLK and in the megahertz range, or ACLK, which is typically much slower and usually 32 KHz. A few peripherals, such as analog-to-digital converters, can also use MCLK and some, such astimers, have their own clock inputs. The frequencies of all three clocks can be divided in the BCM+ as shown in Figure 5.8. For example, you might wish to run the CPU at 8MHz for rapid execution of code and therefore choose fMCLK = fDCOCLK = 8MHz. On the other hand, it may be more convenient if the peripherals run from a slower clock, in which case you might configure the divider for SMCLK with DIVSx to give fSMCLK = fDCOCLK/8 =1MHz. Mostperipherals have their own dividers for their clock sources, which gives yet more control. Up to four sources are available for the clock, depending on the family and variant:Low- or high-frequency crystal oscillator, LFXT1: Available in all devices. It is usually used with a low-frequency watch crystal (32 KHz) but can also run with a high-frequency crystal (typically a few MHz) in most devices. An external clock signal can be used instead of a crystal if it is important to synchronize the MSP430 with other devices in the system.

High-frequency crystal oscillator, XT2: Similar to LFXT1 except that it is restricted to high frequencies. It is available in only a few devices and LFXT1 (or VLO) is used instead if XT2 is missing.Internal very low-power, low-frequency oscillator, VLO: Available in only the more recent MSP430F2xx devices. It provides an alternative to LFXT1 when the accuracy of a crystal is not needed.Digitally controlled oscillator, DCO: Available in all devices and one of the highlights of the MSP430. It is basically a highly controllable RC oscillator that starts in less than 1 _s in newer devices.

Crystal Oscillators, LFXT1 and XT2Crystals are used when an accurate, stable frequency is needed:Accurate means that the frequency is close to what it says on the package, typically within 1 part in 105.Stable means that does not change significantly with time or temperature.Crystals are cut from carefully grown, high-quality quartz with specific orientations to give them high stability. Traditional crystals oscillated at frequencies of a few MHz but most small microcontrollers use low-frequency watch crystals with a frequency of 32 KHz. These are machined into complicated tuning fork shapes to give the low frequency. A disadvantage is that their frequency is more sensitive to temperature than high-frequency crystals, but they are designed to be most stable near 25◦C. A change of 10◦C in the temperature causes the frequency to fall by about 4 parts per million (ppm). Detailedspecifications are given by the manufacturers, such as Micro Crystal.

Internal Low-Power, Low-Frequency Oscillator, VLOThe VLO is an internal RC oscillator that runs at around 12 KHz and can be used instead of LFXT1 in some newer devices. It saves the cost and space required for a crystal and reduces the current drawn. The data sheet for the F2013 shows that LFXT1 draws about 0.8_A, which falls to 0.5_A with the VLO. (Both are impressively

small currents.) Of course this comes at a cost: accuracy and stability. The same data sheet quotes a range of frequency for fVLO from 4 to 20 KHz. This looks terrible at first sight but closer reading shows that it covers the full operating range of the device in voltage and temperature. A variation of 10◦C changes the frequency by about 5% instead of 5 ppm for a crystal. Clearly you would not use the VLO for serious timing. On the other hand, its purpose is often to wake the device periodically to check whether any inputs have changed, and accuracy is not important. ACLK is taken from LFXT1 by default even where the VLO is present. This means that current is wasted in LFXT1 and that pins P2.6 and P2.7 in the F20xx are configured for a crystal. It is usually a good idea to reconfigure the BCM+ to use the VLO and redirect port 2 for digital input/output.

Digitally Controlled Oscillator, DCOOne of the aims of the original design of the MSP430 was that it should be able to start rapidly at full speed from a low-power mode, without waiting a long time for the clock to settle. Early versions of the DCO started in 6_s, which has been reduced to 1–2_s in the MSP430F2xx family. There are no erratic pulses: The output from the DCO starts cleanly after this delay. The stability and accuracy also improved significantly since the early days. The frequency can be controlled through sets of bits in the module’s registers at three levels. The numbers are taken from the data sheet for the F2013. The first two levels setthe DCO to a constant frequency:RSELx: Selects one of 16 coarse ranges of frequency. The frequencies in each range are larger than those in the one below by a factor of 1.3–1.4. The overall range is about 0.09–20 MHz.DCOx: Selects one of eight steps within each range. Each step increases the frequency by about 8%, giving a factor of 1.7 from bottom to top of the range. Thus the ranges overlap slightly.Frequency-Locked Loop, FLL+The MSP430x4xx family has the more sophisticated FLL+ clock module. Much of this, such as LFXT1 and XT2, is similar to the MSP430F2xx but the registers and bits have different names. For example, the load capacitance for a low-frequency crystal is controlled by the XCAPxPF bits in the FLL_CTL0 register. There are no dividers for the internal clocks but the external signal from ACLK can be divided.The main difference is of course the frequency-locked loop. This is hardware that aims to lock the frequency of the DCO to that of LFXT1. The DCO in the FLL+ has only five ranges but each covers a factor of about 10 in frequency and is divided into 29 taps. The modulator works in the same way as that in the BCM+. The name makes the FLL sound complicated but its basic mode of operation is simple. It relies on a feedback loop shown in Figure 5.11:

The range of the DCO is set with the FN_x bits and modulation may be suppressed by setting SCFQ_M. Its output is at a frequency fDCO.This is divided by a factor D specified with the FLLDx bits. This gives a frequency of fDCO/D.The divided signal is fed into a counter with a period of (N +1), where N is stored in the lower 7 bits of SCFQCTL.The counter overflows at a frequency of fDCO/[D(N +1)], which is compared with the frequency of ACLK.The controller adjusts fDCO one step up or down with the aim of bringing these frequencies together.

Thus the frequency of the DCO itself is given by fDCO = D(N +1)fACLK when the loop has locked but this is not necessarily the frequency of the output. DCOCLK can be taken either before or after the divider according to the setting of the DCOPLUS bit. When this bit is clear, the divided output is taken andfDCOCLK = (N +1)fACLK (DCOPLUS = 0). This does not depend on D. When DCOPLUS is set,fDCOCLK = D(N +1)fACLK (DCOPLUS = 1).

The MSP430 was designed from the outset for low power and this is reflected in a range of low-power modes of operation. There are five in all but two are rarely employed in current devices (they were useful with earlier versions of the DCO). The most important modes are summarized here with typical currents I for the F2013 taken from its data sheet.These are for VCC = 3V, the DCO running at 1 MHz, and LFXT1 at 32 KHz from a crystal. The current in active mode rises with frequency to about 4mA at 16 MHz, although this requires a higher supply voltage.Active mode: CPU, all clocks, and enabled modules are active, I ≈ 300_A. The MSP430 starts up in this mode, which must be used when the CPU is required. Aninterrupt automatically switches the device to active mode. The current can be reduced by running the MSP430 at the lowest supply voltage consistent with the frequency of MCLK; VCC can be lowered to 1.8V for fDCO = 1MHz, giving I ≈ 200_A.LPM0: CPU and MCLK are disabled, SMCLK and ACLK remain active, I ≈ 85_A. This is used when the CPU is not required but some modules require a fast clock from SMCLK and the DCO.LPM3: CPU, MCLK, SMCLK, and DCO are disabled; only ACLK remains active; I ≈ 1_A. This is the standard low-power mode when the device must wake itself at regular intervals and therefore needs a (slow) clock. It is also required if the MSP430 must maintain a real-time clock. The current can be reduced to about 0.5_A by using the VLO instead of an external crystal in a MSP430F2xx if fACLK need not be accurate.

LPM4: CPU and all clocks are disabled, I ≈ 0.1_A. The device can be wakened only by an external signal. This is also called RAM retention mode.

It is common to describe a device as sleeping when it is in a low-power mode, although this is a little vague in the MSP430 with its range of modes. Similarly, waking means that the device returns to active mode. Many processors are put into low-power modes by issuing special sleep or stop instructions but these are not required with the MSP430. Instead its operation is controlled through the four bits: SCG0, SCG1, CPUOFF, and OSCOFF in the status register. All these are clear in active mode and particular combinations are set for each low-power mode. For example, setting only CPUOFF disables the CPU and MCLK, putting the MSP430 into LPM0.

Active vs Stand-By current consumption

Explain this topic with using low power modes table and clock sources in that table( which is present in above topic)

FRAM vs Flash

IntroductionWhat makes a microcontroller a microcontroller? That’s part of this chapter’s discussion. Theinclusion of memory – especially non-volatile memory – makes a microprocessor into amicrocontroller.Non-volatile memory (NVM for short) is an important part of a microcontroller’s memory system;this type of memory stays initialized (i.e. keeps its data) even when power is removed from thedevice. Storing program code is the most obvious use of NVM, though many applications storedata tables and calibration data in NVM, as well.Flash technology is the most common type of NVM used in today's microcontrollers. In the lastcouple of years, though, Texas Instruments has introduced the use of FRAM technology into theirMSP430 microcontroller family. With near infinite write cycles and extremely low power

dissipation, it is a great fit for many end applications.

Non-Volatile Memory: Flash & FRAM

Non-Volatile Memory (NVM) retains its information, even when power is removed. This is differentthan RAM (e.g. SRAM, DRAM) memory which loses its information when powered down.NVM is important for storing your microcontroller’s code. It doesn’t do much good to write thecode into a microcontroller if it disappears whenever the processor is turned off. Microprocessorssolve this problem by using external non-volatile memory, which has to be loaded up each timethe processor starts up. This is unattractive in many applications since it raises the cost and

greatly increases start-up time.

Users really needed a way to program (and erase) their processor memories themselves. Thisneed has driven a number of enhancements in NVM since the early days of ROM’s.MCU’s adopted Erasable/Programmable Read-Only Memory (EPROM). These devices had alittle window over the silicon that allowed the user to erase the program with a UV light. The codecould be programmed electrically with a special stand-alone programmer. Due to a demand forlow-cost, EPROM chips ended up being packaged in plastic without a window; these werecommonly known as OTP’s – for one-time programmables.

Nowadays, Flash memory technology is used by most microprocessors. This allows processorsto be programmed – and erased – electronically. Companies can purchase “empty” devices andprogram them on their own; erasing them and re-programming, as needed.While Flash was a major step forward in NVM technology, it has a few limitations, such as powerhungrywrites and limited endurance (i.e. the number of times you can erase and re-write thememory).

FRAM technology, which has been available for a decade in stand-alone devices, is nowavailable from Texas Instruments in their MSP430 line-up. With low-power in its DNA, FRAM

technology is a natural fit for many MSP430 applications.

Flash MemoryFlash memory made it cheap and convenient to create microcontrollers that were electrically

erasable and programmable.

How do flash devices work? In a nutshell, they use the concept of a floating gate transistor.Usually a transistor is “off” or “on” depending upon the value applied at its control gate. Applypower to the gate and it causes electrons to flow from the source to the drain; take the poweraway from the gate and the electricity stops.Flash memories use floating gates that are “sticky”; that is, they can “remember” their value. Bysubmerging the floating gate in a sea of dielectric, its charge value takes a very long time(hundreds of years+) to leak away.But, if it takes a long time to lose their value, how do you program a new value into them? Youmust use a very high voltage – somewhere around 14 Volts – to program a new value into them.Since most MCU’s run off of 5 Volts (or less), single-chip MCU manufacturer’s embed chargepumps into them to generate the voltages required.Even with the need for this extra high-voltage circuitry, flash memories have served the industryquite well. Many of the MSP430 devices, such as the MSP430F5529 utilize flash non-volatile

memory.