6

- to remove this inconvenience the BnZS (bipolar with n zeros substitution) code was developed.

- the encoding rule is identical to the one of the AMI code, except for “0”-bit sequences longer or equal to

n, a natural number. Should such a sequence occur, it is replaced by a completion sequence.

- for n = 6, the completion sequence is 0VB0VB, see figure 10:

0 - “0”-bit coded with 0 volts

V – “1”-bit coded with a +/- A level that violates the AMI encoding rule

B - “1”-bit coded with a +/- A level that observes the AMI encoding rule

- the violations of the AMI encoding rule are employed for the identification of these sequences at the

receiving end, where they should be replaced by n-bit “0” sequences.

- The power spectral density of the BnZs code is distributed similarly to the one of the AMI code

- other codes developed to improve the synchronization capability of the AMI code are the HDB3

(high-density bipolar-3 zeros) and 4B3T (4-binary, 3-ternary.

The MLT-3 code – see the notes on the blackboard

Implementation of the BB encoding – this section will be used in the laboratory classes and is presented

in Annex 1 of this material

Decoding of the baseband codes

- the biphase-S code

- the decoding of the biphase–S code is based on the encoding equations (3).

- considering that bit bk+1 was encoded during the half-periods 2k+1 and 2k+2 of the bit-clock;

- using (3) and performing the additions for three half-periods separated by a bit-period, we get (4).

- the bit bk+1, encoded during half-periods 2k+1 and 2k+2, is decoded during half-periods 2k+2 and 2k+3,

inserting a half bit-period delay.

- the decoding of the next data bit bk+2 is started during the 2k+4 interval.

b b b k 1 b b k 1 b k 1 k 1

b b b b b k 1 b k 1

b b b k 2 b b k 2 b k

s (2k 2) s (2k) s (2k 1) b s (2k) s (2k) b s (2k) 1 b b ;

s (2k 3) s (2k 1) s (2k 2) s (2k 1) s (2k 1) b s (2k 1) b ;

s (2k 4) s (2k 2) s (2k 3) b s (2k 2) s (2k 2) b s (2k 2) 1 b

+ + + +

+ +

+ +

+ ⊕ = + ⊕ ⊕ = ⊕ ⊕ = ⊕ =

+ ⊕ + = + ⊕ + = + ⊕ ⊕ + =

+ ⊕ + = + ⊕ ⊕ + = + ⊕ ⊕ + = ⊕ 2 k 2b ;+ +=

(4)

- the decoding of the Miller code is accomplished by similar additions, that employ signals delayed with 1,

2, 3 and 4 bit half-bit periods.

- the decoding of the CMI code is performed by adding modulo 2 the coded signals delayed with one half-

bit period.

- for all three codes, the signals resulted from the summation circuits should be “sampled” with a bit clock,

with frequency fbit, whose phase differs from code to code.

- the biphase and CMI codes the sampling bit-clock should be shifted with 270º, compared to the bit clock

obtained by dividing by 2 the fsincro clock delivered by the dynamic synchronization circuit.

- for the Miller code the sampling clock has to be shifted with 90º compared to the same reference signal

Considerations regarding the implementation of the BB decoding – these section is intended for the

laboratory classes and is presented in Annex 2 of this material

Block diagram of a baseband modem

- it is presented in figure 11

- the TxD are delivered to the encoder, using the bit clock Tx Ck delivered by the Oscillator-Divider

block. The desired BB code is selected by the internal control “Code Type”.

- the encoded signal is sent to the line unit which transfers the signal into the physical signal.

- the Transmission Control block is commanded by the RTS interface signal; it sends back to the

computer the confirmation CTS signal, after the RTS/CTS time interval, while delivering to the encoder

the synchronization sequence. - depending on the 2w/4w connection, one or two pairs of twisted wires are employed.

- for the 2w half-duplex operation, the transmission has priority, the Transmission Control circuit disabling

the receiver’s input stage when the RTS signal is active. On the 4w full-duplex operation this conditioning

is not applied.

- the input stage ensures the transfer from symmetrical to asymmetrical circuit, the amplification and

filtering of the received signal and the equalization of the attenuation inserted by the wires.

7

- the signal is then limited and used, as a reference signal, by the synchronization circuit, which delivers the

fsincro clock, required by the demodulator and the receive clock RxCk

- the limited signal is also sent to the decoder, together with the fsincro clock, for the “extraction” of the

received data RxD.

- the signal delivered by the input stage is employed by the Carrier Detector block, which monitors the level

of the input signal and enables/disables the receiver if its level is higher/smaller than some preset levels; this

bloc delivers to the computer the CD interface signal.

- the modem may contain circuits that implement the test loops, scramble-descrambler and circuits for the

generation and analysis of the test data; these circuits were not inserted in fig. 12.

Error probability of the BB transmissions

- the frequency band available on the physical channels is usually larger than the useful BW of the BB-

coded signals, therefore an input filtering is required for the improvement of SNR.

- because the useful bandwidth differs between codes there are two options:

1. with an adaptable BP filter that changes the passing band in terms of the code employed

2. with a BP filter that has a BW equaling the BW of the biphase coded signal (which is the largest).

- the transmission codes presented in this chapter are either 2-level codes (+/-A; M = 2), i.e. biphase,

Miller and CMI, or 3-level codes (+/-A, 0V; M = 3), i.e. AMI, BnZs, HDB3 and 4B3T.

- the average signal power Ps, for the two types of codes is given by 5. a and 5. b, respectively, and the

power of the Gaussian noise, with a N0 power spectral density, at the output of the input filter with a

BW = Bf is given by 5.c:

Ps2 = A2; a. Ps3 = A

2/2; b. Pz = BWf · N0; c. (5)

- we assume that the received signal is affected by the a Gaussian noise of null mean and variance σ ,

which is added to the useful signal, i.e.:

( ) ( ) ( )trr t s t n t= + (6)

- Therefore, the probability that the received signal would equal r at the sampling moment, if the

transmitted level was m is:

( )( )

2

2

r m1p r | m exp ;

22

−= −

σπ ⋅σ (7)

- Since the decided levels are obtained based on the minimum Euclidean distance between the received

level and the permitted levels, the symbol(bit)-error probability equals the occurrence probability of a

noise amplitude which makes the level of the received signal to be closest to a permitted level that

differs from the level that was transmitted in that symbol period.

- If within a symbol period level mk is transmitted, with probability Pmk, then the probability to have that

symbol erred after the decision is given by (8), where Nk,A is the number of permitted levels that are

placed at a distance 2A0 from the level mk and A0 is half of the minimum distance between two

transmitted levels.

T r a n s. C o n tr o l

C o d e r

L in e U n i t

O s c . D iv .

D e c o d e r

C .D .

S yn c h r o n iz a tio n

In p u t

s t a g e + E Q .

L

I

M

R T S

C T S

T x D

T x C k

R x C k

R x D

C D

fb it

f a t a c

C E C o d e S e le c Ń

C o d e d s ig n a l

fb it

f s in c ro - lo c a l

R e c e i v e d s ig n a l - l im ite d

4 w - T x

4 w - R x 4 w

2 w

2 w

f a ta c

Figure 11. Simplified block diagram of a BB modem

8

( )( )0e mk k 0 k,A

k

p P p r m A N ;= ⋅ − > ⋅∑ (8)

- The probability ( )0kp r m A− > actually represents the occurrence probability of a noise-level greater

than A0 in the probing moment; this probability is:

( )( )

( )0

2

k 0k 0 k2

A

r m A1p r m A exp d r m Q ;

22

∞ − − > = − − = σ σπ

∫ (9)

where

2

t

1 uQ(t) exp du;

22

∞ = −

π ∫ (10)

- Since the power of a Gaussian noise equals σ2

the signal/noise ratio in linear expression is:

2

s s

z

P P

Pρ

σ= = (11)

by expressing σ from (11) and replacing it in (9) we get:

( )0 0 ;k

s

p r m A Q AP

ρ − > =

(12)

- Q is a strictly decreasing function, i.e. the error probability increases with the decrease of the

signal/noise ratio ρ (in linear expression).

- Recall that:

s

z

PSNR 10lg 10lg

P= ρ =

(13)

- the Q function is a strictly descending function, i.e. the BER increases with the decrease of the SNR.

Considerations regarding the BER of 2-level codes - the subsequent considerations assume that the average power of the received coded signal is Ar

2, for 2-

level codes (+/- Ar), the power spectral density of the noise equals N0, and the noise power in the useful

band of code x equals N0·LBx.

- for the 2-level codes the half of the minimum distance between two levels is given by (14), i.e. the

decision thethold is placed at 0.

0 r

A A= (14)

- replacing (14) and (5.a) in (8) and taking into account that each level has only one neighbour at distance

2A0 and that all levels are equiprobable, we get the average error-probability of a level (symbol), which

equals the bit-error probability of a bit, as:

( )2 0 02 2

0 0

0.5 1 0.5 1ep Q A Q A QA A

ρ ρρ

= ⋅ ⋅ + ⋅ ⋅ =

(15)

1. input BPF with a BW adapted to the code employed

- considering the useful BW of the biphasic, Miller and CMI codes are:

Bbiph ≈ 2fN; BMil ≈ 1fN; BCMI ≈ 1,8fN (16)

- the SNR values, rated to the one of the biphasic code, are: 2 2

r rbiph Mil biph Mil biph

N 0 N 0

2r

CMI biph CMI biphN 0

A A; 2 ; SNR SNR [dB] 3dB;

2f N 1 f N

A1,11 ; SNR SNR [dB] 0,46dB;

1,8 f N

ρ = ρ = = ⋅ρ → = +⋅ ⋅ ⋅

ρ = = ⋅ρ → = +⋅ ⋅

(17)

- and the BER is computed using (15), for M = 2 :

9

( )-2

e2e

p Q ;2

ρ

= ρ ≈⋅ πρ

(18)

- considerations regarding the Q(t) function and its approximation will be discussed in the PSK chapter.

- equations (16) and (17) show that, for the same values of N0 and of the received signal’s level, the SNR

value of the Miller and CMI codes is greater with 3 dB, and 0.46 dB respectively, than the SNR ensured by

the biphasic code. Since the Q function is strictly descending, the BERs ensured by the Miller and CMI

codes are smaller than the one provided by the biphasic code.

- to compare the levels of the received signal and of N0 which ensure the same value of BER for the two

codes, we should first note that, due to the bijectivity of the Q and square-root functions, we may write:

ebif eMill bif Mill bif Millp p Q( ) Q( )= ⇔ ρ = ρ ⇔ ρ = ρ (19)

- the two ratios ρ may be expressed in terms of energy-per-bit/power-spectral-density ratio, Eb/N0; relation

(11) shows the computation for the Miller code and presents the final reult for the CMI code as well:

rbif rbif b bif b MillrMill rMill

0bif bif 0Mill Mill 0bif bit 0Mill bit 0bif 0Mill

b bif b Mill b r

0bif 0Mill 0 0 bit

b bif b CMI

0bif 0CMI

P P E EP P2

N LB N LB N f N 0, 5 f N N

E E E P[dB] [dB] 3dB; where ;

N N N N f

E E[dB] [dB] 0, 46dB

N N

− −

− −

− −

= ⇔ = ⇔ = ⋅ ⇔⋅ ⋅ ⋅ ⋅ ⋅

⇔ = + =⋅

= +

(20)

- relation (20) shows that, in order to ensure the same BER at the same bit rate D, the Miller and CMI codes

allow the decrease of the received signal’s power and/or the increase of the N0, so that the Eb/N0 ratio would

be smaller with 3 dB, and 0.46 dB respectively, than the Eb/N0 ratio required by the biphasic code.

2. if the input filter has the constant BW = Bbiph, the three codes require the same SNR (the one required by

the biphasic code) to provide a certain value of BER, for the same value of N0 and the same bit rate D.

Considerations regarding the BER of 3-level codes - for the AMI code, the received levels +Ar and -Ar have occurrence probabilities equalling 0.25, while the 0

level has the occurrence probability 0.5 (since the „1” and „0” bits are equiprobable). Therefore the decision

thresholds are set at +/- Ar/2, so A0 for these ciodes equals: :

0

2

rA

A = (21)

- the 0 level has two neighbours at a distance equalling 2A0, while the other two levels have only one

neighbour at the same minimum distance.

- based on the above considerations and using relations (8), (5.b) and (21) the error-probability of the 3-

level AMI codes can be expressed as:

3 2 2 2

1 2 1 2 1 2 31 2 1

4 2 2 2 4 2 2 2

⋅ ⋅ ⋅= ⋅ + ⋅ + ⋅ =

r r re

r r r

A A Ap Q Q Q Q

A A A

ρ ρ ρ ρ (22)

1. input BPF with a BW adapted to the code employed

- considering the BW of the AMI, BnZs and HDB3, N = 3, equal to BAMI ≈ fN and a bit rate with fbit = 2fN,

the SNR would be: 2

AMI0 N

A;

2 N fρ =

⋅ ⋅ (23)

- the BER is computed using (22) for ρAMI

- to obtain a relation similar to (19), we would consider an equivalent signal/noise ratio, ρ’AMI, which

includes the effect of the increased number of levels of the coded signal, see relations (9) and (22):

AMI AMI bif AMI bif

1 1' ; ' [dB] [dB] 3dB;

2 2ρ = ⋅ρ = ⋅ρ ⇔ ρ = ρ − (24)

- equations (16), (23) and (24) show that, at the same values of N0 and for the same bit rate, the value of the

signal/noise ratio of the ternary codes (AMI type) is smaller with 3 dB, than the one of the biphasic code.

10

This value should be furthermore increased with about 0.5 dB to compensate the effect of the 1.5 factor

from (22). Since the Q function is strictly descending, the BERs ensured by the AMI-type codes are greater

than the BER provided by the biphasic code.

- to compare the levels of the received signal and of N0 which ensure the same value of BER for the two

codes, we should first note that, due to the bijectivity of the Q and square-root functions, we may write (25),

where the factor 3/2 was approximated by 1:

ebif eAMI bif AMI bif AMIp p Q( ) Q( ' ) '= ⇔ ρ = ρ ⇔ ρ = ρ (25)

- the two ratios ρ may be expressed in terms of energy-per-bit/power-spectral-density ratio, Eb/N0:

2 2rbif rbif b bif b AMIrAMI rAMI

0bif bif 0AMI AMI 0bif bit 0AMI bit 0bif 0AMI

b AMI b bif b r

0AMI 0bif 0 0 bit

P A E EP A1 1 1

N LB 2 N LB N f 2 2 N f / 2 N 2 N

E E E P[dB] [dB] 3dB; where

N N N N f

− −

− −

= ⋅ ⇔ = ⋅ ⇔ = ⋅ ⇔⋅ ⋅ ⋅ ⋅ ⋅

⇔ = + =⋅

(26)

- relation (26) shows that, in order to ensure the same BER at the same bit rate D, the AMI-type codes

require the increase of the received signal’s power and/or the decrease of the N0, so that the Eb/N0 ratio

would be greater with 3 dB than the Eb/N0 ratio required by the biphasic code. This value should be

furthermore increased with about 0.5 dB to compensate the effect of the 1.5 factor from (22).

- finally, the AMI-type ternary codes require a Eb/N0 higher with 3.5 dB than the biphasic code to ensure

the same BER, at the same bit rate, if the BW of the input filter is modified according the code used..

- table 1 presents the useful BW and Eb/N0 values, rated to the one of the biphasic code, required by the BB

codes to ensure the same BER, if the input filter bandwidth Bf is modified according to the employed code.

- the increase of the number of levels of the coded signal (M = 3), when the maxim level is kept constant

(+/-A) to keep the peak power constant, leads to a smaller distance between two neighboring levels, from

2A, for codes with M = 2, to A, for codes with M = 3. This fact explains the increase of the Eb/N0 required

by the M= 3 codes to ensure the same BER as the codes with M = 2.

2- for a constant BW input filter, Bf = Bbif,

- the relation between the SNR values needed by the ternary codes and the biphasic code becomes, see (24): 2r

AMI bif AMI bif0 N

1 A 1' ' [dB] [dB] 6dB;

2 N 2f 4ρ = ⋅ = ⋅ρ ⇒ ρ = ρ −

⋅ (27)

- 0.5 dB should be added to the difference of 6 dB to compensate the 1.5 factor from (22);

- by a reasoning similar to the one described by relations (25) and (26), the values of the received Ar and N0

for the AMI-type codes, which ensure a certain BER for a given bit rate, should ensure an Eb/N0 greater

with about 6.5 dB than the one required by the biphasic code to provide the same BER for the same bit rate.

This greater difference is generated by the greater noise bandwidth permitted by the filter (2fN instead of

fN), while the signal’s power is the same as in case 1.

- the BER computation for the 4B3T and MLT-3 code is more complex and is beyond the scope of this

course;

- the modification of the BW of the input filter to match the useful BW of the employed code may increase

significantly the BER performances of the transmission.

- the filtering of the BB-coded signal might exhibit adverse effects which should be removed by the

filtering itself and by subsequent processing.

- the computations above consider only the power of the received coded signal. But, due to their

different positioning of the absolute-frequency axis and to the different attenuation inserted by the cable

for different frequencies, the signals coded with these codes suffer different attenuations; therefore, in

the assumption of the same transmitted power, the received power is depending on the code employed.

The computation of the received power in terms of transmitted power and the effects of the different

attenuations inserted by the cable will be dealt with in the seminar classes.

Code Biphasic M = 2 Miller, M = 2 CMI; M = 2 AMI, BnZs, HDB3; M = 3

LBf ≈2·fN ≈1·fN ≈1,8·fN ≈1·fN

Eb/N0 [dB] Eb/N0bif Eb/N0 bif – 3 dB Eb/N0 bif – 0,46 dB Eb/N0bif + 3,5 dB

11

Synchronization of the bit-clock in the receiver

Necessity - the recovery and synchronization of the local bit-clock in the receiver is required for two reasons:

• the sampling of the coded received signal should be performed with a clock synchronized with this

signal;

• the decoding of the received encoded sequence also requires a clock signal synchronized with the

encoded signal

- the decoding of the biphasic, Miller and CMI codes, which have the minimum duration of the level of

the coded signal of a half bit-period, a local clock with flocal = 2·fbit, is required.

- in these cases, the bit clock is obtained by a frequency division of the local clock(flocal). But this division

might insert an 180º uncertainty between the local clock and the coded signal, due to the initial condition

of the divider; this uncertainty should be removed.

- The decoding of the AMI code and its variants require a clock with flocal = fbit ;

- the phase shift between the received encoded signal, and the local RxCk has the following causes:

• the different starting moments of the two oscillators; this generates the initial phase shift which takes a

random value between 0º and 180º;

• the difference between the frequencies of the two pilot oscillators that deliver the two clock signals; it

generates a dynamic phase shift which varies according to: ∆φd=∆ω·t; (28)

• the distortions inserted by the channel

• the 180º uncertainty induced by the initial state of digital frequency dividers

- by synchronization between the locally gene-rated clock and the received coded signal, we mean the

synchronism between the transitions of the coded signal, considered as a phase reference, and the

negative transitions of the locally generated clock flocal, equaling fbit or 2· fbit.

- the synchronization is accomplished in 3 steps:

• the removal of the initial phase shift, named fast or coarse synchronization; this operation is performed

only once at the beginning of the transmission;

• the removal of the 180º uncertainty, called resynchronization; this is required only by the decoding of the

Miller code. The decoding of the other codes presented does not require this operation;

• the removal of the dynamic phase shift (caused by the frequency diff. and by channel phase hits) between

the received coded signal and the locally generated clock, called dynamic synchronization. It operates

during the whole transmission, after the other two steps have been performed. If the fast synchro is missing,

the removal of the initial phase shift is also performed by the dynamic synchro.

• the dynamic and fast (when used) synchros are accomplished by means of Phase-Lock Loops (PLL).

PLL. General Aspects

– it is an ensemble of circuit that provides a local signal whose phase is aligned to the phase of an in

comming reference signal. Its block diagram

is shown in figure 12.

Figure 12. Block diagram of a PLL

- the phase detector (PhD) outputs a error-

voltage signal whose amplitude is (ideally)

proportional to the phase difference between

the incoming (reference signal si(t) and the

locally generated so(t).

- the loop filter (LF) is a low-pass filter

which retains only the low-frequency components of the error-voltage, e.g. attenuates the high-frequency

components of the noise) and generates a control voltage which modifies dynamically the momentary

frequency of the locally generated signal to decrease the phase offset between the si(t) and so(t).

- ideally, this process continues until the phase offset reaches zero, which corresponds to aconstant value of

the error-voltage (usually this contant value equals zero)

- in many of the practical implementations, the momentary frequency of the VCO is adjusted in order to

decrease, and bring to zero, the error-voltage.

- if the error-voltage equals zero, the frequency of the signal provided by rthe VCO is denoted as free-

running frequency.

Phase Detector Loop Filter sφ(t)

Voltage Controlled Oscillator (VCO)

si(t)

vφ(t)

so(t)

12

Types of PLLs

• analogue or linear loops (APLL or LPLL)

o the phase detector is implemented with analogue circuits (e.g. analogue multiplier), the loop filter

might be an active or passive analogue filter. This type of PLL uses a VCO.

• digital loops (DPLL)

o is actually an analogue PLL, that has the PhC implemented with digital circuits (gates, JK flop-flops,

etc.). It might include a digital frequency divider and can be used as a frequency multiplier.

• all digital loops (ADPLL)

o all blocks in the loop are implemented with digital circuits, and the VCO might be replaced by a

controlled divider.

• software PLL (SPLL)

o it is implemented using programable circuits

Deescriptions and Functionalities of the component blocks Phase Detector- PhD

- it outputs an error signal sφ(t) which varies with the offset ( )Φ − Φi o between the momentary phases of

the input (reference) signal si(t) (i

Φ - the phase of the reference signal) and of the output (locally

generated) signal so(t) (Φo - the phase of the local signal).

- the PhD can be implemented with analogue or digital circuits.

- according to the dependency-law between the error-voltage and the phase-offset ( )i lΦ − Φ , the PhC

could be divided in one of the following types, see figure 13:

• PhD with linear dependency (or sawtooth)

o usually these comaparators are implemented with digital circuits, while the imput signals are

rectangular ones. These circuits are also named Phase-Frequency Detectors (PFD).

• PhD with sinusoidal dependency

o these PhD are implemented with analogue circuits, e.g. analogue multipluiers, and the input

signals are harmonic, e.g. sine or cosine signals.

• PhD with triangular dependency

o implemented with digital circuits

and input signals are rectangular

• PhD with signum (sgn)

dependency

o provides only the the phase

offset’s sign;. implemented with

digital circuits, while the input

signals might be either analogue

or digital.

Figure 13 Types of dependencies of the

Phase Detector

Voltage Controlled Oscillator -VCO

- it is an oscilator generting a (co)sinusoidal (or rectangular) waveform whose frequency deviation from the

the free-running frequency (fOL) is proportional to the error-voltage Vφ(t).

- If the error-voltage equals zero, the frequency of the generated wavefor equals fOL.

Loop Filter - LP

– it usually is a LP filter, which affects the dynamics and stability of the loop, because its transfer function

affect the behaviour of the loop at the frequency variations of the input signal. In the same time, the

charactyeristic of this filter affects the widths of the lock-in and hold-in ranges (see below) and the lock-in

(synchronization) time.

Lock-In Range

– it is the frequency range (band) of the input reference signal within which the PLL is able to modify the

frequency of the local signal so that the phase of the local signal to be equal to the phase of the incoming

reference signal, see figure 14.

- this rule applies for the case when the local signal is not initially synchronized to the incoming one.

π

sφ

Sinusoidal

Triangular

Sawtooth

sgn

π/2

−π/2 −π

Φe- Φi

13

Figure 14. Frequency variation of the local signal vs.

the frequency of the reference signal

Hold-in Range –

it is the frequency range of the input signal within

which the frequency of the locally generated signal,

after it has been synchronized to the reference signal,

can be modified so that its phase would follow the

phase of the reference signal, i.e. the phase offset

between the two signals would tend to zero, see figure

14.

Lock-in (Synchronization) Time

– it is the time interval required by the PLL to

‚capture” then phase of the incoming signal, i.e. to make the phase of the local signal equal to the phase of

the reference (incoming) signal.

Dynamic Synchronization

- due to the ∆ω (28) the perfect phase synchronization between the local clock and the transitions of the

received code signal is impossible.

- the aim of the dynamic synchro is to keep the modulus of the phase shift between the two signals below

an a priori established value, called synchronization

step.

- the considered transitions of the two signal are

aligned only at random moments; the transitions of

the local clock are either ahead or behind the trans. of

the coded signal, the ref. signal, but the modulus of

the phase offset would always be smaller than the

preset value x.

- the phase-width of the “dynamic equilibrium” is 2x,

see figure 15.

- the block diagram of the dynamic synchro

circuit is shown in figure 16.

- the phase comparator senses the relative

position between the trans. of the RCS and the

negative trans. of local clock; it generates a

command so that a controlled phase shift, in

advance or delay, is accomplished.

- if the local clock is delayed, compared to the

reference RCS, the CP will activate the

Advance-clock circuit which will act upon the

first cell in dividing chain, by inserting

additional transitions which will shift the local

clock in advance.

- if the local clock is in advance, compared to the ref. RCS, the CP activates the Delay-clock circuit which

acts upon the first cell in dividing chain, by deleting transitions, thus shifting the local clock behind.

- the CP controls only the sign (sense) in which the local clock is phase-shifted; it does not control the

phase shift’s modulus inserted at every correction.

- the phase of the local clock signal is modified by temporarily modifying the dividing factor of the high-

frequency fatack clock; this is named “phase-shift by controlled division” method.

- the CP would always indicate the phase-shift from the closest transition of the reference signal; therefore

the modulus of the maximum possible phase-shift will be 180º.

- for decoding AMI, BnZs, HDB3 and 4B3T codes, fsincro = fbit,

- for decoding biphasic, Miller, CMI, fsincro= 2fbit.

- as an example of the phase shift by controlled division, we describe a dynamic synchro that synchronizes

a local clock fsincro, employing a divider clock with a frequency fatack= 2n = 32 ·fsynchro.

R eceived

coded signal

Local S yncro

C lock

D elay Advance

2x – dynam ic

Equilibrium zone

x x x x

t

t

x – Syncro

step

Figure 15. Dynamic equilibrium zone

F ro m t h e b lo ck in g

o u tp u t o f t h e fa s t s y n c ro

P h a s e

C o m p a

rat o r

C i rc .

A d v . c d

C ir c .

D e l ay cd

N ·f s i n cr o

D i v i d e r b y N / 2 f s in c r o - lo ca l

J

K

C k

Q

R

R

C o d e d

re c ei v e d s i g n al

Figure 16. Block diagram of the dynamic synchro circuit

fOL

fOL

Hold-in range

fi

fo

Lock-in range

14

- Fig. 17 shows the case when the fsynchro is advanced, compared to ref. signal, and has to be delayed;

- the CP acts upon the J-K inputs of the first cell of the dividing chain, inhibiting the flip-flop during one

active clock transition. So, a transition of its output signal is suppressed, and the transitions of the fsynchro

signal are delayed with one period of the fatack signal.

- the dashed lines indicate the states of the circuit after the delay circuit takes its action.

- Fig. 18 presents the case when the fsynchro is delayed, compared to ref. signal, and has to be advanced

The moment when the delay-circuit acts

Momentul în care acŃionează circuitul de întârziere Defazaj în avans – Advance phase-shift; Defazaj în întârziere – delay ph-sh

Tact în avans - s.c.r.

Clock advanced - RCS

Tact întârziat - s.c.r.

Clock delayed - RCS

32·

fsincro

16·

fsincro

8·

fsincro

4·

fsincro

2·

fsincro

fsincro

s.c.r.

Uînt-JK

Figure 17. The delay phase-shift of the local clock by controlled division

Delay phase-shift – Def. in intirziere; Defazaj în avans- Advance ph-sh

Tact întârziat faŃă de s.c.r.

Delayed clock - RCS Tact în avans - s.c.r.

Advanced clock - RCS

The moment when the advance- circuit acts

Momentul în care acŃionează circuitul de avans

32·

fsincro

16·

fsincro

8·

fsincro

4·

fsincro

2·

fsincro

fsincro

s.c.r.

Uavans- R

Figure 18. The advance phase-shift of the local clock by controlled division

15

- the CP acts upon the Reset (or Set if another configuration is employed for the divider) input of the first

cell of the dividing chain.

- If the Reset is activated when the inverted Q is in “0”, an additional transition is inserted in the signal at

output of this cell, generating the advance in phase of fsynchro with a period of the fatack signal.

- generalizing, an additional transition is inserted in the signal at the output of this cell if we activate the

Reset when the inverted Q is in “0”, or if we activate the Set when the Q output is in “0”.

- the dashed lines indicate the states of the circuit after the advance circuit takes its action.

- in both cases the advance or delay circuit operates only once during the period of the fsynchro signal.

- the dynamic synchro can act only if there are transitions in RCS; otherwise the dynamic synchro has no

phase-reference (transition of the RCS) and will keep the phase-shifting sense established at the last phase

comparison performed.

- this fact shows the necessity of a number, as great as possible, of transitions in the RCS.

- the phase step with which the correction is performed, corresponds to a period of the fatack signal, both for

the delay and advance correction.

- expressed in degrees this equals (29) where n is the number of cells of the dividing chain:

np n

atack

sin cro

360 360 360; N 2 ;

f N 2f

° ° °∆Φ = = = = (29)

- the phase amplitude of this step can be modified by changing the number of cells of dividing chain and by

changing, correspondingly, the fatack frequency to maintain the value of the frequency of the signal that has

to be synchronized, fsynchro.

-this dynamic synchronization circuit might be regarded as a ADPLL of order 0. Its lock-in range equals its

hold-in range and its width is given in (30.a)

- its lock-in time is expressed by (30.b), where tm denotes the average time interval between two

consecutive transitions of the input reference signal, while ∆Φmax denotes the maximum initial phase offset

that has to be compensated

max; ; . ; . 1 1

∆Φ = = = ⋅ + − ∆Φ

atac atacLK HD s m

p

f fBW BW a t t b

N N

(30)

- ∆Φmax can be reduced by using the fast (coarse) synchronization circuit, see the next paragraph

- this PLL does not reach a static equilibrium, but since the the modulus of the phase offset is smaller

than an imposed arbitrarily small value ∆Φp, it can be considered to ensure a dynamic equilibrium.

- another version of the dynamic synchro circuit that allows a phase-step ∆Φp = 360 º/N, with N a natural

number will be discussed in the laboratory classes.

- this type of synchronization circuit is also employed by other classes of modems to synchronize the

symbol and the bit clocks.

Fast (Coarse) Synchronization - the block diagram of the fast synchro circuit is shown in figure 19, and its principle of operation is

described in figure 20.

- the fast synchro operates in three steps:

• The initial synchronization that is performed only once at the beginning of the reception of a message;

• The disabling of the fast synchro circuit during the reception, so that the dynamic synchro would not be

affected;

• The “re-enabling” of the fast synchro circuit at the end of the reception of a message, so that it should be

able to act at the beginning of reception of the next message.

- at the beginning of the step, the sensor of the first transition is assumed to be “activated”, blocking, by

the activation of the Q output of the 16-counter, the generation of the local clock fsynchro.

- when the first transition of the RCS occurs, the transition sensor gives a pulse which resets the 16-counter,

Q =”0”, which releases the reset of the dividing chain of the dynamic synchro, thus allowing the generation

of the local clock fsynchro = 2fbit.

16

- assuming that the divide with N starts to

count at the arrival of the first transition of

the RCS and that the time interval between

two transitions of the RCS is approximately

equal with the period of fsynchro, we see that

the first negative transition of the local clock

will be coincident with the next transition of

the RCS. This indicates the removal of the

initial phase-shift.

- But the N-counter (from the dynamic

synchro) would actually start counting only at

the occurrence of the first negative transition

of the fatack = N·fsincro, i.e. with a maximum

delay of a period of the fatack signal. This fact

makes the negative transition of the fsynchro to

occur with a delay of maximum ∆Φmax,

compared to the arriving moment of the

second transition of the RCS, see fig. 19 and

(31):

N=2n; → ∆Φmax=360º·fsincro/(N·fsincro) =

360º/2n; (31)

- (31) holds valid when all the cells of the N-

counter are reset by the output of the 16-

counter of the fast synchro.

- if the fast synchro opeartes only upon the

first m stages from the otput of the 2n-divider, then the maximum initial phase-shift would be:

∆Φimax=360º/2m

; (32)

- note that during a period of the fsynchro signal, the fast synchro circuit decreases the initial phase to the

value of the phase-step of the dynamic synchro, bringing the system in the dynamic equilibrium zone, from

where the synchronization is taken over by the dynamic synchro circuit.

- once the initial phase shift is removed, the fast synchro circuit should be disabled during the rest of the

reception, to allow the dynamic synchro to compensate the dynamic phase shift and the phase-shifts

inserted by the transmission channel

- the disabling of the fast synchro circuit during the reception, employs the fact that the maximum time

interval between two consecutive transitions of the RCS is 2-bit periods, or 4 periods of the fsynchro signal.

So, the 16-counter from the fast synchro circuit is reset by the transition sensor, after two bit periods and is

it is not able to reach the “1”value, which would disable the N-counter of the dynamic synchro circuit. This

accomplishes the second step of the fast synchro operation.

- at the end of reception, for 8 bit periods, the 16-counter is no longer reset, there are no transitions since

there is no RCS; its output will jump to “1”, resetting the N-counter of the dynamic synchro and so the fast

synchro circuit is “re-armed” fulfilling the third step of operation of the fast synchro.

Resynchronization - as mentioned earlier, the resynchronization is intended to remove the uncertainty of 180º which might

occur between the bit-clock at the transmission end and the bit-clock at the receiving end.

- it is performed only once at the beggining of the transmission, after the action of the fast synchro circuit;

this synchronization is required by the Miller code; the biphasic code does not require it, due to its

differential structure. This property makes it suitable for burst-type transmissions, as the ones in the local

computer networks. This goes for the CMI code as well.

C o d e d

sig n a l

S e n s o r o f

tr a ns i t io n s

C o u n te r w i th 1 6

R

Q C k

C k :N C k : 2 Q N · fs i nc r o

f bi t

D y n a m ic sy n c hr o c i r c u i t

S e n s o r o f t h e f i r s t t r a n s i t i o n

R e c e iv e d

f si nc ro

R R

Figure 19 Block diagram of the fast synchro circuit

S em nal codat recep Ńionat - R C S

N ·fsin cro; N = 16

N ·fsin cro; N = 16

active inactive

fsincro

R elease R eset D ivider N

Start counting

∆Φ = 360º/N

Initial phase-sh ift

A fter Fast-synchro

t

t

t

t

R eset

Figure 20. Operating principle of the fast synchro circuit

17

Annexes

Annex 1

Implementation of the BB encoding – this section will be used in the laboratory classes - the encoding of the BB codes can be implemented using the mathematical relations that describe the

encoded signal, e.g. relation (3) for the biphase code.

- the implementation can be significantly simplified if the some particularities of the encoding rules are

considered.

- due to the different numbers of levels of the encoded signals and to the different durations of a level in the

coded signals, half of the bit-period or a bit-period, the encoding of the biphase, Miller and CMI codes

should be approached in a different manner, as opposed to the encoding of the AMI-type codes.

- the biphase-S, and CMI have a common rule of encoding the “1”-bit, namely by alternating the level H

and L. This can be implemented with J-K flip-flop, clocked by the bit clock, which has on its J and K inputs

the data signal. - the two codes also transmit the bit clock signal, during the “0”-bit

- the CMI code encodes the « 0 » bit by the bit-clock signal.

- the biphase-S encodes the “0”-bit either by the bit-clock or by the inverted bit-clock, depending on the

level (H or L) which encoded the previous “1”-bit.

- based on these considerations a common encoder for the biphase-S and CMI codes might be built using

a J-K flip-flop and an electronic switch; an additional switch should be used to select the desired code.

- to ensure the bipolar carrier, C-MOS circuits that operate using the +/- V levels should be employed.

- the Miller can be generated by dividing by (in frequency) the biphase-S coded signal.

HOMEWORK: Design the electric diagram of an encoder for the three codes with C-MOS digital circuits

using the considerations mentioned above.

- the encoding of AMI should consider that the coded signal has three amplitude levels.

- It could be generated using a level converter that operates similarly to a 2-bit D/A converter and whose

sign bit is toggled alternatively, for the “1” input bits.

- another approach employs a J-K flip-flop for the encoding of “1” (see considerations above) and a switch

that has an input to the electrical ground, for the “0”-bit, controlled by the input data.

- for the encoding of the BnZS codes, prior to the AMI encoder there should be inserted a circuit that

identifies the n-bit “0” series and replaces them with completion (synchronization) sequence of the

code.

- the implementation of MLT-3 and other baseband codes is literature

Annex 2

- the block diagram of a decoder that can decode thelbiphase, Miller and CMI codes is in figure A21.a.

- the K1 switch selects the decoded signal; the K2 switch selects the sampling clock, both depending of the

code to be decoded

- the decoding of the AMI, BnZs and HDB3 codes employs the fact that the “1” bit is encoded with levels of

modulus A, and the “0” bit is encoded with a level of 0 volts.

- the decoding of the AMI code requires the 2-wave rectification of the received coded signal which is

sampled with a locally-recovered bit clock.

- then a comparison with +A/2 threshold performs the decision of the received bit, see figure A21.b. Before

the comparison, an AGC ensures a constant level of the received signal.

- the decoding of the BnZs and HDB3 codes require the insertion, besides the AMI decoding, of a dedicated

circuit that recognizes the synchronization sequence, inserted at the transmission end, and replace with n or

4 bits of "0".

- the decoding of the 4B3T code is more complex since it has to establish the alphabet employed for the

encoding of the current symbol, and involves the employment of the inserted redundancy for the error

correction, see Bota

- the input BP filter should limit the bandwidth of received signal to the useful BW of the employed BB

code. The filtering characteristic should be a „raised cosine –RC” – to be discussed later.

- the recovery of the symbol clock in AMI decoders might be performed using the” energetic” method – se

the QAM lectures later.

18

Fig. A21 a. Block diagram of the biphase-S, CMI and Miller decoders; b. Block diagram of the AMI and BnZs decoders

D Q

C k

fs in c ro

= 2 fb it

D Q

C k

D Q

C k

D Q

C k

D Q C k

S e m n a l

r ec . c o d a t S 2 k + 1 S 2 k + 2 S 2 k + 3 S 2 k + 4

S d e c - b if

S d e c - M ille r fb it

Σ

b k

D P

a .

D Q

C k

b .

R e c t 2 a l t

R ec o v e r y +

S in cr o fb it

S ig n a l

A M I

S .

B n Z s

Id en ti fi ca t ion

S yn ch r o S eq .

C o m p a ra tor R e p la c e m e n t o f

S yn c h r o S e q .

+ V /2 fb it

b - A M I

b -B n Z s

S d e c - C M I K 1

fb it-2 7 0 º

B i f s a u C M I

fb it-9 0 º

M il ler

K 2

A G C