hfe0710 salleh part2

44 High Frequency Electronics

High Frequency Design

FAST SETTLING PLL

Design Method for theFastest Settling Type 2Phase Lock Loop: Part 2

By Akmarul Ariffin Bin SallehAgilent Technologies, Malaysia

This article is continuedfrom last month, withanalysis of higher-orderloop filters.

4th Order Type 2Fastest Settling PLL

I started the analysisof 4th order with the loop filter shown inFigure 9. Basically, additional pole due to Rp2and Rp2 are added at the output of the op ampincrease the order from 3rd to 4th. After somelengthy analysis, which will not be shownhere, I found out that it is impossible to matchthe denominator of the CL(s) to the GaussianLPF since this require the pole due to Rp2 andRp2, to be the complex conjugate of the poledue Rz, Cp and Cz as in (30). Both of these polecan only be real so this loop filter topology willnot work.

To solve this problem, the loop filter topol-ogy shown in Figure 10 needs to be used. Byusing this topology, the two poles created by Lpand Cp will definitely be complex conjugate ofeach other, and Rp can be used to furtherdefine the placement of the complex pole.

We start with the 4th order Gaussian lowpass filter, whose values normalized are listedin Table 1 (in Part 1). Figure 11 shows the cor-responding schematic. The transfer function ofthe circuit in Figure 11 can be shown to be ofEquation (44).

Next is to calculate the OL(s) of the 4thorder PLL in Figure 10. The OL(s) will be the

OL(s) of the 2nd order as in (12), but multiplywith the transfer function due to Rp2, Cp2 andLp2. The transfer function due to Rp2, Cp2 andLp2 is shown in (45),

(45)

(45) is of 2nd order and for a 2nd order sys-tem, it can be completely represented in termsof the damping factor ξ and the natural fre-

LF ss L C R C sp p p p

21

122 2 2 2

( ) =+ +

The author shows that mapping the denominator

of the closed loop PLLtransfer function to the

Gaussian function results inthe fastest settling time

Figure 9 · Initial 4th order type 2 PLL.

Figure 10 · Final 4th order type 2 PLL.

H sL C L C s

sL

L C L C L CL C L C

sC CC C

s( ) =

+ + + + + +1 1

4 3 2 1 43

4

2 1 4 1 4 3

4 3 2 1

2 3 1

3 1

++ 1

4 3 2 1L C L C(44)

From July 2010 High Frequency ElectronicsCopyright © 2010 Summit Technical Media, LLC



FAST SETTLING PLL

quency ωn, as shown in (46). These 2 constants, ξ and ωn,completely describe the 2nd order circuit, so the value ofRp2, Cp2 and Lp2 can be calculated, if these two values areknown. The OL(s) can be written as in (47).

(46)

(47)

The ω0 is calculated from (47) by setting the OL gainto 1 and s = jω0, as shown in (48). A new variable Xon,which is a ratio of ω0 to ωn, is defined in (49). Xon is also aconstant that needs to be solved simultaneously in orderfor the denominator of the close loop transfer function tobe of Gaussian.

(48)

(49)

The CL(s) can now be calculated, and after substitut-ing Xoz, Xon, we have the finalized CL(s) shown in (50). M4in (51) is to simplify CL(s)

(50)

(51)

Now we can equate the denominator of (51) to thedenominator of (45). As before, we are interested to findthe Xof, rather than just ωo. Therefore we have the fol-lowing set of equations,

(52)

(53)

(54)

(55)

Solving (52) to (55) simultaneously, the value of Xop,Xoz and Xof can be calculated.

Xoz = 2.5647 (56)

Xon = 0.3337 (57)

Xof = 1.3222 (58)

ζ = 0.7695 (59)

From (47), the phase margin can be calculated as fol-lows,

PM = 38.669

The phase margin for 4th order is a little bit small at38.669. Nevertheless, at this phase margin, the loop isstill stable, and it is not uncommon to find a PLL withsuch a phase margin. Another point to note is that, theXoff is smaller than of the 3rd order, which indicates that4th order PLL is faster than 3rd order, for a given ω0.

5th Order Type 2 Fastest Settling PLLBy now, we should have seen the trend that the high-

er the order, the faster will the settling time of the PLL.The penalty that we have to pay is that, the PM gets

PM phase j phase jo

z

o

n

o

n

= + − − +( ) (( ) )1 1 22

2

ωω

ωω

ωω

ξ

X

XM

L C L Cof

on N N N N

4

44 3 2 1

1=

X X

XM

C CC C

of oz

on

N N

N N

3

2 43 1

3 1

= +

( )X

XL C L C L C

L C L Cof

on

N N N N N N

N N N N

2 2 1 4 1 4 3

4 3 2 1

= + +

21

4

ξX

X Lof

on N

=

MX X

Xon on

oz

4

2 2 2

2

1 2

1=

− +

+

( ) ( )ξ

CL sC

K K s

sX

sX

sXz z

p v z n p

o

on

o

on

o oz

( )( )

( )

( )=

+

+ + +

1

2

2

4 3 2 23ω

ω ω ω

ξ ω ω ωXX

M sX

Mon

o

on2 4

4

4+ ω

Xono

n

= ωω

ωξ

op

zoz

on on

vK

CX

X X

KN

2

2 2 21

1

1 2= +

− +( ) ( )

OL sK

sCs

ss

KN s

p

z z

n n

v( ) ( )= ++ +

112

12

2

ωω

ξω

LF ss

sn n

212

12

2

( ) =+ +

ωξ

ω

Figure 11 · 4th order low pass filter circuit. Figure 12 · 5th order low pass filter circuit.



FAST SETTLING PLL

smaller with increasing order. Lower PM will cause abump around LBW, on the close loop response. This bumpwill translate into a bump on the phase noise at the out-put, so precaution need to be taken and proper simulationof phase noise need to be carried out.

We start with the 5th order Gaussian low pass filter,whose normalized values are listed in Table 1. Figure 12shows the corresponding schematic. The transfer functionof the circuit in Figure 12 is in (60), see below.

The PLL circuit for 5th order is the extension of 4thorder PLL, where there is additional capacitor Cp aroundthe op amp. This is shown in Figure 13.

The corresponding OL(s) is shown in (61). As per 4thorder analysis, ξ and ωn describes the 2nd order circuitdue to Rp2, Lp2 and Cp2, as in (46)

(61)

The ωo can be calculated from (61) by substituting swith jωo and set the gain to 1. The corresponding equationto calculate ωo is in (62). Xoz, Xop and Xon were definedpreviously

(62)

The CL(s) can now be calculated, and the final equa-tion is shown in (63), see below. M5 in (64) is to simplifyCL(s).

(64)

Now we can equate the denominator of (64) to thedenominator of (60). We are interested in Xof rather than

ωo, therefore we have the followings sets of equations tobe solved simultaneously.

(65)

(66), see below

(67)

(68)

(69)

Solving (66) to (70) simultaneously, the value of Xop,Xoz, Xon, Xof and ξ can be calculated.

Xoz = 2.5439 (70)

Xop = 0.2611 (71)

Xon = 0.3228 (72)

X M

X X C L C L Cof

op on N N N N N

552

5 4 3 2 1

1=

X X M

X XC C C

C L C L Cof oz

op on

N N N

N N N N N

45

25 3 1

5 4 3 2 1

= + +

X

X XL C L C L C

C L C L Cof

op on

N N N N N N

N N N N N

3

22 1 4 1 4 3

5 4 3 2 1

= + +

( )21

5

ξX

X

X

X Cof

on

of

op N

+ =

MX X X

X

op on on

oz

5

2 2 2 2

2

1 1 2

1=

+ − +

+

( ) ( )ξ

ωξ

02

2

2 2 2 2

1

1 1 2=

+

+ + − +

K K X

N C C X X Xp v oz

z p op on on( ) ( ) ( )

OL s K

s

ss

C C ss

KN sp

z

pz p

n n

v( )( )

( )( )=

+

+ + + +

1

1

12

12

2

ω

ω ωξ

ω

Figure 13 · 5th order Type 2 PLL.

H sC L C L C s

sC

C L C C L C C L C C L CC L C

( ) =+ + + + +

1 1

5 4 3 2 1 54

5

3 2 1 5 2 1 4 4 1 5 4 3

5 4 3LL Cs

L C L C L CC L C L C

sC C CC L C L C

sC2 1

3 2 1 4 1 4 3

5 4 3 2 1

2 5 3 1

5 4 3 2 1 5

1+ + + + + + +LL C L C4 3 2 1

(60)

(63)

(66)

CL sC

K K s

sX X

sX

z z

p v z n p

o

on

o

op

o

op

( )( )

( )

( ) (=

+

+ + +

1

22

2

5 42ω

ω ω ω

ξ ω ω ξωXX X

sX X

sX M

X Xs

MX Xon

o

on

o

op on

o oz

op on

o

op on

+ + + +ω ω ω ω2

23

3

22

45

2

55

2)

( )2 2 2

23 2 1 5 2 1 4 4 1 5ξ X

X X

X

XC L C C L C C L C C Lof

op on

of

on

N N N N N N N N N N+ = + + + 44 3

5 4 3 2 1

N N

N N N N N

CC L C L C



FAST SETTLING PLL

Xof = 1.1326 (73)

ξ = 0.508 (74)

From (61), the phase margin can be calculated as fol-lows,

PM = 33.799

As far as stability is concerned, the phase margin of33.799 is quite small but still stable. Because of the smallphase margin as well, proper calculation and simulationsneed to be carried out to ensure that the PLL is stableover the whole operating frequency. Some LBW compen-sation circuitries might need to be in place.

6th Order Type 2 Fastest Settling PLLThere are still extra PM left before the loop goes

unstable, so it is still doable to solve for 6th order. I’mgoing to cut short the analysis for 6th order (and for 7thorder after this) since it basically follows the same stepsshown before, and it would take a lot of area to write theequations. Instead of trying to solve for the transfer func-tion of the 6th order LPF similar in Figure 11, I’ll just pro-vide the coefficients of the denominator. The 6th orderLPF will have a transfer function shown in (75)

(75)

For Gaussian LPF, values of each coefficients are list-ed below, for ω3dB = 1 rad/s

g5 = 10.19368g4 = 47.60398g3 = 128.789374g2 = 210.709533g1 = 196.100192g0 = 80.573668

For the 6th order PLL circuit, we have two choices,either to use the circuit in Figure 14 or the circuit inFigure 15. I considered Figure 16 initially but found outthat there will be no solutions since there can only be onenon-zero passive pole. PLL in Figure 16 has two non-zeropasive poles, one due to Rz, Cz and Cp, and the other onedue to Rpd and Cpd. Figure 14 requires 3rd order circuit atthe output of the op amp, and this is not so convenientsince there are no specific 3 parameters to completelydefine a 3rd order network. Figure 15 has two 2nd ordernetworks before the op amp and after the op-amp. This

will be easier to solve and hence will be used for the anal-ysis. The OL(s) of the PLL shown in Figure 15 is in (76)

(76)

The ξpd and ωnpd are for the 2nd order network beforethe op amp. A new ratio Xonpd will have to be defined,

(77)

The ωo can be calculated or solved by using (76). (76)is also used to calculated the required Kp to get therequired ωo.

Xonpdo

npd

= ωω

OL sK K

s NC

s

ss

ss

p v

z

z

npd

pd

npd n n

( ) =+

+ +⋅

+ +2 2

2

2

2

1

21

12

1

ω

ωξ

ω ωξ

ω

H sg

s g s g s g s g s g s g( ) =

+ + + + + +0

65

54

43

32

21 0

PM phase j phase j phase jo

z

o

p

o

n

o

n

= + − + − − +( ) ( ) (( ) )1 1 1 22

2

ωω

ωω

ωω

ωω

ξ ))

Figure 14 · Option 1 for 6th order PLL.

Figure 15 · Option 2 for 6th order PLL.

Figure 16 · 6th order PLL that will not generate fastestsettling PLL.



FAST SETTLING PLL

(78)

The CL(s) will also not be shown here as it is too longbut the coefficients in the denominator will be included,and equate it to g5 to g0.

(79)

(80)

(81)

(82)

(83)

(84)

M4 was defined before in (52) and M6 is defined in (85).Both are used to simplify the equations.

(85)

Solving (79) to (84) simultaneously, the value of Xonpd,Xoz, Xon, Xof, ξ and ξpd can be calculated.

Xoz = 2.5424 (86)

Xon = 0.3179 (87)

Xonpd = 0.2364 (88)

Xof = 1.0446 (89)

ξ = 0.3271 (90)

ξpd = 0.9104 (91)

The phase margin can be calculated from (76), as in thetop equation below.

PM = 30.989 deg

7th Order Type 2 Fastest Settling PLLThe 6th order LPF has the transfer function:

(92)H sg

s g s g s g s g s g s g s g( ) =

+ + + + + + +0

76

65

54

43

32

21 0

M X Xonpd pd onpd62 2 21 2= − +( ) ( )ξ

X

X XM M gof

on onpd

6

2 2 4 6 0=

X X

X XM M gof oz

on onpd

5

2 2 4 6 1=

X

X Xgof

onpd on

4

2 2( )=

22

3

X

X X

X

X

X

Xgof

onpd onpd

of

on

of

onpd

( )ξ ξ+ =

42 2

2

2

2 4ξ ξpdof

onpd on

of

on

of

onpd

X

X X

X

X

X

Xg+ + =

2 2 5ξ ξX

X

X

Xgof

onpd

of

onpd

+ =

ωξ ξ

02

2

2 2 2 2 2

1

1 2 1 2=

+

− + − +

K K X

NC X X X Xp v oz

z onpd pd onpd on on( ) ( ) ( ) ( )22

Figure 17 · 7th order type 2 PLL.

PM phase j phase j phaseo

z

o

n

o

n

o= + − − + − −( ) (( ) )) ((1 1 2 12

2

2ωω

ωω

ωω

ξ ωωnnpd

o

npdpdj2 2) ))+ ω

ωξ

(94)

(96)

ωξ

02

2

2 2 2 2

1

1 1 2 1=

+

+ + − + −

K K X

N C C X X X Xp v oz

z p op onpd pd onpd on( ) ( ) ( ) ( 22 2 22) ( )+ ξ Xon

4 2 22 2

2

2

2

2

ξ ξ ξ ξpdof

onpd on

of

on

of

onpd

of

op onpd

ofX

X X

X

X

X

X

X

X X

X+ + + +

22

5X Xg

op onpd

=

PM phase j phase j phase jo

z

o

p

o

n

o

n

= + − + − − +( ) ( ) (( ) )1 1 1 22

2

ωω

ωω

ωω

ωω

ξ )) (( ) ))− − +phase jo

npd

o

npdpd1 2

2

2

ωω

ωω

ξ

XX X X X X X X X

X Xofonpd on pd on onpd on op pd onpd op

on op

32 2

2

4 2 2+ + + +ξ ξ ξ ξXX

gonpd

2 4= (97)

For Gaussian LPF, values of each coefficients are list-ed below, with ω3dB = 1 rad/s

g6 = 12.4533g5 = 172.476871g4 = 252.870805g3 = 566.484058g2 = 809.023329g1 = 678.141182g0 = 256.114957

The PLL circuit to be used is shown in Figure 17.Figure 17 is leveraged from Figure 15, with additional Cpacross the op amp to create one more pole/order.

The OL(s) of the PLL shown in Figure 17 is in (93)

(93)

The ωo can be calculated or solved by using (94, seebelow). The CL(s) will also not be shown here as it is toolong, but the coefficients in the denominator will beincluded, and equate it to g6 to g0.

(95)

(96), see pg. 52

(97), see pg. 52

(98)

(99)

(100)

(101)

M5 and M6 were defined in (64)and (85). Solving (95) to (101) simul-taneously, the value of Xonpd, Xoz, Xon,Xof, Xop, ξ and ξpd can be calculated.

Xoz = 2.5447 (102)Xop = 0.206 (103)

Xon = 0.3149 (104)Xonpd = 0.2228 (105)Xof = 0.9611 (106)ξ = 0.206 (107)ξpd = 0.7568 (108)

The phase margin can be calculated from (93), as inthe bottom equation on pg. 52.

PM = 29.1758 deg.

Design ExampleLet’s say a fastest settling PLL with the following

parameters needs to be designed. To avoid confusion, allfrequencies variable will be in rad/s.

Order = 7thωo = 100k rad/sFout = 5G rad/sFref = 10M rad/sKv = 100M rad/s/vKp = Tunable from 10 µA/rad to 3 mA/rad

Solution: The circuit in Figure 17 is the one that wewant to design. For 7th order, listed below are the con-

X

X X XM M gof

op on onpd

7

2 2 5 6 0=

X X

X X XM M gof oz

op on onpd

6

2 2 5 6 1=

X

X X Xgof

op onpd on

5

2 2( )=

XX X X

X X Xgof

op pd onpd on

on op onpd

42 2 3

2 2+ +=

ξ ξ

X

X

X

X

X

Xgof

op

of

onpd

of

onpd

+ + =2 2 6ξ ξ

OL sK K

s NC

s

s ss

sp v

z

z

p npd

pd

npd n

( ) = ⋅+

+⋅

+ +⋅

+2 2

2

2

2

1

1

12

1

12

ω

ω ωξ

ω ωξ

ωnn

s + 1



FAST SETTLING PLL

stant that need to be used. These were from (102)-(108).

Xoz = 2.5447Xop = 0.206Xon = 0.3149Xonpd = 0.2228Xof = 0.9611ξ = 0.206ξpd = 0.7568

We start by solving ωz, Rz and Cz first.

Rz can be independently selected and a smaller valueis preferred so to minimize phase noise contribution. Onan additional note, we don’t want Rz to be too small suchthat the Cz will be relatively huge. It is preferable to useCOG capacitor for Cz to avoid dielectric absorption, andCOG is hard to find for high capacitance. Dielectricabsorption will cause the PLL to settle really slow, whichwould defeat our objective of designing fast settling PLL.

Rz = 316 ohm

Next, ωp and Cp can be solved. Cp is solved using (29)

Next is to solve for ωn, Rp2, Lp2 and Cp2.

Rp2 can be selected independently and again a smallvalue is preferable to minimize noise.

Rp2 = 31.6 ohm

(46) and (47) are used to solve for Lp2 and Cp2.

Same calculations need to be carried out of the 2ndorder network before the op-amp. Rpd can be selectedindependently and again a small value is preferable tominimize noise.

Rpd = 31.6 ohm

(45) and (46) are used to solve for Lpd and Cpd.

The feedback ratio N can be calculated from Fout andFref,

Finally, Kp can be calculated by using (94)

M5 and M6 were defined in (64) and (85). Even thoughthe example is for 7th order, knowing how to design 7thorder will enable ones to design lower orders easily.

Settling Speeds and Phase Noises ComparisonsThe time domain response was calculated by first mul-

tiplying the CL(s) with a step response ΔFref/s. ΔFref iscalculated from (6). Then inverse Laplace transform iscarried out to convert from frequency domain to timedomain.

The settling speeds of type 2 PLLs with varying ordersfrom 2nd to 5th are shown in Figure 14. The x-axis is insecond and is scaled by ωo. This is so that the settling ofeach order could be correctly compared. Normalizing thex-axes to ωo will also give ones some rough ideas of the

KN C C

KM M mA radp

z p

v

=+

=ω0

2

5 6 1 5016( )

. /

NFF

vco

ref

= = 500

LC

uHpp n

22

2

146 504= =

ω.

CR

nFpp n

22

2106 707= =ξ

ω.

LC

uHpp n

22

2

1241 462= =

ω.

CR

nFpp n

22

241 056= =ξ

ω.

ω ωn

o

onXkrad s= = 317 6034. /

CC

R CnFp

z

p z z

=−

=ω 1

7 0939.

ω ωp

o

opXkrad s= = 485 393. /

CR

nFzz z

= =180 529

ω.

ω ωz

o

ozXkrad s= = 39 2974. /

Figure 18 · The frequency settling time of fast settlingPLL for varying orders.

settling time, for a given ωo. Forexample, let’s say the ωo is designedat 1Mrad/s. The unnormalized x-axiswould then read 2us, 4us, up to 10us.The y-axis is the Fout and is normal-ized to the equivalent frequency stepat the output. Referring to Figure 14,it can be seen that the higher theorder, the faster the settling, for thesame ωo. And also, as the denomina-tor is of Gaussian, the time domainresponse will just overshoot (due toωz of type 2), and then just settle withno more undershoot or overshoot.

Figure 14 illustrate the settlingtime roughly. In some application, itis critical to know how long it take forFout to settle to within some percent-age, and one example is in a networkanalyzer design. In a network ana-lyzer, the source and LO frequenciesare tuned so that they are offset bythe IF frequency. This IF will thenhas to go through a digital filter cen-ter around IF, and with a bandwidththat could be as small as 10 Hz. Thesource and the LO has to settle with-in half the IF bandwidth, before mea-surement can take place. If measure-ment is done without waiting foreither the source or the LO to settle,then the IF will not be at the centerof the filter and we end up measuringnoise. On a different scenario where-by we wait much longer than theactual settling time, then the sweepspeed performance of the networkanalyzer will be impacted.

Table 2 listed down the normal-ized settling time for different PLLorder and for different frequency set-tling %. Let’s do a quick example onhow to use the table. Let’s say wehave 5th order fast settling PLL andthe ω0 is designed at 500 krad/s. TheVCO or Fout has to be stepped by 100krad/s, and we would like to find thesettling time after the Fout has settleto within 0.001% of the step Fout.

From Table 2, the normalized set-tling time for 0.001% settling and for5th order is shown below.

tsN = 11.1231


FAST SETTLING PLL

The actual settling time is simply,

As mentioned in the previous sec-tion, the PM will be lower for higherorder. For 7th order, the PM is assmall as 29.1758 degree so it is a goodidea to check the phase noise since

low PM could lead to a bump onphase noise around ω0. Figure 18shows the phase noise plot for 2ndorder, 3rd order and 4th order, where-as Figure 19 is for 5th order, 6thorder and 7th order. The phase noisefrom the divider N dominates theoverall phase noise below ω0 and thephase noise from the VCO dominate

the overall phase noise above ω0.From Figure 18, only phase noise ofthe 2nd order is quite high, and thephase noise of 3rd, and 4th order arepretty much similar. On top of that,no bump can be observed.

As we increase the order to 5th, abump start to appear on the phasenoise plot, as can be seen in Figure19. This bump is at the ωn of the 2ndorder network due to small PM. Thebump on the phase noise plotincrease in magnitude as we increasethe order to 6th and 7th order, sincethe PM of the 2nd order networkreduces with increasing order.

Let say a 7th order settling per-formance and good phase noise with-out a bump are required. This can beachieved by switching different val-ues of Rpd, Rz, and Rp2, and shortedout Lpd and Lp2, once Fout has settledto required value. Shorting out Lpdand Lp2 will change both the 2ndorder network to 1st order network sothere will be no peaking. On top ofthat, switching Lp2 and Lpd will notcause any transient since it is memo-ryless as far as voltage is concern.Cpd, Cp2 and any capacitor in general

tt

usssN

o

= =ω

22 246.

Table 3 · Design constants summary for 2nd, 3rd, 4th,5th, 6th and 7th order fast settling PLL.

Figure 19 · Phase noise comparison between 2nd, 3rdand 4th order PLL.

Figure 20 · Phase noise comparison between 5th, 6thand 7th order PLL.

Table 2 · Normalized settling time for different fre-quency settling %.


should not be switched as this willcause additional transient. Figure 20compare the phase noise of the 7thorder PLL, before and after switchingRpd, Rz, Rp2, Lp3 and Lp2. Both Rpdand Rp2 were reduced by 50% and Rzwas increased by 12.67%. The ω0remains the same but the PMimproves to 44.4 degrees.

SummaryIt was proven that if the denomi-

nator of the CL(s) is of Gaussian,then the type 2 PLL will settle thefastest. A step response of type 2PLL, whose denominator is ofGaussian, is equivalent of the sum ofimpulse response and step responseof Gaussian LPF.

The design parameters or con-stants for fast settling PLL have beenderived for 2nd, 3rd, 4th, 5th, 6th and7th order. The tabulated values areshown in Table 3. Refer to Figure 1,Figure 7, Figure 10, Figure 13, Figure15 and Figure 17 for 2nd, 3rd, 4th,5th, 6th and 7th order PLL circuit.

A table that listed down the nor-malized settling time for a given fre-quency settling % is included. Thistable is useful in finding an accuratesettling time. The typical phase noiseplot is also included and no phasenoise bump can be observed.

Part 1 of this article appeard inthe June 2010 issue, and is availableonline in the Archives section ofwww.highfrequencyelectronics.com

References1. F. M. Gardner, Phaselock

Techniques, Wiley Interscience, NewJersey, US, 2005.

2. W. F. Egan, Phase-Lock Basics,Wiley Interscience, New Jersey, US,2008.

3. Anatol I. Zverev, Handbook ofFilter Synthesis, Wiley Interscience,New Jersey, US, 2005

4. Alexander W. Hietala,“Parameter Tolerant PLL Synthe-sizer,” US Patent 5055803.

5. http://www10.pcbcafe.com/book/phdThesis/Appendix-3.php

Author InformationAkmarul Ariffin Bin Salleh is an

RF/microwave R&D engineer, focus-ing mainly on high performance PLLdesigns. Akmarul joined AgilentTechnologies in 2000 as a ProductEngineer taking care of NetworkAnalyzer. He joined R&D in 2005 and

has delivered products to the market,including the N9912A NetworkAnalyzer/Spectrum Analyzer comboand the N9923A Handheld VNA.Akmarul graduated from VanderbiltUniversity with a B.E. in ElectricalEngineering and also majoring inMathematics.

Figure 21 · Phase noise improvement on 7th order PLL after switching fewcomponents.

hfe0710 salleh part2

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