Fairchild Semiconductor Power Seminar 2013-2014 1

Driving High-Brightness LEDs in High-Power

Industrial Lighting Fixtures Steve Mappus

Abstract — High-power, industrial Light Emitting Diode (LED)

fixtures use series-parallel strings of High Brightness (HB) LEDs to

produce superior lighting fixtures compared to traditional, “ballast-

based” systems. HB-LEDs are configured in series or series-parallel

strings and require Constant-Current, Constant-Voltage (CC-CV)

power supplies, typically operating within the range of 50 W-200 W.

Voluntary and mandated industry requirements; such as the need for

Power Factor Correction (PFC), extended universal input voltage

range, high efficiency, current accuracy, load control, and dimming;

are all met with the usual challenges of reducing cost, size, and

design complexity. This paper addresses some of the specific

challenges designers face when considering power supply design

solutions for these unique LED lighting applications.

A 100 W, dual-stage, quasi-resonant flyback converter is

presented and shown to meet specifications typical of a high-power

industrial LED lighting fixture. The converter operates from an

extended universal input range of 85VRMS<VAC<308VRMS with a

peak efficiency of 92%. The design also demonstrates a Power Factor

(PF) greater than 0.9 over the entire input voltage range while

meeting EN61000-3-2 Class-C lighting limits for Total Harmonic

Distortion (THD) and is compatible with analog and PWM dimming.

Current sharing accuracy is better than ±2%, exceeding that of

competing LED load control techniques at this power level.

I. INTRODUCTION

High-power industrial lighting fixtures are found in

airports, tunnels, bridges, highways, parking lots,

walkways, high and low bays, sporting arenas, “big-box”

retail establishments, and industrial manufacturing

complexes. Compared to competing light sources, such

as linear fluorescent, High-Intensity Discharge (HID),

and sodium or mercury vapor lamps; a properly designed

LED industrial lighting system can offer the following

improvements:

Efficiency – LEDs require less power to produce

higher luminous output than traditional light sources.

Reliability – Industrial LED fixtures have lifetime

ratings of 50,000 hours or higher compared to less

than 20,000 hours for traditional light fixtures.

Maintenance – LEDs require almost no maintenance

and therefore save on associated labor costs.

Instant On – LEDs are solid-state devices, instantly

responding to changes in forward current, allowing

the exact amount of light to be used when needed.

Dimming – LEDs can be dimmed, without flicker,

using analog DC or digital PWM input signals.

Temperature – Conventional light sources waste

more energy in heat than LEDs. Indoor industrial

facilities can save air conditioning costs using LEDs.

Light Quality – LEDs maintain a warm or cool light

quality that is consistent over the life of the fixture.

Contrary to fluorescent light fixtures, LEDs do not

degrade over their life-cycle.

UV Free – Ultraviolet light rays can cause

degradation to food and textiles. LED fixtures can

help keep produce and meats fresher longer.

Mercury Free – HID and fluorescent fixtures include

small amounts of mercury. When these light fixtures

break, mercury is released as a toxic vapor. LED

fixtures contain no mercury and do not require glass

in their construction.

Given the long list of LED advantages, the reasons to

upgrade are compelling. However, while the

development of industrial LED fixtures that outperform

existing lighting systems is rapidly evolving, one of the

biggest barriers toward full acceptance is the associated

upfront costs.

One similarity shared across all industrial lighting

sources is that they require a specific type of power source

where electrical energy is converted into light output. HID

and fluorescent lamps use a ballast capable of producing a

high “starting voltage” (i.e. 10 kV) to ignite a plasma

reaction between two electrodes. After the internal gasses

ignite, the ballast must provide a voltage (i.e. 120 V)

capable of sustaining the plasma reaction.

LED power supply requirements are quite different.

Since a single HB-LED die cannot produce the

illuminance expected from an industrial lighting fixture,

many individual HB-LEDs are arranged in series or

series-parallel combinations. Typical HB-LEDs used in

these types of applications have a 1 W-5 W power rating

and arrangements of such HB-LEDs can easily consume

50 W-200 W of power, depending on the specific

assembly. The first step to designing an LED power

supply, or any power supply, is understanding the source

being connected and the load being powered.

Fairchild Semiconductor Power Seminar 2013-2014 2

Offline power supplies are often designed to operate

worldwide and therefore must be able to handle a

universal input range of 85 VRMS < VAC < 265 VRMS. A

universal input power supply is beneficial because a

manufacturer can limit producing different power

supplies specific to certain regions of the world. In some

US installations, utility feeds for industrial lighting can

be as high as 308 VRMS (upper limit of 277 VRMS

industrial single phase). In other cases, industrial

lighting fixtures might be installed in facilities using a

115 VRMS dedicated lighting feed. The extended

operating voltage range for industrial lighting should be

considered 85 VRMS < VAC < 308 VRMS, where 308 VRMS

is the upper limit of 277 VRMS industrial single phase.

Designing an efficient LED power supply with PFC

capable of meeting THD over such a wide input range

poses a definite challenge, but has become a real

industry requirement.

The LED load requires a power supply capable of

producing a tightly regulated Constant-Current (CC)

during normal operation. In the event that the LED

voltage exceeds a set maximum limit, the power supply

should shift to Constant-Voltage (CV) regulation with

current fold-back or at least limit the maximum

allowable LED string voltage. A more thorough

understanding can be gained by examining the

characteristics and drive requirements of the HB-LED.

II. HB-LED CHARACTERISTICS

HB-LEDs are non-linear, P-N junction devices with

exponential current and voltage (IV) characteristics

similar to a diode.

VF, Forward Voltage (V)

I F, F

orw

ard

Cu

rre

nt

(mA

)

0 0.5 1.5 2 2.5 3 3.5 4 4.5

100

200

300

400

500

600

700

800

900

0

200mA

100 °C

25 °C

Fig. 1. 1 A, LED typical IV curve, temperature variation

Assuming a constant voltage of 3.5 V used to drive a

single 1 A, HB-LED with typical IV characteristics, such

as those shown in Fig. 1; a 200 mA change in forward

current can be seen as a function of operating

temperature. VF can vary by as much as 20%, making it

difficult to maintain equal branch currents when driving

parallel LEDs from a voltage source. Slight variations

between parallel branch currents translate into gross

variations in LED light color and intensity. This can lead

to an overall degradation in light quality as well as a

decrease in reliability.

The task of paralleling LEDs is complicated by their

negative temperature coefficient (NTC). As LED

junction temperature increases, VF decreases, which

increases IF and further raises junction temperature.

Current sharing between series-connected, parallel LED

strings can be a difficult, but necessary requirement for

designing high-power industrial LED lighting fixtures.

Maintaining high reliability requires an acceptable

amount of de-rating applied to the maximum allowable

forward current. The de-rating curve shown in Fig. 2

highlights the important fact that maximum LED current

must be limited in accordance with a properly designed

thermal heat sink. While the discussion of LED thermal

management is beyond the scope of this paper, HB-

LEDs generate a large amount of heat that must be

properly managed to avoid device failures.

Ambient Temperature (°C)

Ma

xim

um

Cu

rre

nt

(mA

)

0 20 40 60 80 100 120 140 160

200

400

600

800

1000

1200

0

ΘJA = 5°C/W

ΘJA = 10°C/W

ΘJA = 15°C/W

Fig. 2. 1 A, LED typical de-rating curve

When considering the LED characteristics shown in

Fig. 1 and Fig. 2, it becomes apparent that LED loads,

especially series-parallel industrial loads, need be driven

with a tightly regulated, CC source. A DC-DC or AC-

DC, CC power supply dedicated to driving LED loads is

Fairchild Semiconductor Power Seminar 2013-2014 3

commonly referred to as an “LED driver” (or driver).

Drivers used in industrial LED lighting fixtures are just

one of three important functional blocks that define a

well-designed LED lighting system.

III. HB-LED SYSTEM REQUIREMENTS

An industrial LED lighting system operating from a

universal, offline AC voltage must include the ability to

maintain high power factor over a wide range of input

and output operating conditions. For example, meeting

the Department of Energy (DOE), Energy Star Program

for solid-state lighting explicitly requires a minimum

power factor of 0.7 and 0.9, respectively, for residential

and commercial fixtures greater than 5 W. In addition,

the European standard, EN61000-3-2, for Class C

lighting equipment imposes stringent THD limits most

easily met using active power factor correction.

The AC-DC power block shown in Fig. 3 is

representative of the input EMI filter, AC rectifier, and

active PFC circuitry. There are several widely accepted

control methods used for achieving PFC. For power

conditioning in the range of 25 W < POUT < 200 W, the

optimal choice for meeting EN61000-3-2 and

maintaining high efficiency would generally call for a

Boundary Conduction Mode (BCM) PFC. BCM PFC

benefits from the use of a smaller, more efficient boost

inductor and exploits the use of Zero-Voltage Switching

(ZVS) and Zero-Current Switching (ZCS) to maintain

high efficiency. From a power-conditioning point of

view, the goal of a PFC circuit used in LED lighting is

no different from most other AC-DC power applications,

such as computing for example.

AC-DC DC-DCCCCV

LOAD

CONTROLAC

ANALOG

DIM

PWM

DIM

LED DRIVER

PFC

EMI

BIAS

(OPTIONAL)

Fig. 3. Industrial LED lighting, simplified system block diagram

The LED driver is comprised of the DC-DC converter;

load control; LED-specific functions, such as dimming;

and any necessary protection functions. The primary

function of the driver is power conversion. The DC-DC

converter provides safety isolation from the AC mains

while converting the high-voltage PFC output to a DC

current suitably matched to the requirements of the LED

load. The LED load control is necessary for current

sharing when several, series-parallel LED strings are

used in high-power LED fixtures. In some cases, the

DC-DC and load control blocks, shown in Fig. 3, can be

combined where the load control provides CC-CV

feedback information to the DC-DC converter. Under

normal operation, the LED driver should operate in CC

regulation; however, there may be times when the driver

should operate in CV mode. For example, if the LED

string voltage increases beyond some maximum rated

value, the driver needs to respond quickly by changing

from CC to CV mode to protect the DC-DC converter

power-stage components. When the driver is operating

in CV mode, the LED current should be limited or

folded back, providing over-current protection to the

LED load. In addition to power conversion, a secondary

function of the driver is to enable dimming capability.

There are many different configurations for operating

dimmable LED light fixtures. Industrial LED lighting

systems typically use an analog or PWM dimming

interface in conjunction with occupancy sensors,

daylight sensors, and other controls to optimize the most

efficient light use. Analog dimming uses a 1-10 V (or 0-

10 V), DC control voltage to linearly adjust LED

brightness by controlling the LED DC current. A 1-10 V

control voltage adjusts the LED dimming range from

100% (10 V) to 10% (1 V). Because the light output can

only dim down to 10%, a separate switch is required for

ON/OFF control. Similarly, a 0-10 V control voltage

should result in 100% LED brightness at 10 V and any

voltage less than 1 V produces “minimum” brightness.

Minimum brightness is the lowest current level that the

driver can manage. Some drivers’ minimum output is

OFF, while other drivers’ minimum can be as high as

10%. Incompatible 0-10 V operation among different

drivers is one of the disadvantages of analog dimming.

Also, since the LED current level is directly affected, the

LED light output can experience a visible color shift.

Analog dimming is therefore not preferred in

applications where accurate color temperature is critical.

Fairchild Semiconductor Power Seminar 2013-2014 4

PWM dimming adjusts LED brightness by varying the

amount of time forward current is flowing through the

LED. The LED is switched ON and OFF at a frequency

greater than 100 Hz. 100 Hz is considered a high enough

frequency that most people cannot detect the presence of

LED flicker. The human eye “averages” the switching

LED current and perceives a change in brightness

proportional to the on-time of the LED. Many

controllers used in LED drivers have dedicated PWM

dimming inputs compatible with a wide range of PWM

frequencies and amplitudes. Pulsing the current allows

the LED to be on at full rated current during the time

that the PWM signal is HIGH. The advantage this has

over analog dimming is that the color temperature is

accurately preserved and no color shift is detected during

dimming. Whether using analog or PWM dimming, the

input signal can come from the DC-DC converter

directly or remotely, as shown in Fig. 3, by the ORing

function feeding each of the dimming blocks.

IV. HIGH-POWER HB-LED TOPOLOGIES

The flyback and LLC power topologies are two

popular choices commonly used in LED lighting

systems in the 25 W < POUT < 200 W range. In general,

the flyback is a simple, low-cost option for less than

100 W; while the LLC is a more sophisticated, high-

efficiency choice covering LED loads greater than

100 W. However, advanced LED lighting requirements

have blurred the line where each topology fits best.

The flyback converter can be designed using a single-

stage approach, as shown in Fig. 4. A single-stage refers

to the single power stage and controller used to handle

the PFC, isolation, and power conversion.

AC-DC

AC

EMI

PFC

FL7930B/C

CCCVFB

Fig. 4. Single-stage CC-CV PFC flyback

Since a flyback is really just an isolated boost

converter, a natural controller choice is to use a BCM

PFC controller, as shown in Fig. 4. When operating with

a boost converter, these controllers use a constant on-

time, variable-frequency control algorithm for sinusoidal

input current shaping. However, when used in a flyback

topology, the BCM controller must be forced to operate

with a fixed frequency, fixed duty-cycle[6]

to draw

sinusoidal input current. Changing from variable- to

fixed-frequency operation requires additional external

circuitry for the BCM PFC flyback to maintain high

power factor. The single-stage flyback also suffers from

higher voltage stress on the switching MOSFET, making

it difficult to optimize a design for high efficiency across

a wide input voltage range. Because the output ripple

voltage occurs at twice the line frequency (<120 Hz),

large output filter capacitors are required. Since LED

loads are sensitive to even small changes in LED

voltage, secondary post regulators are used to decrease

voltage variations caused by excessive ripple. The

combined requirements of high PF, low THD, extended

universal input range, and high efficiency can quickly

exceed the limitations of a single-stage flyback

converter. The single-stage flyback approach is best

reserved for LED lighting applications around 50 W or

slightly higher power when the input voltage range is

restricted to low-line or high-line only.

Although more complex, a two-stage design can

overcome many of the problems associated with single-

stage designs. A typical two-stage design includes an

AC-DC, PFC boost converter whose output is the input

to a downstream DC-DC converter. Since the output of

the PFC tends to be a regulated, high-voltage DC bus;

the LLC converter is a natural choice for a high-

efficiency DC-DC stage.

AC-DC

AC

EMI

PFC

FL7930B/C

FAN7621S

or

FLS Series

CCCVFB

VBULK=460VDC

30VDC<VLED<60VDC

Fig. 5. Two-stage, BCM PFC and CC-CV LLC

Fairchild Semiconductor Power Seminar 2013-2014 5

The two-stage design shown in Fig. 5 highlights a PFC

boost regulator operating in BCM mode. For extended

universal input range, the maximum peak input voltage

can be as high as 435 VPK (308 VRMS). Allowing for at

least 5% margin, the PFC output voltage should be set to

about 460 VDC. Adding a dedicated PFC stage allows

near unity PF over a wide input range, but hinders

overall efficiency. For example, achieving 90% system

efficiency with a two-stage design requires each stage

operate at 95% efficiency. Since the LLC converter is

operating from a regulated DC input voltage, the

efficiency is optimized and has been shown to reach a

peak of near 97% in an application such as this.

Similarly, the BCM PFC can reach very high efficiency

at high line, but is penalized at low-line due to the higher

peak switching currents and large input-to-output

conversion ratio. For industrial LED applications above

100 W, the two-stage PFC LLC solution can meet all the

system requirements mentioned in Section III and is a

popular choice where high efficiency is most important.

Two-stage designs can reach overall system efficiencies

approaching 95% at high line, but can fall below 90%

during low-line operation.

It can help increase low-line efficiency to operate the

PFC stage as a “boost-follower” instead of a regulated

output voltage. The PFC output of a boost follower

regulates to a fixed value during low-line operation, but

tracks (follows) the input as VIN is increased above some

set value. As long as the output voltage is always greater

than the input voltage, the conditions for the boost

regulator are satisfied. For example, if the PFC output is

250 VDC for 85 VRMS < VAC < 160 VRMS, the boost

conversion ratio is smaller and the PFC sees an

efficiency increase. For 160 VRMS < VAC < 308 VRMS, the

PFC output can follow the input, plus some headroom,

of say, 5%. This means the PFC output is always 5%

higher than the AC peak input for 160 VRMS < VAC <

308 VRMS. The downstream converter of the two-stage

design also sees an efficiency benefit, operating from a

lower DC input voltage during low-line AC operation.

The one major drawback of using the boost follower

with the LLC DC-DC converter is that the input voltage

to the LLC is no longer a fixed, regulated DC voltage.

Using a 2:1 input range and a varying output voltage

range is unacceptable for an LLC. However, the flyback

can handle wide input voltage variations, but has

difficulty maintaining high PF when used as single-stage

converter. Using a flyback in a two-stage design allows

the BCM PFC to operate as a boost follower, while

removing the burden of PFC from the flyback stage. If

the LLC converter shown in Fig. 5 is replaced with a

DC-DC flyback and the PFC is operated as a boost

follower, can comparable performance be achieved?

FLYBACK

FAN6300

HVIC

FAN7382

CCCVFB

250VDC<VBULK<460VDC

30VDC<VLED<60VDC

AC-DC

AC

EMI

PFC

FL7930B/C

Fig. 6. Two-stage, BCM PFC, CC-CV two-switch, quasi-resonant flyback

The proposed two-stage topology shown in Fig. 6,

illustrates a BCM PFC operating as a boost follower and

a two-switch flyback DC-DC converter. The drain-

source voltage stress for each MOSFET used in a two-

switch flyback is half that of its single-switch

counterpart. Reducing the maximum drain-source

voltage by half allows the use of more efficient, lower-

voltage MOSFETs for the flyback stage. The cost

incurred is that there are two primary switches and the

need for a high-side gate drive. While this is significant

compared to a single-switch flyback, it is on par with the

requirements for the LLC and a necessary step for

achieving high efficiency. In addition, since the

transformer primary is diode clamped between VIN and

GND, any energy clamped is re-circulated and used to

process power to the secondary. Therefore, there is no

need for a dissipative snubber normally found on a

single-switch flyback converter. Precise gate drive

timing requirements are also less critical with a two-

switch flyback. With the LLC, the potential for

damaging shoot-through current exists if the two

primary MOSFETs inadvertently conduct

simultaneously. The flyback controller must be a

variable frequency, Quasi-Resonant (QR) controller

capable of achieving high efficiency and lower EMI

through valley-switching during MOSFET turn-on.

Fairchild Semiconductor Power Seminar 2013-2014 6

Valley-switching reduces MOSFET switching loss by

turning on when the drain-source voltage is minimal.

Optimizing the circuit shown in Fig. 6 is no simple

task considering the wide variation of AC input voltage,

PFC output voltage, and LED voltage. The design details

of the two-switch flyback are shown with measured

verification in sections VI and IX.

V. LOAD CONTROL FOR HB-LEDS

High-power industrial LED fixtures consist of tens or

even hundreds of individual LEDs arranged in series or

series-parallel combinations. With series-parallel strings,

the main challenge is controlling the individual string

currents to achieve high current sharing accuracy.

Placing all the LEDs into a single series string is a

simple way to guarantee equal current through each

individual LED.

VCS

VLEDIF

VF

VF

VF

VF

CC LED

DRIVER

OUT

FB

GND

Fig. 7. High-voltage series LED string

Referring to the series LED string shown in Fig. 7, the

LED driver is representative of a switching regulator

operating in CC mode. Consider a given design

specification using IF=500 mA and VF=3.5 V with a total

of 60 LEDs in series. Assuming typical VF values for

every LED, the total string voltage is

VLED=60×3.5V=210 V (neglecting VCS), with a total

output power of 105 W. The cost of this high output

voltage comes at the expense of having to use LED

driver components with higher voltage ratings, which

can have a negative impact on driver efficiency.

Secondly, when considering that each VF can vary by as

much as 20%, the more LEDs placed in series, the wider

the variation on VLED, resulting in having to over-design

the power stage. While the current regulation can be

very accurate, additional circuitry is required to limit the

maximum output voltage. If any LED in the string fails

open, VLED could increase beyond the driver’s maximum

component ratings. Finally, from a safety point of view,

a 210-V output may not be acceptable for certain

industrial lighting applications. For example, compliance

with the UL 1310 safety standard limits the LED driver

maximum output voltage to 60 V. In addition, the

maximum LED current must be <5 A and the output

power <100 W. In summary, the higher the number of

LEDs required by a given application, the more thought

that should be given to a series-parallel configuration.

Driving a series-parallel LED arrangement solves the

high-voltage problem associated with a much larger

single series string, but introduces the need for current

balancing between parallel strings. Current balancing is

an important parameter because it affects the overall

light quality, as well as the long-term reliability of the

LEDs. Using a direct parallel connection might seem

like a simple approach, but this arrangement is plagued

with trouble. As shown in Fig. 8, the total LED current is

regulated by the CC LED driver and it is assumed that

the individual string currents share equally. Due to wide

variations in VF however, this is rarely the case. The

more series LED connections placed in a string, the

greater the current variation between strings.

CC LED

DRIVER

OUT

FB

GND VCS

VLEDIF1

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

IF2 IFN

ILED

RB1 RB2 RBN

Fig. 8. Series-parallel LED strings with balance resistors

Fairchild Semiconductor Power Seminar 2013-2014 7

Balancing resistors placed in series with each LED

string can help, but this also has a negative impact on

efficiency, especially at higher current levels. The circuit

does not account for faults, such as an open LED. If any

string fails due to an open LED, the CC driver continues

to source the regulated LED current, ILED; causing the

current in the remaining strings to increase accordingly.

The light output of the remaining lit LEDs increases

dramatically or may fail if the additional load current

exceeds the maximum LED current rating. While this

configuration is simple and inexpensive, it is not a viable

approach for most industrial LED lighting systems.

Accurate current balance requires the current in each

LED string to be regulated independently. In

applications where string currents might be <200 mA,

simple CC linear regulators can be used, as shown in

Fig. 9. This circuit uses a voltage pre-regulator to

provide a regulated DC voltage designed to source the

desired amount of total LED current. The current in each

string can be precisely set to the desired level and is

independent of VF variations. Also, if a single LED fails

open, the remaining strings continue to regulate at their

set LED current level. While this approach is straight-

forward for regulating parallel string currents, it suffers

from several shortcomings.

VOLTAGE

PRE-REG

OUT

FB

GND

VBUSIF1

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

IF2 IFN

ILED

CC

REG

CC

REG

CC

REG

Fig. 9. Series-parallel LED strings with CC linear regulators

The additional pre-regulator voltage necessary to

cover VF variations is dropped across the linear

regulators, which has a negative impact on efficiency.

The most “efficient” way to implement this circuit

depends upon using LEDs with matched VF, which

increases LED cost. The maximum current and power

dissipation ratings associated with these types of linear

regulators limits their use in many higher power

industrial LED lighting fixtures. One way to overcome

the inefficiency of linear current regulators is to replace

them with more efficient switching regulators.

For LED strings where the maximum string voltage is

<80 V, the LED voltage is usually less than the

minimum DC voltage from the pre-regulator, VBUS.

These types of applications can use a CC buck topology

switching regulator in each string, as shown in Fig. 10.

The buck regulator requires the output voltage be less

than the input voltage and it operates most efficiently

when the ratio of VOUT/VIN (duty cycle) is closest to 1.

Depending upon input and output conditions, the

efficiency of the CC buck regulator can be as much as

20%-30% higher compared to the CC linear regulators

used in Fig. 9. Each individual LED string current is

sensed by a dedicated current-sense resistor, RCS, used to

accurately regulate the current. Since the current is

sensed on every switching cycle, these regulators have

the ability to provide cycle-by-cycle current limit. These

types of CC buck regulators are primarily chosen based

on their input and output voltage ratings, switching

frequency capability, and maximum allowable duty

cycle. CC buck regulators targeting the LED market can

also contain unique features required by LED lighting

applications. Analog or PWM dimming capability and

open- and short-LED protections are important for high

power industrial LED lighting systems.

In spite of the many advantages CC buck regulators

have over their linear counterparts, the obvious

consequence of their use is higher component count and

cost. For the purpose of simplicity, the diagram shown in

Fig. 10 fails to illustrate most of the supporting

components required to complete each buck regulator.

To minimize the size of inductors and capacitors, CC

buck regulators need to operate at switching frequencies

in the range of several-hundred KHz. Operating

multiple, high-frequency, switching regulators

independently can generate random and unpredictable

Electromagnetic Interference (EMI) emissions. Higher

levels of EMI have a second order impact on efficiency

when considering the size of the front-end EMI filter

design. Finally, current sharing accuracy is hindered by

cumulative differences between component and set point

tolerances among individual CC buck regulators.

Fairchild Semiconductor Power Seminar 2013-2014 8

Achieving an overall current balance variation better

than 5% is considered successful using this approach.

Nonetheless, the popularity of using CC buck regulators

for current balance in high-power LED systems is

evident by the number of controllers in the market today.

VOLTAGE

PRE-REG

OUT

FB

GND

VBUS

IF1

VF

VF

VF

VF

ILED

SW

CSVIN

GND

RCS1

CC BUCK

IF2

VF

VF

VF

VF

SW

CSVIN

GND

RCS2

CC BUCK

IFN

VF

VF

VF

VF

SW

CSVIN

GND

RCSN

CC BUCK

Fig. 10. Series-parallel LED strings with CC switching regulators

A better current balancing approach would require

fewer components, use linear load control to minimize

EMI, offer better than 5% current sharing accuracy, and

include all of the LED functions typically required by a

high-performance, industrial lighting fixture.

FAN7346

CURRENT

BALANCE

OVR

FB1

GND VCS1

VLEDIF1

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

IF2 IFN

ILED

VCS2 VCSN

FB2

FBN

CC-CV

LED

DRIVER

OUT

GND

FB FB OUT1

OUT2

OUTN

CH1

CH2

CHN

ADIM

PWMN

FO

Q1

Q2

QN

VMINNC

Fig. 11. FAN7346, 4-channel LED current balance controller

The FAN7346 LED current balance controller can

manage up to four, 100-V parallel LED strings with

±1.5% current-sharing accuracy. As shown in Fig. 11, a

CC-CV LED driver provides the required LED current,

ILED. The control and feedback to determine CC or CV

regulation is provided by the FAN7346 in this case.

Each sensed LED string current uses an internal

comparator and precision reference to control the drain

voltage of the external MOSFET. The gate voltage of

each MOSFET is adjusted to precisely maintain 1 V on

the drain. As a result, the external MOSFETs are

operated in their linear region and are not switching, so

there is no additional EMI generated with this control

scheme. When regulating in CC mode, the FAN7346

uses a feedback signal, FB, to precisely control the

minimum required amount of headroom voltage, VLED,

necessary to maintain 1 V on the drain of each external

MOSFET. Minimizing the drain voltage on the control

MOSFETs is important for reducing power dissipation.

The FB signal can be connected directly to a secondary-

side CC-CV driver (as shown in Fig. 11) or, more

commonly, connected to a primary-side CC-CV driver

via an optocoupler.

For applications that might require more than four

strings, two or more FAN7346 controllers can be

paralleled using a “master / slave” arrangement, such as

the one shown in Fig. 12.

Fairchild Semiconductor Power Seminar 2013-2014 9

FAN7346

CURRENT

BALANCE

OVR

FB1

GND VCS1

IF1

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

IF2 IFN

ILED

VCS2 VCSN

FB2

FBN

CC-CV

LED

DRIVER

OUT

GND

FB FB OUT1

OUT2

OUTN

CH1

CH2

CHN

ADIM

PWMN

FO

Q1

Q2

QN

FAN7346

CURRENT

BALANCE

OVR

FB1

GND VCS5

VLEDIF5

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

VF

IF6 IFN

VCS6 VCSN

FB2

FBNFB OUT1

OUT2

OUTN

CH1

CH2

CHN

ADIM

PWMN

FO

Q5

Q6

QN

NC

VMINVMIN

MASTER SLAVE

Fig. 12. FAN7346, 4-channel LED current balance controller, master / slave configuration

As shown in Fig. 12, the FAN7346 master FB pin

provides the CC-CV feedback information to the PWM

controller for the LED driver. The FAN7346 slave FB is

left open. The VMIN pin acts as synchronization pin;

therefore, the VMIN pins must be connected together.

During single FAN7346 operation, the VMIN is left

open, as shown in Fig. 11. The FO pins are also

connected together so that any LED fault occurring in

any string generates a fault output.

Control inputs for analog and PWM dimming are also

included. The analog dimming function requires a 0-5 V

DC input to dim all four LED channels simultaneously

from 100% to 12% minimum. For PWM dimming, each

LED string has a dedicated PWM input. This allows

each channel to be dimmed independently or

simultaneously from 100% down to 0.5% brightness.

The controller includes open-LED, short-LED, and over-

current protection for each string. In the event of a fault,

an open-drain Fault Output (FO) signal is generated and

can be used as a flag to signal that an LED fault has

occurred. During fault modes or dimming, perfect

current balance is accurately retained.

For CV operation, the maximum allowable LED

voltage, VLED, is set by a resistor divider. In the event

that VLED reaches the set value, the FAN7346 switches

from current regulation to voltage regulation. As the

LED load is driven deeper into voltage regulation, ILED

reduces accordingly. For industrial LED lighting

applications, none of the other methods discussed herein

can match the current-sharing accuracy, efficiency,

reduced EMI, reduced component count, or performance

features of the FAN7346 LED load control solution.

VI. DESIGN EXAMPLE

A design example for a general-purpose industrial

LED lighting driver is detailed. The primary design

goals for the design are:

Wide input 85 VRMS < VAC < 308 VRMS

Maximize efficiency over a wide operating range

Configurable for single-channel or 4-channel LED

operation

Compatible with 0 V-10 V analog dimming and 0%-

100% PWM dimming

Lowest possible design profile

Designing for the single string operation and four

series-parallel strings is achieved by using one of two

controller cards that can be inserted into a main power

board common to both options. The targeted design

specifications are summarized in Table 1.

Fairchild Semiconductor Power Seminar 2013-2014 10

TABLE 1. DESIGN EXAMPLE SPECIFICATIONS

Parameter Min. Typ. Max.

BCM PFC Stage

VAC (VRMS) 85 308

fVIN(AC) (Hz) 50 60 65

VOUT_PFC (V) Fixed Regulation 440 450 465

VOUT_PFC(V) Boost Follower 245 VIN(PK)+30 465

POUT_PFC (W) 120

fSW_PFC (kHz) 40 300

tSOFT_START (ms) 50

tON_OVERSHOOT (V) 10

η_PFC 0.9 0.95

Two-Switch Flyback DC-DC LED Stage

VIN (V) 250 460

VOUT_LED (V) 30 60

IOUT_LED (A) Single Channel 2

IOUT_LED (mA) 4-Channel (Per Channel) 350

POUT_LED (W) 100

fSW_LED (kHz) 50 150

η_LED 0.9 0.95

Total System

η_120V 0.90

η_230V 0.90

Parameter Min. Typ. Max.

PF_120V 0.95 0.99

PF_230V 0.95

Mechanical and Thermal

Height (mm) 30

TJ (°C) 60

BCM PFC DESIGN

PFC boost power converters are operated in

Continuous Conduction Mode (CCM), Discontinuous

Conduction Mode (DCM), or Boundary Conduction

Mode (BCM). For power levels less than about 200 W,

BCM control offers higher efficiency due to ZCS, VDS

valley switching, and the smaller physical size of the

boost inductor. A BCM PFC design using the FL7930C

Boundary-Mode PFC Controller is shown in Fig. 13.

The PFC converter must operate over the full input

voltage range of 85 VRMS < VAC < 308 VRMS and includes

a configurable option for boost follower circuitry.

FL7930C1

2

3

4 5

6

7

8

OUT

VCC

GND

ZCDCS

COMP

RDY

INV PBIAS

ZCD

ZCD

ACEMI

FILTER

RDY

(TO FLYBACK)

BF

ON

OFF

VOUT

(TO FLYBACK)

1

2

3

R5

R6

C4

C5

R7

R8

R9

R10 R11

D6

D7 Q3

Q4

Q5

L1

D8

C6

C7

NB

NAUX

VIN

RZCD

RCS

J1

Fig. 13. FL7930C BCM PFC with boost follower

Fairchild Semiconductor Power Seminar 2013-2014 11

The fundamental waveforms of the BCM PFC

converter are shown in Fig. 14. Each switching period,

TS, is made of three distinct time intervals, tOFF, tRES, and

tON. During tOFF; the MOSFET, Q3 is OFF; the boost

diode, D8 is conducting; and the inductor current is

ramping downward from IL(PK) to 0 A. During tRES; the

MOSFET drain voltage, VDS, resonates from VOUT down

to some minimum value equal to 2×(VOUT -VIN). When

Q3 is turned on at the VDS minimum value, this is called

“valley switching.” For VOUT=2xVIN, the minimum VDS

voltage resonates to 0 V or lower, setting up the

condition for ZVS. Q3 turn-on is determined by an

auxiliary (AUX) winding coupled to the main L1 boost

winding. A Zero-Current Detect (ZCD) signal is

generated from VAUX. During tRES, ZCD resonates below

a 1.4-V threshold, triggering the internal gate drive turn-

on command. Since the ZCD detection occurs while the

inductor current is negative, a 150 ns ZCD delay is

introduced, allowing Q3 turn-on under ZCS conditions.

0V

VDS

tREStOFF tON

TS

0V

VAUX

0V

VZCD

0.65V

0A

IL

0V

VGS

VIN

VOUT

2x(VOUT – VIN)

1.4V

t

ZCD Delay

(150ns)

NAUX

NB

x (VOUT – VIN)

NAUX

NB

x VIN

1.5V

IL(PK)

Fig. 14. BCM PFC fundamental waveforms

BCM control relies on a constant on-time, variable-

frequency control algorithm for maintaining near unity

PF. Constant on-time control requires the MOSFET on-

time remain constant within a full line cycle. Since the

MOSFET is turned on at zero current and the on-time is

constant, the peak inductor current is proportional to the

line voltage. The waveforms shown in Fig. 15 highlight

the BCM operation within a half line cycle. The

switching frequency is shown much slower than normal

to illustrate the waveforms and frequency variation. The

average current is derived from half the value of each

triangular inductor current peak and is therefore

proportional to the AC line voltage. The maximum

switching frequency occurs near the zero crossing of the

AC line voltage, while the peak voltage coincides with

minimum switching frequency.

t

VGS

IL

t

FS

t

Fig. 15. BCM constant on time, variable frequency waveforms

The PFC efficiency benefits from ZCS, ZVS, and valley

switching are critical for achieving high system-level

efficiency. However, efficiency for all PFC boost

converters tends to decrease at low-line. This is mostly

due to the fact that boost converters process power more

efficiently at lower duty cycle corresponding to higher

input voltage. Generally, the PFC output voltage is fixed

at 400 V, resulting in a maximum power conversion

ratio during low-line operation. The BCM boost can be

operated in a boost follower mode with input and output

voltage characteristics, as shown in Fig. 16.

Fairchild Semiconductor Power Seminar 2013-2014 12

The rectified AC voltage represents the peak values

expected for 85 VRMS < VAC < 308 VRMS. The boost

follower output should be fixed at 250 V for low-line

operation. For VAC > 160 VRMS, the PFC output voltage

should follow the input voltage to within VAC(PK) + 30 V,

up to 308 VRMS. Allowing the boost follower to track the

input voltage down to 85 VRMS benefits the low-line

efficiency of the PFC, but the downstream flyback

converter is penalized by having to handle such a wide

input voltage range of 3:1. Setting the boost follower

output voltage to track between 250 V < VOUT < 465 V

offers a good compromise between PFC and flyback

efficiency, while limiting the flyback converter input

voltage range to 2:1. J1, shown in the boost follower

circuitry in Fig. 13, can be configured in one of three

ways: (1) BF-ON enables boost follower mode, 250 V <

VOUT < 460 V; (2) BF-OFF regulates the PFC output

voltage to 465 V; and (3) BF-OPEN regulates the PFC

output voltage to 250 V.

time (ms)

Vo

lta

ge

(V

)

0 20 40 60 80 100 120 140 160

50

100

150

200

250

300

350

400

450

0

500

180 200

VOUT=465V

250V<VOUT<475V

85VRMS<VAC<308VRMS

Fig. 16. PFC boost follower voltage characteristics

A circuit for achieving the boost follower voltage

profile of Fig. 16 is shown in Fig. 17. R4 and R5 form the

output voltage divider that is always present for any

voltage regulated PFC converter. In this case, the divider

is set to the minimum boost follower output voltage, VO1

= 250 V. R5 is chosen by setting I2 to 150 µA when the

FL7930C is in regulation and is calculated by:

𝑅5 =𝑉𝑅𝐸𝐹

𝐼2 (1)

=2.5𝑉

150𝜇𝐴= 16.7𝑘Ω

R4 is calculated by:

𝑅4 =𝑅5 × (𝑉𝑂1 − 𝑉𝑅𝐸𝐹)

𝑉𝑅𝐸𝐹 (2)

=16.7𝑘Ω × (250𝑉 − 2.5𝑉)

2.5𝑉= 1.65𝑀Ω

R1

R2

Vf

Vbe

R3

R4

R5

1

3COMP

INV VREF

(2.5V)

FL7930C

85VRMS<VAC<308VRMS

VO1=250VDC

VO2=475VDC

Vctrl

VbI1 I2

R6 C1

I3

I4

EA

Q1

D1

Fig. 17. Boost follower circuitry

The boost follower circuitry is comprised of R1, R2,

R3, D1, Q1, and R6 with C1 forming a low-pass filter. The

low-pass filter should be sized to attenuate 120 Hz.

When properly biased, Q1 allows a current, I1, to flow

through R3, pulling additional current through R4. I1 is

linearly proportional to I2 according to the boost

follower voltage gain defined by VO2 and VO1 as:

𝐼1 = 0𝐴, 𝑓𝑜𝑟 𝑉𝐴𝐶 < 160𝑉𝑅𝑀𝑆

𝐼1 = 𝐼2 × [𝑉𝑂2

𝑉𝑂1− 1] , 𝑓𝑜𝑟 𝑉𝐴𝐶 = 308𝑉𝑅𝑀𝑆

(3)

= 150µA × [475V

250V− 1] = 135µA, 𝑓𝑜𝑟 𝑉𝐴𝐶 = 308𝑉𝑅𝑀𝑆

From Eq (3), an additional current of I1=135µA is

required when VOUT=475 V. The boost follower control

voltage, Vctrl, is fixed according to the base voltage, Vb.

Vb must be must be carefully chosen so as not to saturate

Q1 during high-line operation:

𝑉𝑐𝑡𝑟𝑙 = 𝑉𝑏 − 𝑉𝑏𝑒 , 𝑓𝑜𝑟 𝑉𝐴𝐶 = 308𝑉𝑅𝑀𝑆 (4)

= 2𝑉 − 0.7𝑉 = 1.3𝑉, 𝑓𝑜𝑟 𝑉𝐴𝐶 = 308𝑉𝑅𝑀𝑆

Fairchild Semiconductor Power Seminar 2013-2014 13

For Vctrl=1.3 V during VAC=308 V, R3 can then be

calculated as:

𝑅3 =𝑉𝑐𝑡𝑟𝑙

𝐼1 (5)

=1.3𝑉

135𝜇𝐴= 9.53𝑘Ω

The VAC divider formed by R1 and R2 is sized to set

Vb=2 V at VAC=308 VRMS. R2 is calculated by choosing

I4 as 1 mA:

𝑅2 =𝑉𝑏 + 𝑉𝑓

𝐼4 (6)

=2𝑉 + 0.5𝑉

1𝑚𝐴= 2.5𝑘Ω

And R1 can now be determined by:

𝑅1 =𝑅2 × [√2 × 𝑉𝐴𝐶(𝑀𝐴𝑋) − (𝑉𝑏 + 𝑉𝑓)]

𝑉𝑏 + 𝑉𝑓 (7)

=2.5𝑘Ω × [√2 × 308𝑉𝑅𝑀𝑆 − (2𝑉 + 0.5𝑉)]

2𝑉 + 0.5𝑉= 433𝑘Ω

Ideal calculated component values used in Eq (1)–Eq

(7) provide a reasonable starting point. However, actual

component values may need to be modified due to

inaccuracies in estimating Vbe and Vf. Using ideal

component values, the calculated dynamic range for Vctrl

can be plotted over the full AC line range of 85 VRMS <

VAC < 308 VRMS. The boost follower control voltage as a

function of AC line voltage is given as:

𝑉𝑐𝑡𝑟𝑙(𝑉𝐴𝐶) = (𝑅2

𝑅1 + 𝑅2) × √2 × 𝑉𝐴𝐶 − (𝑉𝑓 + 𝑉𝑏𝑒) (8)

Eq (8) is used to create the plot shown in Fig. 18. As

determined from Eq (4), Vctrl = 1.3 V for VAC =

308 VRMS. For VAC < 150 VRMS, Vctrl = 0 V and VOUT is

determined from the R4, R5 divider and I2. The

breakpoint at which the boost follower output begins

tracking the AC input occurs near VAC = 150 VRMS.

Fig. 18. Vctrl vs. VAC

Vctrl, I1, and I2 for the most critical values of VAC are

summarized in TABLE 2. Additional details and variations

of the boost follower implementation are highlighted in

Equation [9].

TABLE 2. BOOST FOLLOWER CONTROL VARIABLES

VAC (VRMS) Vctrl (mV) I1 (µA) I2 (µA)

85 0 0 150

150 19 2 150

160 95 10 150

308 1287 135 150

Designing the PFC power stage begins with

calculating the peak and RMS inductor current, where a

20% design margin is applied to POUT:

𝐼𝐿(𝑃𝐾) =4 × 𝑃𝑂𝑈𝑇

𝜂 × √2 × 𝑉𝐴𝐶(𝑀𝐼𝑁)

(9)

=4 × 144𝑊

0.95 × √2 × 85𝑉𝑅𝑀𝑆

= 5𝐴𝑃𝐾

𝐼𝐿(𝑅𝑀𝑆) =𝐼𝐿(𝑃𝐾)

√6 (10)

𝐼𝐿(𝑅𝑀𝑆) =5𝐴𝑃𝐾

√6= 2𝐴𝑅𝑀𝑆

The boost inductor is determined by output power and

minimum operating frequency. A typical starting point is

between 40~50 kHz, which is above the maximum

audible frequency of 20 kHz. Because the boost follower

output voltage varies, the inductor is calculated for

maximum high-line (308 VRMS) and maximum low-line

(160 VRMS) and the lowest value is selected.

Fairchild Semiconductor Power Seminar 2013-2014 14

𝐿𝐻𝐿

=𝜂 × (√2 × 𝑉𝐴𝐶(𝑀𝐴𝑋))

2

4 × 𝐹𝑀𝐼𝑁 × 𝑃𝑂𝑈𝑇 × (1 +√2 × 𝑉𝐴𝐶(𝑀𝐴𝑋)

𝑉𝑂𝑈𝑇 − √2 × 𝑉𝐴𝐶(𝑀𝐴𝑋)

)

(11)

=0.9 × (√2 × 308𝑉𝑅𝑀𝑆)

2

4 × 45𝑘𝐻𝑧 × 144𝑊 × (1 +√2 × 308𝑉𝑅𝑀𝑆

460𝑉 − √2 × 308𝑉𝑅𝑀𝑆

)

𝐿𝐻𝐿 = 350𝜇𝐻

𝐿𝐿𝐿

=𝜂 × (√2 × 𝑉𝐴𝐶(𝑀𝐼𝑁))

2

4 × 𝐹𝑀𝐼𝑁 × 𝑃𝑂𝑈𝑇 × (1 +√2 × 𝑉𝐴𝐶(𝑀𝐼𝑁)

𝑉𝑂𝑈𝑇 − √2 × 𝑉𝐴𝐶(𝑀𝐼𝑁)

)

(12)

=0.9 × (√2 × 160𝑉𝑅𝑀𝑆)

2

4 × 45𝑘𝐻𝑧 × 144𝑊 × (1 +√2 × 160𝑉𝑅𝑀𝑆

250𝑉 − √2 × 160𝑉𝑅𝑀𝑆

)

𝐿𝐿𝐿 = 168𝜇𝐻

𝐿𝐿𝐿 < 𝐿𝐻𝐿 ∴

𝐿 = 𝐿𝐿𝐿 ≅ 170𝜇𝐻

For the calculated peak current corresponding to the

calculated inductor value, maximum on-time is given by:

𝑡𝑂𝑁(𝑀𝐴𝑋) = 𝐿 ×𝐼𝐿(𝑃𝐾)

√2 × 𝑉𝐴𝐶(𝑀𝐼𝑁)

(13)

= 170𝜇𝐻 ×5𝐴𝑃𝐾

√2 × 85𝑉𝑅𝑀𝑆

= 7𝜇𝑠

The result is less than the minimum; maximum on-

time from the FL7930C datasheet of 35 µs.

The inductor core selected is a low-profile EFD30

with properties shown in Table 4. The estimated air gap

length to achieve 170 µH is given by Eq (42) as:

𝑙𝑔 =4π × 10−7 𝐻

𝑚× 41𝑇2 × 69𝑚𝑚2

170𝜇𝐻= 0.9𝑚

The number of turns, NB, for the boost winding is

calculated by:

𝑁𝐵 =𝐿 × 𝐼𝐿(𝑃𝐾)

𝐵𝑃𝐾 × 𝐴𝑒 (14)

=170𝜇𝐻 × 5𝐴𝑃𝐾 × 108

3000𝐺 × 0.69𝑐𝑚2 = 41𝑇

The auxiliary (AUX) winding must produce enough

voltage to cross the 1.5 V ZCD threshold. The minimum

number of AUX turns is:

𝑁𝐴𝑈𝑋 =1.5𝑉 × 𝑁𝐵

𝑉𝑂𝑈𝑇 − √2 × 𝑉𝐴𝐶(𝑀𝐴𝑋)

(15)

=1.5𝑉 × 41𝑇

460𝑉 − √2 × 308𝑉𝑅𝑀𝑆

= 3𝑇

The boost inductor winding stack is shown in Table 3.

AC copper losses are minimized in the boost winding by

using Litz wire. The benefits and use of Litz wire for

designing high-frequency magnetic components are

discussed in the “Two-Switch Flyback Design” section.

TABLE 3. PFC BOOST INDUCTOR WINDING TABLE

Winding Pins (S→F) Wire Layers Turns

Boost 6→1 40/38, Served Litz 2 41

AUX 9→10 2/38, Bifilar 1 3

During VIN = 308 VRMS, the peak voltage seen by the

MOSFET is 435 VPK. When VIN = 85 VRMS, the peak

drain current is IL(PK) = 5 APK. The RMS drain current is

1.6 ARMS as determined by Eq (20). FCP190N60 is a

600 V, 20 A device and is chosen for the PFC boost

MOSFET, Q3. The boost output diode rectifier must

withstand a maximum blocking voltage of 460 V. ES3J

is a 600 V, 3 A, fast recovery diode and is chosen as the

PFC boost rectifier, D8.

Most LED lighting applications do not have a hold-up

requirement, so the output capacitor is sized strictly to

limit the amount of output voltage ripple. If the output

ripple voltage, ΔVOUT, is limited to about 5% of the

minimum boost follower output voltage, the output

capacitance can be calculated by:

𝐶𝑂𝑈𝑇 ≥𝑃𝑂𝑈𝑇

𝑉𝑂𝑈𝑇(𝑀𝐼𝑁) × 2𝜋 × 𝐹𝐿(𝑀𝐼𝑁) × ΔV𝑂𝑈𝑇 (16)

≥144𝑊

250𝑉 × 2𝜋 × 50𝐻𝑧 × (0.05 × 250𝑉)= 150𝜇𝐹

Fairchild Semiconductor Power Seminar 2013-2014 15

The voltage rating for COUT is 460 V. High-voltage,

low-profile, bulk capacitors are limited to about

450 VDC. Therefore, to achieve the required voltage

rating; two 330-µF, 250-V rated aluminum electrolytic

capacitors are used in series for C4 and C5 in Fig. 13.

Configuring the FL7930C begins with setting the ZCD

resistor value. The ZCD signal is internally clamped to

0.65 V, as shown in Fig. 14. The minimum ZCD resistor

for clamping is chosen to satisfy Eq (17):

𝑅𝑍𝐶𝐷(1) ≥

𝑁𝐴𝑈𝑋

𝑁𝐵× √2 × 𝑉𝐴𝐶(𝑀𝐴𝑋) − 0.65𝑉

3𝑚𝐴 (17)

≥

3𝑇41𝑇

× √2 × 308𝑉𝑅𝑀𝑆 − 0.65𝑉

3𝑚𝐴= 10.5𝑘Ω ≅ 11kΩ

The ZCD resistor also influences the FL7930C control

range by setting the maximum on-time. From a control

point of view, the ZCD resistor is calculated as:

𝑅𝑍𝐶𝐷(2) ≥28𝜇𝑠

Δ𝑡𝑂𝑁(𝑀𝐴𝑋)×

√2 × 𝑉𝐴𝐶(𝑀𝐴𝑋) × 𝑁𝐴𝑈𝑋

0.469𝑚𝐴 × 𝑁𝐵 (18)

≥28𝜇𝑠

35µs − 7µs×

√2 × 308𝑉𝑅𝑀𝑆 × 3𝑇

0.469𝑚𝐴 × 41𝑇= 68.1𝑘Ω

To guarantee enough dynamic control range to cover

the wide input range and variable output voltage, a ZCD

resistor close to the value of RZCD(2) is used.

𝑅𝑍𝐶𝐷 = 𝑅𝑍𝐶𝐷(2) = 68.1𝑘Ω

The current-sense resistor, RCS, is used for Over-

Current Protection (OCP) only and is calculated by:

𝑅𝐶𝑆 =𝑉𝐶𝑆(𝐿𝐼𝑀)

𝐼𝐿(𝑃𝐾)

(19)

=0.7𝑉

5𝐴𝑃𝐾= 140𝑚Ω

The RMS current through RCS is the same as the

MOSFET RMS current and is given by:

𝐼𝐷(𝑅𝑀𝑆) = 𝐼𝐿(𝑃𝐾) × √1

6−

4 × √2 × 𝑉𝐴𝐶(𝑀𝐼𝑁)

9𝜋 × 𝑉𝑂𝑈𝑇 (20)

= 5𝐴𝑃𝐾 × √1

6−

4 × √2 × 85𝑉𝑅𝑀𝑆

9𝜋 × 250𝑉= 1.6𝐴𝑅𝑀𝑆

The power dissipated in RCS is given by:

𝑃𝑅𝐶𝑆 = 𝐼𝐷(𝑅𝑀𝑆)2 × 𝑅𝐶𝑆 (21)

𝑃𝑅𝐶𝑆 = 1.6𝐴𝑅𝑀𝑆2 × 140𝑚Ω = 360𝑚𝑊

Two 280 mΩ, 1210, surface-mount resistors rated for

500 mW each are used in parallel to meet the 360 mW

power requirement.

The FL7930C also includes a ready (RDY) function,

as shown in Fig. 13. The RDY function is used to

disable the downstream, two-switch flyback until the

PFC output reaches 89% of the set regulated voltage.

TWO-SWITCH FLYBACK DESIGN

The two-switch, QR flyback design uses the

FAN6300H current mode PWM controller as the control

integrated circuit (IC) and the FAN7382 high-voltage IC

(HVIC) to develop the dual gate drives. Much of the

design procedure is fundamental for the flyback and is

covered in various application notes. Therefore, this

design example focuses on aspects important for high

efficiency and functionality applicable to industrial LED

lighting. The critical power-stage components and gate

drive circuitry are shown in Fig. 19.

Fairchild Semiconductor Power Seminar 2013-2014 16

CC

CVFB

FAN6300H1

2

3

4 5

6

7

8

NC

HV

VDD

GATEGND

CS

FB

DET

FAN73821

2

3

4 5

6

7

8

HO

VB

VS

LOCOM

LIN

HIN

VCCPBIAS

VIN

R1

R2

R3

Q1

Q2

D1

D2

D3

D4D5

ACIN

R4

C1

VA

VLED

VHS

C2

C3

(FROM PFC)

(FROM PFC)

RDY

PBIAS

Fig. 19. Simplified two-switch flyback power stage and gate drive circuitry

The basic operation can best be explained by referring

to the key switching waveforms shown in Fig. 20. QR

flyback converters use variable-frequency control to

maintain operation at the boundary of CCM and DCM.

In a two-switch QR flyback, there are two primary

referenced MOSFETs switching synchronously, as

indicated by VGS(HS) and VGS(LS). Matching exact timing

between the two gate drives is not so critical because

there is no direct connection between the high-side (HS)

and low-side (LS). However, the primary transformer is

only energized during the time that both MOSFETs are

conducting. A switching period, TS, is made of three

distinct time intervals: (1) tON where both primary

MOSFETs are conducting and the transformer primary

is energized, (2) tOFF where both primary MOSFETs are

OFF and power is transferred to the secondary, and (3) tf

where the drain voltage resonates down to some

minimum value. The gate drive turn-on command is

initiated when the DET pin sources a current, IDET >

30 µA, as determined by the AUX winding voltage, VA,

and the DET resistor divider, R1 and R2. The gate turn-

on signal is triggered 200 ns after IDET > 30 µA. The gate

turn-on coincides with the minimum VDS valley voltage,

reducing COSS x VDS2 power loss. Extended valley

switching occurs if the first valley is not detected. In this

case, turn-on can occur at any subsequent valley.

Switching losses are further reduced by ZCS achieved at

turn-on since ID always starts from 0 A. The DET

voltage is diode clamped to within 0.7 V when VA < 0 V

and the DET resistor divider is set to maintain less than

2.5 V during normal operation. After a 5 µs blanking

period, if the 2.5 V threshold is crossed, output Over-

Voltage Protection (OVP) is enabled. OVP is latching

and reset only by VDD < UVLO.

Fairchild Semiconductor Power Seminar 2013-2014 17

0V

VDS

0A

IDS

tftOFF tON

TS

0A

ID

VA VA

0V

0V

VDET

0V

VIN

PBIAS

VIN+VHS

VGS(HS)

VGS(LS)

0.7V

5µs

2.5V

VO

OVP

IDET(SOURCE)>30µA

tDELAY=200ns

VRO

2

VRO

2

VIN

2

VIN

2

Fig. 20. Two-switch flyback key switching waveforms

The design procedure starts with the power-stage

components. The theoretical duty cycle limit is 0.5, but

allowing for rise and fall delays and some additional

design margin, the maximum duty cycle is limited to

0.45. The drain-source resonant fall-time, tf, is estimated

to be 600 ns and verified using Eq (28) once the power

stage components are determined. The output rectifier

forward voltage drop, Vf, is assumed to be 2 V.

Calculate the required transformer turns ratio, n, as:

𝑛 =𝑉𝐼𝑁(𝑀𝐼𝑁) × 𝐷𝑀𝐴𝑋

(1 − 𝐹𝑀𝐼𝑁 × 𝑡𝑓) − 𝐷𝑀𝐴𝑋

×1

𝑉𝑂 + 𝑉𝑓 (22)

=250𝑉 × 0.45

(1 − 50𝑘𝐻𝑧 × 600𝑛𝑠) − 0.45×

1

60𝑉 + 2𝑉= 3.48

Round n to 3.5 and calculate the reflected output

voltage, VRO, and the maximum drain-source voltage

stress for each of the primary MOSFETs:

𝑉𝑅𝑂 =𝑛 × (𝑉𝑂 + 𝑉𝑓)

2 (23)

=3.5 × (60𝑉 + 2𝑉)

2= 108.5𝑉

𝑉𝐷𝑆(𝑀𝐴𝑋) =𝑉𝐼𝑁(𝑀𝐴𝑋)

2+ 𝑉𝑅𝑂 (24)

=460𝑉

2+ 108.5 = 338.5𝑉

Calculate the transformer primary magnetizing

inductance, LM:

𝐿𝑀 =(𝑉𝐼𝑁(𝑀𝐼𝑁) × 𝐷𝑀𝐴𝑋)

2

2 ×𝑃𝑂

𝑛× 𝐹𝑀𝐼𝑁

(25)

=(250𝑉 × 0.45)2

2 ×100𝑊

0.9× 50𝑘𝐻𝑧

= 1.14𝑚𝐻

Design for LM=1 mH and calculate the maximum peak

and RMS MOSFET currents as:

𝐼𝐷𝑆(𝑃𝐾) =𝑉𝐼𝑁(𝑀𝐼𝑁) × 𝐷𝑀𝐴𝑋

𝐿𝑀 × 𝐹𝑀𝐼𝑁 (26)

=250𝑉 × 0.45

1.14𝑚𝐻 × 50𝑘𝐻𝑧= 2𝐴𝑃𝐾

𝐼𝐷𝑆(𝑅𝑀𝑆) = √𝐷𝑀𝐴𝑋

3× 𝐼𝐷𝑆(𝑃𝐾) (27)

= √0.45

3× 2𝐴𝑝𝑘 = 775𝑚𝐴𝑅𝑀𝑆

For a two-switch flyback, each primary MOSFET is in

series with the transformer primary. So the current

flowing through all three is equal. Therefore, choose an

N-channel MOSFET with a maximum voltage rating

greater than 338.5 V and a current rating able to handle

the average current as defined by Eq (27). FDP22N50 is

a 500 V, 22 A device with excellent high-frequency

switching characteristics. From the datasheet, the typical

output capacitance, COSS, for the FDP22N50 is 351 pF.

Fairchild Semiconductor Power Seminar 2013-2014 18

When valley switching operation occurs, it takes half the

resonant period for the drain voltage to fall from

VDS(MAX) to the first minimum valley. This resonant fall-

time was originally estimated as 600 ns, but can now be

calculated as:

𝑡𝑓 = 𝜋 × √𝐿𝑀 ×𝐶𝑂𝑆𝑆

2 (28)

= 𝜋 × √1𝑚𝐻 ×351𝑝𝐹

2= 1.3𝜇𝑠

Since the error between the estimated tf of 600 ns and

the calculated tf of 1.3 µs is about 2:1, a slight decrease

in DMAX can be expected. Rearranging Eq (22) and

solving for DMAX gives:

𝐷𝑀𝐴𝑋 =𝑉𝑂 − [(𝑉𝑂 + 𝑉𝑓) × 𝐹𝑀𝐼𝑁 × 𝑡𝑓]

𝑉𝐼𝑁(𝑀𝐼𝑁)

𝑛+ (𝑉𝑂 + 𝑉𝑓)

(29)

=60𝑉 − [(60𝑉 + 2𝑉) × 50𝑘𝐻𝑧 × 1.3𝜇𝑠]

250𝑉3.5

+ (60𝑉 + 2𝑉)= 0.42

The new value for maximum duty cycle is calculated

to be 0.42 and can probably be increased to 0.45. Using

DMAX=0.45 and tf=1.3 µs, the transformer turns ratio, n,

can be recalculated using Eq (22). The new value for n is

3.7 and shall be used for the transformer design. The

“area product” method for estimating transformer core

size is commonly used for core selection.

𝐴𝑒 × 𝐴𝑤 =𝑃𝑂 × 108 × 𝐹𝐾

2 × 𝐹𝑀𝐼𝑁 × 𝐵𝑃𝐾 × 𝑊𝐹 × 𝐶𝐷 × 𝑈𝐹 (30)

=100𝑊 × 108 × 1

2 × 50𝑘𝐻𝑧 × 3000𝐺 × 0.25 × 350 × 1

= 0.38𝑐𝑚2𝑐𝑚2

where:

FK = Cooling Factor (1=no cooling, 0.3=100 CFM)

BPK = AC Flux Density (Gauss)

WF = Window Factor (<1, practical<0.5)

CD = Current Density (250<CD<550, CM/A)

UF = Magnetization (1=single-end, 2=double-end)

The result of the area product calculation, estimated

that a core with an area product greater than

0.38 cm2cm

2 should have enough cross-sectional area

and window area to support the design. To meet the

30 mm maximum height requirement, horizontal low-

profile ferrite cores should be considered. From the

manufacturer’s datasheets:

TABLE 4. LOW-PROFILE FERRITE CORE CHOICES

Core Ae Aw AwAe Height

EFD30 0.69 cm2 0.63 cm

2 0.44 cm

2cm

2 14 mm

EER28L 0.81 cm2 0.97 cm

2 0.79 cm

2cm

2 25 mm

The area product is usually not directly specified for a

given core and bobbin set. However, the core cross-

section, Ae, and the window area, Aw, are listed on the

core and bobbin datasheets and can be multiplied to get

AeAw. The EFD30 core is very low-profile, but has an

area product only slightly greater than 0.38 cm2cm

2. It is

marginally acceptable, but the smaller window area is

not ideal for copper utilization, forcing the use of smaller

gauge wire and a larger number of turns. Consequently,

the EER28L core set available from numerous

manufacturers is chosen for this application. Suitable

high-frequency, ferrite materials such as 3F3, PC90, or

N49 are readily available from different vendors and

work well within the range of 200 kHz < f <500 kHz.

The required number of primary turns is calculated as:

𝑁𝑃 =𝐿𝑀 × 𝐼𝐷𝑆(𝑃𝐾) × 108

𝐵𝑃𝐾 × 𝐴𝑒 (31)

=1𝑚𝐻 × 2𝐴𝑃𝐾 × 108

3000𝐺 × 0.81𝑐𝑚2 = 82𝑇

The number of primary turns is determined to be 82

and this can now be used to calculate the number of

secondary turns. The transformer requires two secondary

turns. The main secondary, NLED, is for the LED output

voltage. Two primary referenced secondary windings,

NA and NHS, are also needed for the FAN6300 DET

function and high-side drive. The DET voltage, VDET,

needs to be set to 12 V at VIN(MIN).

𝑁𝐿𝐸𝐷 =𝑁𝑃

𝑛 (32)

=82𝑇

3.7= 22𝑇

𝑁𝐴 = 𝑁𝐿𝐸𝐷 ×𝑉𝐷𝐸𝑇

𝑉𝑂 + 𝑉𝑓 (33)

Fairchild Semiconductor Power Seminar 2013-2014 19

= 22𝑇 ×12𝑉

60𝑉 + 2𝑉= 4𝑇

𝑁𝐻𝑆 = 𝑁𝐿𝐸𝐷 ×𝑉𝐻𝑆

𝑉𝑂 + 𝑉𝑓 (34)

= 22𝑇 ×8𝑉

60𝑉 + 2𝑉= 3𝑇

The primary wire gauge used for NP is selected based

on a desired current density, CD, of 350 CM/A (Circular

Mils per Amp). A general rule is to design for

250 CM/A < CD < 550 CM/A. The required number of

CMs is given by:

𝐶𝑀 = 350𝐶𝑀

𝐴× 𝐼𝐷𝑆(𝑅𝑀𝑆) (35)

350𝐶𝑀

𝐴× 775𝑚𝐴𝑅𝑀𝑆 = 271𝐶𝑀

Referring to the American Wire Gauge (AWG) lookup

table shown in Table 5, the closest wire gauge to

271 CM is AWG#26 specified at 254 CM. AWG#26 can

handle the 775 mARMS current, but it is limited to an

effective frequency of 107 kHz. Since this design can

operate up to 200 kHz, stranded or Litz wire is used to

minimize AC resistance, lowering high-frequency

copper losses.

TABLE 5. AWG TABLE

Gauge Diameter DiameterCircular

MilsArea Resistance Weight Skin Depth

(AWG) (inches) (mm) CM (inches2)(Ohms/100

0 ft.)

(lbs./100

0 ft.)

Max. Freq. for

100% Skin

Depth- Solid

Copper

19 0.0359 0.91186 1288 0.001012 8.0512 3.8991 21 kHz

20 0.032 0.8128 1021 0.000802 10.1524 3.0921 27 kHz

21 0.0285 0.7239 810 0.000636 12.8019 2.4522 33 kHz

22 0.0253 0.64262 642 0.000505 16.1429 1.9447 42 kHz

23 0.0226 0.57404 509 0.0004 20.3558 1.5422 53 kHz

24 0.0201 0.51054 404 0.000317 25.6682 1.223 68 kHz

25 0.0179 0.45466 320 0.000252 32.367 0.9699 85 kHz

26 0.0159 0.40386 254 0.0002 40.814 0.7692 107 kHz

27 0.0142 0.36068 201 0.000158 51.4655 0.61 130 kHz

28 0.0126 0.32004 160 0.000126 64.8968 0.4837 170 kHz

29 0.0113 0.28702 127 9.95E-05 81.8334 0.3836 210 kHz

30 0.01 0.254 100 7.89E-05 103.19 0.3042 270 kHz

31 0.0089 0.22606 80 6.26E-05 130.1202 0.2413 340 kHz

32 0.008 0.2032 63 4.96E-05 164.0786 0.1913 430 kHz

33 0.0071 0.18034 50 3.94E-05 206.8992 0.1517 540 kHz

34 0.0063 0.16002 40 3.12E-05 260.8951 0.1203 690 kHz

35 0.0056 0.14224 32 2.48E-05 328.9827 0.0954 870 kHz

36 0.005 0.127 25 1.96E-05 414.8395 0.0757 1100 kHz

37 0.0045 0.1143 20 1.56E-05 523.1029 0.06 1350 kHz

38 0.004 0.1016 16 1.23E-05 659.6206 0.0476 1750 kHz

39 0.0035 0.0889 12 9.8E-06 831.7663 0.0377 2250 kHz

40 0.0031 0.07874 10 7.8E-06 1048.8379 0.0299 2900 kHz

AC skin depth for a single copper conductor is

calculated as:

𝛿 =65𝑚𝑚

√𝐹𝑀𝐴𝑋

(36)

=65𝑚𝑚

√200𝑘𝐻𝑧= 0.145𝑚𝑚

For full AC current penetration, multiply the skin

depth by two and choose the closest wire gauge less than

0.290 mm diameter. AWG#29 or smaller is suited for

200 kHz operation. However, AWG#29 is only rated for

127 CM. From Eq (35), 271 CM is required. To meet

AC and DC current requirements, multiple strands of

AWG#29 are needed. 271 CM / 127 CM implies the

need for at least three parallel strands of AWG#29.

Additional parallel strands can be used to lower the DC

resistance, but must be checked against available

window area. Litz wire is sold in bundled strands and is

specified as strands/AWG#. Numerous combinations

exist, but available lab stock for this design allows the

use of 15/38, served Litz wire with 141.76 mΩ/m

(43.21 Ω / 1000 ft) resistance and 0.559 mm outer

diameter. AWG#38 is rated for 16 CM and 15 parallel

strands yield 15 x 16 CM = 240 CM, which is close to

the 271 CM result from Eq (35).

From the manufacturer’s datasheet, the EER28L

bobbin specifies an average length per turn, lW, as

51.7 mm/T and a window width, WW, of 21.8 mm.

Using the entire bobbin width implies no safety

isolation. Depending on the type of wire insulation

chosen, barrier tape is sometimes used to meet creepage

and clearance specifications. The use of barrier tape

reduces the amount of available window width and

would therefore have to be subtracted from the

manufacturers specified bobbin width. For this design

example, the use of barrier tape is neglected and the DC

resistance is calculated by estimating the total length of

wire needed as:

𝑇/𝐿𝑎𝑦𝑒𝑟 =𝑊𝑊

𝐷𝑖𝑎𝑚𝑒𝑡𝑒𝑟 (37)

=21.8𝑚𝑚

0.559𝑚𝑚= 38 𝑇/𝐿𝑎𝑦𝑒𝑟

Fairchild Semiconductor Power Seminar 2013-2014 20

𝐿𝑎𝑦𝑒𝑟𝑠 =𝑁𝑃

𝑇/𝐿𝑎𝑦𝑒𝑟 (38)

=82𝑇

38𝑇/𝐿𝑎𝑦𝑒𝑟= 2.2𝐿𝑎𝑦𝑒𝑟𝑠

𝐿𝑒𝑛𝑔𝑡ℎ = 𝑀𝐿𝑇 × 𝑁𝑃 (39)

= 51.7𝑚𝑚

𝑇× 82𝑇 = 4,239𝑚𝑚 = 4.24𝑚

𝑅𝐷𝐶(𝑃𝑅𝐼) = 𝑅𝐴𝑊𝐺 × 𝐿𝑒𝑛𝑔𝑡ℎ (40)

= 141.76𝑚Ω

𝑚× 4.24𝑚 = 600𝑚Ω

RDC and IDS(RMS) can be used to calculate the DC

copper loss in the primary winding as:

𝑃𝐷𝐶(𝑃𝑅𝐼) = 𝐼𝐷𝑆(𝑅𝑀𝑆)2 × 𝑅𝐷𝐶 (41)

𝑃𝐷𝐶(𝑃𝑅𝐼) = 7752𝑚𝐴𝑅𝑀𝑆 × 600𝑚Ω = 360mW

The AC resistance normally calculated for using a

single conductor is neglected here. Since full AC current

penetration is assumed for the 15/38 Litz wire chosen,

the AC resistance is mitigated for the frequencies in the

range of this design.

From Eq (35), the 2 A LED secondary requires a

current density of 700 CM, which is close to an

equivalent AWG#22. Since the secondary experiences

the same frequency as the primary, AWG#38 is used for

the LED secondary winding. 700 CM / 16 CM implies at

least 44 strands of AWG#38. AWG#38 has 71 mΩ/m

(21.61 Ω / 1000 ft) resistance and 0.787 mm outer

diameter. Two secondary windings in parallel with 30/38

served Litz give 60 equivalent strands equal to 960 CM.

22 turns fits onto a single winding layer, so the full LED

secondary requires 2x22T (or two layers). The total wire

length, DC resistance, and power loss is again calculated

using Eq (37)-(41) and given as:

𝐿𝑒𝑛𝑔𝑡ℎ = 51.7𝑚𝑚

𝑇× 22𝑇 = 1,137𝑚𝑚 = 1.14𝑚

𝑅𝐷𝐶(𝐿𝐸𝐷) = 71𝑚Ω

𝑚× 1.14𝑚 = 81𝑚Ω, per winding

For two secondary windings in parallel, the equivalent

DC resistance is 40.5 mΩ.

𝑃𝐷𝐶(𝐿𝐸𝐷) = 22𝐴𝑅𝑀𝑆 × 40.5𝑚Ω = 162mW

The transformer core gap is applied to the center leg

only and is estimated to be:

𝑙𝑔 =𝜇Ο × 𝑁𝑃

2 × 𝐴𝑒

𝐿𝑀

(42)

𝑙𝑔 =4π × 10−7 𝐻

𝑚× 82𝑇2 × 81𝑚𝑚2

1𝑚𝐻= 0.7𝑚𝑚

The final transformer design is detailed in Fig. 21 and

Table 6.

1

NP(2-3)=38TNLED=22T

4

3

11

9

NHS(1-2)=3T2

5

6

NP(3-4)=44T

NDET(6-5)=4T

NLED=22T

12

10

Fig. 21. Flyback transformer

The DET and HS windings carry minimal current, so

two strands of AWG#38 can be used for each winding.

The LED secondary is interleaved between the primary

to reduce leakage inductance.

TABLE 6. FLYBACK TRANSFORMER WINDING TABLE

Winding Pins

(S→F) Wire Layers Turns

½ Primary 2→3 15/38, Served Litz 1 38

Secondary (LED) 9→11 30/38, Served Litz 1 22

Secondary (LED) 10→12 30/38, Served Litz 1 22

½ Primary 3→4 15/38, Served Litz 1+ 44

Secondary (DET) 6→5 2/38, Bifilar 1 4

Secondary (HS) 2→1 2/38, Bifilar 1 3

The output capacitance must be correctly sized to

minimize the amount of peak to peak voltage ripple, ΔV,

seen by the LED load. A secondary requirement is that

number of output capacitors must be rated to handle the

full RMS current.

Fairchild Semiconductor Power Seminar 2013-2014 21

𝐶𝑂 > 𝐼𝑂 ×4 × 𝑡𝑂𝑁(𝑀𝐴𝑋)

∆𝑉 (43)

𝑡𝑂𝑁(𝑀𝐴𝑋) =𝐷𝑀𝐴𝑋

𝐹𝑀𝐼𝑁 (44)

=0.45

50𝑘𝐻𝑧= 9𝜇𝑠

The minimum LED voltage is specified as 30 V.

Limiting the LED ripple voltage to less than 0.5% and,

allowing for 20% capacitor tolerance, gives:

𝐶𝑂 > 2𝐴 ×4 × 9𝜇𝑠 × 1.2

0.005 × 30𝑉= 576𝜇𝐹

The secondary peak current is also the current seen by

the output rectifier diode and is determined from the

primary peak current, IDS(PK), multiplied by the

transformer turns ratio, n:

𝐼𝐷(𝑃𝐾) = 𝐼𝐷𝑆(𝑃𝐾) × 𝑛 (45)

= 2𝐴𝑃𝐾 × 3.7 = 7.4𝐴𝑃𝐾

The secondary RMS current is:

𝐼𝐷(𝑅𝑀𝑆) = 𝐼𝐷(𝑃𝐾) × √1 − 𝐷𝑀𝐴𝑋

3 (46)

= 7.4𝐴𝑃𝐾 × √1 − 0.45

3= 3.17𝐴𝑅𝑀𝑆

Finally, the output capacitor RMS current is:

𝐼𝐶𝐴𝑃(𝑅𝑀𝑆) = √(𝐼𝐷(𝑅𝑀𝑆))2 − 𝐼𝑂2 (47)

= √3.17𝐴𝑅𝑀𝑆2 − 2𝐴2 = 2.5𝐴𝑅𝑀𝑆

The required RMS current can be reduced by using

NCAP number of parallel capacitors and assuming each

carries a proportional amount of the RMS current. For

two parallel capacitors, the minimum required equivalent

series resistance (ESR) is calculated by:

𝑅𝐸𝑆𝑅 <𝑁𝐶𝐴𝑃 × ∆𝑉

𝐼𝐶𝐴𝑃(𝑅𝑀𝑆) (48)

<2 × 0.005 × 30𝑉

2.5𝐴𝑅𝑀𝑆= 120𝑚Ω

Two Panasonic EEU-FC1J471L capacitors rated at

470 µF, 63 VDC, 2.09 ARMS, and 55 mΩ in parallel meet

the electrical and mechanical requirements.

From Eq (46), the output rectifier diode must have a

forward current rating greater than 3.17 ARMS and a

reverse voltage rating greater than:

𝑉𝐷 = 𝑉𝑂(𝑀𝐴𝑋) +𝑉𝐼𝑁(𝑀𝐴𝑋)

𝑛 (49)

= 60𝑉 +460𝑉

3.7= 185𝑉

Since the converter is operating at the boundary of

CCM and DCM, reverse recovery losses in the output

rectifier should be negligible. Therefore, a fast recovery

or better switching diode can be used. FFPF20UP40S

20 A, 400 V ultra-fast diode is selected.

The gate drive circuit uses a FAN7382 HVIC that is

intended for driving a half-bridge power stage. In a half-

bridge, the two inputs, primary MOSFETs Q1, and Q2

are driven asynchronously and the VS node is always

switching, which allows PBIAS to charge C2.

Conversely, the two-switch flyback drives Q1 and Q2

synchronously, as shown in Fig. 20. As a result, the

operating principle is notably different. Fig. 22 shows

the FAN7382 inputs connected together and driven

synchronously from the PWM.

FAN73821

2

3

4 5

6

7

8

HO

VB

VS

LOCOM

LIN

HIN

VCCPBIAS

VIN

R1

R2

R3

Q1

Q2

D1

D2

D4D5

VA

VHS

C2

C3

DETPWM

(FROM PFC)

Fig. 22. Two-switch flyback gate drive

The high-side drive for Q1 is based on the principal

that the boot capacitor, C2, is floating 12-V (PBIAS)

above VIN. The red line in Fig. 22 indicates that PBIAS

can only charge C2 during the time that Q1 is OFF and

Fairchild Semiconductor Power Seminar 2013-2014 22

Q2 is conducting, but this is contrary to normal operation

of the two-switch flyback. During steady-state operation,

C2 is charged from VHS. However, an interesting

situation arises during startup or when the converter

comes in or out of burst mode.

0V

0V

0V

PBIAS

VHS

UVLO

VGS(HS)

VGS(LS)

Fig. 23. Gate drive startup waveforms

The FAN7382 is pre-biased with PBIAS before

switching begins. When VC2 (or VHS) is less than UVLO,

the high-side MOSFET is OFF, as shown in Fig. 23; but

the low-side MOSFET is always driven by PBIAS. With

only the low-side MOSFET conducting, the transformer

primary is not being energized, but C2 is charged from

PBIAS. Within the next switching cycle, the high-side

begins switching, but C2 may give up enough charge to

again cross UVLO. Although this startup sequence

appears unusual, the high-side winding voltage, VHS,

tracks the LED output voltage and continues to supply

the necessary charge to C2 during steady-state operation.

The FAN7882 and FAN6300H configuration is

addressed in the respective datasheets and various

application notes and is not repeated here. The details for

setting the DET resistor divider, current sense, and high-

voltage startup should be closely followed according to

the procedure shown in the datasheet[8]

.

LED LOAD CONTROL

The design includes two options for closing the

feedback loop of the two-switch flyback converter.

Option 1 is for CC-CV LED load control of a single

string, rated for VLED=50 V and ILED=2 A. The circuit

shown in Fig. 24 can be used to regulate CC-CV and can

be applied to the output of any DC-DC converter.

VL

SBIAS

2.5VREF

FB

R12

R13

R14

R15

R16

R17

R18

R19

R20R21

R22

D8

D9

30V<VLED<50V

C8

C9

ILED=2A

U1a

U1b

FAN4274

FAN4274

FOD817AU2

VAO

Fig. 24. Option 1 - single LED string CC-CV load control

The feedback compensation is comprised of two error

amplifiers, U1a and U1b. During CC mode, U1a regulates

the LED current to 2 A for 30 V < VLED < 50 V. If the

LED voltage exceeds 50 V, U1b takes over and regulates

the LED voltage while the current is reduced. The

outputs of the current amplifier and voltage amplifier are

diode OR’ed together so that the amplifier with the

highest output dominates. The error amplifier(s) output

drives an optocoupler, with R20 limiting the current on

the secondary side. R21 limits the FB current sourced

from the FAN6300H and can be used to adjust the

secondary to primary current gain, if necessary. A 0.5%

shunt regulator sets the 2.5 V reference voltage used for

each amplifier. 2 A of LED current flowing through R12

should result in a voltage drop of about 200 mV, a good

trade-off between resistor size and noise immunity. All

calculated resistor and capacitor values are rounded to

the closest standard component values.

The FAN6300H is designed for peak current mode

control. The peak primary current through a current

sense resistor, R3 in Fig. 19, is converted to a voltage

Fairchild Semiconductor Power Seminar 2013-2014 23

and used as the control signal at the non-inverting input

of the FAN6300H internal PWM. The value of the

current sense resistor, R3 is calculated by:

𝑅3 =𝑉𝐹𝐵 − 1.2𝑉

3 × 𝐼𝐷𝑆(𝑃𝐾) (50)

And the normal operating control range for the

feedback voltage is designed for 1.2 V < VFB < 3 V:

𝑅3 =3𝑉 − 1.2𝑉

3 × 2𝐴𝑃𝐾= 300𝑚Ω

The optocoupler selected is FOD817A with current

transfer ratio, 80% < CTR < 160%. The saturation

voltage for the FOD817A photo-transistor is given as

VCE(SAT) = 100 mV and the diode forward voltage is

specified as VF(OPTO) = 1.2 V. Accounting for worst-case

CTR and allowing for some additional headroom,

2.25 mA of optocoupler diode current should be enough

to meet the control range of FB current,

800 µA < IFB < 2 mA, corresponding to the feedback

voltage control range, 1.2 V < VFB < 3 V. From the

FAN6300H datasheet, the condition where IFB = 2 mA

and VFB = 1.2 V corresponds to zero duty cycle. For a

desired optocoupler diode current, IOPTO = 2.25 mA, the

optocoupler biasing resistor, R20 is calculated by:

𝑅20 =(𝑉𝐴𝑂 − 𝑉𝐹(𝑂𝑃𝑇𝑂)) × 𝐶𝑇𝑅𝑀𝐼𝑁

𝐼𝑂𝑃𝑇𝑂 (51)

=(3𝑉 − 1.2𝑉) × 0.8

2.25𝑚𝐴= 649Ω

The LED current is set by calculating R12 as:

𝑅12 =200𝑚𝑉

𝐼𝐿𝐸𝐷 (52)

=200𝑚𝑉

2𝐴= 100𝑚𝛺

The power dissipated in R12 is:

𝑃𝑅12 = 𝐼𝐿𝐸𝐷2 × 𝑅12 (53)

𝑃𝑅12 = 2𝐴2 × 100𝑚Ω = 400𝑚𝑊

Two 0.2 Ω 1812-size resistors are used in parallel to

handle the 400 mW power dissipation. The inverting

input of U1a is set to 200 mV by the R13, R14 resistor

divider. Since R12 is much smaller compared to R13+R14,

R12 is neglected and R13 is chosen as 1 kΩ. R14 is

calculated by:

𝑅14 =𝑅13 × (𝑉𝑅𝐸𝐹 − 200𝑚𝑉)

200𝑚𝑉 (54)

𝑅14 =1𝑘Ω × (2.5𝑉 − 200𝑚𝑉)

200𝑚𝑉= 11.5𝑘Ω

Because LED current is a constant load, designing for

fast transient response is not a primary concern and U1a

can be set for relatively low bandwidth of approximately

1 kHz (1 ms response) with a mid-band absolute gain of

about 5. R13 is 1 kΩ; therefore, R18 is chosen as

5 x 1 kΩ = 4.99 kΩ and C8 is determined by:

𝐶8 =1

2𝜋 × R18 × 1kHz (55)

=1

2𝜋 × 4.99kΩ × 1kHz= 33𝑛𝐹

For the voltage amplifier, the R16, R17 resistor divider

on the non-inverting input is set to 50 V by Eq (56):

𝑅17 =𝑅16 × 𝑉𝑅𝐸𝐹

𝑉𝐿𝐸𝐷 − 𝑉𝑅𝐸𝐹 (56)

And if the current through R16+R17 is arbitrarily

limited to about 500 µA:

𝑅17 =𝑉𝐿𝐸𝐷 − (500𝜇𝐴 × 𝑅16)

500𝜇𝐴 (57)

Solving Eq (56) and Eq (57) for R16 gives:

𝑅16 =𝑉𝐿𝐸𝐷 − 𝑉𝑅𝐸𝐹

500𝜇𝐴 (58)

=50𝑉 − 2.5𝑉

500𝜇𝐴= 95.3𝑘Ω

Putting the result of Eq (58) back into Eq (56) gives

the value for R17 as:

𝑅17 =95.3𝑘Ω × 2.5𝑉

50𝑉 − 2.5𝑉= 4.99𝑘Ω

R19 and C9 are selected based on maintaining low gain

bandwidth. Similar to the current amplifier feedback, the

bandwidth is chosen as 1 kHz and R19 arbitrarily selected

as 1 kΩ. C9 is calculated as:

𝐶9 =1

2𝜋 × R19 × 1kHz (59)

𝐶9 =1

2𝜋 × 1kΩ × 1kHz= 180𝑛𝐹

Fairchild Semiconductor Power Seminar 2013-2014 24

The single string controller calculated values give an

approximate starting point for designing a stable CC-CV

control loop. The loop gain and phase ultimately need to

be measured in the lab, where final optimization of

component values can be made. For this design example,

the circuit shown in Fig. 24 was built on a daughter card

that could be inserted into the main power board,

allowing single-string CC-CV control.

Option 2 is for CC-CV LED load control of four

individual LED strings, rated for VLED=50 V and

ILED=350 mA per string. The circuit shown in Fig. 25

uses the FAN7346 4-channel LED current balance

controller to close the feedback loop around the

FAN6300H PWM controller.

FAN73461

2

3

4 25

26

27

28GND

VMIN

CMP

FB

OVR

21

22

23

24

17

18

19

20

15

16

8

7

6

5

12

11

10

9

14

13

PWM2

PWM3

PWM4

FO

SLPR

ADIM

ENA

PWM1

VCC

REF

FB1

OUT1

CH1

CH3

FB2

OUT2

CH2

OUT4

CH4

FB3

OUT3

FB4

VDD

VL

SBIAS

ADIM

ON

OFF 1

2

3

SBIAS

ADIM

PWM1

PWM2

PWM3

PWM4

ADIM

FB

FOD817AU2

30V<VLED<50V

ICH1 ICH2 ICH3 ICH4

RS1 RS2 RS3 RS4

R23

R24

R25

R26R27

R28

R29

R30R21

R32

R33

R34

R35

C10

Fig. 25. Option 2 – four-string CC-CV load control

Each of the four LED string currents, ICHx, is

individually sensed through a dedicated feedback

resistor. The LED string current is controlled by FBx

and internally compared to one-tenth the ADIM voltage,

as shown in Fig. 26. Consequently, VADIM is used as the

CC reference as well as analog dimming control. The

range of VADIM is 0.5 V < VADIM < 4 V and the range of

VREF(LED) is 50 mV < VREF(LED) < 400 mV. VADIM is

internally clamped to 0.5 V and 4 V and the maximum

voltage on ADIM is limited to 6 V. Therefore, even

when analog dimming is not being used, a voltage of 4 V

< VADIM < 5 V must be present on the ADIM pin for full

LED brightness. The ADIM resistor divider is formed by

R25 and R26 and SBIAS is 13 V. If R26 is arbitrarily

chosen as 4.99 kΩ, R25 is calculated as:

𝑅25 =𝑅26 × (𝑆𝐵𝐼𝐴𝑆 − 𝑉𝐴𝐷𝐼𝑀)

𝑉𝐴𝐷𝐼𝑀 (60)

=4.99𝑘Ω × (13𝑉 − 4.5𝑉)

4.5𝑉= 9.53𝑘Ω

Fairchild Semiconductor Power Seminar 2013-2014 25

The LED current-sense resistors for each string are

calculated by:

𝑅𝑆𝑥 =𝑉𝐴𝐷𝐼𝑀

10 × ICHx (61)

=4𝑉

10 × 350mA= 1.143Ω

The power dissipated in Rsx is:

𝑃𝑅𝑆𝑥 = 𝐼𝐶𝐻𝑥2 × 𝑅𝑆𝑥 (62)

= 350𝑚𝐴2 × 1.143Ω = 140𝑚𝑊

Two 1206 resistors, rated for 250 mW, used in parallel

(2.32 Ω // 2.26 Ω = 1.145 Ω), handle the 140 mW power

dissipation and allow accurate current setting.

If FBx is higher than 1 V for 20 µs, then over-current

protection (OCP) for that particular CHx is enabled and

the LED current in that string is latched off. If an

individual channel, CHx, is in OCP, the remaining

channels continue to regulate. The OCP level for each

channel is given by:

𝐼𝑂𝐶𝑃 =𝑉𝑂𝐶𝑃(𝑇𝐻)

𝑅𝑆𝑥 (63)

=1𝑉

1.145Ω= 874𝑚𝐴

RSx

VADIM/10

1V

Vf

VDS

VS

Gm

OVR

DCDC

OUT

FB

CMP

FB

CHx

OUTx

FBxFAN7346

ICHx

1.42V

ILED

50mV<VREF(LED)<400mV

Qx

VLED

VF

VF

VF

VF

Fig. 26. FAN7346 control block diagram

The drain voltage of Qx is sensed by CHx and

compared to the Gm amplifier 1 V reference. The

transconductance error amplifier generates an error

voltage proportional to maintaining 1 V on the drain of

Qx. The Gm amplifier can be externally compensated via

the CMP pin. The error voltage drives the FB pin,

varying the optocoupler cathode voltage, which sends

the control signal to the primary-side PWM feedback.

VLED is set to the minimum value necessary to regulate

Qx(VD) to 1 V. Since Qx is operated in its linear region, it

is selected based on DC current and power dissipation.

The power dissipated in Qx is dominated by VDS×ID and

can be estimated by:

𝑃𝑄𝑥 = [1𝑉 − (𝐼𝐶𝐻𝑥 × 𝑅𝑆𝑥)] × 𝐼𝐶𝐻𝑥 (64)

= [1𝑉 − (350𝑚𝐴 × 1.145Ω)] × 350𝑚𝐴 = 210𝑚𝑊

FDT86256 is a 150 V, 1.2 A N-channel MOSFET in a

SOT-223 package with a junction-to-ambient thermal

resistance, RΘJA, of 55˚C/W. The expected temperature

rise is:

𝑇𝑟 = (𝑅Θ𝐽𝐴 × 𝑃𝑄𝑥) + 𝑇𝐴 (65)

= (55℃/𝑊 × 210𝑚𝑊) + 25℃ = 36.55℃

When the non-inverting input of the OVR amplifier

exceeds 1.42 V, the FB pin is proportionally pulled

LOW, reducing ICHx, while regulating VLED according to

the OVR voltage. The maximum VLED voltage for this

design is set for 50 V. Selecting the upper OVR resistor,

R23, as 100 kΩ allows calculation of the lower OVR

resistor, R24, as:

𝑅24 =1.42𝑉 × 𝑅23

𝑉𝐿𝐸𝐷 − 1.42𝑉 (66)

=1.42𝑉 × 100𝑘Ω

50𝑉 − 1.42𝑉= 2.94𝑘Ω

The FAN7346 also includes open-LED and short-LED

protections. If one LED in any string is shorted, Vf

decreases and the drain voltage on Qx increases. If Qx(VD)

exceeds the LED short threshold voltage, VSLP(th), for

20 µs; that LED string is forced off and the remaining

strings continue to regulate ICHx. VSLP(th) is defined by the

voltage applied to the SLPR pin in Fig. 25 as:

𝑉𝑆𝐿𝑃(𝑡ℎ) = 10 × 𝑉𝑆𝐿𝑃 (67)

Fairchild Semiconductor Power Seminar 2013-2014 26

The range of VSLP is 0 V < VSLP < 45 V and is set by

the R34, R35 resistor divider. If VSLP(th) is set high, the

power dissipation in Qx can become much higher than

the 210 mW estimated by Eq (64). Setting VSLP(th) to 5 V

enables detection for two shorted LEDs (Vf=3 V). For

VSLP(th)= 5 V, VSLP must be set to 0.5 V. The R34, R35

resistor divider is given by:

𝑅35 =𝑉𝑆𝐿𝑃𝑅 × 𝑅34

𝑉𝑅𝐸𝐹 − 𝑉𝑆𝐿𝑃𝑅

(68)

If R34 is selected as 10 kΩ, R35 is calculated as:

𝑅35 =0.5𝑉 × 10𝑘Ω

5𝑉 − 0.5𝑉= 1.1𝑘Ω

If any LED in a string fails open, the Qx drain voltage

is pulled to ground. The FAN7346 open-LED protection

(OLP) detection threshold is 0.3 V. If CHx is lower than

0.3 V for 20 µs, that channel’s contribution to FB is

removed and FB is controlled by the remaining normal

operating LED strings.

Fairchild Semiconductor Power Seminar 2013-2014 27

VII. DESIGN SCHEMATICS

Fig. 27. Power board - BCM PFC schematic

Fairchild Semiconductor Power Seminar 2013-2014 28

Fig. 28. Power board – two-switch flyback

Fairchild Semiconductor Power Seminar 2013-2014 29

Fig. 29. Power board – high-voltage flyback bias supply

Fig. 30. Option 1 – 50 V, 2 A, single-string, CC-CV controller card

Fairchild Semiconductor Power Seminar 2013-2014 30

Fig. 31. Option 2 – 50 V, 350 mA / CH, 4-channel, multi-string controller card

Fairchild Semiconductor Power Seminar 2013-2014 31

VIII. DESIGN BUILD

Fig. 32. Power board profile, 25 mm (0.99 in), (H)

Fig. 33. Power board partitioning, 229 mm (9 in) × 76 mm (3 in), (L×W)

AC Input, EMI Filter, Inrush Current Limiting

Flyback Bias Regulator (SBIAS, PBIAS)

BCM PFC

Two-Switch, QR Flyback

Removable Controller Card (FAN7346 Multi-String

Controller Shown Inserted)

PWM Dimmer Circuits

LED Output Terminal Block

Fig. 34. Option 1 & 2, CC-CV controller cards

Fairchild Semiconductor Power Seminar 2013-2014 32

IX. LED DRIVER PERFORMANCE

BCM PFC

Graphical representation of efficiency vs. output

power highlights the low-line efficiency benefit of using

the boost follower. A 1.8% efficiency improvement can

be seen at 20% load and the peak low-line. Boost

follower efficiency was measured as 97% at 90% load.

Fig. 35. BCM PFC boost follower efficiency gain

The measured PF vs. output power is shown in Fig.

36, for VAC = 120 VRMS and 230 VRMS. The area shown

between the dashed lines highlights the expected LED

power range with respect to the PFC converter. The low-

line peak PF is 0.994 and PF > 0.9 for low-line and high-

line over the entire LED power range.

Fig. 36. PF vs. POUT

The boost follower also offers an efficiency benefit to

the downstream DC-DC converter. The two-switch

flyback efficiency vs. input voltage (PFC output voltage)

curve is shown in

Fig. 37 and shows a 0.68% efficiency improvement at

low-line. For the boost follower, VIN=250 V corresponds

to VAC<160 VRMS and this is compared to the efficiency

when the input voltage (PFC output voltage) is regulated

to a fixed 450 V.

Fig. 37. Boost follower benefit to two-switch flyback

The measured PFC boost follower voltage profile is

shown in Fig. 38 and can be compared to the predicted

graph of Fig. 16. The boost follower output linearly

“follows” (tracks) VAC at VAC + 30 V for 150 VRMS < VAC

< 308 VRMS.

Fig. 38. Boost Follower VOUT vs. VAC

94.02%,

250V

93.34%,

450V

Δƞ=1.8%,

@20% POUT

LED Power Range

Δƞ=0.68%

Fairchild Semiconductor Power Seminar 2013-2014 33

ZVS and ZCS are two important characteristics of

BCM PFC converters, as highlighted in Fig. 39. The

steady-state operating waveforms show that VDS

resonates to zero (ZVS) when VIN < ½ VOUT, (120 VPK <

125 V). The inductor current at full load is also shown to

start from 0 A at every switching cycle (ZCS) and

reaches a peak value of 5 APK, as calculated by Eq (9).

Fig. 39. CH1-VGS, CH2-VDS, CH3-ZCD, CH4-IL; VIN=85 VRMS,

POUT=120 W

The steady-state operating waveforms seen in Fig. 40

show the PFC gate drive operating at very narrow duty

cycle and the inductor current measured as 2 APK for

VAC=300 VRMS. Since VIN > ½ VOUT, (425 VPK > 230 V),

ZVS is lost and VDS resonates to some minimum value

(valley switching).

Fig. 40. CH1-VGS, CH2-VDS, CH3-IL; VIN=300 VRMS, POUT=120 W

Fig. 41 shows the boost follower PFC output voltage

responding to a positive 115 VRMS to 300 VRMS, VAC line

transient. As can be seen, the boost follower follows the

line transient by adjusting VOUT from 250 V to 460 V.

Fig. 41. CH1-VAC, CH2-BFVOUT; VIN=115 VRMS to 300 VRMS

Fig. 42 shows the boost follower PFC output voltage

responding to a negative 300 VRMS to 115 VRMS, VAC line

transient. As can be seen, the boost follower follows the

line transient by adjusting VOUT from 460 V to 250 V.

Compared to the positive AC line transient, the boost

follower output voltage tracking is not as fast due to the

additional energy stored in the PFC bulk capacitance

Fig. 42. CH1-VAC, CH2-BFVOUT; VIN=300 VRMS to 115 VRMS

Fairchild Semiconductor Power Seminar 2013-2014 34

Two-Switch Flyback

The FAN6300H two-switch flyback, low-side, VDS

and VGS waveforms are shown in Fig. 43 for VIN=250 V

(85 VRMS < VAC < 150 VRMS). At POUT = 70 W, the duty

cycle and frequency is measured as D = 40% and

f = 65 kHz, respectively.

Fig. 43. CH1-VGS(LO), CH2-VDS(LO); VIN=250 VDC, POUT=70 W, f=65 kHz,

D=40%

When VIN=460 V, the duty cycle and frequency is

measured as D=23% and f=95 kHz at POUT=70 W as

shown in Fig. 44. In Fig. 43 and Fig. 44, the LED output

voltage is 50 V for each case. Since VOUT < ½ VIN, valley

switching always occurs for all LED voltages less than

125 V (at VIN=250 V).

Fig. 44. CH1-VGS(LO), CH2-VDS(LO); VIN=460 VDC, POUT=70 W, f=95 kHz,

D=23%

In Fig. 45, POUT is increased to 85 W and the duty

cycle and frequency are measured as D=42% and

f=63 kHz. For POUT=100 W, the maximum duty cycle

was measured as D=45%, which agrees with the chosen

D value used in Eq (22).

Fig. 45. CH1-VDS(LO), CH3-VGS(LO); VIN=250 VDC, POUT=85 W, f=63 kHz,

D=42%, valley switching

During dimming or light-load operation, there may be

instances where the FAN6300H is forced to operate at

its internally set minimum off-time, tOFF(MIN)=13 µs.

Under these specific conditions, gate drive turn-on at the

first minimum VDS valley may not be possible. The

FAN6300H then reverts to “extended valley switching”

shown in Fig. 46. It is important to note that extended

valley switching can occur at any multiple with respect

to the first valley. In Fig. 46, extended valley switching

occurs at the fifth valley of VDS.

Fig. 46. CH1-VDS(LO), CH3-VGS(LO); VIN=250 VDC, POUT=24 W (analog

dimming), f=68 kHz, D=11%, extended valley switching

Fairchild Semiconductor Power Seminar 2013-2014 35

The FAN7382 startup waveform, shown in Fig. 47,

verifies the theoretical waveform of Fig. 23. Several

low-side gate drive pulses initially occur without any

simultaneous high-side pulses. This continues until the

high-side boot capacitor and boot winding from the

flyback transformer reach steady state.

Fig. 47. CH1-VGS(HO), CH2-VGS(LO), CH3-V(CBOOT); FAN7382 gate drive

startup

Further examination of the FAN7382 gate-drive

during startup, reveals three distinct periods (highlighted

in Fig. 48) where the low-side gate is switched on, while

the high-side gate is missing. Once the boot capacitor is

fully charged, normal switching results where the high-

side and low-side gate drive signals are coincident.

Fig. 48. CH1-VGS(HO), CH2-VGS(LO), CH3-V(CBOOT); FAN7382 gate drive

startup to steady-state operation

System Performance

The importance of the FAN7930C RDY (ready) signal

can be seen in the Fig. 49 startup waveform. PBIAS

supplies 12 VDD to the FAN7930C. After the PFC output

voltage reaches 89% of its set regulated value, PBIAS is

applied to the FAN6300H (two-switch flyback) via the

RDY signal. This bias sequencing is important in two-

stage power converters because it limits power drawn

from the PFC bulk capacitors during startup. The result

is a smooth monotonic startup of LED voltage, VLED.

Fig. 49. CH1-PBIAS, CH2-RDY, CH3-VOUT(PFC), CH4-VLED; VIN=115VRMS,

POUT=70W, Start-Up

The shutdown sequence is shown in Fig. 50, where the

RDY signal terminates as soon as the PFC output

voltage falls below 89% of the set regulation value.

Fig. 50. CH1-PBIAS, CH2-RDY, CH3-VOUT(PFC), CH4-VLED; VIN=115VRMS,

POUT=70 W, shutdown

Fairchild Semiconductor Power Seminar 2013-2014 36

The AC line current and voltage are shown in Fig. 51

for VIN=85 VRMS, POUT=85 W. The voltage and current

appear in phase and since the line current is near

maximum (a favorable operating condition for high PF)

the power factor is measured near unity at PF=0.994.

Fig. 51. CH1-VIN(AC), CH2-IIN(AC); VIN=85 VRMS, POUT=85 W, PF=0.994

Conversely, for VIN=300 VRMS and POUT=85 W, the

AC line current shows significant distortion, as seen in

Fig. 52. The voltage and current appear in phase and,

since the line current is near minimum (an unfavorable

operating condition for high PF), the power factor

decreases to PF=0.915.

Fig. 52. CH1-VIN(AC), CH2-IIN(AC); VIN=300 VRMS, POUT=85 W, PF=0.915

Since VIN and VOUT are directly coupled, all PFC

boost converters suffer from excessive inrush current

during startup. Limiting the inrush current is important

for long-term reliability. The waveforms shown in Fig.

53 indicate a 15.25 APK inrush current spike the instant

VAC is applied. Although the LED voltage appears

unaffected, the PFC bulk capacitor absorbs this high

current every time the converter is initially powered.

Fig. 53. CH1-VIN(AC), CH2-IIN(AC), CH3-VLED; VIN=120 VRMS, POUT=70 W,

I(PK)=15.25 A, inrush circuit disabled

The LED driver design presented here includes an

inrush current-limiting circuit comprised of R7, R12 and

associated shorting circuitry shown in Fig. 27. The

beneficial performance of this circuit is shown in Fig.

54, where the inrush current spike is measured as

3.18 APK. A comparative 79.2% inrush current spike

reduction is achieved.

Fig. 54. CH1-VIN(AC), CH2-IIN(AC), CH3-VLED; VIN=120 VRMS, POUT=70 W,

I(PK)=3.18 A, inrush circuit enabled, 79.2% reduction

PWM dimming measurements are shown in Fig. 55.

The design includes two on-board adjustable PWM

dimmer circuits, shown in Fig. 28. Each circuit produces

a 5 V, 250 Hz, PWM signal with an adjustable duty

cycle variation between 1% < D < 99.9%. PDIM1

Fairchild Semiconductor Power Seminar 2013-2014 37

controls LED strings 1 and 2, while PDIM2 controls

LED strings 3 and 4. The FAN7346 allows each of the

four LED strings to be dimmed independently. The

measured waveforms below correspond to string 1 and 2

dimmed to 35 mA and string 3 dimmed to 176 mA.

String 4 (not shown) is left undimmed at 350 mA. Under

these varying dimming conditions, the measured

efficiency and power factor were η=87.02% and

PF=0.971 with no visible LED flicker.

Fig. 55. CH1-PWM(CH3), CH2-PWM(CH1,2), CH3-ILED(CH3), CH4-

ILED(CH1,2); ILED(CH1,2)=35 mA, ILED(CH3)=176 mA, ILED(CH4)=350 mA,

PF=0.971, η=87%, FAN7346 PWM dimming mode

Fig. 56 shows the linearity of the FAN7346 dimming

capability. All four LED strings dim simultaneously

from 0% to 100% full brightness. 0% brightness (fully

off) is only achievable when the PWM dimming pin for

a corresponding string is pulled LOW.

Fig. 56. FAN7346 PWM dimming

The test results for analog dimming are shown in Fig.

57. All four LED strings are dimmed simultaneously, as

the ADIM voltage is varied from 0 V to 5 V. The

FAN7346 ADIM function only allows dimming down to

12% minimum brightness. The ADIM pin is internally

clamped to 4 V, corresponding to 100% / full brightness.

Fig. 57. FAN7346 analog dimming; four strings dim simultaneously;

minimum dimming = 12%

The CC-CV curve for four-channel operation is shown

in Fig. 58. The minimum LED bus voltage for stable

operation measured at 30 V for 1.4 A CC. The FAN7346

over-voltage regulation (OVR) is set to 52 V for 50 V,

1.4 A operation.

Fig. 58. FAN7346 CC-CV load line, VLED(MIN)=30 V

The current harmonics for VAC=115 VRMS

(VOUT(PFC)=250 V) are shown in Fig. 59, along with the

EN61000-3-2 Class-C limit for lighting fixtures with

PIN>25 W. The LED driver is operated in boost follower

Fairchild Semiconductor Power Seminar 2013-2014 38

mode with measured efficiency and harmonic distortion

given as η=91% and THD=8.91%.

Fig. 59. η=91.1%, THD=8.91%, BF mode (115VRMS=250VOUT)

Similarly, the current harmonics for VAC=230 VRMS

(VOUT(PFC)=400 V) are shown in Fig. 60, along with the

EN61000-3-2 Class-C limit for lighting fixtures with

PIN>25 W. The LED driver is operated in boost follower

mode with measured efficiency and harmonic distortion

measured as η=91.5% and THD=21.52%.

Fig. 60. η=91.5%, THD=21.5%, BF mode (230 VRMS=400 VOUT)

The total system efficiency vs. AC input voltage is

plotted in Fig. 61, comparing the PFC boost follower

mode to a fixed 450 V PFC output. The efficiency data

supports expectations that the boost follower enables

greater efficiency improvement at low-line. An overall

efficiency improvement of 1% was measured at low-line

with a peak efficiency of 91.8%. The efficiency data

considers all aspects of the entire system, including the

EMI line filter and bias power supply.

Fig. 61. BF yields 1.2% overall peak efficiency gain

The total system efficiency vs. AC input voltage is

plotted in Fig. 62, comparing output power of 70 W to

85 W. Both cases operate in boost follower mode.

Measured efficiency for POUT=85 W is greater than 90%

over the entire AC line range.

Fig. 62. Efficiency measurements include EMI filter and flyback bias

supply; both cases operating in BF mode, 91.8% peak

The measured system power factor for POUT=85 W,

was PF>0.9 over the entire AC line range of 85 VRMS <

VAC < 308 VRMS. The PF data shown in Fig. 63 was

taken while operating in boost follower mode.

Interestingly, a comparison of PF between fixed-PFC

output voltage (450 V) and boost follower mode showed

no measurable difference in PF.

Fairchild Semiconductor Power Seminar 2013-2014 39

Fig. 63. PF(PK)=0.996, PF>0.9 for 85 VRMS < VAC <308 VRMS, for

POUT>85 W

X. CONCLUSION

Several power topologies and LED load control

methods suitable for use in high-power industrial

lighting fixtures were reviewed. A scalable, 100 W,

dual-stage, QR flyback, LED driver was designed, built,

and tested. Maximizing efficiency and PF over an

extended input range was achieved by operating the

BCM PFC in boost follower mode and optimizing both

power stages. Design calculations for proper selection of

power-stage components and high-frequency

transformer design critical for achieving high efficiency

were shown. Design techniques were explained leading

to a higher level of performance than generally

encountered with flyback converters. The design was

shown to be configurable for single-string CC-CV or

multi-string operation using the FAN7346 LED

controller. Various LED protection functions and

dimming techniques were also presented. All

calculations were verified by experimental test results.

REFERENCES

[1] “FL7930C – Single-Stage Flyback and Boundary-Mode PFC Controller

for Lighting,” Datasheet, Fairchild Semiconductor, March 2011.

[2] “FAN6300H – Highly Integrated Quasi-Resonant Current Mode PWM Controller,” Datasheet, Fairchild Semiconductor, December 2009.

[3] “FAN7382 – High- and Low-Side Gate Driver,” Datasheet, February

2007.

[4] “FAN7346 – 4-Channel LED Current Balance Controller,” Datasheet,

Fairchild Semiconductor, May 2011.

[5] “FSL138MRT – Green-Mode Fairchild Power Switch (FPS™) for High Input Voltage,” Datasheet, Fairchild Semiconductor, May 2012.

[6] M. Weirich, “A High Power Factor Flyback with Constant-Current

Output for LED Lighting Applications,” Fairchild Power Seminar 2010-2011. Available for download at

http://www.fairchildsemi.com/support/resources/onlineseminars/

[7] “AN-9732 – LED Application Design Guide Using BCM Power Factor Correction (PFC) Controller for 200 W Lighting System,” Fairchild

Semiconductor, March 2011.

[8] “AN-9736 – Design Guideline of AC-DC Converter Using FL6961 & FL6300A for 70 W LED Lighting,” Fairchild Semiconductor,

April 2011.

[9] L. Balogh, “AN-8021 – Building Variable Output Voltage Boost PFC with the FAN9612 Interleaved BCM PFC Controller,” Fairchild

Semiconductor, June 2010.

Steve Mappus is a principal Systems Engineer working in Fairchild Semiconductor’s Power Conversion group

located in Bedford, NH, USA. In his current role, he is responsible for new product development of power-

supply control and MOSFET gate drive ICs. He has more

than 22 years of power supply design experience, including ten years designing military and commercial

power systems for avionic applications. He has spent the last twelve years

working within the field of power-management semiconductors, specializing

in systems and applications engineering. His areas of interest include high-

power converter topologies, soft-switching converters, synchronous

rectification, high-frequency power conversion, and power factor correction.