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ELCT 1003:High Speed ADCs

High-Speed Analog to

Digital Converters

Ann Kotkat Ayman Sakr

Barbara Georgy Heidi El-Feky

Mahmoud Tantawi Nourane Gamal

1


Outline

■ Introduction.

■ Process of ADC.

■ ADC Specifications.

■ Flash ADC.

■ Pipelined ADC.

■ References.

2


Flash ADC

● Architectural details

• Comparator

• Resistive ladder

• Thermometer code

● Problems and Solutions

• Bubbles → T\H

• Metastability → Grey encoding

● Pros and cons

3


Architectural Details

One Bit ADC

4


Architectural Details

● circuit employs 2N-1 comparators. A resistive-divider with 2N

resistors provides the reference voltage. The reference voltage for

each comparator is one least significant bit (LSB) greater than the

reference voltage for the comparator immediately below it.

● Each comparator produces a 1 when its analog input voltage is

higher than the reference voltage applied to it. Otherwise, the

comparator output is 0. Thus, if the analog input is between VX4

and VX5, comparators X1 through X4 produce 1s and the remaining

comparators produce 0s.

● The point where the code changes from ones to zeros is the point

at which the input signal becomes smaller than the respective

comparator reference-voltage levels.

5


Tracing example

6


Problems

● Bubbles:

Normally, output of the comparator is thermometer code, such as 00111111. Errors

may cause an output like 0011011. The spurious "0" in the result sequence is

called a sparkle or a bubble. The bubble can be due to comparator timing

mismatch. The magnitude of the error can be quite large and can be avoided by

employing an input track-and-hold in front of the ADC along with an encoding

technique that suppresses sparkle codes

7


Problems

Measuring spurious-free dynamic range (SFDR) is a good

way to observe converter performance. The "effective bits"

achieved by the ADC is a function of input frequency; it can

be improved by adding a track-and-hold (T/H) circuit in front

of the ADC. The T/H circuit allows dramatic improvement,

especially when input frequencies approach the Nyquist

frequency, as shown in the next Figure.

8


Problems

● Meta-Stability:

• A severe limitation in very high-speed converters is meta-stability. It increases

rapidly at high sampling frequencies. Meta-stability is caused by the finite gain in

the comparators. Certain input signals generate output signals that can not be

detected by the digital circuit

• Gray-code encoding can be used to improve metastability. (How?!)

9


Problems (cont.)

10


Problems (cont.) ● The encoder is composed of two parts, the one out of N (1-of-N) circuit and Gray ROM. The 1-of-N

circuit is used to detect the “1” to “0” transition occurred in the Thermometer code which indicates

the input voltage level, by an array of two input NAND logic gate with one input inverted

● ROM is actually a truth table in hardware form.Next Figure shows an example of 3 bit Gray ROM

based Thermometer to Gray encoder. Every input Thermometer code combination corresponds to

an address, which is “read” to produce 3-bit Gray code.

● When the input in the non-inverted port is “1” and the inverted port “0” then only the output will be

equal to “0”. For the other input patterns the output will be equal to “1”. In general if no bubble errors

occurred there will only one “1” to “0” transition detected in the Thermometer code. So there will be

only one“0”appearing at the output of 1-of-N circuit. This “0” signal used to enable the corresponding

row in the Gray ROM.

11

ELCT 1003:High Speed ADCs 12

Dec Thermometer code Grey Code Binary

D T[7] T[6] T[5] T[4] T[3] T[2] T[1] G[2] G[1] G[0] B[2] B[1] B[0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 1 0 0 1 0 0 1

2 0 0 0 0 0 1 1 0 1 1 0 1 0

3 0 0 0 0 1 1 1 0 1 0 0 1 1

4 0 0 0 1 1 1 1 1 1 0 1 0 0

5 0 0 1 1 1 1 1 1 1 1 1 0 1

6 0 1 1 1 1 1 1 1 0 1 1 1 0

7 1 1 1 1 1 1 1 1 0 0 1 1 1


Problems (cont.) Now to understand how the Grey code encoding solves the problem of Metastability let’s assume the

case where the input voltage is almost equal the reference voltage of the 4th comparator hence T[4] is

Metastable. thus we get a Thermometer code like this : 000X111

where X is undefined. Let’s assume further that this X is interpreted as 1 and 0 by the 4th and 5th NAND

gates respectively. Now both the 4th and 5th NAND gates will produce zero selecting the corresponding

value stored in the ROM.

In case of the Binary ROM: 4th NAND will enable B[2].But the 5th NAND will enable B[1] and B[2]. then

the value obtained is 111 while either 011 or 100 was expected.

In case of Gray ROM: 4th NAND will enable G[2] and G[1].But the 5th NAND will enable G[1]. And the

value obtained will be 110 which is true.

→ Gray-code encoding allows only one bit in the output to change at a time. The comparator outputs are

first converted to gray-code encoding and then later decoded to binary.

15


Advantages and Disadvantages

● Advantages

• Very large Bandwidth

• A special nonlinear behaviour can be approached by varying the

values of the resistors in the ladder, which could be used in some

applications.

● Disadvantages

• Area (2N-1 comparators)

• Power and Cost

• limited resolution (Max 8 or 10 bits)

16


Semi-Flash ADC

For a trial to decrease the area and the number of comparators used.

2 flash ADCs are used, each will output half the number of bits; coarse ADC to output the most significant

bits & fine ADC to output the least significant bits.

The number of comparators are reduced drastically :

Example:

An 8-bit flash ADC has : (2^N - 1) ; N= 8 ; 255 comparators.

An 8-bit semi-flash is realized by having two 4-bit flash ADCs

(2^Nc -1) + ( 2^Nf -1) ; Nc = 4, Nf = 4 ; = 15 + 15 = 30 comparators.

17


Semi-Flash ADC

The Semi-Flash has 2 extra blocks : DAC & subtractor

Thus the latency of this ADC would be more than 2 times of the Flash latency, because the coarse ADC waits for

the output of the fine ADC.

- An amplifier of G = 2^Nc

would be added after subtractor

-to avoid the small residue signals

that are sensitive to noise.

-to make the signal swing equal for both

ADCs

- to simplify the design, Both ADCs use

same Ladder.

18


Pipelined ADC...

Binary search ..

19


Pipelined ADC...

Basic Architecture

20


Pipelined ADC...

To check in the binary tree:

check polarity of “Vin - α Vref” ….

where α= ½ , ¼ or ¾ , ⅛ or ⅜ or ⅝ or ⅞ ,........so on

“α” changes every stage!!

But we need a recursive function..

Assume we have the function 𝑓=Vres

𝑓(Vin , Vref) = 2 Vin - Vref if Vin > 1/2 Vref

= 2 Vin if Vin < 1/2 Vref

21


Pipelined ADC...

For the 1st stage:

if (Vin > ½ Vref ) then

𝑓(Vin , Vref) = 2 Vin - Vref = 2*(Vin - ½ Vref) ……First check #

else

𝑓(Vin , Vref) = 2 Vin ….Second check #

end if;

next stage it must be (Vin - ¾ Vref) for first check and (Vin - ¼ Vref) for

second check..

22


Pipelined ADC...

For the 2nd stage:

● First check

𝑓(2 Vin - Vref , Vref) = 4 Vin - 2 Vref - Vref = 4*(Vin - ¾ Vref)

● Second Check

𝑓(2 Vin , Vref) = 4 Vin - Vref = 4*(Vin - ¼ Vref)

*You can go on and check all the following steps to make sure you get the binary search right.

23


Pipelined ADC...

MDAC Implementation..

24


Pipelined ADC...

Adding comparators to the design..

25


Pipelined ADC...

● Fully differential from -Vref to Vref

1 Bit/stage ADC

Over range problems due to:

1. gain/slope: (a result of

capacitors mismatch).

2. Comparator offset:

(ex, if -1mV input was read as

2 mV).

26


Pipelined ADC...

1.5 bit/stage ADC:

𝑓(Vin , Vref) = 2 Vin - Vref

if Vin > ¼Vref

= 2 Vin

if -¼Vref < Vin < ¼Vref

= 2 Vin + Vref

if Vin < -¼Vref

27


Summary of an MDAC stage

Figure. MDAC structure

O/P


Summary of an MDAC stage

Fig. Sampling and Conversion Configurations for an

MDAC


Latency vs Throughput !

Fig. Pipelined behavior of the ADC


- Stages operate on the input like a shift register . - New output data EVERY clock cycle, but each stage introduces at least one half clock Latency .


Digital Correction - The DCL is actually a simple circuit of Half & Full adders to add the LSB of the higher stage ( the error

bit) to the MSB (certain bit) of the next stage .. The Last stage LSB is TRUNCATED !

- As long as the individual thresholds deviate no more than Vr/4 from an ideal value, then the error can

be corrected by adding shifted digital outputs of each of the stages.


- OpAmp Finite gain → Sol ? Use a high gain Cascode amplifier designed to give a 20dB

gain around the sampling frequency.

- Capacitances Mismatching & the appearance of parasitic capacitances → Sol? Design the

feedback gain of the OpAmp including Cp in the calculations … Accurate capacitance

matching between Cs and Cf .

High Speed Problems


High Speed Problems

Fig. Cascode Structure Amplifier For High Gain


References

● http://www.ti.com/lit/an/slaa510/slaa510.pdf

● http://www.te.kmutnb.ac.th/msn/223361report512.pdf

● SAR, Pipelined Versus. "A Tale of Two ADCs." IEEE SOLID-STATE CIRCUITS 39 (2015).

● http://www.ece.umn.edu/~harjani/courses/8331/ADC-pipeline_lecture.PDF

● http://www.allaboutcircuits.com/textbook/digital/chpt-13/flash-adc/

● https://www.maximintegrated.com/en/app-notes/index.mvp/id/810

● https://www.researchgate.net/publication/274713910_Thermometer_to_Gray_Encoders

● http://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf

● http://www.analog.com/media/en/training-seminars/tutorials/MT-004.pdf

● https://www.maximintegrated.com/en/app-notes/index.mvp/id/748

● Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, ISBN 0-916550-27-3.

37

http://www.ece.umn.edu/~harjani/courses/8331/ADC-pipeline_lecture.PDF




https://www.researchgate.net/publication/274713910_Thermometer_to_Gray_Encoders










http://www.analog.com/media/en/training-seminars/tutorials/MT-003.pdf




























https://www.maximintegrated.com/en/app-notes/index.mvp/id/748













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