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High Speed Mixed Signal IC DesignNotes set 5:Digital IC design at the Gate level

Mark RodwellUniversity of California, Santa Barbara

[email protected] 805-893-3244, 805-893-3262 fax


High speed digital IC design at the transistor level

ECL and CML gate designs, DC design

circuit structures for and / or / xor / latches …

large-signal delay analysis, design for high speed

transmission line interconnects, signal distribution

power-delay relationships


Basic Gates, Logical Description

A=1 A=0B=1 C=1 C=0B=0 C=0 C=0

A=1 A=0B=1 C=1 C=1B=0 C=1 C=0

A=1 A=0B=1 C=1 C=0B=0 C=0 C=1

And

OR

XOR(exclusive OR)


ECL gate, circa ~1965

This is an *OR/NOR gate….port 3 is high if ports 1 or 2 are high…port 4 is the logical complement of port 3


ECL gate, circa ~1965

Emitter follower buffering of interconnect capacitance(good ? Bad ?)

DC output swing is 400 Ohms * 1 mA= 400 mV…..IoRL in generalMinimum Input voltage swing is 2kT/q+2IoRex. Need IoRL>>(2kT/q +2IoRex) for adeguate noise margin

…typically 500-600 mV output swing employed

Current sources replaced by resistors or current mirrors

Vout

Vin

-Vbe-IoR/2

-Vbe

-Vbe-IoR

2kT/q+2IoRex


Problems with old-fashioned ECL gate

Gate is single-ended….differential ckt generally preferredwhy ? (standard reasons given are not so convincing…)one reason is 2:1 lower permissible logic swing, less power

Gate uses emitter followers on **output**….this can result in strong transmission-line ringing….

( )

power lsubstantia consumes isVolts...th 2- e.g.at biased line, of end recevingon resistordown -pullby biased EF :mitigation Partial

strongly. ringcan Line....capacitive is end recevingon Loadinductive. is which , //1

isfollower emitter of impedanceOutput

τfjfRgZ Lmout +≈


Differential Gates, CML and ECL

CML ECL


Differential CML gate, other attributes

Operates with complementary inputs and outputsQuite low power consumption, as not many pull-down currentsources...


Differential CML gate, DC operation.

satce

Loonbece

onbece

exoin

LoLogic

VRIVV

VVRIqkTV

RIV

,

,

,

LOW with HBT Needon when at operates Transistor

off when at operates Transistor2/2 is rangeinput linear DC

is swingoutput DC

−=

=+=∆

=∆

Vout

Vin

-IoR

2kT/q+2IoRex


Differential CML AND / NAND gate

2-input logic gates must be implemented using series gated current steering. 3 input gates would require cascading 2-level gates, or 3-level series current steering. 3 level currrent steering is faster, but needs a more negative supply. OR/NOR gate is created by taking complements of both inputs and output.


Differential Current-Steering Series-Gated Bipolar Logic Gates

Zo

CML ECL

Zo


Direct-coupled FET logicNeed enhancement-mode and depletion-mode devicesslow driving long wiressingle-ended…threshold problems with low ∆V

Source-Coupled FET logic:Need a monolithic diode level-shiftfairly high power due to source followersSource follows needed for level-shifting

FET equivalent of CML :Need a monolithic diode level-shiftneed enhancement mode devicewould be best for fast / low-power

SCFL

DCFL

Zo

FET equivalent of CML

Zo

Logic family plays strong role in powerNeed diodes for SCFL

DCFL needs enhancement mode HEMTs:

HEMT Logic Gates


Differential CML XOR gate

the 6-transistor cell is often referred to as a Gilbert cell (originating with his analog multipliers…). Note that the whole gate requires 3 pull down current sources


Differential ECL buffer / inverter

emitter followers on high "A-level" inputs result in faster gate operation and larger Vce across switching transistors, at expense of considerably higher current consumption. Emitter followers are usually assocaiated with gate inputs, not outputs.


Differential ECL AND / NAND gate

Same circuit structure as CML gate, except note added emitter followers on B level inputs and added diode level shifts on A-level inputs


Differential ECL XOR gate

….


Driving Interconnects: EF associated with gate outputs

This can ring quite badly, due to inductive EF output impedance and capacitive CS input impedance.

τπfRL Leq 2/=

mexLout gRRR /1)/( ++= β

)/(2 logicVICCC fojecbin ∆++= τ

LR


Driving Interconnects, and basic power-delay products

sending end termination….matched termination….line should not (ideally) ring…actually does due to receivingend capacitive load... logic swing is Io*Zo…with Zo of 100 Ohms typical, this requires 2 mA drive current for 200 mV logic swing in a 100 Ohm environment...

Zo

Zo

Zo

Zo

Io


Driving Interconnects Receiving end termination

Zo

Zo

Zo Zo

Io

receving end termination….matched termination….line should not (ideally) ring…actually does due to transistor capacitances ... logic swing is Io*Zo…with Zo of 100 Ohms typical, this requires 2 mA drive current for 200 mV logic swing in a 100 Ohm environment...


Double line termination

Zo

Zo

Zo

Zo

Zo Zo

Io

double matched termination….ringing more strongly suppressed, use where needed….... logic swing is Io*Zo/2…with Zo of 100 Ohms typical, this requires 4 mA drive current for 200 mV logic swing in a 100 Ohm environment...


unterminated lines

here lines are not terminated. Acceptable only when line delay is short in comparison with risetimes of concern. A short unterminated line will act as a capacitive load; a long unterminated line will ring. More on this in a few slides.

... logic swing is Io*RL…current consumption greatly reduced (and smaller HBTs used)….

RL>>Zo

RL>>Zo

Zo

Zo

Io


unterminated lines: delay due to wiring capacitance

RL>>Zo

RL>>Zo

Zo

Zo

Io

wire

oicwirewireLwirewireL

wirewirewirewirewirewire

wireLLwirewireL

fallrisewire

ZIV

ZRCR

ZZvlC

CRRLZRT

)/()/(

:constant timeCharging//

:Theninductance wiringignorecan & / then , ifonly and If

ct.interconne lumped ascan treat , ifonly and If

logctinterconne

/

∆===

==

<<>>

<<

τττ

τ

τ


Power Consumption in ECL and CML with singly-terminated Lines

CML Gate:Fastemitter followers on lower level only (level-shifting)Vcc = 3Vbe+300 mV <--IR drop on mirror resistor

I=3Iswitched=3*∆Vlogic/Zo (approx.)

ECL Gate:Adds emitter followers on upper levelSomewhat fasterVcc = 4Vbe+300 mV I=5Iswitched=5*∆Vlogic/Zo (approx.)

E2CL Gate:Double emitter followers driving both levelshelps with f/fτ, higher Vce for high J/CVcc = 5Vbe+300 mV I=7Iswitched=7*∆Vlogic/Zo (approx.)

Need to use CML for low power

Zo

CML

ECL

Zo


Power and Power-Delay Products

Device sized for 100 Ω load:(300 mV ECL logic swing)0.25 µm x 6 µm emitterJpeak=2 mA/um^2→ peak speed at 2 mA

Shorter stripe length device:0.25 µm x 0.5 µm emitterpeak speed at 250 µA bias

The smaller device consumes 12:1 less power but cannot use terminated lines. The lines then act as capacitive parasitics, and circuit speed is reduced due to the resuling RLCwire time constant.


Power-Delay Product for a “Baseline” Device1 µm by 1 µm emitter

0.5 mA per transistor, 1.5 mA total for gate. 3.3 V supply

Power consumption:- 5 mW @ FO=2

Power-delay product(assuming 5 ps delay):25 fJ @ FO=2

P ≈ 3 • (3.3V) • (5 •104 A/cm2 ) • (1 µm)2 = 5 mW

Q1aQ1b

Q2a Q2b

RL RL

Wiring capacitance ignored


Power-Delay Product for Scaled Device

Design rules reduced to 0.1 µmassume gate delay still - 4 ps

0.1 µm by 0.1 µm emitter5 microamps per transistor

Power consumption:- 50 µW @ FO=2

Power-delay product:0.2 fJ @ FO=2

P ≈ 3 • (3.3V) • (5 •104 A/cm2 ) • (0.1 µm)2 = 50 µW

Q1aQ1b

Q2a Q2b

RL RL

Wiring capacitance ignored


Low-power gates have large delay from wiring capacitance

RL>>Zo

RL>>Zo

Zo

Zo

Io

limited-ctinterconne becomesproduct delay-power and smaller, becomes scaled, are rs transistoAs

2)(

2

gateper sourcescurrent ofnumber theis where,2

2)2/(2/

termstransistorlogic


gate


termstransistorctinterconnegate

logicctinterconne

ττ

τττ

τττττ

τττ

oeewire

wireee

oeewireo

wireoeegate

oeegate

wireowire

wireowirewireLwirewireL

NIVZ

VNV

NIVZI

VNIVP

NNIVPZI

VZI

VZRCR

+∆

=

+∆

=

=

+∆

=+=

∆===


Minimum allowable logic voltage swing

Vout

Vin

-IoR

2kT/q+2IoRex

? reducing tolimits theareWhat

smaller. made is assmaller becomesdelay limited-ctInterconne2

)(

logic

logic


gate

VV

NIVZ

VNVP oee

wire

wireeegate

∆

∆

+∆

= τττ

this. timesseveral bemust /2 is range ageinput voltLinear

logic

0

VRIqkT ex

∆+


Minimum Logic Voltage Swing

exoexolinear

exolinear

RIRIqkTVV

fkTR

RIqkTV

6mV 150~6/6*3~need margin we noise"" adequate have order toIn

margin ringing"EMI" called be instead should 4 noise mal with therdo tonothing **y*absolutel* has

margin noise"" called ismargin safety Thiscoupling groundor supply todue ceinterferen gate-gate

a2) level-circuit ects,(interconn ringing signal toduen degradatio signalagainst margin need We

2/2 is gate theof range ageinput voltlinear The

logic ++=∆>∆

+

∆

+=∆


Vin

Vout

Vin(t)

t

t

Vout(t)

diffusion+ depletioncapacitance

only depletioncapacitance

exolinear RIqkTVV 6/6*3logic +=∆>∆

exolinear RIqkTV 2/2 +=∆


Vout

Vin

time

Vin

time

Vout

linearVV

∆

∆

n larger tha

timesseveral bemust EMI, and ringing tolerateTo

logic


Circuits become interconnect limited

Interconnect limits: as transistors are scaled, wiring capacitance dominates

Power•delay becomes dependent only on supply voltage & logic voltage swing

independent of design rules, independent of transistor bandwidth

mask design rules

device-limited

interconnect-limited


gate 2)(

τττ oeewire

wireeegate NIV

ZVNV

P +∆

=


Power-delay product in interconnect limit

bipolar logic (static power)

PgateTprop = 1/ 2( )CwireVcc∆Vlogic

Pgate / fclock = 1/ 2( )CwireVcc∆Vlogic

CMOS logic (dynamic power)

( ) ~1−clockprop fT number gates between latches

For fast, low-power logic: reduce Vcc∆Vlogic


The Interconnect Limit and Logic Gate Design

I2I1

Q1aQ1b

Q2a Q2b

RL RL

I1

Av =RL

2kT qI2

=I2 RL

2kT q=∆Vlogic

2kT q

Voltage Gain must be >> 1

∆Vlogic = 10 • (kT / q)

PgateTgate = 1 2( )Vcc∆VlogicCwire

So:

But:

PgateTgate = 1 2( )(1.5 Volt) (10 • kT / q)Cwire

(power•delay) is constrained by interconnects

a fast transistor doesn't result in a fast IC

conclusion: a better circuit design is needed

Similar derivation for CMOS (Meindl, Proc IEEE, 1995)

>

>


Wiring capacitance ? What if we use terminated transmission lines ? (which we often do...)

wireiceeowirewireiceeoiceewiredelaygate

oiceewireoiceegatedelaygate

wirewirewire

wiregatedelay

oiceeoeegate

oic

CVVZvlVVZVVTTPZVVTZVVTTP

vlTTTT

ZVVIVPqkTaboutZIV

logloglog

loglog

log

0log

)/()/(

)/()/(/

/

/*5

∆=∆=∆>

∆+∆==

+=

∆==

>=∆

so, even though “wiring capacitance” is no longer an accurate description, CVcc∆Vlogic is still an accurate expression for the power-delay limit

I0

Z0

Z0

Z0 Z0

Vee


ECL Latch

When clock is high, output = input.When clock is low, output = input at just before clock changed from high to lowNote the positive feedback pair which holds the output levelwhen clock_bar is high

D Q

C Q


Master-Slave Latch

Cascading a pair of latches creates a circuit which reads the data input D, and outputs it as the value Q,Only on a falling edge of clock….output is otherwise held constant…. MS latch is used as timing control element…outputis a version of the input, but sampled only at falling edge of clock

D Q

C QQ

Q

DC

D Q

C Q


Master-Slave Latch timing diagram

time

clock

master in

master out

slave out

D Q

C Q

D Q

C Q

Q

Q

DC


What are latches and MS latches used for ?

timing controlin logic system, prop delays will be function of transititon & critical path.timing errors/fluctuations will accumulate…role of latch is to suppress this, restore timing.

decision element.in ADCs and in communcations receveviers, must decide whethera signal exceeds / does not exceed a critical thresholdat a particular set of points in time defined by a clock signal.


E2CL M/S Latch

Popular in Si/SiGe due to (1) H212 current gain and

(2) larger Vce across switching transistors helps Ccb/I ratio


ECL M/S Latch connected as 2:1 static frequency divider


Fast ECL 2:1 static frequency divider


Logic Propagation delay analysis: start with one-level CML gate

First, basic assumptions: 2:1 fan-out, chain of identical gates


Basic Assumptions for Propagation delay analysis

swing. logic theis whereetc. / ,/ :analysis signal-Large

etc. / ,/ :analysis signal-Small? solve wedo how nonlinear, is Transistor

..

..

VVIgVQC

dVdIgdVdQC

mss

mss

∆∆∆≡∆∆≡

≡≡


Basic Assumptions for Propagation delay analysis

charge storedcollector and base HBTby isit than escapacitancdeplectionby controlled moremuch is speed Logic 10. offactor

aroughly e...by capacitancdiffusion theand gm of valueseffective thereducesgreatly operation signal large that Note

/)(/

/))((/

1/

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:implies Thisetc. / ,/ :analysis signal-Large

arg,

,arg,

,

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,

,

cbcbsignalelcb

effje

V

VV jesignalelje

inoutv

fmfoLffodiffusionbe

oLLoom

mss

CVVCVQC

CVdVvCVQC

VVAgqkTIRVIVQC

kTqIRRIIVIg

VIgVQC

onbe

onbe

=∆∆=∆∆=

=∆=∆∆=

−=∆∆=

=<<=∆=∆∆=<<==∆∆=

∆∆≡∆∆≡

−

∆−− ∫

ττττ


Why isn't base+collector transit time so important ?

1:10~ is which ,/

of ratioby reduced ecapacitancdiffusion signal-Large

)(

)(Q :Operation Signal-LargeUnder

swing. voltage/over only ...active

/)(

)(

)(Q :ecapacitancDiffusion

base

base

∆

∆∆+

=

+=∆

+=

+=

+=

qkTV

VV

II

qkT

VqkT

I

VdVdII

LOGIC

LOGICLOGIC

dccb

Ccb

beCcb

bebe

Ccb

Ccb

ττττ

δττ

δττ

δττδ

Depletion capacitances present over full voltage swing, no large-signal reduction

Vin

Vout

Vin(t)

t

t

Vout(t)

diffusion+ depletioncapacitance

only depletioncapacitance


Gate Propagation delay analysis

∑∑ −

−

−=

−=−

++++++

=

stagesemitter -commonsignallarge,

followersemitter 1

1

11

11

221

221

// Findconstants timeof method by the Find

2/)( is points) switching 50% theto(delaydelay mean the1/2 hence ),( isfunction transfer

theof *delaymean * that theshow math to elementary isIt

...1...1

offunction transfer hasCircuit models *signal-large*r with theirs transistoreplace :Method

delay gatefor solve now We

mcbmbe

gate

bandmidin

out

in

out

gCgCba

baTba

sasasbsb

VV

VV


Gate Propagation delay analysis

limitation serious a is which neglected, is ringingfollower -emitter that ly,specifical

means, This neglected. arefunction ansfer circuit tr in the effectsorder -2nd that note toimportant isit casesboth In

)(121

21 e.g.

method, control-charge by the analysisdelay toidentical iscircuit, signal)-(large linearized on the analysisdelay MOTC

different, quite be appear to methods healthough t that Note

2a

dVvCII

QThigh

low

V

Vgate ∫∑∑ ∆

=∆∆

=


One-level CML Propagation delay analysis

delaymean the(1/2) e.g. , 2/T gives which , with timecharging nodelinear assumed

instead have weused, sassumption theofaccuracy of level theTo behaviour. charging ))/exp(1(

assuming toequivalent is )2ln(T Taking

prop

prop

τ

τ

τ

=

−−

=

t


One-level CML Propagation delay analysis: fan-outs

Here we are analyzing a gate chain with a fan-out of 2:1

RLCcbx

Ccbi

Rbe

Cbe

RL


Simplifying treatment of fan-outs

area dhighlighte in the capacitorsonly consider must wegate,per ONCE ecapacitanc parasiticeach count order toIn

arguments.symmetry by 2by replaced is LL RR

RLCcbx

Ccbi

Rbe

Cbe

2*RLCcbx

Ccbi

Rbe

Cbe


Gate Delay Calculation

[ ] [ ]

[ ]

)/)((/)(

)12(

)11(

)11(

)1()1)(()(

logic1

logic

logic

logic1

logiclogic

logiclogiclogic

logic1

1

ocbicbxmcbicbx

bbcbio

cbicbxfo

bbfo

jebbje

oocbx

oobbcbi

obb

foje

LvLcbxLvbbLcbiLbbbe

IVCCgCCb

RCIV

CCNVI

RNIVN

CRCa

IV

IVN

C

IV

IVN

RCIVN

RVI

Ca

RANRCRARNRCNRRCa

∆+−=+−=

+

∆+++

∆++

∆+=

∆++

∆+

∆++

∆++

∆+

∆+=

+−++−+++=

ττ

τ

RLCcbx

Ccbi

Rbe

Cbe

N*RLCcbx

Ccbi

Rbe

Cbe


Gate Delay Calculation: Single-level CML gate at N:1 fanout

[ ]

densitycurrent high and swings logic small of use thefavorsstrongly This

dominate.usually terms)/( and )/( that theNote

)22(

2

logiclogic

logiclogic

logic

ojeocb

oje

ocbicbx

fobb

fbbcbibbjegate

IVCIVCIVN

CIV

CCN

VI

R

NRCRCT

∆∆

∆+

∆+++

∆+

++=

τ

τ


Effect of Current Density

logiclogic

logic

logiclogic

logic

)22()(

2

)22(

2

VNJA

CJT

VAAN

VJ

AR

NRCRCTJA

VNC

JAV

TAN

VAJ

R

NRCRCT

oe

je

oce

cfoebb

fbbcbibbjegate

oeje

oec

cfeobb

fbbcbibbjegate

∆+

∆++

∆+

++=

∆+

∆++

∆+

++=

ετ

τ

ετ

τ


Effect of Logic Voltage Swing

( )[ ]( ) ( )

( ) t.nondominan

beingusually term elimit...th with thisconsistent possible, as small as be should swing voltageLogic

6mV 150~6/6*3~ need than weRecall

2/2 is gate theof range ageinput voltlinear that theNote

)22(

2

logic

logic

logiclogic

logic

VIR

RIRIqkTVV

RIqkTV

IVNCIVCCNVIRNRCRCT

fobb

exoexolinear

exolinear

ojeocbicbx

fobbfbbcbibbjegate

∆

++=∆>∆

+=∆

∆+∆+++

∆+++=

τ

ττ


Effect of Logic Voltage Swing

( )[ ]( ) ( )

( ) ( )( )( )( )

obtained isbenefit no and increase,must swing voltage theOtherwise,

area.unit per resistanceemitter thereducemust but we time,charging Ccb reduce do wedensity,current uppush weIf

/ that Note

that Note

6mV 150~6/6*3~But

)22(

2

0

logiclogic

logic

logiclogic

logic

eexeex

eeccocb

exoexolinear

ojeocbicbx

fobbfbbcbibbjegate

ARJRIJVAATIVC

RIRIqkTVV

IVNCIVCCNVIRNRCRCT

=

∆=∆

++=∆>∆

∆+∆+++

∆+++=

ε

ττ


Scaling Laws, Collector Current Density, Ccb charging time

baseemitter

collector

subcollector

baseemitter

collector

subcollector

Collector Field Collapse (Kirk Effect)

Collector Depletion Layer Collapse

)2/)(/( 2 εφ cdsatcb TqNvJV −+>+

)2/)(( 2min, εφ cTqNV dcb +>+

2min,max /)2(2 ccbcbsat TVVvJ φε ++=⇒

Collector capacitance charging time is reduced by thinning the collector while increasing current

( )( ) ( )

+

∆=∆=∆

sat

C

CECE

LOGICCLOGICcCLOGICcb v

TAA

VVVIVTAIVC

2/

emitter

collector

min,collectorε

cecbbe VVV ≅+≅ )( hence , that Note φφ


ECL Propagation delay: upper-level circuit

again assume a fan-out of N:1Simplify by assuming beta>>1, Ree>>Re.

RLCcbx

Ccbi

Rbb

Cbe

N*RLCcbx

Ccbi

Rbb

Cbe RexRee


ECL Propagation delay: upper-level circuit

Next key point:Depending upon the details of the IC design, the emitter-followers may or may not switch. For now, let us assuem they do not. We consequently use small-signal quantities for the EFs, and large-signal quantities for the CS transistors.

RLCcbx

Ccbi

Rbb

Cbe

N*RLCcbx

Ccbi

Rbb

Cbe RexRee


[ ][ ]

[ ][ ]

[ ][ ]

[ ][ ]211logic2

0logic2112

0logic112

0logic221111

0logic221111

211logic2

0logic2112

0logic112

111111

/)/(

/)/(2

/)/(2

)/)(()(2

)/)(()/)(/(

/)/(

/)11)(/(

/)11)(/(

)/)(/()(

bbeexofje

bbeexcbi

eexcbx

cbicbxbbLcbiLcbxgate

cbicbxeefje

bbeexofje

bbeexcbi

eexcbx

eefjebbLcbiLcbx

RqIkTRVICIVRqIkTRC

IVqIkTRCIVCCRNRCNRCbaT

IVCCqIkTkTqICbRqIkTRVIC

IVRqIkTRCIVqIkTRC

qIkTkTqICRNRCNRCa

++∆++

∆++++

∆+++

∆++++=−=

∆+−+=

++∆++

∆+++++

∆++++

++++≈

τ

τ

τ

τ

RLCcbx

Ccbi

Rbb

Cbe

N*RLCcbx

Ccbi

Rbb

Cbe RexRee


[ ] [ ]

ratio / improved hence , increased permits Larger )3

/ buffing toduet improvemen *slight* 2) termscharging ofnumber Reduced 1)

todue CMLan smaller th little a isdelay net that theNote

)/(2)/(

))(/(

)/)(/(//2

22: Writing

logic2,

0logic20logic1

21logic

1logic112112

221122

cbcce

ofdiffbe

cbL

cbcb

bbexof

eofeexjeeexcb

bbjebbcbicbibbgate

cbicbxcb

CIJVVIC

CR

IVCIVNCRRVI

qIkTVIqIkTRCqIkTRCRCRCCRT

CCC

∆=

∆+∆+

+∆+

∆+++++

++=+=

τ

τ

τ

RLCcbx

Ccbi

Rbb

Cbe

N*RLCcbx

Ccbi

Rbb

Cbe RexRee


Do the emitter-followers switch ????

Cin

Io

time

time

inV

eIefI

logicV∆

TVCI L ∆∆=∆ /logic

T∆

)/(

2

logicVICCC

fo

jecbL

∆+

+=

τ

0IefI

efI

TVCI L ∆∆=∆ /logic


Do the emitter-followers switch ????

. of gdischargin limited-rate-slew is This

/ whichFrom

/0:zero iscurrent EF minimum thepulse, falling aon Second,

limits.effect -Kirk below iscurrent peak that thisensuremust We

/iscurrent EFpeak thepulse, rising aon First, dangers. 2 are There

logicmin

logicmin,

logic,

L

efL

Lefefef

Lefefpeakef

CIVCT

TVCIIII

TVCIIII

∆=∆

∆∆−=∆−==

∆∆+=∆+=


CML Propagation delay: two-level circuit


NRL

NRL

NRL

RL

Cbe

Ccbi

Ccbx

Rbb

Cbe

CcbiCcbx

Rbb

Cbe

CcbiCcbx

RbbRex

Ree

Q1Q2

Q3 Q4

4

logic

in Q3 ofcollector theloadssimply and off remains Q4 then low, is Q4andhigh is Q3 of base theIf CB. is Q3 and CE, is Q2

EF,an is Q1path that switching level B on the that Note

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ECL Propagation delay: two-level circuit


Logic Speed

Caveat: ignores interconnect capacitance and delay, which is very significant

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Yoram BetserRaja Pullela


Logic Speed: definition of terms

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swing voltagelogic :areaemitter unit per current emitter :

mestransit ticollector and base of sum :areaemitter unit per ecapacitanc basecollector extrinsic :

areaemitter unit per ecapacitanc basecollector intrinsic :

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What HBT parameters determine logic speed ?

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Caveats: assumes a specific UCSB InP HBT (0.7 um emitter, 1.2 um collector 2kÅ thick, 400 Å base, 1.5E5 A/cm^2)

ignores interconnect capacitance and delay, which is very significant

Cje Ccbx Ccbi (τb+τc) ( I/∆V) total∆V/ I 33.5% 6.7% 27.8% 68.4%∆V/ I 12.3% 12.3%(kT/q) I 1.4% 0.1% 0.4% 0.5% 2.5%Rex -1.3% 0.1% 0.3% 0.9% 0.1%Rbb 10.2% 2.8% 3.7% 16.7%total 43.8% 6.8% 31.3% 17.5% 100.0%

38%

Yoram Betser, Raja Pullela

high speed mixed signal ic design notes ... - uc santa barbara€¦ · class notes, ece594a,...

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