high-speed pipelined adc using a bucket brigade …wp775fw8173/thesis final-augmented.pdfhigh-speed...

HIGH-SPEED PIPELINED ADC USING

A BUCKET BRIGADE FRONT-END

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Noam Dolev Geldbard

August 2013

This dissertation is online at: http://purl.stanford.edu/wp775fw8173

© 2013 by Noam Dolev Geldbard. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

ii

http://purl.stanford.edu/wp775fw8173

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Boris Murmann, Primary Adviser


Mohammad Arbabian


Bruce Wooley

Approved for the Stanford University Committee on Graduate Studies.

Patricia J. Gumport, Vice Provost for Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.

iii

iv

Abstract

Advanced wireless technologies, such as LTE and LTE advanced, require low-

power, high-speed, and high-resolution analog-to-digital converters (ADCs). At present,

only the pipelined ADC architecture is capable of meeting the stringent bandwidth,

linearity, and resolution requirements for this application. However, in current products,

the power efficiency of this architecture is limited by the use of operational amplifiers as

inter-stage gain elements.

This research investigates an approach where the critical operational amplifiers

are replaced by a pulsed-based bucket brigade amplifier, which achieves voltage gain by

redistributing charge form a large sampling capacitor to a small load capacitor. This

circuit performs the residue amplification with lower power, but is weakly nonlinear and

therefore requires digital linearization. Since the power overhead for digital arithmetic in

modern CMOS technologies is low, this approach has the potential to yield large overall

power savings.

To evaluate this concept, a prototype ADC was implemented in 65-nm CMOS.

The converter operates at 200 MS/s, consumes 11.5 mW from a 1-V supply, and occupies

0.26 mm2. It achieves an SNDR of 65 dB at low input frequencies and 57.6 dB near

Nyquist, which corresponds to an SNDR-based Schreier FOM of 164.5 dB and 157 dB,

respectively. These results validate the concept of the proposed pulse-based bucket

brigade amplification, and the achieved performance compares favorably with the state of

the art.

v

Acknowledgments

Being a graduate student at Stanford was one of the best experiences I had, and I

could not have done it without the help of many people that I want to thank here. First, I

want to thank my advisor Prof. Boris Murmann. It has been an honor being his student.

Having him as a mentor was the highlight of my experience in Stanford and I could not

achieve this without his help and guidance. I also want to thank Prof. Bruce Wooley and

Prof. Amin Arbabian for serving on my thesis reading committee and oral examination

committee. I want to thank Prof. Mark Horowitz for serving on the oral examination

committee and Prof. Norbert J. Pelc for chairing the oral examination committee.

For funding, I want to thank Renesas and C2S2 Focus Center (FCRP). Specially,

I want to thank Miki Takahiro from Renesas for his guidance and help. I want also to

thank TSMC for the fabrication of the prototype and Berkeley Design Automation for the

use of the Analog Fast SPICE Platform (AFS).

I want to thank Ann Guerra, our team administrative assistant. Ann always took

care for all the administrative tasks and helped to solve any problem in the best way. In

addition, I want to thank Joe Little, the computer system administrator. Joe always gave

the best solution for any computer problem, any day, any time of the day.

For current and former students in the team: Dr. Siddharth Seth, Dr. Alireza

Dastgheib, Dr. Donghyun Kim, Dr. Pedram Lajevardi, Dr. Ray Nguyen, Dr. Yoonyoung

Chun, Dr. Drew Hall, Dr. Justin Kyungryun Kim, Dr. Wei Xiong, Dr. Clay Daigle, Dr.

Manar El-Chammas, Dr. Parastoo Nikaeen, Dr. Yangjin Oh, Dr. Echere Iroaga, Vaibhav

Tripathi, Bill Chen, Kevin Zheng, Ryan Boesch, Nikolaus Hammler, Ross Walker, Alex

vi

Guo, Man-Chia Chen, Douglas Adams, Jonathon Spaulding, Alex Omid-Zohoor, Nishit

Harshad Shah, Valerie Barry, Lita Yang, Mahmoud Saadat, and Ilina Mitra, It has been

great experience working with all of them and I want to thank them for all the help and

support. Especially, I want to thank Dr. Jason Hu for introducing me to the world of

highly efficient pipeline ADCs, and to Martin Kramer for helping me design part of the

supporting circuits for the testchip.

I want to thank my parents, for guiding me through life and always driving me to

achieve the best out of me. I want to thank my wife, Einat, for going with me in this

journey and making it all possible. Thanks You. Last, but not least, I want to thank my

kids, Leaya and Dan who always reminded me that there is more to life than studies and

always put a smile on my face.

vii

Table of Contents

Abstract .............................................................................................................................. iv

Acknowledgments............................................................................................................... v

Table of Contents .............................................................................................................. vii

List of Tables ..................................................................................................................... xi

List of Figures ................................................................................................................... xii

List of Abbreviations ....................................................................................................... xvi

1. Introduction ............................................................................................................ 1

1.1. Motivation ....................................................................................................... 1

1.2. Background ..................................................................................................... 1

1.3. Pipeline ADC Inefficiencies ............................................................................ 3

1.4. Power Reduction Strategies ............................................................................. 7

1.4.1 Architecture Level .................................................................................... 7

1.4.2 Using Digital Circuitry for Power Reduction ........................................... 7

1.4.3 Amplifier Level......................................................................................... 8

1.4.4 The Quest for a Virtual Ground ................................................................ 8

1.5. Inspiration ...................................................................................................... 10

1.6. Organization .................................................................................................. 12

2. Bucket Brigade Circuit Basics ............................................................................. 13

2.1. Basic Operation ............................................................................................. 13

2.2. Bucket Brigade Circuit with Amplifier in Boosting Configuration .............. 15

2.3. Pulse-Based Bucket Brigade Amplifier......................................................... 16

2.3.1 Pulse Wave Shape ................................................................................... 17

2.3.2 Pulse-Based Bucket Brigade vs. Boosted Amplifier Configuration ....... 18

viii

2.3.3 Pulse-Based Bucket Brigade Amplifier Linearity .................................. 19

2.4. Summary ....................................................................................................... 21

3. The Bucket Brigade Amplifier ............................................................................. 22

3.1. Large Signal Analyses ................................................................................... 22

3.1.1 Constant VG ............................................................................................ 23

3.1.2 Gain Function ......................................................................................... 26

3.1.3 RC-shaped Vg ......................................................................................... 26

3.2. Voltage Input vs. Charge Input ..................................................................... 29

3.2.1 Charge Input Scheme Overview ............................................................. 31

3.2.2 Gain Expression for the Charge Input Scheme ....................................... 32

3.3. Bias Voltages Value ...................................................................................... 33

3.4. Thermal Noise ............................................................................................... 36

3.4.1 Thermal Noise due to Sampling on CS ................................................... 37

3.4.2 Thermal Noise due to Pre-charge of the Load Capacitor CL .................. 37

3.4.3 Thermal Noise from Charge Redistribution Phase ................................. 37

3.5. Summary ....................................................................................................... 39

4. ADC Stage Design ............................................................................................... 40

4.1. Differential Implementation .......................................................................... 40

4.2. DAC Implementation .................................................................................... 42

4.2.1 DAC Linearity ........................................................................................ 42

4.2.2 DAC Thermal Noise ............................................................................... 46

4.2.3 DAC Layout Considerations ................................................................... 47

4.3. Sub-ADC Design ........................................................................................... 49

4.3.1 Multi-bit Implementation ........................................................................ 49

4.3.2 Comparator Implementation .......................................................................... 50

4.4. Timing ........................................................................................................... 51

4.4.1 Wave Shapes ........................................................................................... 54

ix

4.5. Summary ....................................................................................................... 55

5. Circuit Implementation ........................................................................................ 56

5.1. Top Level ...................................................................................................... 56

5.1.1 ADC High Level Architecture ................................................................ 56

5.1.2 Capacitor Sizing ...................................................................................... 57

5.2. Stage One ...................................................................................................... 58

5.2.1 Switch and Transistor Sizing .................................................................. 60

5.2.2 Stage 1 Comparators ............................................................................... 61

5.2.3 Calibration .............................................................................................. 63

5.3. Stage Two ...................................................................................................... 64

5.4. Stages 3-5: Bucket Brigade Circuit with Differential Boosting Amplifier ... 65

5.5. Stage Six ........................................................................................................ 70

5.6. Stages 7-13 .................................................................................................... 72

5.7. Summary ....................................................................................................... 73

6. Measurement Results ........................................................................................... 74

6.1. Introduction ................................................................................................... 74

6.2. Test Setup ...................................................................................................... 77

6.3. Measured Results .......................................................................................... 78

6.3.1 Dynamic Linearity .................................................................................. 78

6.3.2 Static Linearity ........................................................................................ 82

6.3.3 Thermal Noise......................................................................................... 83

6.3.4 Jitter ........................................................................................................ 85

6.3.5 Power ...................................................................................................... 87

6.3.6 Calibration Power ................................................................................... 88

6.4. Performance Summary .................................................................................. 89

6.5. Performance Comparison .............................................................................. 90

6.6. Summary ....................................................................................................... 93

x

7. Conclusion ........................................................................................................... 94

7.1. Summary ....................................................................................................... 94

7.2. Future Work .................................................................................................. 95

8. Bibliography ........................................................................................................ 97

xi

List of Tables

Table ‎1.1: ADC requirements for LTE and LTE-Advanced for the user device and

base-station ............................................................................................................ 2

Table ‎3.1: Model parameters ............................................................................................ 25

Table ‎3.2: Output voltage (Vout) and charge transferred to the output capacitor (Qout)

for voltage input scheme and charge input scheme ............................................. 30

Table ‎3.3: Bias voltage requirements ................................................................................ 33

Table ‎5.1: Stages architecture summary ........................................................................... 58

Table ‎5.2: Stage 1 comparator transistor sizes .................................................................. 62

Table ‎6.1: Thermal noise results, measurement vs. simulations ....................................... 84

Table ‎6.2: Power per stage architecture ............................................................................ 87

Table ‎6.3: Performance Summary .................................................................................... 89

Table ‎6.4: Performance Comparison ................................................................................ 92

xii

List of Figures

Figure ‎1.1: ADC survey ‎[3] bandwidth vs. SNDR ............................................................. 2

Figure ‎1.2: ADC survey, energy per Nyquist sample vs. SNDR ........................................ 3

Figure ‎1.3: Basic structure of a pipeline ADC .................................................................... 4

Figure ‎1.4: Switched-capacitor pipeline ADC stage ........................................................... 4

Figure ‎1.5: Two phase of operation of a standard switched-capacitor stage ...................... 5

Figure ‎1.6: (a) Class-A amplifier (b) Current directed to the load capacitor as a

function of the time. ............................................................................................... 6

Figure ‎1.7: Zero crossing based switched-capacitor circuit ‎[17] ........................................ 9

Figure ‎1.8: Dynamic Source follower amplifier ‎[18] ....................................................... 10

Figure ‎1.9: The bucket brigade device ‎[21] ...................................................................... 11

Figure ‎1.10: Bucket brigade for pipeline ADC using boosting amplifier ‎[24] ................. 12

Figure ‎2.1: Bucket brigade amplifier operation ................................................................ 13

Figure ‎2.2: Bucket brigade circuit basic operation - wave shapes .................................... 14

Figure ‎2.3: Bucket brigade circuit with ampifier in boosting configuration ..................... 15

Figure ‎2.4: Source voltage and gate voltage of bucket brigade circuit with an

amplifier in boosting configuration ..................................................................... 16

Figure ‎2.5: Gate voltage, source voltage and source current for closed-loop, constant

gate, and RC shaped pulse-based bucket brigade circuit. Left column: circuit

topology, middle column: gate voltage and source voltage (dotted), right

column: source current ......................................................................................... 18

Figure ‎2.6: Pulse-based bucket brigade amplifier vs. bucket brigade with boosted

amplifier ............................................................................................................... 19

xiii

Figure ‎2.7: Linearity simulation of the pulse-based bucket brigade amplifier (256-

point FFT) ............................................................................................................ 20

Figure ‎3.1: Bucket brigade circuit .................................................................................... 22

Figure ‎3.2: Source voltage comparison of constant Vg circuit, model vs. SPICE

simulation............................................................................................................. 25

Figure ‎3.3: Source voltage comparison on pulse-based RC-shaped Vg circuit, model

vs. simulations ..................................................................................................... 28

Figure ‎3.4: Matlab analysis results for the RC-shape model. SFDR for 3rd

harmonic is

41 dB and SFDR for 5th harmonic is 81 dB ......................................................... 29

Figure ‎3.5: Charge input vs. voltage input bucket brigade circuit .................................... 30

Figure ‎3.6: Charge input bucket brigade circuit - basic operation .................................... 32

Figure ‎3.7: Voltage allocation for bucket brigade circuit ................................................. 34

Figure ‎3.8: Bucket brigade amplifier operation ................................................................ 35

Figure ‎3.9: Small signal model for noise calculations ...................................................... 38

Figure ‎4.1: Bucket brigade topology in the sampling and charge-redistribution phases .. 41

Figure ‎4.2: Circuit scheme to prevent common mode amplification ................................ 42

Figure ‎4.3: Modulation through the DAC ......................................................................... 43

Figure ‎4.4: Standard DAC implementation applied to the bucket brigade stage .............. 43

Figure ‎4.5: DAC implementation in the pulse-based bucket brigade stage ...................... 44

Figure ‎4.6: Simulated amplifier transfer function for different DAC values .................... 45

Figure ‎4.7: Horizontal difference between the residue segments ..................................... 46

Figure ‎4.8: DAC circuit for a multi-bit stage with 8 capacitors ........................................ 47

Figure ‎4.9: DAC layout..................................................................................................... 48

Figure ‎4.10: Layout of the DAC switches ........................................................................ 48

Figure ‎4.11: Comparator scheme ...................................................................................... 49

Figure ‎4.12: Multi-bit implementation for the sub-ADC .................................................. 50

xiv

Figure ‎4.13: Low kickback noise comparator ................................................................... 51

Figure ‎4.14: Four phases of operation .............................................................................. 52

Figure ‎4.15: First stage scheme ........................................................................................ 53

Figure ‎4.16: Stage timing .................................................................................................. 53

Figure ‎4.17: First stage wave shapes for VS, VG and Vout .................................................. 54

Figure ‎5.1: ADC architecture ............................................................................................ 57

Figure ‎5.2: Stage 1 transfer function with two modes of operation .................................. 59

Figure ‎5.3: Stage 1 architecture ........................................................................................ 60

Figure ‎5.4: Annotation of switch types in stage 1 ............................................................. 61

Figure ‎5.5: Stage 1 voltage comparator implementation .................................................. 62

Figure ‎5.6: Calibration scheme ‎[20] ................................................................................. 63

Figure ‎5.7: Stage two architecture .................................................................................... 65

Figure ‎5.8: Stage 3-5 transfer function ............................................................................. 66

Figure ‎5.9: Stage 3-5 architecture ..................................................................................... 67

Figure ‎5.10: Illustration of the issue of using two single-ended boosting amplifier

implementation .................................................................................................... 68

Figure ‎5.11: Differential boost amplifier for the bucket brigade stage ............................. 69

Figure ‎5.12: Connection diagram for the boosting differential amplifier in the bucket

brigade circuit ...................................................................................................... 69

Figure ‎5.13: Source and gate voltages of the transistor in bucket brigade with

differential boosting amplifier circuit .................................................................. 70

Figure ‎5.14: Stage six architecture .................................................................................... 71

Figure ‎5.15: Stage 7-12 architecture ................................................................................. 72

Figure ‎6.1: Test chip die photo ......................................................................................... 75

Figure ‎6.2: Package bonding diagram. All black pads are down-bonded to the thermal

pad ........................................................................................................................ 75

xv

Figure ‎6.3: Down-bonding to thermal pad ........................................................................ 76

Figure ‎6.4: Layout of the ADC ......................................................................................... 76

Figure ‎6.5: Test setup ........................................................................................................ 77

Figure ‎6.6: ADC spectral performance for a low frequency input before calibration.

SNDR is 44.17 dB, the SFDR is 57.14 dB, and the THD is -49.50 dB ............... 78

Figure ‎6.7: ADC spectral performance for low frequency input after calibration.

SNDR is 65.05 dB, the SFDR is 82.56 dB, and the THD is -81.74 dB ............... 79

Figure ‎6.8: Measured peak SNDR, SFDR and -THD vs. input frequency ....................... 80

Figure ‎6.9: Measured SNDR vs. input signal amplitude at fs=200 MHz .......................... 80

Figure ‎6.10: SNDR and SFDR as a function of input frequency for coefficients

optimized for each frequency and for coefficients optimized at 0.96 MHz ......... 81

Figure ‎6.11: Measured INL and DNL ............................................................................... 83

Figure ‎6.12: Histogram results for thermal noise measurements ...................................... 84

Figure ‎6.13: Clock path for the sample and hold .............................................................. 85

Figure ‎6.14: Detailed clock path ....................................................................................... 85

Figure ‎6.15:‎Estimated‎jitter‎limit‎of‎the‎ADC’s‎SNDR ................................................... 86

Figure ‎6.16: Power breakdown (excluding reference, I/O and external calibration

engine) ................................................................................................................. 87

Figure ‎6.17: ADC Survey, FOMS vs. sampling frequency ............................................... 90

Figure ‎6.18: ADC Survey, FOMS vs. sampling frequency. Only pipeline ADCs

without time interleaving are shown .................................................................... 91

xvi

List of Abbreviations

ADC – Analog to Digital Converter

LTE – Long Term Evolution

BW – Bandwidth

DAC – Digital to Analog Converter

SAR – Successive Approximation (ADC)

ΔΣ‎– Delta Sigma (ADC)

RMS – Root Mean Square

SNR – Signal to Noise Ratio

SNDR – Signal to Noise and Distortion Ratio

SFDR – Spurious Free Dynamic Range

THD – Total Harmonic Distortion

BBD – Bucket Brigade Device

FOM – Figure of Merit

FOMs – Figure of Merit by Schreier

DDR – Double Data Rate

LVDS – Low Voltage Differential Signaling

I/O – Input Output (pad)

USB – Universal Serial Bus

FFT – Fast Fourier Transform

Chapter 1: Introduction 1

1. Introduction

1.1. Motivation

Pipeline analog-to-digital converters (ADCs) are traditionally used where a

moderate-to-high resolution (8-14 bits) is required with a high sampling rate (50-500

MS/s). Lately, this architecture has been losing its edge, mainly because of its power

inefficiency, and engineers are searching for alternative ADC architectures to achieve the

same level of performance at lower power levels. This work explores the source of the

inefficiencies and will present a new solution – the pulse-based bucket brigade amplifier,

which has the potential to position the pipeline ADC in line with the most efficient

published ADCs (such as time interleaved SAR ADCs).

1.2. Background

The world of computing is changing and mobile devices such as smartphones and

tablets are beginning to replace traditional desktops and laptops for many day-to-day

tasks. The size and weight of batteries make the power efficiency of its internal

components a crucial requirement for mobile devices. At the same time, the demand for

high bandwidth connectivity presents a challenge for the data transceiver design, where a

high bandwidth, high resolution ADC is required. The specifications for the ADC in a

mobile device can be derived from current and future standards (LTE, and LTE advanced

‎[1], ‎[2]) and are presented in Table ‎1.1.


LTE LTE-Advanced

User Device Sampling frequency: 100 MS/S

Resolution: 10 bit

Sampling frequency: 200-250 MS/S

Resolution: 10-11 bit

Base-Station Sampling frequency: 250 MS/S

Resolution: 12 bit

Sampling frequency: 500 MS/S

Resolution: 14 bit

Table ‎1.1: ADC requirements for LTE and LTE-Advanced for the user device and base-

station

To find the most suitable architecture for this set of specifications, an ADC

survey ‎[3] is used. This data set contains all ADCs that were published between 1997 and

2013 at the ISSCC and VLSI Circuit Symposium. Figure ‎1.1 shows the ADC bandwidth

(BW) as a function of the signal-to-noise and distortion ratio (SNDR) with the target

specification range highlighted. It is clear that the pipeline ADC is the most popular

architecture in this range.

Figure ‎1.1: ADC survey ‎[3] bandwidth vs. SNDR

SNDR and bandwidth performance provide only part of the picture; Figure ‎1.1

omits the power efficiency parameter. Figure ‎1.2 shows the same ADC survey data, but

20 30 40 50 60 70 80 90 100 11010

4

106

108

1010

SNDR [dB]

BW

[H

z]

Flash

Pipeline

SAR

Other

1psrms

Jitter

0.1psrms

Jitter


plots the energy per Nyquist sample (P/fS, which represents power efficiency of the ADC)

against the SNDR. From this figure, we can see that pipeline ADCs do not shine in terms

of energy efficiency.

Figure ‎1.2: ADC survey, energy per Nyquist sample vs. SNDR

1.3. Pipeline ADC Inefficiencies

Fundamentally, pipeline ADCs, tradeoff latency for resolution and (to a lesser

extent) speed of operation. Figure ‎1.3 shows the basic structure of a pipeline ADC ‎[4].

Each stage of the ADC operates in two clock phases. In the first phase, part of the data is

extracted using the sub-ADC. In the next phase, the sub-ADC output is converted back to

an analog representation using a digital-to-analog converter (DAC) and subtracted from

the analog input to generate the residue signal. The operational amplifier amplifies the

residue to the same full-scale signal swing as the original input, which is then passed to

the following stage to perform the same operations.

20 30 40 50 60 70 80 90 100 110

10-12

10-10

10-8

10-6

SNDR [dB]

P/f

s [J]

Flash

Pipeline

SAR

Other

FOMS=170dB

FOMW

=10fJ/conv-step


+

SUB

ADCDAC

-

D1

Vres1Vin1

Stage

1

Stage

n-1

Stage

nS&H

Vin

Align & Combine Bits

Dout

G1

Stage

2

Stage

3

Stage

4

Figure ‎1.3: Basic structure of a pipeline ADC

A popular implementation of this architecture is done using a switched-capacitor

circuit ‎[4]. Figure ‎1.4 shows a single ended representation of the standard switched-

capacitor pipeline ADC stage. There are two inefficiencies in the depicted architecture

that add to the energy per Nyquist sample.

CS

CF

VD

AC

VIN

VOUT

Flash

ADCDAC

DOUT

Φ1

Φ1Φ2

Figure ‎1.4: Switched-capacitor pipeline ADC stage


The first inefficiency arises from the handling of the charge in the switched

capacitor stage. That charge is used in each stage, and then thrown away instead of being

reused as a source of charge for the following stage. To better explain this, Figure ‎1.5

shows the two phase operation of a standard switched-capacitor circuit. In the first phase

the charge is sampled on capacitor CS, and in the second phase it is redistributed on to CF.

When the sampling capacitor of the next stage is charged, a new charge packet is taken

from the power supply, while the charge that was used in the current stage is thrown

away.

CS

CF

Qin

CS

CF

Qin

Phase 1

Phase 2

CL

CLΦ1

Φ1

Φ1

Φ2 Φ2

Φ2

Φ1

Φ1

Φ1

Φ2 Φ2

Φ2

Φ1

Φ2

Figure ‎1.5: Two phase of operation of a standard switched-capacitor stage

The second inefficiency arises from the implementation of the amplifier. To

achieve fast operation, a class-A topology is typically used. Class-A topology require an


always-on bias current that is only occasionally used to charge the output capacitor ‎[5].

To see this, Figure ‎1.6 shows typical output voltage and current waveforms when the

amplifier is used to charge the output load. In the first phase, when the input is sampled

on the sampling capacitor, the amplifier does not perform any function, but still takes

current from the power supply. This can be solved at the architecture level as will be

discussed shortly. However, in the second phase, when the amplifier is driving the output

capacitor, only a very small portion of the charge taken from the power supply is used to

charge the load. Since the current is the derivative of the output voltage signal, only in the

first part of the phase most of the charge goes to the load. Toward the end of the phase,

when the amplifier performs the precise settling, almost none of the current is going to

the load.

Figure ‎1.6: (a) Class-A amplifier (b) Current directed to the load capacitor as a

function of the time.

The goal of this research is to implement a new approach for the gain function in

an efficient way, such that the charge that is used to drive the output load will be reused

from the charge on the input capacitor with minimal wasted charge.

G

Time

Isupply

Iout

[Amplify]

“Wasted”

charge

[Sample]

Class-A Switched-Capacitor Stage

“Wasted”

charge

Current

(a) (b)


1.4. Power Reduction Strategies

1.4.1 Architecture Level

Several inefficiencies can be addressed at the architecture level. As discussed

above, the amplifier consumes power when the stage is sampling the input signal without

performing any useful function. This can be fixed by either powering down the amplifier

in this phase ‎[6], ‎[7] or by sharing the amplifier between two consecutive stages ‎[8]. Both

approaches have some impact on the speed of operation. In the first approach, the

amplifier needs time to start up. In the second, the amplifier needs to be reset to ensure

that no memory effects are introduced.

Next the overall power of the ADC can be reduced by scaling down the

capacitors ‎[9]. This is effective because capacitor size is dictated by thermal noise limits

and the thermal noise requirement is most stringent in the first stage and is relaxed in

later stages. Capacitor scaling allows for optimizing the amplifier for each stage to save

power. This technique is used in most pipeline ADCs, as well as in this research.

1.4.2 Using Digital Circuitry for Power Reduction

Digital circuitry can be used to calibrate and correct analog circuitry, thus

improving performance. In the same way, for a given performance level, digital circuitry

can help to reduce the power of analog circuits by designing them with lower accuracy

and lower power consumption and compensating for these deficiencies in the digital

domain. In pipeline ADCs, there are two levels of calibration methods to correct

amplifier errors. The first corrects the linear closed-loop gain error of the amplifier, as

presented in ‎[10]. This method is particularly useful in that it allows sizing the capacitor


according to the thermal noise specification and not by the matching requirement. This

leads to smaller capacitors and reduces the amplifier power.

The second calibration method, corrects the nonlinearities in addition to the first

order gain error ‎[11], ‎[12], ‎[13]. In ‎[11] the introduction of background calibration for the

nonlinearities of the amplifier allowed the replacement of the traditional closed-loop

topology, which requires a high gain, high bandwidth amplifier, with an open-loop

amplifier that achieves the same overall performance at much lower power. With an

understanding of these calibration capabilities, new amplification methods can be

explored to achieve breakthrough performance.

1.4.3 Amplifier Level

The next step to reduce the power even further was achieved with the same open-

loop amplifier but using incomplete settling ‎[14]. Incomplete settling allows for operation

at a lower bias current, which saves power, while the same calibration engine accounts

for the additional errors introduced by incomplete settling.

Alternatively, the traditional class-A amplifier can be replaced with a class-AB

amplifier. This idea was explored in ‎[15] and it showed high power efficiency, however

the settling behavior of the class-AB amplifier limited the sampling frequency to 30

MHz.

1.4.4 The Quest for a Virtual Ground

The main function of the amplifier in a traditional switched-capacitor circuit is to

provide a virtual ground at the negative input node of the amplifier; this allows charge-


redistribution from the sampling capacitor to the feedback capacitor while enforcing a

known voltage at this node. Any attempt to replace the amplifier in charge-redistribution

configuration with a new circuit will need to perform this functionality. One approach is

to replace the amplifier with a comparator ‎[16], ‎[17]. This circuit is known as a zero

crossing based switched-capacitor circuit and is shown in Figure ‎1.7. A comparator that

control an output current source achieves virtual ground (to first order) because once VX

reaches VCM, IX is turns off by the comparator and the charge on the output capacitor CL

stabilizes.

Figure ‎1.7: Zero crossing based switched-capacitor circuit ‎[17]

The main advantage of this approach is its efficiency. Current is only taken from

the power supply to charge the load capacitor and is turned off when the charging is

complete. The main limitation lies in its implementation, since it suffers from errors

introduced by the comparator delay. From the time it take the comparator to sense that VX

equals VCM to the time it turns off the current source, excess charge is deposited on CL.

Published results showed that the performance of this architecture is limited by either its

resolution ‎[16] or by its sampling frequency ‎[17].

The second approach uses the threshold voltage of the CMOS transistor VT to

achieve a virtual ground. First attempt to use this idea ‎[18], ‎[19] is shown in Figure ‎1.8.


In the sampling phase the source, drain and bulk shorted together, and the input signal is

sampled on to the transistor’s intrinsic capacitances. The total capacitance of this

sampling configuration is CGS+CGD+CGB. In the amplification phase, the drain is

connected to VDD and the source is connected to the load capacitance. The transistor will

transfer charge as long as the voltage on the gate-source is higher than VT . When the

gate-source voltage is equal to VT the charge transfer will stop. The signal component is

transferred to capacitor CGD and amplified by (CGS+CGD+CGB)/CGD. This configuration is

very efficient; however, it is limited by the nonlinearity of the MOS capacitor. Since the

signal is directly sampled on the transistor’s‎ intrinsic‎ capacitors,‎ which‎ are inherently

nonlinear, it is not compatible with calibration method such as ‎[20] that assume that the

sampling operation is linear and the nonlinearity is only introduced by the amplifier. To

achieve higher resolution and to allow for nonlinear calibration, a new approach is

needed.

Vbias

Vin

Cload

Vout

VDD

Gate

Floating

Sample Amplify

Figure ‎1.8: Dynamic Source follower amplifier ‎[18]

1.5. Inspiration

The new idea that is explored in this thesis is based on a very old one: the bucket

brigade device. This circuit was first proposed in 1969 ‎[21] and was used to implement

an analog delay line. This circuit, as shown in Figure ‎1.9, moves charge from one


capacitor to the next using a single device. This circuit was used for several years and

was replaced by CCD first and by digital processing later. A very similar idea was later

used to achieve voltage gain by scaling down the capacitors. The resulting circuit was

used as a sense amplifier ‎[22] and as a comparator pre-amp ‎[23]. Recently, a similar idea

has been used to implement a pipeline ADC ‎[24]. However, as shown in Figure ‎1.10, this

implementation still used an amplifier, which limits its power efficiency. Enabling this

technology for high speed ADCs without the use of amplifiers is the key idea in this

research. Its implementation will enable a highly efficient, high performance pipeline

ADC.

Figure ‎1.9: The bucket brigade device ‎[21]


Figure ‎1.10: Bucket brigade for pipeline ADC using boosting amplifier ‎[24]

1.6. Organization

The remainder of this thesis is structured as follows. Chapter 2 explains the basic

operation of a bucket brigade device and introduces the pulse-based bucket brigade

amplifier. Chapter 3 includes a detailed analysis of the bucket brigade amplifier. Chapter

4 discusses the implications of using this circuit in a pipeline ADC stage. Chapter 5

describes the ADC top-level configuration, including the various stage configurations

that were used in this prototype. Chapter 6 summarizes the measured results of the 65-nm

prototype IC and, finally, Chapter 7 summarizes this work.

Chapter 2: Bucket Brigade Circuitry Basics 13

2. Bucket Brigade Circuit

Basics

2.1. Basic Operation

Figure ‎2.1 shows the basic operation of the bucket brigade circuit with sampling

capacitor CS and load capacitor CL (VH, VL, VP and VG are bias voltages whose values will

be discussed later). Figure ‎2.2 shows the associated wave shapes of the signal during the

two phases of operation.

Φ1

Φ2

CSVIN Vout

VH

VL

VSVXCL

VHVP

VG

CSVIN Vout

VH

VL

VSVXCL

VHVP

VG

Phase 1 Phase 2

Φ1

Φ1

Φ1

Φ1 Φ2

Φ2

Figure ‎2.1: Bucket brigade amplifier operation


1.2

1.0

0.2

0.4

0.6

0.8

Phase 1 Phase 2

0

Vs

VL

VP

VH

Vout

Vout

Vx

Vx

VsVG

Figure ‎2.2: Bucket brigade circuit basic operation - wave shapes

In phase 1, the input signal is sampled on CS relative to VH and the output

capacitor CL is precharged to the voltage VP. Note here, that VH and VP are required to be

higher than VG–VT, and therefore the transistor is in the ‘off’‎ state‎ and‎ no‎ current‎ is‎

flowing through the transistor. Since the signal in this circuit is represented by charge, the

precharge operation is important to maintain the correct voltages in the circuit while the

charge signal is redistributed. In phase 2, as the top plate of CS is connected to VL, VS is

pulled down to a voltage that is lower than VG–VT. At the same time, as the bottom plate

of CL is connected to VH and the voltage Vout is pulled up. Now, since the voltage on the

source of the transistor is lower than VG–VT, and the source voltage is lower than the drain

voltage, charge will be transferred from CS to CL. The charge transfer will continue as

long as VS is lower than VG–VT. When VS=VG–VT (and, for the time being, ignoring sub-

threshold currents) the charge-redistribution will stop. When this occurs, the voltage on

CS is equal to VG–VT–VL and is independent of the input signal (to first order) and


therefore, the signal component of the charge was distributed into CL. If CL is smaller

than CS a voltage gain AV is achieved.

L

SV

C

CA (‎2-1)

2.2. Bucket Brigade Circuit with Amplifier in

Boosting Configuration

Because of sub-threshold current, charge-redistribution does not stop when

VS=VG–VT. Therefore, at the end of phase 2, the voltage on CS will have a component of

the input signal, which will cause gain reduction and introduce distortion. To address this

limitation, a boosting amplifier can be added to achieve accurate settling ‎[25], ‎[24]. As

shown in Figure ‎2.3, the virtual ground of the amplifier at the negative input node

enforces VS=V0 at the end of the charge-redistribution phase.

CSVin

CL

Vout

VL VH

VS

V0

VG

VH

Figure ‎2.3: Bucket brigade circuit with ampifier in boosting configuration

The operation of this circuit is similar to the standard bucket brigade circuit. The

difference is that the gate of the transistor is dynamically controlled by the amplifier.

Figure ‎2.4 shows simulated voltage waveforms of VG and VS in the charge-redistribution


phase. The bias voltages VH and VL are the same as in section ‎2.1. When the source

voltage of the transistor (and the negative input node of the amplifier) is pulled down, the

input voltage of the amplifier become positive and the amplifier output (and the gate

voltage of the transistor) starts to rise at a rate that is set by the bandwidth of the

amplifier. This sets the condition for charge transfer from capacitor CS to capacitor CL

and causes the voltage on the source of the transistor to go up, and accordingly causes the

gate voltage to go down until the source voltage settle to V0.

Figure ‎2.4: Source voltage and gate voltage of bucket brigade circuit with an amplifier in

boosting configuration

2.3. Pulse-Based Bucket Brigade Amplifier

Using an amplifier to achieve accurate settling can provide a solution for the

settling problem, but it has reduced the efficiency of the ADC. Even though this

configuration is more efficient than the standard switched-capacitor stage, the amplifier is

still the limiting factor. To circumvent this shortcoming I introduce the pulse-based

bucket brigade amplifier topology. This topology removes the boosting amplifier, and

0 0.5 1 1.5

0

0.2

0.4

0.6

0.8

1

[V]

Time [ns]

Vs

Vg


instead uses a pulse that mimics the behavior of the amplifier output voltage, to drives the

transistor gate. Digital calibration is used to handle gain error and distortion.

2.3.1 Pulse Wave Shape

The wave-shape of the gate pulse defines the current waveform that passes

through the transistor. Figure ‎2.5 shows the gate and source voltage waveforms and the

associated source current for the bucket brigade with boosting amplifier, the standard

bucket brigade, and the pulse-based bucket brigade topologies. For the bucket brigade

with boosting amplifier (a), the source voltage settles while the current wave shape is

maintained at a low level. The standard bucket brigade (b) generates a very large current

spike through the transistor. This current must be supplied by a voltage source that has

high current, high bandwidth and low input resistance. Implementing such a voltage

source may not be feasible or will consume high power. Finally, an RC-shaped pulse-

based bucket brigade is shown in (c). In this case the current wave shape is similar to the

bucket brigade with boosting amplifier configuration.


ISVS

VS

VS

VG

VG

VG

IS

IS

(a)

(b)

(c)

31 32 33 34-5

0

5

10

15

time [ns]

Is [

mA

]

31 32 33 34

0.2

0.4

0.6

time [ns]

Am

pli

tud

e [

V]

31 32 33 34-5

0

5

10

15

time [ns]

Is [

mA

]

31 32 33 34

0.2

0.4

0.6

time [ns]

Am

pli

tud

e [

V]

31 32 33 34-5

0

5

10

15

time [ns]Is

[m

A]

31 32 33 34

0.2

0.4

0.6

time [ns]

Am

pli

tud

e [

V]

Figure ‎2.5: Gate voltage, source voltage and source current for closed-loop,

constant gate, and RC shaped pulse-based bucket brigade circuit. Left column:

circuit topology, middle column: gate voltage and source voltage (dotted), right

column: source current

2.3.2 Pulse-Based Bucket Brigade vs. Boosted Amplifier Configuration

Figure ‎2.6 shows the transistor gate and source for both the RC-shaped pulse-

based bucket brigade and the bucket brigade with boosting amplifier. As shown in the

figure, in the first part where the ‘gate‎voltage boost’‎ takes place, both configurations

track the same voltage level. After‎the‎initial‎‘gate‎voltage‎boost’, the waveforms diverge

as the feedback amplifier precisely controls the settling by lowering VG and the pulse-

based configuration continues with its open loop pulse. As shown by the current

waveform in Figure ‎2.5, most of the charge is transferred during the initial period when

the boosted amplifier and the pulse-based waveforms are identical. Since the speed of the


initial transient voltage is the same for both cases it allows the pulse-based bucket brigade

to achieve nearly identical operation speed, but will require calibration for the gain error

and distortion it introduced.

Figure ‎2.6: Pulse-based bucket brigade amplifier vs. bucket brigade with boosted

amplifier

2.3.3 Pulse-Based Bucket Brigade Amplifier Linearity

The pulse-based bucket brigade amplifier does not settle. Therefore, the final

value of the charge on the sampling capacitor at the end of the charge-redistribution

phase has a component of the input signal remaining. Thus, the gain of the circuit is

signal dependent, which introduces distortion. The calibration scheme detailed in ‎[11],

‎[12], ‎[13] can be used to fix the distortion in the circuit on the condition that the

nonlinearity is limited to the first three harmonics. To verify that this condition is met, the

RC-shaped pulse-based bucket brigade amplifier was simulated with sampling frequency

of 200 MHz and the power spectral density shown in Figure ‎2.7. As seen here, the circuit

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0

0.2

0.4

0.6

0.8

1

[V]

Time [ns]

Vs for Pulse-Based

Bucket Brigade

Amplifier

Vs for boosted amplifier

Vg for boosted amplifer

Vg for pulse-based

bucket brigade amplfier


is limited by the third harmonic, which is 51.3 dB below the fundamental. The linearity

requirement is set by the backend resolution, which means that by itself this circuit

cannot achieve the performance target outlined in Section ‎1.2, which was an SNDR in the

range of 60-70 dB. However, the fifth harmonic is 76.3 dB below the fundamental, which

meets the spec target. Thus, the calibration techniques in ‎[11], ‎[12], ‎[13] which can

correct the third harmonic, can bring the linearity level of the circuit to that of the fifth

harmonic, allowing the RC-shaped pulse-based bucket brigade amplifier to achieve the

performance target for this project.

Figure ‎2.7: Linearity simulation of the pulse-based bucket brigade amplifier (256-point

FFT)

0 20 40 60 80 100-150

-100

-50

0

Ma

gn

itu

de [

dB

]

fin

[MHz]

Linearity requirement

51.3 dB 76.3 dB


2.4. Summary

This chapter has presented the basic operation of the bucket brigade circuit and

showed its accuracy limitations due to incomplete settling. Introducing a boosting

amplifier was presented as a way to solve to the accuracy problem. However, the addition

of this amplifier reduces the power efficiency of the circuit. Furthermore, the boosting

amplifier provides current wave shapes that reduce the specifications of the voltage

reference generator. The pulse-based bucket brigade circuit with nonlinear calibration

was proposed to achieve the benefits of the boosting amplifier without reducing the

efficiency of the circuit. This circuit achieves very similar current wave shape and meets

the linearity requirements for 3rd

order digital linearization. Simulation results of this

circuit were presented to confirm this approach.

Chapter 3: The Bucket Brigade Amplifier 22

3. The Bucket Brigade

Amplifier

The basic concept of the bucket amplifier was explained in the Chapter 2. In this

chapter, we will analyze its behavior, generate a large signal model, investigate the effect

of various charge and voltage input signals, determine the requisite bias voltages and

analyze‎the‎circuit’s‎thermal‎noise.

3.1. Large Signal Analyses

We begin our large signal analysis by establishing the relation between Vin, VS,

VG and Vout as depicted in Figure ‎3.1.

CSVIN Vout

VH

VL

VSVXCL

VHVP

VGΦ1

Φ1

Φ1

Φ1

Figure ‎3.1: Bucket brigade circuit

Using a first order approximation and the principle of charge conservation, we

obtain:


HoutLGSgsLSS

HoutLGSgsLSS

VtVCtVtVCVtVC

VVCVVCVVC

0000 (‎3-1)

Solving (‎3-1), for the output voltage as a function of time yields:

000 GG

L

gs

SS

L

Sgs

outout VtVC

CVtV

C

CCVtV

(‎3-2)

Using the initial conditions:

HPout VVV 0

(‎3-3)

inL

Sgs

SHS VV

CC

CVV

0 (‎3-4)

Vout(t) can then be written as:

0GG

L

gs

HS

L

Sgs

inL

L

SHPout VtV

C

CVtV

C

CCVV

C

CVVtV

(‎3-5)

Eq. (‎3-5) shows that Vout(t) depends on both VS(t) and VG(t). We will solve this

expression for two cases – constant VG(t) and RC-shaped Pulse-based VG(t).

3.1.1 Constant VG

From Figure ‎3.1 it is apparent that the current through CL (the transistor drain

current) is equal to the total current through CS and Cgs

dt

VVdC

dt

VVdCtI

gS

gsLS

Sd

(‎3-6)


For most of the settling time VG is near VG–VT, which means that the transistor is in the

sub-threshold region. It is therefore reasonable to model the transistor drain current as:

tV

nkT

q

Sd

ov

eItI (‎3-7)

where

TSGOV VtVVtV (‎3-8)

After combining (‎3-6) and (‎3-7) we have

dt

VtVdC

dt

VtVdCeI

gs

gsLs

S

tVnkT

q

S

ov

(‎3-9)

Eq. (‎3-9) can be solved for VS(t)

0

lnovV

nkT

q

gsS

STgS et

CC

I

nkT

q

q

nkTVVtV (‎3-10)

Using (‎3-10) and substituting:

nkT

qIg S

m (‎3-11)

and

gs

S

gs

mT

CnkT

qI

C

g 1 (‎3-12)

yields:

0

lnovV

nkT

q

gsS

gs

TTgS etCC

C

q

nkTVVtV (‎3-13)


This equation gives good insight into the settling behavior of this circuit. Note

that the settling time is limited by ωT of the transistor and by the ratio of the sampling

capacitor and the gate-source capacitor.

Figure ‎3.2 shows the relation given in Eq. (‎3-13) plotted with SPICE simulation

results. We observe good agreement between the two. The parameters that were used for

the model are listed in Table ‎3.1 and are taken from the SPICE model.

Figure ‎3.2: Source voltage comparison of constant Vg circuit, model vs. SPICE simulation

Parameter Description Value

VG Gate Voltage 0.69 V

VH Bias voltage 0.8 V

VL Bias voltage 0.2 V

VP Bias voltage 0.4 V

CS Sampling capacitor 8 pF

CGS Gate-source capacitor 60 fF

CL Load capacitor 1.75 pF

ft Transit frequency 256 GHz

w Transistor width 174.72 µm

l Transistor length 60 nm

Table ‎3.1: Model parameters

0 2 4 6 8 100.15

0.2

0.25

0.3

0.35

0.4

0.45

time [ns]

[V]

model

Simulation


3.1.2 Gain Function

Calculating the gain (dVout/dVin) using equations (‎3-13) we obtain:

distortion andn degradatioGain

0

gainIdeal

inSGS

S

inSGS

S

VCC

C

nkT

q

GSS

GST

VCC

C

nkT

q

L

SGS

L

S

in

out

etCC

CK

e

C

CC

C

C

dV

dVGain

(‎3-14)

where

L

SGS

SHTG V

CC

CVVV

nkT

q

eK0 (‎3-15)

Equation (‎3-14) give insight to the achievable gain of this circuit. The first term

provides the ideal gain if all the charge is transferred from CS to CL, and the second term

accounts for gain degradation and distortion. As an example, consider using equation (‎3-

14) to calculate the gain of this circuit using the parameters in Table ‎3.1. The ideal gain is

4.57 however the gain degradation reduce this to only 3.1, which matches the simulation

value.

3.1.3 RC-shaped Vg

In this case, VG is represented by Eq. (‎3-16), where VG0 is VG final value, and τ is

the time constant.

t

GG eVV 10 (‎3-16)

Using (‎3-9), (‎3-16) we get:


t

gsS

SG

OVtV

nkT

q

gsS

S eCC

CV

dt

tdVe

CC

I ov

10 (‎3-17)

where

TSGOV VtVtVtV (‎3-18)

(‎3-17) and (‎3-18) can be solved for VS(t) to obtain:

(‎3-19)

t

gsS

SGi

gsS

ST

t

gsS

gs

gS eCC

CV

nkT

qE

nkT

q

CC

IK

q

nkTVe

CC

CVtV 010 log1

In this result, Ei is the exponential integral function and defined as:

x

t

i dtt

exE (‎3-20)

and K1 is equal to:

gsS

SGi

gsS

SnkT

q

CC

CVVV

CC

CV

nkT

qE

nkT

q

CC

IeK gsS

SGTS

01

0

(‎3-21)

Figure ‎3.3 plots the model given by (‎3-19) and (‎3-21) (with parameters taken

from Table ‎3.1) against SPICE simulation results. Once again, we observe good

agreement between the two.


Figure ‎3.3: Source voltage comparison on pulse-based RC-shaped Vg circuit, model vs.

simulations

Using (‎3-4), (‎3-5), (‎3-19), (‎3-21), and the parameters in Table ‎3.1, the linearity of

the circuit can be predicted by running Matlab analysis with a sinusoidal input signal.

The output spectral density is shown in Figure ‎3.4. As seen in this figure, the third

harmonic is 41 dB below the fundamental and the fifth harmonic is 81 dB below the

fundamental. As mentioned in Section ‎2.3.3, the application of the calibration techniques

introduced in ‎[11], ‎[12], and ‎[13], the RC-shaped pulse-based bucket brigade amplifier

has the potential to achieve the performance target.

0 2 4 6 8 100.15

0.2

0.25

0.3

0.35

0.4

0.45

time [nS]

Am

pli

tud

e [V

]

Simulation

Model


Figure ‎3.4: Matlab analysis results for the RC-shape model. SFDR for 3rd

harmonic is 41

dB and SFDR for 5th

harmonic is 81 dB

3.2. Voltage Input vs. Charge Input

There are two ways to implement the proposed bucket brigade circuit. The first

method, shown in Figure ‎3.5(b), is the one we have discussed so far and will be referred

to as the ‘voltage input scheme’.‎The second is shown in Figure ‎3.5(a) and will be called

‘charge‎input‎scheme’.

0 20 40 60 80 100-350

-300

-250

-200

-150

-100

-50

0

Mag

nit

ud

e [

dB

]

Frequency [MHz]

81 dB41 dB

Linearity Requirement


CSVIN Vout

VH

VL

VSVXCL

VHVP

VG

Cs

QIN Vout

VG

VS

VP

VH VH

CL

VL

VP

CPAR1CPAR1

(a) Charge Input Scheme (b) Voltage Input Scheme

CPAR2

Figure ‎3.5: Charge input vs. voltage input bucket brigade circuit

At first glance, these two topologies may seem to have the same behavior.

However, when taking into account the parasitic capacitances at nodes VS and VX we see

differences between the two. If we assume the voltage on VS at the end of the charge-

redistribution phase to be independent of the input voltage or charge, then, the relations

that dictated output voltage (Vout) and the charge transferred to the output capacitor (Qout)

are given in Table ‎3.2.

Circuit

Input signal

representation

Voltage input scheme Charge input scheme

Input signal is a

voltage

Sinout CVQ

L

Sinout

C

CVV

1parSinout CCVQ

L

parS

inoutC

CCVV

1

Input signal is

charge

in

parS

Sout Q

CC

CQ

2

L

in

parS

Sout

C

Q

CC

CV

2

inout QQ

L

inout

C

QV

Table ‎3.2: Output voltage (Vout) and charge transferred to the output capacitor (Qout) for

voltage input scheme and charge input scheme


From Table ‎3.2 it is clear that in order to reduce the effect of parasitic, the

voltage input scheme should be used when the input signal is represented by voltage, and

the charge input scheme should be used when the input signal is represented by charge.

Therefore, for the first stage of the ADC where the input signal is represented by voltage,

the voltage input scheme is used. Since the output of a bucket brigade stage is a signal

represented by charge (including the first stage), all the subsequent stages use the charge

input scheme.

3.2.1 Charge Input Scheme Overview

So far, only the voltage input scheme was explained and analyzed. Since there

are several differences between the voltage input scheme and the charge input scheme, a

discussion on this scheme is required and will be done here. Since the input signal is in

the charge domain, the input and output capacitors need to be precharged to have defined

voltages in the circuit. Therefore, an additional clock phase is needed to precharge the

capacitors. In phase one, as shown in Figure ‎3.6, both capacitors are precharged to VP. In

phase two, the bottom plate of CS is connected to VH and the input charge is sampled on

capacitor CS. In phase three, the bottom plate of CS is connected to VL and the bottom

plate of CL is connected to VH and the charge is redistributed from CS to CL.


Cs

QIN Vout

VG

VS

VP

VH VH

CL

VL

VP

Cs

QIN Vout

VG

VS

VP

VH VH

CL

VL

VP

Cs

QIN Vout

VG

VS

VP

VH VH

CL

VL

VP

(a) Phase 1 (b) Phase 2 (c) Phase 3

Figure ‎3.6: Charge input bucket brigade circuit - basic operation

It should be noted that in an actual pipeline ADC implementation, four phases are

used. In phase one, CS is precharged, in phase two, the input signal is sampled on CS, in

phase three, CL is precharged, and in phase four, the charge is redistributed from CS to CL.

This will be further discussed in Chapter 4.

3.2.2 Gain Expression for the Charge Input Scheme

For the charge input scheme, the input signal is not inverted and therefore the

gain is positive (unlike the voltage input scheme where the voltage gain is negative).

Referring back to the large signal analysis of Section ‎3.1 and replacing the initial

condition in Eq.(‎3-4), with:

Sgs

gs

G

Sgs

SL

gsS

inSCC

CV

CC

CV

CCQV

10 (‎3-22)

The output voltage and charge are recalculated as:


tVC

CtV

C

CCV

C

C

C

QVVtV G

L

gs

S

L

Sgs

L

L

S

L

inHPout

(‎3-23)

tVCtVCCVCQVVCtQ GgsSSgsLSinHPLout (‎3-24)

The solutions for VS in the cases of constant VG and RC-shaped VG as derived in

Sections ‎3.1.1 and ‎3.1.3, Eq. (‎3-23), (‎3-24) can be used to extract the output voltage,

output charge, and gain function with charge input signal schemes.

3.3. Bias Voltages Value

The values of the bias voltages VH, VL, VP and Vg are set to meet the requirements

for charge-redistribution as listed in Table ‎3.3.

Requirement Time Explanation

1. Vg-VS > VT At the start of phase

two

To enable charge-redistribution through the

transistor

2. Vout > VS During phase two To enable charge-redistribution through the

transistor

3. VH+VP < VMAX To meet maximum allowed voltage in the

process

Table ‎3.3: Bias voltage requirements

Figure ‎3.7 shows the voltage allocation for the circuit. At the start of the charge-

redistribution phase, the full range of the voltage signal can appear on VS. Also, at the end

of the phase, the full range of the signal can appear on Vout. Therefore, enough headroom

must be allocated to the associated bias voltage for the transistor to stay in saturation

given the signal swing on both nodes. In this work, the signal swing is set to 0.4 V (0.8 V


differential peak-to-peak). Given a 1 V power supply this allocates 0.2 V for the

transistor.

VH

VL

Vout

VS

Vdd=1.0

Vss

Vout

VS

0.4

0.4

0.2VG

CL

CS

Figure ‎3.7: Voltage allocation for bucket brigade circuit

For the circuit depicted in Figure ‎3.8, if we assume that the input common level

is the same as VH, then the signal is sampled on CS without common mode. Therefore, at

the start of phase two, when the top plate of the capacitor is set to VL, the quiescent point

of the signal at VS will be equal to VL. This helps to set the bias voltages to the following

levels:

VH is the quiescent point voltage for Vin and Vout and will be equal to 0.8V

VL is the quiescent point voltage for VS in the start of phase two and will be equal

to 0.2 V

VP is defined by the max allowed voltage (VH+VP=VMAX) and for VMAX of 1.2 V

VP will be equal to 0.4 V


Φ1

Φ2

CSVIN Vout

VH

VL

VSVXCL

VHVP

VG

CSVIN Vout

VH

VL

VSVXCL

VHVP

VG

Phase one Phase two

Φ1

Φ1

Φ1

Φ1 Φ2

Φ2

Figure ‎3.8: Bucket brigade amplifier operation

VG is the last bias voltage that needs to be defined and it is set to meet the

common mode requirement at the end of phase two, the quiescent point at Vout is equal to

VH. Assuming charge conservation, Eq. (‎3-25) shows the relation between the different

bias voltages.

V

Vout

L

S

V

VS

VV

SPHinin

tG

TVC

CVTVVV

8.02.0

0

max V 1.2Limited Technolgy

0

202

(‎3-25)

For a zero input signal, at the beginning of the charge-redistribution phase, the voltage on

the source of the transistor will be:

LVS VTVin

0

2 (‎3-26)

At the end of the charge-redistribution phase, the source voltage will then approach:

tGS VVTV (‎3-27)


Since we want to achieve a quiescent point voltage of VH at the output at the end of the

charge-redistribution phase, we will require:

HVout VTVin

0

(‎3-28)

Applying (‎3-26), (‎3-27), and (‎3-28) to Eq. (‎3-25), we obtain:

tL

S

LPG VV

C

CVV (‎3-29)

For example, with CL/CS=0.25 (i.e., stage gain of 4), VG is equal to 0.65V.

In general, there are multiple solutions to the problem of how to set the bias

voltages without assuming the input common mode is equal to VH. Using:

LcomHS VVVV 0 (‎3-30)

Eq. (‎3-29) can be rewritten in general form as:

Lt

S

LP

S

LcomHG VV

C

CV

C

CVVV

2 (‎3-31)

However, when trying to maximize the signal swing, Eq. (‎3-29) provides good solution.

3.4. Thermal Noise

There are two sources of thermal noise in the bucket brigade amplifier. The first

relates to the kT/C noise on the sampling and load capacitors due to pre-charging. The

second is the noise added by the transistor during the charge-redistribution phase. The

noise is analyzed under the assumptions of differential implementations where two copies


of the circuit in Figure ‎3.8 are used one for the positive side of the circuit and one for the

negative side.

3.4.1 Thermal Noise due to Sampling on CS

The thermal noise, referred to input due to sampling the input signal into CS is:

S

nC

kTV 22

1 (‎3-32)

where the factor of two is due to the differential implementation of the circuit.

3.4.2 Thermal Noise due to Pre-charge of the Load Capacitor CL

The thermal noise, referred to input due to precharge of the load capacitor CL is

2

2

2

12

VL

nAC

kTV (‎3-33)

where the factor of two is due to the differential implementation of the circuit and AV is

the voltage gain.

3.4.3 Thermal Noise from Charge Redistribution Phase

The thermal noise, referred to input due to charge-redistribution from CS to CL is

calculated using the small signal model:


in rogm

CS

CL

Vout

VS

Figure ‎3.9: Small signal model for noise calculations

Using nodal analysis, we find:

SS

o

SoutSmn CjV

r

VVVgi

(‎3-34)

and,

L

SSout

C

CVV (‎3-35)

Solving (‎3-34) and (‎3-35), the thermal noise referred to the input is:

SomL

Lom

S

nCrgC

Crg

C

kTV

122

3 (‎3-36)

where the factor of two is due to the differential implementation of the circuit and γ is the

thermal noise coefficient for MOS transistors, gm is the transconductance of the transistor

and ro is the output resistance of the transistor.


3.5. Summary

This chapter presented a mathematical analysis for the bucket brigade circuit. As

a first step, we analyzed the standard bucket brigade circuit to derive the settling wave

shape and to calculate the achievable gain. Next, we showed the settling behavior of the

pulse-based bucket brigade circuit and used this analysis to predict its linearity using

Matlab simulations. Then we discriminated between a bucket brigade circuit with voltage

input signal and one with a charge domain input signal. We explained how to choose the

values for the various bias voltages, and finally, an analysis for the thermal noise of the

bucket brigade amplifier was provided.

Chapter 4: ADC Stage Design 40

4. ADC Stage Design

The focus of Chapter 3 was to study the behavior of the pulse-based bucket

brigade circuit as an amplifier. In this chapter, we will discuss how this circuit can be

augmented to create a complete pipeline ADC stage. Specifically we will discuss the

amplifier’s‎operation‎in‎a‎differential‎configuration,‎implementing‎the‎sub-DAC and sub-

ADC, and clock timing within the stage.

4.1. Differential Implementation

The bucket brigade circuit requires well-defined bias voltages for proper charge-

redistribution to occur. As shown in Figure ‎4.1, in the sampling phase the bottom plate of

the sampling capacitor needs to be connected to the bias voltage VH and in the charge-

redistribution phase the top plate of the sampling capacitor needs to be connected to the

bias voltage VL. Building a pseudo differential circuit ‎[26] with two copies of this circuit

has a common mode problem since the common mode is amplified together with the

differential mode. This is impractical, since any input common variations are amplified

from stage to stage and will drive the last few stages away from their proper operating

point.


CSVIN Vout

VH

VL

VSVXCL

VHVP

VG

CSVIN Vout

VH

VL

VSVXCL

VHVP

VG

Sampling Charge-

redistribution

Figure ‎4.1: Bucket brigade topology in the sampling and charge-redistribution phases

To mitigate this problem, a common mode rejection strategy that is commonly

used in the context of operational amplifier based circuits is applied ‎[27], ‎[28]. As shown

in Figure ‎4.2, the sampling capacitor is divided into two capacitors. In the sampling

phase, the input is sampled onto the parallel connection of the two capacitors. During

charge redistribution, one of the two capacitors is connected to the reference voltage VL,

and the second one is tied to the same point in the other half circuit. In a case of a 1-bit

stage with a gain of two, the capacitor is divided into two equal units. In this case, half of

the common mode signal is amplified and the other half is rejected. Therefore, the overall

common mode gain is unity. For a 2-bit stage with a gain of four, the sampling capacitor

is divided into two capacitors with ¼ and ¾ of the original capacitance. The quarter

capacitor is connected to the voltage reference and the three-quarter capacitor is

connected to the other half circuit. This technique redistributes some of the common

mode along with the differential mode, but does not amplify it. Choosing a capacitor ratio

that allows common mode gain of less than one, increases the sensitivity to parasitic

capacitances on node VL. This may cause the voltage to change and to lose the conditions

for proper charge-redistribution and is therefore avoided. This technique enables the


implementation of a high-resolution pipeline ADC using pseudo-differential bucket

brigade circuits without common mode errors that are amplified from stage to stage.

CS/2VINP Voutp

VH

VS

VG

VL

VINN Voutn

VH

VS

VG

VL

CS/2

CS/2

CS/2

CS/2VINP Voutp

VH

VS

VG

VL

VINN Voutn

VH

VS

VG

VL

CS/2

CS/2

CS/2

Sampling Charge-redistribution

Figure ‎4.2: Circuit scheme to prevent common mode amplification

4.2. DAC Implementation

4.2.1 DAC Linearity

Calibration techniques that linearize the stage by modulating the signal in the

DAC require that the input summing node at the input of the amplifier must be as linear

as the required stage linearity (as in Figure ‎4.3 ‎[11]).


+-

Ving

g-1

Backend

A/D

Dout

D/A

MOD

A/D

12

Vres+MOD

Dback

+

+

Figure ‎4.3: Modulation through the DAC

The DAC in a pipeline stage is typically implemented by applying voltage

references to the top plate of the sampling capacitor. However, applying the same

technique to the pulse-based bucket brigade pipeline stage, as shown in Figure ‎4.4, yields

poor results.

CSVIN Vout

VH

VDAC

VSVXCL

VHVP

VG

Figure ‎4.4: Standard DAC implementation applied to the bucket brigade stage


The circuit depicted in Figure ‎4.4 does not settle, and at the end of the charge-

redistribution phase, there is still current flowing through the DAC switch. Furthermore,

the switch resistance is different for each DAC value and the voltage drop across that

resistance introduces nonlinearity beyond the target specification. Reducing the resistance

of the switch by increasing its size or by adding clock boosting, improves the linearity but

it remains difficult to suppress the nonlinearities to the required level.

To solve this problem, a different DAC scheme is used (see Figure ‎4.5). A

dedicated DAC capacitor Cdac is added and is precharged during the sampling phase to

the voltage Vdacp-Vdacn. In the charge-redistribution phase, the capacitor is connected

between the circuit nodes VSP and VSN and the polarity of the connection is determined by

the decision of the sub-ADC.

CS/2VINP Voutp

VH

VS

VG

VL

VINN Voutn

VH

VS

VG

VL

CS/2

CS/2

CS/2

CdacVdacp Vdacn

CS/2VINP Voutp

VH

VSP

VG

VL

VINN Voutn

VH

VSN

VG

VL

CS/2

CS/2

CS/2

CdacVdacp Vdacn

Phase 1 - Sampling Phase 2 – Charge redistribution

Figure ‎4.5: DAC implementation in the pulse-based bucket brigade stage


For a multi-bit implementation, several capacitors can be used and each one of

them will be connected according to the sub-ADC decision to implement the desired

residue function.

In this circuit, the DAC charge, and the sampled charge are redistributed in a

similar fashion. The only difference between one DAC value and the other is the polarity

of the DAC capacitors connection. Using this approach, the output of the pipeline stage

was simulated using a three-level (2-bit) DAC. Figure ‎4.6 shows the transfer function of

the amplifier for the three different DAC values. Figure ‎4.7 shows the horizontal

difference between the three DAC values. Taking the horizontal difference between

modes should yield only the DAC voltage, any difference beyond that voltage

corresponds to the linearity error of the DAC. The maximum DAC nonlinearity is 11 µV,

which is about 11% of the LSB size for 12 bit resolution.

Figure ‎4.6: Simulated amplifier transfer function for different DAC values

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

-0.4 -0.2 0.0 0.2 0.4

Vou

t [V

]

Vin [V]

Mode 0

Mode 1

Mode 2


Figure ‎4.7: Horizontal difference between the residue segments

4.2.2 DAC Thermal Noise

Adding a DAC capacitor at the source of the transistor adds thermal noise to the

amplifier. The thermal noise, referred to the input is:

22

2 14

VL

dacn

AC

kTCV (‎4-1)

where Cdac is the DAC capacitor, CL is the load capacitor and AV is the voltage gain of the

stage. The charge noise kTCdac is sampled on Cdac, and subsequently transferred to CL,

and referred to the input via 1/AV2. The factor of four arises because that the capacitor

Cdac is connected between the positive side and negative side of the circuit. For each half

circuit the effective size is 2 Cdac. For the full differential mode, there is another factor of

two.

-20

-15

-10

-5

0

5

10

15

20

-0.20 -0.10 0.00 0.10 0.20

[µV

]

Vin [V]

Mode 1 - Mode 0

Mode 2 - Mode 1


4.2.3 DAC Layout Considerations

Layout implementation can have a strong impact on the DAC performance. For a

multi-bit implementation with eight DAC capacitors, as shown in Figure ‎4.8, any

parasitic capacitance will affect the amount of charge injected by the DAC.

CdacVdacnVdacp

Vsp

Vsn

X8

Figure ‎4.8: DAC circuit for a multi-bit stage with 8 capacitors

To mitigate this problem, several layout techniques are used to achieve 12-bit

performance. First, as shown in Figure ‎4.9, all the capacitors are laid out in an array with

dummies on the perimeter to achieve good matching. Second, as shown in Figure ‎4.10,

the layout of the switch transistors is optimized to reduce the parasitics between source

and drain. Also, each DAC unit element was separated by guard rings that included high

metal stack to ensure that the parasitics for all the transistors are the same.


Figure ‎4.9: DAC layout

Figure ‎4.10: Layout of the DAC switches


4.3. Sub-ADC Design

In the proposed design the voltage comparators of the sub-ADC are placed at

node VS and the reference voltages for the comparators are applied at the top plate of the

sampling capacitors. Figure ‎4.11 shows an example for a single-bit sub-ADC.

Vout

VH

VSCL

VHVP

VG

VIN VXCS

VCmp_ref

Dout

VL

Figure ‎4.11: Comparator scheme

4.3.1 Multi-bit Implementation

To enable a multi-bit implementation of the sub-ADC, where several

comparators are used, the same number of capacitors is also required. As shown in Figure

‎4.12, the additional switch S5_x was added after the transistor M1_x to divide the signal

path into several parallel channels. The sampling capacitor CS is split according to the

number of parallel channels. As shown in Figure ‎4.12, when the comparison is

performed, a different value of Vcmp_ref is applied to each channel to enable comparison

with different reference level.


Dout[1]

VH VPVH

VL Vcmp_ref1

VG

Vin

Vout

Dout[2]

VH VPVH

VL Vcmp_ref2

VG

Vout

Channel 1

Channel 2

To next channelTo next channel

To next channel To next channel

M1_1

M1_2

S1_1

S2_1 S3_1

S4_1

S5_1

S1_2

S2_2 S3_2

S4_2

S5_2

Figure ‎4.12: Multi-bit implementation for the sub-ADC

4.3.2 Comparator Implementation

Since the comparator is tied to the signal path, and since the signal is charge,

kickback charge from the comparator can distort the signal and limit the ADC

performance. Therefore, a comparator with low kickback was selected ‎[29]. As shown in

Figure ‎4.13, this comparator is different from a standard dynamic comparator in that the

clock switch on the source of the input pair is replaced with a current source and a pair of


clocked switches are added above the input pair. As a result of this change, the drain

voltages of the input transistor pair move from VSS at the beginning of the comparison to

VSS at the end of the comparison, generating very low kickback noise.

clk

clk

clk

clk

clk

clk

clkclk

Vinp Vinn

Vdd

Voutn Voutp

Vss

Figure ‎4.13: Low kickback noise comparator

The transistors are sized according to the mismatch, kickback noise and

metastability requirements (see discussion in Section ‎5.2.2).

4.4. Timing

The ADC stage operates with four main phases: precharge, sample, compare and

charge-redistribution. Figure ‎4.14 shows these four main phases. The first and third are

short phases with a nominal length of 0.5 ns. The second and fourth are longer with


nominal length of 1.6 ns (at a clock frequency of 200 MHz). The clocks are non-

overlapping with a spacing of 0.2 ns.

5 ns

Φ1

1.6 ns0.5 ns

Φ2

Φ3

Φ4

1.6 ns0.5 ns

Figure ‎4.14: Four phases of operation

Delayed phases are also required to implement bottom plate sampling ‎[30].

Figure ‎4.15 shows the topology of the first stage and Figure ‎4.16 shows the timing of the

switches. Precharge is not required for the first stage because the input signal is a voltage,

which is why the first phase is not used here. The sampling phase is timed with clocks Φ2

and Φ2d, where the input sampling switch is timed with clock Φ2d and the bottom plate

switch is timed with clock Φ2. The comparator references are timed with clock Φ3 and

the comparator is timed with phase Φ3d, which its rise-time is delayed after Φ3 to allow

the comparator references time to settle. The charge-redistribution is timed with clock

Φ4d, for the switches that connect the top plate of one of the capacitor CS/2 to voltage VL

and the second to the other half of the circuit.


CS/2

Vin Qout

VH

CS/2

VL

Vc

mp

_re

f

To the

negative

half

circuit

Φ3d

Cdac

Vdac_pre_p Vdac_pre_n

X8

Φ2 Φ2

Comparator

controlled

switch on Φ4

To the

negative

half

circuit

To the

negative half

circuit

Φ2Φ2d

Φ2d

VG(Φ4d)

Φ3

Φ3

Φ4d

Φ4d

M1

Figure ‎4.15: First stage scheme

5ns

Φ1

Φ2

Φ2d

Φ3

Φ3d

Φ4

Φ4d

Figure ‎4.16: Stage timing


4.4.1 Wave Shapes

Figure ‎4.17 shows the wave shapes for VS, VG and Vout. During the second phase,

the source is connected to VH (0.8 V), while the gate voltage VG is grounded and Vout is

connected to VL (0.2 V) as part of the charge-redistribution in the next stage. In phase

three, VS changes its value according the value of Vcmp_ref, while VG is still grounded and

Vout is connected to VP (0.4 V) as part of the precharge of the second stage input

capacitor. In the fourth phase, VG is driven by the RC-shaped pulse, VS is pulled down

when the top plate of the sampling capacitor is connected to VL, and Vout is pulled up

when the bottom plate of the sampling capacitor of the second phase is connected to VH.

This sets the condition for the charge-redistribution to occur until VG is pulled down at

the end of phase four.

1.2

1.0

0.2

0.4

0.6

0.8

Phase

1

Phase

3

Phase

2

Phase

4

0

VS

VG

Vout

[V]

Time

Figure ‎4.17: First stage wave shapes for VS, VG and Vout


4.5. Summary

This chapter presented the ADC stage design considerations. The first challenge

we discussed was how the application of this circuit in a differential configuration, and

how to reject a common mode signal. Following that, we discussed the implementation of

the DAC to achieve a linear summing node at the input of the amplifier, which is required

for nonlinear calibration. Then we discussed the implementation of the sub-ADC to allow

a multi-bit implementation and a comparator topology with low kickback noise. The

chapter ended with a discussion of the circuit timing and the signals wave shape.

Chapter 5: Circuit Implementation 56

5. Circuit Implementation

5.1. Top Level

5.1.1 ADC High Level Architecture

The target specifications for the ADC were set for a resolution of 12 bits and a

sampling rate of 200 MS/s. To achieve these specifications while maintaining low power,

the architecture shown in Figure ‎5.1 was chosen. In the first two stages, where the

thermal noise requirements are the most stringent, the largest capacitors are needed.

Therefore, the most efficient stage architecture was chosen, which is the pulse-based

bucket brigade amplifier. Each of the two stages uses a 2-bit sub-ADC. Nonlinear digital

correction ‎[20] is used to compensate the errors that are introduced by these stages. From

stage three onward, where the required performance is between 8 and 8.5 bits, nonlinear

correction is inefficient since the power required for calibration is higher than the power

needed to make the stage inherently linear. The bucket brigade architecture with a

boosting amplifier was chosen for the next three stages. As discussed in Section ‎2.2, the

boosting amplifier enforces accurate settling and calibration only needs to compensate for

linear gain errors. These three stages are using a 1.5-bit sub-ADC.

In a bucket brigade architecture the capacitors in each subsequent stage must be

scaled down to achieve voltage gain. If the entire ADC were built with bucket brigade

stages then the capacitors at the end of the pipeline would be very small (in the 1-2 fF

range). This would have been difficult to implement and the design would have been

highly sensitive to parasitic capacitors. Therefore, in order to create a more robust

design, stages 6-13 are implemented with a standard opamp-based stage-topology


because it does not require capacitor scaling. For this prototype, the digital calibration

engine is implemented off chip.

Vin

Dout

On Chip

Off Chip

2 StagesPulse-Based

Bucket Brigade

2 bits/stage

3 StagesBoosted Bucket

Brigade

1.5 bits/stage

8 StagesTraditional

Opamp stages

1.5 bits/stage

Nonlinear background calibration for stages 1, 2

Linear foreground linear calibration for stages 3-12

Figure ‎5.1: ADC architecture

5.1.2 Capacitor Sizing

The size of the sampling capacitors in each stage is determined with several

considerations in mind: thermal noise, voltage gain, and sensitivity to parasitics. Using

the expressions that were developed in Chapter 3 for gain and thermal noise, the

following values were chosen.

Architecture Sampling

Capacitor Size

Voltage

Gain

Stage 1 Pulse-based bucket brigade with

voltage input 8 pF 3.1

Stage 2 Pulse-based bucket brigade with

charge input 1.75 pF 3.1

Stage 3 Bucket brigade with boosting

amplifier 384 fF 1.9


amplifier 192 fF 1.9



amplifier 96 fF 1.9

Stage 6 Charge to voltage 48 fF 1.9

Stage 7-12 Opamp based 48 fF 1.9

Stage 13 Single Comparator 48 fF

Table ‎5.1: Stages architecture summary

5.2. Stage One

The input to stage one is a voltage signal with a full-scale range of 0.8 V

differential peak to peak. To meet the thermal noise requirements, the sampling capacitor

is set to 8 pF, the load capacitor is set to 1.75 pF and the voltage gain is 3.1 (1.6 bits

effective resolution). Two modes of operation are used to modulate the DAC signal,

which is required for nonlinear calibration ‎[20]: one with four comparators (mode 0) and

another with three comparators (mode 1). Figure ‎5.2 shows the stage transfer function.

The mode of operation (mode 0 or mode 1) is selected via a control bit.


0 0.1-0.1 0.2-0.2 0.3 0.4-0.3-0.4

0

0.1

-0.1

0.2

-0.2

0.3

0.4

-0.3

-0.4

Vin [V]

Vo

ut [

V]

Mode 0

Mode 1

Figure ‎5.2: Stage 1 transfer function with two modes of operation

To implement this transfer function, seven comparators and seven reference

voltages are needed. This requires dividing the stage into seven parallel channels (as

explained in Section ‎4.3.1). Figure ‎5.3 shows the architecture of the first stage. Each of

the seven channels includes the DAC containing eight unit capacitors. The DAC switches

are controlled by a digital block that uses the comparator outputs to generate the logic

signals that control these switches. The operation of all seven channels is identical in both

the sampling and charge-redistribution phases. During the comparison phase, each

channel is driven by a different reference voltage.


1/4CS

Vin Qout

VH

3/4CS

VL

Vc

mp

_re

f

To the

negative

half

circuit

Φ3

Cdac


X8

Φ2 Φ2

Comparator

controlled

switch on Φ4

To the

negative

half

circuit

To the

negative half

circuit

Φ2Φ2

Φ2

VG(Φ4)

Φ3

Φ3

Φ4

Φ4

X7

CHANNEL

DAC

Figure ‎5.3: Stage 1 architecture

5.2.1 Switch and Transistor Sizing

Figure ‎5.4 annotates the type of switch used in each part of stage one. Three

switches use bootstrapping ‎[31]. First bootstrapping is used in the input sampling switch

(S1) to achieve the required linearity at high input frequencies. Second bootstrapping is

used is for the bias voltage VH (S4). In this case, bootstrapping allows me to replace a

PMOS transistor with an NMOS transistor, helping to decrease the parasitic capacitors at

the transistor’s‎source, thus improving the voltage gain of this stage. The final use of a

bootstrapping is for the DAC switch that connects to Vdac_pre_p. Again, this is done to

allow the use an NMOS transistor instead of a PMOS transistor, however in this case the

choice is made to match the parasitics surrounding the DAC capacitor. The rest of the

switches are designed according to the voltage level at which they operate. Transistor M1


has a width of 175 µm and the minimum length of 60 nm. A 100 ohms resistor with an

equivalent capacitor of 1 pF is used to generate the RC-shaped pulse that drives the gate

of M1. The 1 pF capacitance includes both a dedicated capacitor and the intrinsic gate

capacitance.

1/4CS

Vin Qout

VH

3/4CS

VL

Vcmp_ref

To the

negative

half

circuit


X8

To the

negative

half

circuit

To the

negative half

circuit

Φ2

S1NMOS

Boosted

S1Nmos

Boosted

S2PMOS

S2PMOS

S3NMOS

S3Symmetric

NMOS

S4NMOS

Boosted

M1

S5NMOS

S6NMOS

S7NMOS

Boosted

Φ4

Figure ‎5.4: Annotation of switch types in stage 1

5.2.2 Stage 1 Comparators

The offset voltage specification for the comparators was set to accommodate a‎3σ‎

mismatch of up to 40 mV (20% of the sub-ADC’s‎quantization‎step),‎kickback noise of

less than 10 V (10% of the 12-bit‎ADC’s‎LSB), and regeneration time constant of less

than 15 ps (this yields a mean time to failure (MTF) due to metastability of

approximately 2 days). As explained in Section ‎4.3.2, the comparator design is based on


the low kickback noise architecture from ‎[29]. Figure ‎5.5 shows the comparator

architecture and Table ‎5.2 lists the transistor sizes.

clk

clk

clk

clk

clk

clk

clkclk

Vinp Vinn

Vdd

VREF

Voutn Voutp

M1 M1

M2

M3 M3

M4 M4

M5 M5

M6

M7M7

M8M8

Figure ‎5.5: Stage 1 voltage comparator implementation

Transistor NMOS/PMOS Width / Length

M1, M2, M4 NMOS 4.8 µm / 60 nm

M3 NMOS 9.6 µm / 60 nm

M6 NMOS 2.4 µm / 60 nm

M7, M8 NMOS 1.2 µm / 60 nm

M5 PMOS 4.8 µm / 60 nm

Table ‎5.2: Stage 1 comparator transistor sizes


Circuit simulation yielded a‎3σ‎mismatch‎of‎36‎mV,‎kickback‎noise‎of‎less‎than‎a‎

1 V, and a regeneration time constant of 15 ps, which meets the design target.

5.2.3 Calibration

The first two stages of the ADC were built to incorporate the calibration scheme

described in ‎[20]. In this scheme, the signal is modulated through the sub-DAC and extra

redundancy is added in the sub-ADC. This allows background estimation of the

parameters necessary for inverse decomposition of Dout in the presence of residue

amplifier nonlinearity. Figure ‎5.6 shows the block diagram for the calibration of the first

pipeline stage. The input signal is modulated through the DAC and the inverse function

of the (weakly) nonlinear amplifier is applied in the digital domain. Thus, the signal is

digitized with the same linearity as with a linear amplifier.

+-

Ving

g-1

Backend

A/D

Dout

Analog

Nonlinearity

Digital

Inverse

Coefficient

Estimation

D/A

MOD

A/D

12

Vres+MOD

Dback

+

+

Figure ‎5.6: Calibration scheme ‎[20]


For this scheme to work in practice there are two important circuit requirements.

The first (discussed in Section ‎4.2) is that the summing node at the input of the amplifier

is‎ linear‎ to‎within‎ the‎ stage’s‎precision‎requirements. The second (discussed in Section

‎2.3.3) is that the amplifier is only weakly nonlinear and sufficiently well modeled by a

third order Taylor series. As shown in Sections ‎2.3.3 and ‎4.2, the pulse-based bucket

brigade amplifier meets these requirements.

5.3. Stage Two

Stage two is very similar to the first stage since it also uses the pulse-based

bucket brigade architecture. However, there are a few differences. The first difference, as

shown in Figure ‎5.7, is that the input signal is in the charge domain, and as discussed in

Chapter 3, is configured appropriately. Specifically, a required precharge operation in the

first phase is implemented by switching the two capacitors between the voltages Vpre_ch_p

(0.4 V) and Vpre_ch_n (0 V). Also, due to the capacitor scaling requirement for this

architecture, a 1.75 pF sampling capacitor and a 0.384 pF load capacitor were chosen. All

transistors and switches are scaled down by the same ratio relative to those in stage one.

This maintains an identical voltage gain of 3.1 (1.6 bits effective). The input and output

differential voltage signal ranges are also maintained at 0.8 V peak to peak. The

comparator is the same as in the first stage, without any downsizing.


1/4CS

Qin

VG(Φ4)

Qout

VL

Vpre_ch_p

Vcmp_ref

VH

Vpre_ch_n

Φ1

Φ1 Φ1

Φ2 Φ2

Φ2

Φ4

Φ3Φ3

Φ4

3/4CS

To the

negative half

circuit

Φ3

Cdac


X8

Φ2 Φ2

Comparator

controlled

switch on Φ4

To the

negative half

circuit

To the

negative half

circuit

X7

Figure ‎5.7: Stage two architecture

5.4. Stages 3-5: Bucket Brigade Circuit with

Differential Boosting Amplifier

Stages three to five use the bucket brigade architecture with a boosting amplifier.

This necessitates calibration for linear gain errors and does not require nonlinear

calibration. The input signal is in the charge domain and therefore the charge-input

topology is used. The sampling and load capacitors have a ratio of two, and yield a

voltage gain near two (as specified in Table ‎5.1). The stages use a 1.5-bit sub-ADC and

have the transfer function shown in Figure ‎5.8.


0 0.1-0.1 0.2-0.2 0.3 0.4-0.3-0.4

0

0.1

-0.1

0.2

-0.2

0.3

0.4

-0.3

-0.4

Vin [V]

Vo

ut [

V]

Figure ‎5.8: Stage 3-5 transfer function

Figure ‎5.9 shows the circuit architecture for stages three to five. The resistor R1 is

added before the boosting amplifier, as suggested in ‎[24], to help stabilize the circuit. For

a 1.5 bit-per-stage topology, only two comparators and two DAC channels are required.


1/2CS

Qin Qout

VL

Vpre_ch_p

Vcmp_ref

VH

Vpre_ch_n

Φ1

Φ1 Φ1

Φ2 Φ2

Φ2

Φ4

Φ3Φ3

Φ4

1/2CS

To the

negative half

circuit

Φ3

Cdac

Vd

ac

_p

re_

p

Vd

ac

_p

re_

n

X2

Φ2 Φ2

To the

negative half

circuit

To the

negative half

circuit

X2

To the

negative half

circuit

To the

negative half

circuit

R1

M1

Figure ‎5.9: Stage 3-5 architecture

The circuit here uses a differential boosting amplifier that drives both the positive

and negative sides of the circuit. This is in contrast with ‎[24], which used two single-

ended boosting amplifiers. To explain the reason for this design choice, Figure ‎5.10

shows an attempt to use two single-ended amplifiers with the common mode rejection

technique presented in Section ‎4.1. In this case, since there is a different signal on the

positive and negative sides of the circuit, there will be a small difference in the settling

behavior of each side. When one side of the circuit settles (as shown in Figure ‎5.10, for

the positive side of the circuit) the current will go through the capacitors that connect

between the positive and negative sides of the circuit. This changes the voltage on VSP

after this side of the circuit was already settled and add a gain error to the stage.


CS/2VINP Voutp

VH

VSP

VG

VL

VINN Voutn

VH

VSN

VG

VL

CS/2

CS/2

CS/2

Settled à transistor

turned off

Figure ‎5.10: Illustration of the issue of using two single-ended boosting amplifier

implementation

A differential amplifier solves this problem. Figure ‎5.11 shows the amplifier,

which is used to control the gate voltages of the positive and negative sides of the circuit.

Figure ‎5.12 shows the stage configuration with the differential boost amplifier and Figure

‎5.13 shows the source and gate voltages of the bucket brigade transistor. The amplifier

starts its operation in the fourth phase, as the voltages VSN, VSP, and VCM (in Figure ‎5.12)

are pulled down. This causes the output of the amplifier to increase, which allows charge-

redistribution through the bucket brigade transistors. As the charge passes through the

transistor, VSN, VSP and VCM increase, allowing the amplifier common mode to settle,

which stop the charge-redistribution, while the differential gain of the amplifier ensures

that VSN and VSP are equal.


VinpVinn

Vpbias1

Vpbias2Vpbias2

Vnbias2Vnbias2

Vnbias1Vnbias1

cmfb

VDDA

VoutnVoutp

W=6.4 µm

L=0.36 µm

W=6.4 µm

L=0.36 µm

W=1.6 µm

L=0.36 µm

W=1.6 µm

L=0.36 µm

W=0.8 µm

L=0.36 µmW=0.8 µm

L=0.36 µm

W=7.68 µm

L=80 nm

W=7.68 µm

L=80 nm

W=4 µm

L=120 nm

W=1.2 µm

L=120 nm

W=1.2 µm

L=120 nm

W=1.2 µm

L=120 nm

W=1.2 µm

L=120 nm

Figure ‎5.11: Differential boost amplifier for the bucket brigade stage

CS/2QINP Qoutp

VH

VSP

VGP

VL

QINN Qoutn

VH

VSN

VL

CS/2

CS/2

CS/2

VGN

cmfbVCM

Figure ‎5.12: Connection diagram for the boosting differential amplifier in the bucket

brigade circuit


Figure ‎5.13: Source and gate voltages of the transistor in bucket brigade with differential

boosting amplifier circuit

The same circuit is implemented for stages four and five, except the capacitors

and transistors are scaled down by a factor of two from stage to stage.

5.5. Stage Six

Stage six is the transition stage from the bucket brigade architecture to the

traditional opamp stages that are used in stages seven to twelve. The input signal is in the

charge domain and the output is a voltage. Figure ‎5.14 show the architecture of the stage.

In phase one, the sampling capacitors are precharged to Vpre_ch_p – Vpre_ch_n. In phase two,

the input charge is sampled, while the bottom plate is connected to VH. In phase three, the

comparator references are connected Vcmp_ref. In phase four, one-half of the sampling

capacitance is flipped around the amplifier ‎[32] and the second half is connected to the

DAC reference voltage.

0 0.5 1 1.5 2-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

[V]

Time [ns]

Vsp

Vsn

Vgp

Vgn


QINP

Voutp

VH

CS/2

VCM

CS/2

Vc

mp

_re

f

Vp

re_

ch

_p

Vp

re_

ch

_n

QINN

VH

CS/2

CS/2

Vc

mp

_re

f

Vp

re_

ch

_p

Vp

re_

ch

_n

Voutn

Vp

re_

ch

_n

VH

Vc

mp

_re

f

VR

EF

P

VR

EF

N

Φ1

Φ1

Φ2

Φ3

Φ2

Φ3

Φ4

Φ4

Φ4

Φ1

Φ2

Φ3

Φ4

Φ4

Φ4

Φ1

Φ2

Φ3

Φ1

Φ1

Φ2

Φ2

Φ2

Φ2

Φ2

Φ4

Φ4

Φ4

Φ4

Figure ‎5.14: Stage six architecture


5.6. Stages 7-13

Stages 7-12 use the traditional opamp-based stage. Figure ‎5.15 show the stage

architecture, where each capacitance is 24 fF, and the stage uses the classical 1.5-bit

transfer function with a single-stage folded-cascode amplifier.

VINP

Voutp

CS/2

VCM

CS/2

Voutn

VR

EF

P

VR

EF

N

Φ4

Φ4

Φ4

Φ4

Φ4

Φ4

Φ2

Φ2

Φ2

Φ2

Φ4

VINP

CS/2CS/2

Φ4

Φ2

Φ2

Φ2

Figure ‎5.15: Stage 7-12 architecture

The last stage (stage 13) includes only the input sampling circuit as in stages 7-12

with a single comparator, and no amplifier.


5.7. Summary

This chapter presented the ADC architecture, starting with the top-level

architecture and explaining the choice for the stage topologies. This was followed by a

detailed analysis for each of the employed topologies.

Chapter 6: Measurement Results 74

6. Measurement Results

6.1. Introduction

The testchip for the ADC prototype was fabricated in TSMC’s 65G process.

Figure ‎6.1 shows the die photo of the chip. The total area is 3.33 mm2 and the ADC area

is 0.26 mm2. Low voltage differential signaling (LVDS) I/O pads are used because the

ADC operates at a sampling frequency of 200 MHz. These pads use differential signaling

and therefore require two pads for each output signal. Figure ‎6.2 shows the bonding

diagram of the package. To reduce the number of pads, the stage outputs are multiplexed,

and two consecutive stages use the same output pads with a DDR clocking scheme. In

addition, all the ground pins are shorted together and down-bonded to the thermal pad, as

shown in Figure ‎6.2 and Figure ‎6.3. Using these techniques, the total number of pins on

the package was reduced to 68, while the number of pads on the silicon was 88. This

allowed a smaller package (QFN 68, 10 mm X 10 mm), which in turn allowed for shorter

bond wires improving the signal integrity.


Figure ‎6.1: Test chip die photo

10mm

10m

m

1 2 3 4 5 6 7 8 9

10

Chip

pin 1

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Figure ‎6.2: Package bonding diagram. All black pads are down-bonded to the thermal pad


QFN Package

Pad PadThermal Pad

Die

Down bond

Figure ‎6.3: Down-bonding to thermal pad

Figure ‎6.4 shows the layout of the ADC. As explained in Chapter 5, stage one

and two use the pulse-based bucket brigade architecture and include seven channels to

allow both DAC modes and two bits of resolution. Stages three to five use the bucket

brigade architecture with a boosting amplifier and have a similar layout, but for scaled

down capacitor. Stage six performs the charge to voltage conversion, and stages seven to

thirteen are the backend, which use standard opamp-based switched-capacitor stages.

Figure ‎6.4: Layout of the ADC


6.2. Test Setup

Figure ‎6.5 shows the test setup for the prototype. The analog input signal was

generated using an Agilent 8644B signal-generator and was driven through a filter to the

test board (Allen Avionics for frequencies under 1 MHz and K&L for higher input

frequencies). The ADC digital outputs were then captured using a TI TSW1200 board

and were transferred to a computer using a USB interface for post processing. The test

chip’s‎clock was driven with a signal generator similar to that used as the input signal and

a third signal generator was used to trigger the capture board. All three signal sources

were synchronized to allow coherent sampling. The Matlab post-processing included

signal reconstruction, calibration, and performance assessment.

Signal Generator

HP8644B

Filter

Allen Avionics

ADC

Clock Generator

HP8644B

Data Acquisition

TI TSW1200

Clock Generator

Agilent E4432B

Vin Dout

15 bit

LVDS

Sync

Clo

ck

Clo

ck

USB

GPIO controlNanoriver

mini-board

USB

Matlab

Post processing

Figure ‎6.5: Test setup


6.3. Measured Results

6.3.1 Dynamic Linearity

Figure ‎6.6 and Figure ‎6.7 show the spectral performance before and after

calibration of the ADC for 0.96 MHz input signal and a sampling frequency of 200 MHz.

The FFT was calculated using 16384 samples. Before calibration, the SNDR is 44.17 dB,

the SFDR is 57.14 dB, and the THD is -49.50 dB. After calibration the SNDR is 65.05

dB, the SFDR is 82.56 dB, and the THD is -81.74 dB.

Figure ‎6.6: ADC spectral performance for a low frequency input before calibration.

SNDR is 44.17 dB, the SFDR is 57.14 dB, and the THD is -49.50 dB

0 20 40 60 80 100-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Ma

gn

itu

de

[d

B]

fin [MHz]


Figure ‎6.7: ADC spectral performance for low frequency input after calibration. SNDR

is 65.05 dB, the SFDR is 82.56 dB, and the THD is -81.74 dB

To analyze the performance for different input frequencies and to have realistic

results, the calibration coefficients were calculated for the low input signal frequency and

kept constant for all the subsequent measurements. Figure ‎6.8 shows the peak SNDR,

SFDR, and THD as a function of the input frequency. Figure ‎6.9 shows the measured

SNDR vs. input amplitude for sampling frequency of 200 MHz.

0 20 40 60 80 100-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Ma

gn

itu

de

[d

B]

fin [MHz]


Figure ‎6.8: Measured peak SNDR, SFDR and -THD vs. input frequency

Figure ‎6.9: Measured SNDR vs. input signal amplitude at fs=200 MHz

30

40

50

60

70

80

90

0 20 40 60 80 100

Mag

nit

ud

e [d

B]

fin [MHz]

SNDR

SFDR

-THD

0

10

20

30

40

50

60

70

-70 -60 -50 -40 -30 -20 -10 0 10

SN

DR

[dB

]

Vin [dB]


Figure ‎6.8 shows that between low frequency and Nyquist the SNDR

performance drops by 7.45 dB; this drop is higher than expected. One of the possible

issues was jitter on the clocks that drive the sample and hold circuit. Using the method in

‎[33] the clock jitter in the sample and hold circuit was estimated to be 1.2 ps, which is

higher than expected. The excess jitter stems from a design error in the path of the clock

that drives the sample and hold.

Another notable observation from Figure ‎6.8 is the drop in SFDR performance.

The SNDR performance drop can be explained by high jitter on the sampling clock but it

cannot explain the drop in linearity as measured by the SFDR. As mentioned above, the

results in Figure ‎6.8 were taken using the coefficient parameters for the nonlinear

calibration that were calculated for an input frequency of 0.96 MHz. However, if we re-

optimize the coefficients for each frequency and make the same measurement a different

picture is obtained. Figure ‎6.10 shows the SFDR and SNDR for these two cases. As

shown in this figure, the SNDR shows a minor improvement and the SFDR shows a

major improvement in that it does not drop as much at high frequencies.

Figure ‎6.10: SNDR and SFDR as a function of input frequency for coefficients optimized

for each frequency and for coefficients optimized at 0.96 MHz

30

40

50

60

70

80

90

0 20 40 60 80 100

Mag

nit

ud

e [d

B]

fin [MHz]

SNDR with optimized coefficients

SFDR with optimized coefficients

SNDR with coefficients at 0.96 MHz

SFDR with coefficients at 0.96 MHz


The coefficients were calculated at 0.96 MHz to optimize the SNDR

performance. As the SNDR is limited by jitter, the coefficient set at lower frequency

provides the best performance. However, this frequency may not be ideal for an ADC not

limited by jitter. As shown in Figure ‎6.10, calculating the coefficients for higher

frequencies provides better SFDR performance.

6.3.2 Static Linearity

Figure ‎6.11 shows the INL and DNL performance of the ADC. The

measurements were performed using a sinusoidal code-density test with 131,000 samples.

The maximum DNL is 0.96 LSB with no missing codes. The INL value is +1.23/-0.60

LSB.


Figure ‎6.11: Measured INL and DNL

6.3.3 Thermal Noise

To estimate the ADC’s thermal noise in the lab, the histogram measurements

technique ‎[34] was used. This technique checks the histogram distribution of the ADC

output with no input signal; if there is no thermal noise then all the data would fall into a

single bin of the histogram. However, thermal noise distributes the output over several

bins. From this distribution, the thermal noise can be estimated. Figure ‎6.12 shows the

measurement results. Using the suggested method ‎[34], the RMS noise is estimated to be

120 µV. Table ‎6.1 compares the estimated measured thermal noise with the thermal noise

calculated in simulation using transient noise analysis. The simulated noise is 99.6 µV,

compared to 120 µV measured in the lab. The difference between these two numbers can

0 500 1000 1500 2000 2500 3000 3500 4000-1

-0.5

0

0.5

10 Missing Codes

DN

L

0 500 1000 1500 2000 2500 3000 3500 4000-1

-0.5

0

0.5

1

1.5

INL


be explained by the fact that the transient noise simulation was done with the pre-layout

database. With the parasitic capacitors included, the thermal noise is expected to be

slightly higher.

Figure ‎6.12: Histogram results for thermal noise measurements

Simulations Test setup Noise

[µV]

Pre-layout simulation

with transient noise

analysis

Spectrum

measurements

99.6

Lab – Thermal noise

measurement

Histogram 120

Table ‎6.1: Thermal noise results, measurement vs. simulations

18 18.5 19 19.5 20 20.5 21 21.5 220

2000

4000

6000

8000

10000

12000


6.3.4 Jitter

Figure ‎6.13 shows the main blocks of the clock path. First, the differential clock

passes through the input clock buffer. This block uses three single stage differential

amplifiers (CML) to amplify the off-chip signal and then converts it to rail-to-rail signal.

Following that, the clock goes to the main ADC clock generator block where the clock is

buffered before being used to drive the boosted-switch circuit of the bottom plate switch

of the sample and hold. Unfortunately, while the clock buffer uses the quiet VDD_CLK,

the ADC clockgen and the boosted switch operate with the noisy digital VDD, which

drives all the rest of the digital blocks in the ADC (such as: clocking, logic and

comparators). Figure ‎6.14 details the specific path that the clock takes.

Clock

Buffer

VDD_CLK

ADC

clockgen

VDD

Boosted

Switch

VDD

Board ADC

Figure ‎6.13: Clock path for the sample and hold

Figure ‎6.14: Detailed clock path


An estimate of the jitter limit of the ADC at high frequencies demonstrates that

the ADC is in fact jitter limited. The estimate is calculated by taking measurement of the

ADC at low frequency (0.96 MHz) and adding the noise that is introduced by the

estimated 1.2 ps of jitter at all other frequencies as given by Eq. (‎6-1).

inrmsinjittern fVV 2 (‎6-1)

In this equation, σ‎is‎the‎standard deviation value of the jitter. The results are shown in

Figure ‎6.15; the top line represents the performance limit of the ADC due to jitter (as

calculated above), and the bottom line is the actual performance as measured in the lab.

From this figure, it is clear that the ADC SNDR performance is limited by clock jitter.

Figure ‎6.15: Estimated‎jitter‎limit‎of‎the‎ADC’s‎SNDR

40

50

60

70

80

0 20 40 60 80 100

Magnitude [

dB

]

fin [MHz]

SNDR

Jitter limit


6.3.5 Power

The total power of the ADC is 11.5 mW (excluding reference, I/O and external

calibration engine). Table ‎6.2 presents the power of the analog and digital parts for each

architecture. Figure ‎6.16 show the power breakdown of the ADC.

Architecture

Total Power [mW]

Stages 1-2 Pulse-based bucket

brigade

Analog 0.5

Digital 1.5

Stages 3-5 Bucket brigade with

boosting amplifier

Analog 1

Digital 1

Stages 6-13 Traditional opamp

Analog 6.5

Digital 1

Table ‎6.2: Power per stage architecture

Figure ‎6.16: Power breakdown (excluding reference, I/O and external calibration engine)

Stage 1-2 analog

Stage 3-5 analog

Stage 6-13 analog

Digital stages 1-2

Digital stages 3-5

Digital stages 6-13

Digital - Others


As shown in Figure ‎6.16, the first two stages, which use the pulse-based bucket

brigade architecture, consume the least amount of power. This is in contrast with a

traditional implementation, where the first stage consumes most of the power. The

following stages, 3-5, which use the bucket brigade architecture with boosting amplifier,

consume more power but are still very efficient. The backend of the ADC, which uses the

traditional opamp configuration, consumes most of the power in the ADC. This

emphasizes the power efficiency of the pulse-based bucket brigade architecture in that the

first stage, which drives a load capacitor of 1.75 pF, uses less power than traditional

opamp configuration with load capacitor of 48 fF.

6.3.6 Calibration Power

As mentioned above, the first two stages require nonlinear calibration.

Furthermore, since they operate in open loop and are sensitive to temperature variations,

background calibration is required. This calibration will consume additional power. In

‎[20] the calibration engine was found to require 8400 gates, 64 bytes of RAM and 64 kb

of ROM which consumed 11.5 mW when implemented in 0.35 µm technology. Using

scaling factor of 166 ‎[35] and sampling frequency factor of 2.5, we can estimate that the

calibration engine for a single stage is 175 µW and the total calibration power is 350 µW

for the first two stages. The rest of the stages operate in closed loops and require only

foreground linear calibration for the gain values. Therefore, these stages consume power

for the calibration only once, to obtain the coefficient values, and will not consume

additional power during the regular operation of the ADC.


6.4. Performance Summary

Table ‎6.3 summarize the ADC performance

Parameter Value

Sampling Frequency 200 MHz

Area 0.26 mm2

Power supply 1 V

Power

(excluding reference, I/O and

external calibration engine)

11.5 mW

Input Frequency fin=1 MHz fin=99 MHz

SNDR 65 dB 57.6 dB

SFDR 82 dB 68 dB

FOMs

P

fSNDR S

dB

2log10 10

164.5 dB 157 dB

Table ‎6.3: Performance Summary


6.5. Performance Comparison

To compare this work to other ADCs, the Schreier figure-of-merit ‎[36], ‎[37]

(FOMS) will be used. The FOMS is given by:

P

fSNDRFOM s

dBS

2log10 10 (‎6-2)

Where fs is the sampling frequency and P is the power dissipation of the ADC. Using the

ADC survey ‎[3], Figure ‎6.17 depicts the FOMS for Nyquist input as a function of fs for all

ADCs that were published at the ISSCC and the VLSI circuit symposium from 1997 –

2013. This work is presented here with two performance points, one for low input

frequency and one for Nyquist input frequency. Since the ADC performance is limited by

the jitter of the input clock and not by the ADC performance itself, it is reasonable to

assume that the actual performance of the ADC is between these two points.

Figure ‎6.17: ADC Survey, FOMS vs. sampling frequency

110.0

120.0

130.0

140.0

150.0

160.0

170.0

180.0

1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10 1.00E+11

FOM

S[d

B]

fsnyq [Hz]

Other ADC's 1997-2013 (ISSCC & VLSI)

Pipeline ADC 1997-2013 (ISSCC & VLSI)

This Work (Fin=1 MHz)



It may be interesting to compare this work only to pipeline ADCs, which achieve

high speed of operation without the use of time interleaving. Figure ‎6.18 shows only

these ADCs. This figure highlights the achievement of this work, which provides one of

the best figure-of-merits in this performance range.

Figure ‎6.18: ADC Survey, FOMS vs. sampling frequency. Only pipeline ADCs without

time interleaving are shown

Table ‎6.4 shows a more detailed comparison of ADCs in this performance and

efficiency range. There are several observations that can be noted from this table. The

first is that most ADCs that achieve this level of performance use a combination of

pipeline and SAR architectures to achieve the power efficiency. In addition, most of the

ADCs that achieve high sampling frequencies have to use time-interleaving since the

basic ADC cannot achieve high sampling frequency by itself. For example, the most

efficient ADC in this table by Verbruggen ‎[38] achieve the high speed of operation with

time-interleaving and its high efficiency with a pipeline SAR architecture. Finally, most

of them cannot achieve high resolution. It may be that the most relevant comparison to

110.0

120.0

130.0

140.0

150.0

160.0

170.0

180.0

1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10 1.00E+11

FOM

S[d

B]

fsnyq [Hz]

Other ADC's 1997-2013 (ISSCC & VLSI)

Pipeline ADC 1997-2013 (ISSCC & VLSI)




this work is the one by Chai ‎[39] in which she use standard pipeline architecture but

replace the stage amplifier with two steps of amplification – coarse and fine. By

optimizing each of them, she achieved high efficiency. Still, her work achieves only 10

bits of resolution, and at low fin the figure of merit is lower than in this work.

G. Van

der

Plas

et al. ‎[40]

Y.-Z. Lin

et al. ‎[41]

H-K

Hong

et al. ‎[42]

Zhu

et al.

‎[43]

B.

Verbruggen

et al. ‎[38]

Y. Chai

et al.

‎[39]

This Work

‎[44]

Year ISSCC

2008

VLSI

2010

ISSCC

2013

VLSI

2012

ISSCC

2012

ISSCC

2012

VLSI

2013

Architecture Two-Step SAR SAR, TI

Pipeline

SAR,

TI

Pipeline

SAR,

TI

Pipeline Pipeline

Process [µm] 0.09 0.09 0.045 0.065 0.040 0.065 0.065

fs [MHz] 150 150 900 500 250 200 200

Power [mW] 0.13 1.53 10.8 8.2 1.7 5.37 11.5

Resolution

[bits] 7 9 9 10 11 10 12

SNDR, Low fin 41.0 54.1 53.7 55.4 58.7 57.0 65.0

SNDR, High fin 40.0 53.1 51.2 52.9 56.0 55.0 57.6

FOMs, Low fin 158.5 161.0 159.9 160.3 167.4 159.7 164.5

FOMs, High fin 157.5 160.0 157.4 157.8 164.7 157.7 157.0

Table ‎6.4: Performance Comparison


6.6. Summary

This chapter presented the measurement results for the prototype ADC based on

the pulse-based bucket brigade amplifier. The measured results showed a large

performance drop near Nyquist. The cause for this performance drop was explained as

unintended jitter on the sampling clock, which limited the ADC’s‎ achievable

performance. The ADC’s performance was compared to other state-of-the-art and even

with the jitter limitation, this ADC showed the same level of performance with the best in

class.

Chapter 7: Conclusion 94

7. Conclusion

7.1. Summary

This research started with the capability of applying nonlinear calibration in

pipeline ADCs ‎[11], and with this knowledge we set out to find the most efficient

amplification method that can be used with this technique at hand. After considering

several amplification methods, the bucket brigade circuit showed the highest potential

because of its efficiency and compatibility with nonlinear calibration. Prior to this work,

a bucket brigade had been used only once in a pipeline ADC ‎[24], and that

implementation required a boosting opamp to achieve accurate settling. In seeking the

most efficient amplification method, it became clear that the opamp must be removed and

a new technique, the pulse-based bucket brigade amplifier, was proposed. Even still,

implementation of a complete, highly efficient, high performance pipeline ADC had

many more challenges that had to be resolved, including the problem of common-mode

gain, accurate DAC operation, and many more.

This thesis described the main ideas and the operation of the pulse-based bucket

brigade amplifier in Chapters 1 and 2, and provided a first-order analysis in Chapter 3.

Details on the pipeline stage implementation were covered in Chapter 4, and the

implementation of the prototype ADC was discussed in Chapter 5. Finally, Chapter 6

reported the measurement results taken in the lab and compared the achieved

performance to the state of the art. This comparison showed that despite much progress in

recent years, high-speed, high-resolution pipelined ADCs remain relatively energy

inefficient. Our results partly close this gap, validating the concept of pulse-based bucket


brigade amplification, with performance that compares‎favorably‎with‎today’s‎competing

designs.

7.2. Future Work

The presented measurement results correspond to the best in class performance.

However, as discussed in Chapter 6, a design error in the sampling clock network

prevented us from showing the full potential of this ADC. There is an opportunity to

improve the performance of this ADC by improving the clock circuit that drives the

ADC’s input track and hold.

As a next step, it would be interesting to look into ways to reduce the power that

is consumed by the backend stages (6-13). As discussed in Chapter 6, more than 50% of

the power in this ADC is consumed by these backend stages, even though, this part of the

ADC is relatively low-end and requires resolution of only 6 bits. Using a standard

opamp-based architecture as was done here solves the problem of capacitor scaling to

very small sizes, but consumes too much power. Several alternatives can be considered.

One adds a buffer after the fifth stage to drive a larger capacitor. After the buffer, the

bucket brigade architecture and the capacitor scaling can resume. Another alternative

uses the dynamic amplifier technique, as presented in ‎[18], ‎[19] for the backend stages.

This technique has already been demonstrated for this resolution and sampling frequency.

A third alternative uses a different architecture altogether for the backend stages such as a

SAR ADC, which is also suitable and efficient for the required resolution and sampling

frequency specifications ‎[45].

As for industry adoption, this ADC as a whole may not yet be suitable for a

commercial product due to its complexity. However, for any new design it may be


conceivable to replace only the first stage with the pulse-based bucket brigade

architecture. This alone can reduce the total power consumption of the ADC by about

50% without adding much complexity.

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