hv edmos design with expansion regime suppression · 2015-09-15 · ii hv edmos design with...

HV EDMOS Design with Expansion Regime Suppression

by

Jingxuan Chen

A thesis submitted in conformity with the requirements for the degree of Master of Applied Science

Department of Electrical and Computer Engineering University of Toronto

© Copyright by Jingxuan Chen 2013

ii

HV EDMOS Design with Expansion Regime Suppression

Jingxuan Chen

Master of Applied Science

Department of Electrical and Computer Engineering

University of Toronto

2013

Abstract

Lateral Extended Drain MOSFET (EDMOS) is one of the most popular high voltage

structures used to implement modern smart power integrated circuits. However,

conventional EDMOS suffers from an expansion effect of the IV characteristics under

high Vgs and Vds conditions. This greatly degrades the safe operating area (SOA) of the

devices and the performance of the power ICs. In this thesis, effective methods to

suppress the expansion regime without sacrificing the important baseline device

characteristics are introduced and analyzed. Enhancements to the baseline device

structure include the implementation of PBE (P-Buried Enhancement), double implanted

RESURF (Reduced SURface Field), NDE (N-Drift Enhanced) and NBD (N-Buffered

Drain) layers. The optimized design is simulated and verified experimentally. An n-type

EDMOS with BV of 70V, Ron,sp of 48mΩmm2 and no expansion effect until Vgs reaches

5.5V is successfully fabricated and tested.

iii

Acknowledgments

First of all, I would like to express the deepest appreciation to my research supervisor,

Prof. Wai Tung Ng, who has given a great deal of time, valuable advices, and continuous

guidance from the beginning until the final revision of this research. I have been enjoying

working in the Smart Power Integration & Semiconductor Devices Research Group under

his strong leadership. His knowledge and vision in power electronics has been invaluable

for my career development.

I would like to express my sincere gratitude towards Asahi Kasei EMD. Their technical

support in the device design and fabrication has made the realization of this work

possible. It has been an enriching experience to work with AKPD on this project.

I would also like to thank my fellow graduate students and researchers for many fruitful

discussions over the course of this research as well as their companionship along the way,

namely; Jing Wang, Andrew Shorten, Edward Xu, Jumin Lee, Shuang Xie, Wenfang Du,

Jingshu Yu, Niloufar Hashemi, Zhihua Ning, Ning Yang, Simon Jin, and Weijia Zhang.

Lastly, I would like to extend my appreciation to my fiancé, Patrick Li for his patience,

consideration and encouragement during the past two years. Also, special thanks to my

mother, Huiming Li for her constant support and encouragement throughout my studies.

iv

Table of Contents

Acknowledgement ............................................................................................................. iii

Table of Contents ............................................................................................................... iv

List of Tables ..................................................................................................................... vi

List of Figures ................................................................................................................... vii

List of Glossary ................................................................................................................. xii

List of Symbols ................................................................................................................ xiii

Chapter 1 Introduction ..................................................................................................... 1

1.1 Trends in Power MOSFETs Technology .................................................................. 2

1.2 Later Power MOSFET Design Considerations ......................................................... 6

1.2.1 Quasi-Saturation Effect ...................................................................................... 6

1.2.2 Expansion Effect ................................................................................................. 7

1.2.3 RESURF Principle ............................................................................................ 13

1.3 Research Objective and Thesis Organization .......................................................... 18

Chapter 2 Methods to Suppress the Expansion Regime in EDMOS ......................... 20

2.1 P-body Enhancement Layer .................................................................................... 20

2.2 N-drift Region Design Using Double Implanted RESURF .................................... 24

2.3 Additional N-drift Enhanced Layer and N-buffered Layer ..................................... 28

2.3.1 N-Drift Enhanced (NDE) Layer ....................................................................... 29

2.3.2 N-type Buffered Drain (NBD) .......................................................................... 34

2.4 Chapter Summary .................................................................................................... 35

Chapter 3 Device Optimization with Expansion Regime Suppression ...................... 37

3.1 P-body Region Design ............................................................................................ 37

3.1.1 P-body Implant ................................................................................................. 37

v

3.1.2 LDD Implant ..................................................................................................... 39

3.2 Device Dimensions ................................................................................................. 42

3.3 Summary ................................................................................................................. 48

Chapter 4 Device Fabrication and Experimental Results ........................................... 49

4.1 Low Side Device Fabrication Design ...................................................................... 49

4.1.1 Thermal Budget Control ................................................................................... 51

4.1.2 Calibration of the Diffusion Model .................................................................. 51

4.1.3 Simulation Results ............................................................................................ 53

4.2 Experimental Results and Discussion ..................................................................... 57

4.2.1 Threshold Voltage and IV Characteristics ........................................................ 57

4.2.2 Effect of Ldrift Variations ................................................................................... 60

4.2.3 Effect of Implant Dose Variations .................................................................... 62

4.4 Summary ................................................................................................................. 63

Chapter 5 Conclusions and Future Work .................................................................... 64

5.1 Conclusions ............................................................................................................. 64

5.2 Future Work ............................................................................................................ 66

Reference ......................................................................................................................... 68

vi

List of Tables

Table 4.1 Parameters Modified for Boron Diffusion Model Calibration ......................... 52

Table 4.2 Ion Implant Conditions of the designed EDMOS ............................................. 64

Table 4.3 Key Dimensions of the designed EDMOS ....................................................... 64

Table 4.4 Key Device Performance Parameters Comparison ........................................... 64

Table 5.1 Design Procedures for an EDMOS with Expansion Regime Suppression ....... 65

vii

List of Figures

Fig. 1.1 Evolution of vertical MOSFET structures .......................................................... 2

Fig. 1.2 Schematic representation of (a) Extended Drain MOSFET (EDMOS) (b)

Lateral double-Diffused MOSFET (LDMOS) ................................................. 3

Fig. 1.3 Modern lateral power MOSFETs technology benchmark: Ron,sp vs. BV ............ 5

Fig. 1.4 Applications for power devices with respect to their voltage and current

ratings ................................................................................................................. 5

Fig. 1.5 Ids vs. Vds curves for a conventional High-Voltage (70V) EDMOS.

Vgs is increased from 2V to 16V ....................................................................... 7

Fig. 1.6 Ids vs. Vds curves for a conventional High-Voltage (70V) EDMOS. Vgs is

increased from 2V to 10V .................................................................................. 8

Fig. 1.7 The cross section of a 70V EDMOS used for simulation. The body contact (p+)

and source contact (n+) are combined and grounded together. The cutline is for

the results in Fig. 1.15 ........................................................................................ 9

Fig. 1.8 (a) Illustration of the parasitic BJT and the two hot spots that appear with the

increase of Vds; (b) the electron and hole flow direction when the impact

ionization at hot spot #2 is initiated .................................................................... 9

Fig. 1.9 Hole current vectors with Vgs = 6V and Vds is (a) 5V (b) 20V (c) 50V ......... 10

Fig. 1.10 Impact ionization rate spatial distribution with Vgs = 6V and Vds is (a) 5V (b)

20V (c) 50V ...................................................................................................... 10

Fig. 1.11 Electron and hole concentrations along x = 5µm (center of the n-drift region)

cutline at Vds = 20V/50V (before and after the impact ionization effect occurs)

.......................................................................................................................... 11

Fig. 1.12 Electric field along the x-direction with Vgs = 6V and Vds = 5V/20V/50V. The

cutline is under the LOCOS as shown in Fig. 1.11 .......................................... 11

Fig. 1.13 Potential profile along the x-direction with Vgs = 6V and Vds = 5V~50V (The

intrinsic drain of the MOSFET is at around x = 3.5µm) .................................. 12

viii

Fig. 1.14 (a) A conventional pn diode structure with breakdown limited by the lateral

p+/n-drift region；(b) A RESURF pn diode structure with breakdown limited

by the vertical n-drift region/p-substrate junction ............................................ 13

Fig. 1.15 (a) Potential distribution and (b) surface E-field distribution of an optimized

RESURF diode when Vds = 150V .................................................................... 15

Fig. 1.16 Surface electric field distribution for different n-drift region layer doping

concentrations (Tepi is fixed at 2.5µm) ............................................................. 16

Fig. 1.17 Surface electric field distribution for different n-drift region layer thicknesses,

Tepi (n-drift doping concentration is fixed at 8 1015

cm-3

) ............................... 16

Fig. 1.18 (a) Double RESURF structure with a p-type top layer; (b) double implanted

RESURF with p-type buried layer (PBL) ........................................................ 18

Fig. 1.19 Basic device structure used in this thesis for simulation .................................. 19

Fig. 2.1 EDMOS structure with p-body enhancement layer to suppress the base

resistance of the parasitic BJT .......................................................................... 20

Fig. 2.2 Ids vs. Vds curves with Vgs = 6V (PBE implant energy = 300keV) ................... 21

Fig. 2.3 Impact Ionization rate spatial distribution with Vgs = 6V and Vds = 50V (a)

without and (b) with the PBE layer (PBE dose = 41014

cm2

) ....................... 21

Fig. 2.4 Electron and hole concentrations at x = 5µm (center of the n-drift region)

cutline with PBE (dose is 41014

cm2

) and without PBE ................................ 22

Fig. 2.5 Ids vs. Vds with Vgs = 0V .................................................................................... 23

Fig. 2.6 The Ids vs. Vds curves with Vgs = 6V (PBE implant dose = 41012

cm2

) .......... 23

Fig. 2.7 Breakdown voltage vs. n-drift dose for single RESURF EDMOS structure ... 24

Fig. 2.8 Electric field contour plots upon breakdown with (a) n-drift dose of 11012

cm2

and (b) n-drift dose of 21012

cm2

......................................................... 25

Fig. 2.9 A double RESURF EDMOS structure ............................................................. 25

Fig. 2.10 Breakdown voltage vs. n-drift dose with varying PBL dose. Here the

implantation energy for n-drift is 300keV and for PBL is 800keV .................. 26

ix

Fig. 2.11 Ron,sp vs. PBL dose with varying n-drift dose. Here the implantation energy for

n-drift is 300keV and for PBL is 800keV ........................................................ 27

Fig. 2.12 Ids vs. Vds curves with different PBL implant doses (n-drift dose = 21012

cm2

at 300keV. The PBL implantation energy is 800keV) ..................................... 28

Fig. 2.13 Double RESURF EDMOS structure with an n-drift enhanced layer and an n-

type buffered drain ........................................................................................... 28

Fig. 2.14 Phosphorus doping profile along the cutline at x = 5µm (around the center of

the n-drift region) with and without the NDE implantation ............................. 29

Fig. 2.15 Ids vs. Vds curves for different NDE dose conditions (implantation energy for

NDE layer = 60keV) ......................................................................................... 31

Fig. 2.16 Electric field along the x-direction with Vgs = 6V. The cutline is under the

LOCOS as shown in Fig. 1.11. ......................................................................... 31

Fig. 2.17 Electron and hole concentration along x = 5µm (center of the n-drift region)

cutline with NDE (dose = 31012

cm2

at 50keV) and without NDE ............... 32

Fig. 2.18 Breakdown voltage and Ron,sp vs. NDE implantation dose (implantation energy

for NDE layer = 60keV. n-drift implant is 21012

cm2

at 300keV, and PBL

implant is 1.51012

cm2

at 800keV). ................................................................ 32

Fig. 2.19 Specific on-resistance profile along the surface of the EDMOS during on-state

(Vgs = 5V and Vds = 5V) .................................................................................... 33

Fig. 2.20 Ids vs. Vds curves with and without NBD implant. The NBD implant is

performed at an angle ....................................................................................... 34

Fig. 2.21 Electrical field along the specified cut line for different NBD implants .......... 34

Fig. 2.22 Breakdown voltage and Ron,sp vs. NBD implantation dose (NBD implantation

energy = 100keV) ............................................................................................. 35

Fig. 3.1 Illustration of the p-body region of the EDMOS ............................................. 37

Fig. 3.2 Ids vs. Vgs curves for different p-body dose conditions (Vds = 0.1V) ................ 38

x

Fig. 3.3 Breakdown voltage and Ron,sp vs. p-body implantation dose (implantation

energy for p-body is 100keV) .......................................................................... 38

Fig. 3.4 Ids vs. Vds curves at different p-body dose condition (Vgs = 6V) ...................... 39

Fig. 3.5 Ids vs. Vds curves for different HV_NLDD dose and PBE implant energy

conditions (Vgs = 6V, PBE dose = 41014

cm2

and HV_NLDD implant energy

= 40keV) ........................................................................................................... 40

Fig. 3.6 Breakdown voltage and Ron,sp vs. HV_NLDD implantation dose (implant

energy for HV_NLDD = 40keV) ..................................................................... 40

Fig. 3.7 Specific On-resistance profile along the drift region of the EDMOS structure

during on-state for different HV_NLDD implant dose (Vgs = 5V and Vds = 5V).

.......................................................................................................................... 41

Fig. 3.8 Device structure with labeled dimensions ........................................................ 42

Fig. 3.9 Breakdown voltage and Ron,sp vs. Ldrift.............................................................. 43

Fig. 3.10 Ids vs. Vds curves with varying Ldrift (Vgs = 6V) ................................................. 43

Fig. 3.11 Breakdown voltage and Ron,sp vs. Lbody ............................................................. 44

Fig. 3.12 Ids vs. Vds curves with varying Lbody (Vgs = 6V) ................................................ 44

Fig. 3.13 Impact ionization rate spatial distribution with Vgs = 6V and Vds = 50V (a) Lbody

= 0.1µm (b) Lbody = 0.4µm ................................................................................ 45


cutline with Lbody = 0.1µm and Lbody = 0.4µm .................................................. 45

Fig. 3.15 Net doping concentration along y = 0.4µm cutline when Lbody = 0.1µm and

Lbody = 0.4µm .................................................................................................... 46

Fig. 3.16 Breakdown voltage and Ron,sp vs. Lac length (all the other dimension parameters

and process conditions remained the same, and Lbody = 0.3µm, and Lg = 1.2µm)

.......................................................................................................................... 47

Fig. 3.17 Ids vs. Vds curves with varying Lac length (Vgs = 6V) ........................................ 47

Fig. 4.1 Process steps for n-EDMOS fabrication in 0.35µm CMOS technology .......... 50

xi

Fig. 4.2 Device structures with (a) LV_NLDD implant only and (b) both LV_NLDD

implant and HV_NLDD implant ...................................................................... 51

Fig. 4.3 Boron implantation SIMS and simulation data (before and after simulation) . 52

Fig. 4.4 Phosphorus implantation SIMS and simulation data (The model is accurate

without calibration) .......................................................................................... 53

Fig. 4.5 Ids vs. Vds curves for different Vgs conditions .................................................... 54

Fig. 4.6 Ids vs. Vgs curve with Vds =0.1V ........................................................................ 55

Fig. 4.7 Ids vs. Vds curve for Vgs =5V ............................................................................. 55

Fig. 4.8 Ids vs. Vds curve with Vgs =0V ........................................................................... 56

Fig. 4.9 Electric field contour plot upon breakdown at Vds = 72V ................................ 56

Fig. 4.10 Measured Ids vs. Vgs curve ................................................................................ 57

Fig. 4.11 Measured Ids vs. Vds characteristic with Vgs varied from 2V to 6V .................. 57

Fig. 4.12 Measured breakdown voltage with Vgs =0V ..................................................... 58

Fig. 4.13 Layout design for the proposed EDMOS ......................................................... 59

Fig. 4.14 Ids vs. Vds curves with (a) Ldrift =2µm and (b) Ldrift =2.3µm.............................. 60

Fig. 4.15 Measured breakdown voltage and Ron,sp vs. Ldrift variation .............................. 60

Fig. 4.16 Measure threshold voltage vs. Ldrift variation ................................................... 61

Fig. 4.17 Ids vs. Vds with Vgs =5.5V as Ldrift is varied ....................................................... 61

Fig. 4.18 Ids vs. Vds curves for varying PBE implant dose ............................................... 62

Fig. 4.19 Ids vs. Vds curves for varying n-drift dose and NDE dose .................................. 62

Fig. 5.1 Ron,sp vs. BV curves for this work compared with some recent published results

.......................................................................................................................... 66

Fig. 5.2 Proposed high side EDMOS structure .............................................................. 67

xii

List of Glossary

BPSG Boro-Phospho-Silicate-Glass

BJT Bipolar Junction Transistor

EDMOS Extended Drain MOS

CMOS Complementary Metal Oxide Semiconductor

DMOS Double-diffused MOS

LDMOS Lateral double-Diffused MOS

LDD Lightly Doped Drain

LOCOS LOCal Oxidation of Silicon

MOS Metal Oxide Semiconductor

MOSFET Metal Oxide Semiconductor Field Effect Transistor

NBD N-Buffered Drain

NDE N-Drift Enhanced

PBE P-Buried Enhancement

PBL P-Buried Layer

RESURF REduced SURface Field

SIMS Secondary Ion Mass Spectrometry

SOA Safe Operating Area

UMOS U-shape Gate MOS

VDMOS Vertical DMOS

VMOS V-shaped Gate MOS

xiii

List of Symbols

BV Breakdown Voltage

E-field Electrical Field

Ec Critical Electric Field

εsi Dielectric Constant of Silicon

Ids Drain to Source Current

Lac Accumulation region Length

Lbody Length of P-body implant layer mask opening under gate region

Lchannel Channel Length

Lg Gate Length

Ldrift Drift Length

Lfp Field Plate Length

Ron,sp Specific On-resistance

Vds Drain to Source Voltage

Vgs Gate to Source Voltage

1

Chapter 1

Introduction

Power semiconductor devices play a crucial role in the conditioning and distribution of

power and energy in the world. Their characteristics and limitations are key

considerations in the design of power electronic systems. In recent years, power

semiconductor technology has made impressive progress, greatly benefitting power

electronic systems with increased efficiency and performance [1].

Power switches are essential components of all power electronic systems. The first power

semiconductor switches were the thyristors and the bipolar transistors developed in the

1950’s. Power MOSFETs were introduced in the 1970’s with several advantages over

their bipolar counterparts. They are majority carrier devices, with high input impedance,

high switching speed, ease of paralleling, and superior Safe Operating Area (SOA). This

makes the power MOSFETs attractive for many applications such as industrial and

consumer power supplies, and automotive electronics [1-3].

Lateral power MOSFET is one of the most popular power MOSFET structures since its

fabrication technology is compatible with standard integrated circuit (IC) technology. In

addition, it can be self-isolating, making it attractive for the fabrication of complex high-

voltage ICs (HVICs) and power ICs. Many advancements have already been made to the

design of lateral MOSFET, especially with low on-state resistance and high breakdown

capability using REduced SURface Field (RESURF) technology [2]. However, most

current lateral power MOSFETs, such as the EDMOS devices are still limited by the

quasi-saturation effect at lower voltage and expansion effect at higher voltage operating

condition. The expansion effect, sometimes also referred to as the Kirk effect in power

MOSFETs, could greatly degrade the Safe Operating Area (SOA) of the device and also

the performance of the power electronic circuits [4, 5].

This thesis focuses on effective ways to suppress the expansion effect without sacrificing

the important baseline device characteristics such as breakdown voltage (BV) and specific

on-state resistance (Ron,sp).

2

In this introductory chapter, trends in power MOSFET technology will be reviewed in

Section 1.1; the basic EDMOS design considerations, including the quasi-saturation

effect and expansion effect, as well as the RESURF principle will be reviewed in Section

1.2; the thesis objective and organization will be introduced in Section 1.3.

1.1 Trends in Power MOSFETs Technology

The first power MOSFET introduced in 1970’s is a vertical MOSFET. By using a V-

grove etch and timing the difference in diffusion rates, very short channel (< 1µm) can be

obtained without the availability of fine line photolithography. This structure is known as

the VMOS, and is as shown in Fig. 1.1. The vertical structure is designed to handle much

higher drain currents than the standard MOSFETs. When a positive gate voltage is

applied to the device, the VMOS forms a channel on both sides of the gate. This channel

can be much shorter than the standard MOSFET channel. As a result, the device exhibits

very high drain current per µm of channel width [1].

(a) VMOS Structure (b) DMOS Structure (c) UMOS Structure

Fig. 1.1 Evolution of vertical MOSFET structures.

However, the sharp tip at the bottom of the V-groove creates a high electric field which

would degrade the breakdown voltage. At the same time, the fabrication method for the

V-groove could cause instability in the threshold voltage. Therefore, the VMOS structure

is soon replaced by the Double-diffused MOS (DMOS) structure in late 1970’s. In the

DMOS structure, the sub-micron channel length is produced by simply controlling the

difference between the n+ source and p-base diffusion processes through the same mask

opening. In addition, the incorporation of the drift region greatly improved the

breakdown voltage and provided an effective trade-off with the on-state resistance [1, 3].

3

The UMOS structure, appeared in 1990’s, achieves even better device performance by

using the trench-etch process originally developed for memory cells in DRAM’s. This

greatly decreased the cell size and hence the Ron,sp [3]. In the past two decades, the

vertical power MOSFETs have been further developed based on the improvements in

advanced photolithography, trench technology and vertical super-junction drift layers [6].

Another direction of power MOSFETs development is the lateral power MOSFET

technology mainly aimed for low voltage (less than 100V) and smart integrated power

applications. The main advantage of LDMOS over VMOS is the fact that multiple

devices can be integrated onto the same chip. It can also be designed to be compatible

with advanced VLSI technologies. The ability to fabricate LDMOS devices with modern

VLSI processes makes the prospect of smart power ICs a reality [7].

(a) (b)

Fig. 1.2 Schematic representation of (a) Extended Drain MOSFET (EDMOS) (b) Lateral

Double-diffused MOSFET (LDMOS) [8].

Lateral power MOSFETs could be categorized into EDMOS (Extended Drain MOS) and

LDMOS (Lateral Double-diffused MOS). As shown in Fig. 1.2 (a), the EDMOS with a

thin n-drift region makes the well-known “RESURF” phenomenon possible [9]. At high

drain voltage condition, the lightly doped n-drift region will be fully depleted, and the

positive charge in the depleted n-drift region can be balanced by the negative charge in

the p-substrate underneath. In such case, the more ideal planar junction between the n-

well (n-drift region) and the p-substrate limits the breakdown voltage. This leads to an

effective trade-off between high breakdown voltage and low on-resistance. By

maintaining the charge balance, the breakdown voltage could be further increased by

increasing the n-drift (n-well) length, however, this would result in the increase of Ron,sp

[10].

4

Fig. 1.2 (a) shows the structure of an early EDMOS design. One problem is the premature

punch-through breakdown across the MOS channel that can easily occur due to the

lightly doped p-substrate. The LDMOS employs a lateral double diffusion process to

produce a highly doped and short channel region that could alleviate this punch-through

breakdown. This also, results in a non-uniform doping profile along the MOS channel

[10]. In addition, as shown in Fig. 1.2 (b), the n-type LDMOS structure uses a thick field

oxide and field plate to reduce the surface electric field. This could significantly increase

the breakdown voltage [8]. Therefore, the modern EDMOS structure also implements the

p-body implantation as well as the thick field oxide; which enables much better device

performance.

The merit of modern LDMOS technology is often compared using the vs. Ron,sp plot

as shown in Fig. 1.3. For power switching applications, the driving force for the power

MOSFETs development is always to achieve high blocking capability ( ) and low Ron,sp.

However, there is a trade-off relationship between these two key parameters [11]:

(1.1)

This equation shows a near quadratic relationship between and Ron,sp. A higher than

necessary can result in a significant increase in Ron,sp of the device. Therefore, high

voltage lateral MOSFET always exhibits high on-state resistance. As a result, it is less

area efficient. Modern technologies such as double-RESURF and super-junction concept

were introduced to achieve lower Ron,sp for HV lateral power MOSFET [12, 13].

Compared with the lateral power MOSFET, vertical power MOSFETs have the drift

region located vertically inside the silicon. Hence, a current path can be elongated across

the thickness of the wafer without sacrificing the silicon area. Therefore, a much denser

high voltage layout could be achieved. However, the device’s switching speed is

sacrificed due to the large overlap capacitance between the gate and drain. In addition,

the fabrication technology of the VDMOS is not compatible with the current CMOS

technology due to the bottom drain electrode. Consequently, the VDMOS structures are

not widely adopted for high frequency and low voltage integrated applications.

5

BVdss (V)

10 100

Ro

n,s

p (

m

*mm

2)

1

10

100

1000

STM_BCD6 (0.35um)

STM_BCD8 (0.18um)

Freescale SMOS8 (0.25um)

TI_LBC7 (0.25um)

TI_LBC5 (0.35um)

Si-limit

Fig. 1.3 Modern lateral power MOSFETs technology benchmark: Ron,sp vs. BV [14, 15].

Power MOSFETs are employed in many power electronic applications, such as display

drives, motor controls, automotive electronics, switching power suppliers,

telecommunication circuits and factory automation, etc. Fig.1.4 shows the prominent

application fields for power semiconductors devices with various voltage and current

ratings [1].

Fig. 1.4 Applications for power devices with respect to their voltage and current ratings

[16].

6

The two important applications in below 100V voltage range include switched mode

power supplies for computers, telecommunications or office equipment, and for

automotive electronics. With the proliferation of personal computers, an improvement in

the efficiency of the power supply is essential to reduce wastage of electricity. This will

also lead to a reduction in the size and weight of the computer which is attractive to

consumers. While for the automotive industry; particularly in hybrid, electric, and fuel

cell vehicles. Power MOSFETs are widely used in engine control, vehicle dynamic

control, vehicle safety, and body electronics subsystems in both electric and conventional

internal combustion engine vehicles [1, 3].

1.2 Lateral Power MOSFET Design Considerations

Lateral power MOSFET usually suffers from quasi-saturation and expansion effects. This

section gives a detailed explanation on these phenomena. In addition, the RESURF

principle that can be used for the optimization of BV and Ron,sp is discussed.

1.2.1 Quasi-Saturation Effect

The quasi-saturation effect, also referred to as the compression effect, is one of the

unique effects observed in HV devices due to the existence of the drift region.

As shown in Fig. 1.5, for a conventional 70V EDMOS, at high gate voltages, the increase

in saturation current with increasing gate voltages diminishes, which indicates the onset

of quasi-saturation (reduction in transconductance, gm). This effect does not originate

from the pinch-off of the channel at the drain end, but because of the velocity saturation

in the drift region, prior to the saturation of the intrinsic MOSFET.

This effect is visible when Vgs is high while Vds is lower. The high Vgs causes a significant

reduction in the intrinsic MOSFET channel resistance. The overall device resistance

becomes dominated by the drift region resistance and is relatively independent of the

intrinsic channel resistance. This causes the drain current to be less dependent on the gate

bias at high Vgs and low Vds regime [17, 18].

7

Vds (V)

0 2 4 6 8 10 12

Ids (

A/

m)

0.00000

0.00005

0.00010

0.00015

0.00020

0.00025

0.00030

Vgs=2V

Vgs=4V

Vgs=6V

Vgs=8V

Vgs=10V

Vgs=12V

Vgs=14V

Vgs=16V


increased from 2V to 16V.

1.2.2 Expansion Effect

The expansion effect refers to a sudden increase of the drain current at high Vgs and Vds

condition. The name “expansion” is used in contrast to the “compression phenomenon”

which refers to the quasi-saturation effect [19]. As shown in Fig. 1.6, when Vds is

increased beyond 30V, a sudden step up of the drain current is observed when Vgs is

larger than 4V. With further increase in Vgs, this hump or current enhancement becomes

more severe and the SOA of the device is greatly degraded.

The expansion regime is in fact a combination effect of the parasitic BJT structure

turning on and impact ionization. This expansion phenomenon is first addressed as Kirk

effect [4, 20]; and some recent work also addressed the impact ionization effect as the

Kirk effect. However, this is not accurate. Kirk effect is in fact the well-known “base

pushout” effect in bipolar junction transistors. As the collector current increases, the

concentration of minority carriers leaving the base and entering the collector increases

significantly. This minority carrier concentration can exceed the background doping

concentration in the collector. When this happens, the depletion charge on the collector

8

side of the base-collector space charge region is neutralized by the large number of free

carriers entering the collector, effectively eliminating the depletion region and extending

the base region into the collector, hence the name “base pushout”. The outcome is a

sudden increase of the effective base width with a drop in the current gain as well as the

cut off frequency [21]. The mechanism of the Kirk effect in BJT is different from the

expansion effect in EDMOS. Therefore, later on, the name “expansion effect” or

“expansion regime” is used. Some work also refers to this as “current enhancement effect”

or “saturation effect” [5]. There are also works calling it the impact ionization effect

directly [17, 22]. However, impact ionization is only one of the reasons for the expansion

effect. In this work, the name “expansion effect” will be used for simplicity and accuracy.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.000

0.001

0.002

0.003

0.004

0.005

0.006

Vgs=2V

Vgs=4V

Vgs=6V

Vgs=8V

Vgs=10V


increased from 2V to 10V.

The mechanisms for the expansion effect have already been explored in previous work [4,

19, 23-27]. As shown in Fig. 1.7 and Fig. 1.8, the explanation of the process involves the

parasitic BJT model as well as the impact ionization hot spots due to the peaks in the

electric field distribution. The hot spots generate electron/hole pairs which turn on the

BJT, leading to an increase in the overall current flow. The enhanced current flow

9

produces even more impact ionization hot spots. This regenerative effect will eventually

lead the device to destructive breakdown [5, 19, 23-25].

Fig. 1.7 The cross section of a 70V EDMOS used for simulation. The body contact (p+)

and source contact (n+) are combined and grounded together. The cutline is for the

results in Fig. 1.16.

(a) (b)

Fig. 1.8 (a) Illustration of the parasitic BJT and the two hot spots that appear with the

increase of Vds; (b) the electron and hole flow direction when the impact ionization at hot

spot #2 is initiated.

For a better understanding of the impact ionization process, the hole current vectors and

impact ionization rate contours are extracted at Vgs = 6V and Vds = 5V/20/50V, as shown

in Fig. 1.9 and Fig. 1.10. When Vgs is high (larger than 4V), and Vds is low (less than 5V),

the hot spot for the highest impact ionization rate is at the LOCOS edge near the source

region (hot spot #1 in Fig. 1.8 (a)). The generated hole current flows into the p-body,

creating a forward voltage drop between p-body and n+ source contact (the base and

10

emitter of the parasitic BJT). Therefore, the parasitic BJT is softly turned on and it

injects excess electrons from the source (emitter). These electrons flow into the n-drift

region and begin to cause additional impact ionization near the drain edge (hot spot #2 in

Fig. 1.8 (a)). The hole current flows back to the p-body which further biases the p-

body/n+ junction and the parasitic NPN transistor is now strongly turned on, as can be

seen from Fig. 1.9 (c) and Fig. 1.10 (c).

(a) (b) (c)

Fig. 1.9 Hole current vectors with Vgs = 6V and Vds is (a) 5V (b) 20V (c) 50V.

(a) (b) (c)

Fig. 1.10 Impact ionization rate spatial distribution with Vgs = 6V and Vds is (a) 5V (b)

20V (c) 50V.

As the avalanche process from the drain edge further activates the NPN parasitic

transistor, the snapback phenomenon may occur. Snapback is disruptive to the circuit

operation and the onset of snapback is usually defined as the boundary of the SOA of the

device.

The electric field profile along the x-direction near the surface of the substrate is as

shown in Fig. 1.12. It is clearly shown that the electric field along the drift region

increases with increasing Vds and the peak electric field is shifted from the channel edge

to the drain edge.

11

Distance along Y direction (m)

0.5 1.0 1.5 2.0 2.5

Co

nce

ntr

atio

n (

cm

-3)

0.0

5.0e+16

1.0e+17

1.5e+17

2.0e+17

2.5e+17

Electron concentration when Vds=20V

Electron concentration when Vds=50V

Hole concentration when Vds=20V

Hole concentration when Vds=50V


cutline at Vds = 20V/50V (before and after the impact ionization effect occurs).

Distance along X direction (m)

0 2 4 6 8

Ele

ctr

ic F

ield

(V

/cm

)

0

5e+4

1e+5

2e+5

2e+5

3e+5

3e+5

Vds=5V

Vds=20V

Vds=50V

Fig. 1.12 Electric field along the x-direction with Vgs = 6V and Vds = 5V/20V/50V. The

cutline is under the LOCOS as shown in Fig. 1.7.

12


1.0 1.5 2.0 2.5 3.0 3.5 4.0

Po

ten

tia

l (V

)

-5

0

5

10

15

20

Vds=5V

Vds=20V

Vds=40V

Vds=50V

Fig. 1.13 Potential profile along the x-direction with Vgs = 6V and Vds = 5V~50V (The

intrinsic drain of the MOSFET is at around x = 3.5µm).

Fig. 1.13 shows the potential profile along the surface at Vgs = 6V for different Vds values.

It can be seen that when Vds reaches 50V, the intrinsic MOSFET is already saturated. This

is because of the fact that when impact ionization occurs, the generated electron/hole

current causes the conductivity of the drift region to be greatly increased (or the

resistance of the drift region to be greatly reduced). Therefore, the potential of the

intrinsic MOSFET’s drain region (at the junction of the channel and n-drift region) is

increased to larger than Vgs Vth (here Vth is around 0.6V).

It has already been proven that in real devices, the self-heating effect could alleviate the

impact ionization effect to some extent. In large devices where self-heating is more

pronounced, the impact ionization current is suppressed due to the reduced mean free

path at high temperature. However, in small size power devices which are more efficient

in heat dissipation, the self-heating is relatively smaller and the impact ionization effect

as well as the resulting expansion effect is more pronounced [17].

13

1.2.3 RESURF Principle

Single-RESURF

RESURF (REduced SURface Field) technology is one of the most widely-used methods

in the design of lateral high-voltage, low on resistance devices. Traditional high-voltage

devices usually require thick and lightly doped epitaxial layer, which results in high on-

state resistances. In 1979, Appels and Vaes suggested the RESURF concept to provide a

good trade-off between the breakdown voltage and the on-resistance of lateral devices.

The traditional Single RESURF structure (as shown in Fig. 1.14) is constructed by a

lateral diode that defines the on-resistance characteristic of the device and a vertical diode

which supports a depletion region for high breakdown voltage [9].

(a) (b)

Fig. 1.14 (a) A conventional pn diode structure with breakdown limited by the lateral

p+/n-drift region；(b) A RESURF pn diode structure with breakdown limited by the

vertical n-drift region/p-substrate junction.

The electric field at the surface of the RESURF device assumes a parabolic rather than a

linear distribution as often found in conventional high voltage devices. This helps to

reduce the peak electric field on the surface, hence improving the breakdown

14

performance. The condition to obtain a benefit from the RESURF principle is that the n-

drift region must be fully depleted before the lateral diode breaks down [9].

In Fig. 1.14 (b), the breakdown voltage of the lateral diode and the depletion width

extended vertically into the n-drift are given as:

(1.2)

( ) √

( ) (1.3)

where is the dielectric constant of silicon, is the voltage applied to the cathode,

is the silicon critical electric field which is around 3 1015

V/cm. and are the

doping concentrations of the substrate and drift region, respectively. In order to satisfy

the RESURF condition, the n-drift region must be fully depleted before the lateral

breakdown. This requires that:

( ) (1.4)

where ( ) is the depletion width in the n-drift region at breakdown, is

the drift region layer thickness. Combining Equation 1.3 and 1.4; we could obtain the

optimal integrated charge for the n-drift region as:

√

√

(1.5)

In a practical fabrication process, in order to have reasonable control over the thickness

and doping concentrations of these regions, it is essential that the doping concentration of

the n-drift region to be higher than that for the p-substrate [7]. In such case, we

have , and equation 1.5 can be simplified to:

to (1.6)

This equation could be used as a guide line for the single RESURF structure design.

15

(a) (b)

Fig. 1.15 (a) Potential distribution and (b) surface E-field distribution of an optimized

RESURF diode when Vds = 150V.

Fig. 1.15 shows the potential distribution and surface electric field under RESURF

condition when a cathode voltage of 150V is applied. It can be seen that there is parabolic

distribution of the E-field on the surface, and the electric field peaks at the edges of anode

and cathode. Metal field plates could also be used to reduce the electric field peaks to

some extent.

The influence of the n-drift region doping on the electric field strength near the surface of

the device is as shown in Fig. 1.16. The cathode side has higher electric field when the

doping concentration is lower; meanwhile the breakdown voltage is decreased. With the

increase in doping level, the E-field peak will move towards the anode, which is the p+

and n-drift region junction. In such case, the electric field at the anode side exceeds the

critical value of silicon before complete depletion is achieved. Therefore, a premature

breakdown would occur at the surface of the p+/n-drift junction. The optimal condition is

reached when the doping concentration is around 81015

cm3

where the parabolic

distribution achieves the lowest peaks [7].

Distance from Anode to Cathode(um)

0 2 4 6 8 10 12

Ele

ctr

ic F

ield

(V/c

m)

0

5e+4

1e+5

2e+5

2e+5

16

Distance from Anode to Cathode(µm)

0 2 4 6 8 10 12

Ele

ctr

ic F

ield

(V/c

m)

0

1e+5

2e+5

3e+5

4e+5

5e+5

Nepi=5e15 cm-3

Nepi=8e15 cm-3

Nepi=1e16 cm-3

Nepi=2e16 cm-3

Fig. 1.16 Surface electric field distribution for different n-drift region layer doping

concentrations (Tepi is fixed at 2.5µm).

Distance from Anode to Cathode(µm)

0 2 4 6 8 10 12

Ele

ctr

ic F

ield

(V/c

m)

0.0

5.0e+4

1.0e+5

1.5e+5

2.0e+5

2.5e+5

t(epi)=1.5um

t(epi)=2.5um

t(epi)=3.5um

t(epi)=4.5um

t(epi)=5.5um

t(epi)=6.5um

Fig. 1.17 Surface electric field distribution for different n-drift region layer thicknesses,

Tepi (n-drift doping concentration is fixed at 8 1015

cm-3

).

17

The impact of the variation of the n-drift layer thickness on the surface electric field is as

shown in Fig. 1.17. It is obvious that with thicker drift region layer thickness, the E-field

peaks at the anode. The peak will move towards the cathode with the decrease in the drift

region layer thickness. The trade-off between the n-drift region doping and layer

thickness is actually a charge balance issue which is explained previously by Equation

1.6. When the RESURF condition is optimized and the lateral distance is sufficient to

support cathode voltage applied, breakdown would occur at the planar (horizontal)

junction in the semiconductor bulk under the n+ region, which is the only desired

breakdown location.

Double RESURF

Double RESURF structures are formed by incorporating an extra layer with opposite

doping on top of the existing drift region layer. In the previous lateral diode, either a p-

type top layer or a p-type buried layer could be implemented as shown in Fig. 1.18.

Based on the charge balance theory, the doping concentration of the n-drift region could

be increased, which results in the further decrease of Ron,sp. However, the breakdown

voltage will be degraded at the same time.

For the structure in Fig. 1.18 (a), the p-top layer and the underlying n-drift layer are

required to be fully depleted before lateral diode breakdown. The vertical integrated

charge in the p-top layer and the n-drift layer are approximately 11012

cm2

and

21012

cm2

, respectively. This doubling of the drift region charge allows the double

RESURF device to have a drift region resistance that is about one-half that of the single-

RESURF device [28]. There are many extensions of this structure, such as the

implementation of the Linearly Varying Doped p-top layer [29], or the dual conduction

device which makes the p-layer embedded inside the n-drift region [28]. All these

structures require accurate charge control since variation of charge balance may lead to

lower breakdown voltage causing limitations on the device performance [30]. Therefore,

this kind of structure is usually used for very high voltage devices ( a few 100s of volts)

with very long drift region length.

18

(a) (b)

Fig. 1.18 (a) Double RESURF structure with a p-type top layer; (b) double implanted

RESURF with p-type buried layer (PBL).

The double implanted RESURF structure in Fig. 1.18 (b) utilizes the p-type buried layer

(PBL) to ensure full depletion of the n-type drift region so that the doping concentration

of the n-drift region could be increased. The doping concentration of the PBL should be

carefully designed to achieve optimization between Ron,sp and . Here the PBL shares

the same masking layer with the n-drift layer. Comparing with the structure in Fig. 1.18

(a), the structure with the PBL has easier control of charge balance and thus is better for

lower voltage power MOSFETs ( ) with shorter drift region length [31].

1.3 Research Objective and Thesis Organization

The expansion effect will lead the device to a drastic breakdown at the drain. This

restricts the maximum allowable Vds to a lower value as the drain current is increased. In

addition, the generated excess carriers from impact ionization would cause electrical

instability and degrade the reliability of the device [4, 10].

Much effort has been carried out on the explanation and modeling of the expansion effect

[17, 20, 22]. However, there is a lack of discussion on how to effectively suppress this

effect. The objective of this thesis is to provide a systematic approach on how to design a

19

HV EDMOS (less than 100V) with suppressed expansion effect. At the same time, the

breakdown voltage and Ron,sp must also to be optimized. The thermal effect is not taken

into consideration in this thesis and isothermal condition is used throughout all the

simulations.

The basic EDMOS structure used in this work is as shown in Fig. 1.19. A long drift

region is used for sustaining the high drain voltage. The source and body contacts are

integrated together in order to minimize the intrinsic base resistance and improve the

device robustness [10].

Fig. 1.19 Basic device structure used in this thesis for simulation.

This thesis consists of 5 chapters. Chapter 1 gives a brief overview of the research

background and basic modern EDMOS characteristics.

Chapter 2 introduces the effective methods to suppress the expansion effect in EDMOS.

It includes the implementation of a p-body enhancement layer under the source contact,

the n-drift region doping optimization, as well as use of the additional n-drift enhanced

layer and n-buffered drain layer.

Chapter 3 presents the device optimization with suppressed expansion regime. Various

devices parameters will be considered and their impact on the expansion effect will be

explained.

Chapter 4 describes the fabrication process design for the optimized device. Experimental

results will also be discussed.

Chapter 5 presents the conclusions and suggestions for future work.

20

Chapter 2

Methods to Suppress the Expansion Regime

in EDMOS

This chapter describes the most effective methods to suppress the expansion regime in

EDMOS. The contents are organized as follows: Section 2.1 introduces the method of

inserting a p-body enhancement layer. Section 2.2 presents the design procedures for

double implanted RESURF and how it could minimize the impact ionization effect while

minimizing Ron,sp. Section 2.3 is dedicated to the implementation of additional n-drift

enhanced layer and n-buffered layer. Finally, chapter summary will be provided in

Section 2.4.

2.1 P-body Enhancement Layer

The p-body enhancement (PBE) layer was first introduced to prevent the parasitic BJT

from turning on [32]. It was also found that through proper design of the PBE layer, the

expansion effect could be greatly alleviated [25].

Fig. 2.1 EDMOS structure with p-body enhancement layer to reduce the base resistance

of the parasitic BJT.

As shown in Fig. 2.1, the PBE layer with much higher doping concentration compared to

the p-body could greatly reduce the base resistance of the parasitic BJT and hence reduce

the bias between the base and emitter (p-body and n+ source) junction. In such case, the

21

parasitic BJT would not turn on until the base current becomes very large. Therefore, the

snapback effect can be completely eliminated, as shown in Fig. 2.2.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

0.0025

0.0030

Original device w/o PBE

PBE dose 1e14cm-2

PBE dose 2e14cm-2

PBE dose 4e14cm-2

Fig. 2.2 Ids vs. Vds curves with Vgs = 6V (PBE implant energy = 300keV).

From Fig. 2.2, it is obvious that with higher PBE dose, the suppression of the expansion

phenomenon is more effective. This is because the lower the base resistance, the harder

for the parasitic BJT to turn on. This suppresses the impact ionization effect inside the

drift region and the current hump is mitigated. Fig. 2.3 shows that with the presence of

the PBE layer, the impact ionization rate is reduced both at the channel edge and the

drain edge. As a result, there will be fewer electrons and holes generated in the drift

region due to impact ionization (see Fig. 2.4).

(a) (b)

Fig. 2.3 Impact ionization rate spatial distribution with Vgs = 6V and Vds = 50V (a)

without and (b) with the PBE layer (PBE dose = 41014

cm2

).

22

Vgs=6V and Vds=50V


0.5 1.0 1.5 2.0 2.5

Co

ncen

tra

tion (

cm

-3)

0.0

2.0e+16

4.0e+16

6.0e+16

8.0e+16

1.0e+17

1.2e+17

1.4e+17

1.6e+17

1.8e+17

Electron concentration for device w/o PBE

Hole concentration for device w/o PBE

Electron concentration for device with PBE

Hole concentration for device with PBE

Fig. 2.4 Electron and hole concentrations at x = 5µm (center of the n-drift region) cutline

with PBE (dose is 41014

cm2

) and without PBE.

The impact of the PBE doping has on the breakdown voltage of the device is as

illustrated in Fig. 2.5. With the increase in the PBE dose, the breakdown voltage is

slightly decreased. Further increase in the PBE dose does not seems to have any impact

on the breakdown voltage. It is already well known that higher PBE dose is better for the

suppression of the expansion effect. However, when the PBE dose is very high, several

side effects will arise. First, the extremely high boron dose (in the order of 1014

cm2

or

higher) will cause severe crystalline damage to the substrate and result in un-predictable

out-diffusion of the boron profile. The detail of this effect will be introduced in the

subsequent fabrication design chapter. Second, the high doping concentration of the PBE

layer will increase the electric field at the p-body/n-drift junction considerably. This will

cause the breakdown location of the EDMOS to shift from the bulk region to the p-

body/n-drift junction under the gate. This will give rise to numerous reliability issues.

Finally, the high PBE dose will increase the Vth drastically. As a result, the NLDD (n-

lightly doped drain) dose needs to be increased and a Vth adjustment implantation step

may need to be added in order to achieve proper Vth value. From Fig. 2.2 it is can also be

seen that even with a high PBE dose of 41014

cm2

, the expansion phenomenon is still

obvious when Vgs = 6V.

23

Vds (V)

0 20 40 60 80 100

Ids (

A/

m)

1e-15

1e-14

1e-13

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

Original device w/o PBE

PBE dose 1e14cm-2

PBE dose 2e14cm-2

PBE dose 4e14cm-2

Fig. 2.5 Ids vs. Vds with Vgs = 0V.

Nevertheless, the implantation energy of the PBE layer could also be adjusted to achieve

better control of the expansion effect. As shown in the Fig. 2.6, when the implant energy

is reduced to 200keV, the expansion effect seems to be greatly suppressed. However,

both the Vth and Ron,sp are increased considerably at the same time. One possible solution

is to increase the NLDD doping or using Vth adjutstment implant to balance the high

concentration of boron near surface. However, this will cause the expansion effect to

deteriorate again. The optimization of the p-body region will be discussed in Chapter 3.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

0.0025

0.0030

PBE implant energy is 200keV



Fig. 2.6 The Ids vs. Vds curves with Vgs = 6V (PBE implant dose = 41012

cm2

).

24

It can be concluded that with the PBE layer alone, it is impossible to completely

eliminate the expansion effect without degrading the other performance of the device.

Therefore, other methods are needed to further optimize the device.

2.2 N-drift Region Design Using Double Implanted RESURF

With the p-substrate doping concentration at around 81014

cm3

, the relationship between

the breakdown voltage and the n-drift dose for the single RESURF case can be obtained

as shown in Fig. 2.7.

Breakdown Voltage vs. N-drift Dose

N-drift Dose (cm-2

)

6.0e+11 8.0e+11 1.0e+12 1.2e+12 1.4e+12 1.6e+12 1.8e+12 2.0e+12 2.2e+12

Bre

akd

ow

n V

olta

ge

(V

)

64

66

68

70

72

74

76

Breadkown location is at drain edge near surface

Breakdown location is at channel edge near surface

Fig. 2.7 Breakdown voltage vs. n-drift dose for single RESURF EDMOS structure.

Due to the low doping concentration in the p-substrate, bulk breakdown cannot be

achieved no matter how the n-drift dose is varied. When the n-drift dose is too low, the

peak electric field will be at the drain edge under the bird’s beak of the n-drift region.

When the n-drift dose is getting higher, the peak electric field will shift to the surface at

channel edge adjacent to the n-drift region. From Fig. 2.7, it can be observed that for the

maximum breakdown voltage, the n-drift dose is around 1.51012

cm2

. The breakdown

location is at channel edge under the gate electrode which will cause severe reliability

issues at high operating voltage. The spatial distribution of the electric field upon

breakdown for different n-drift dose is as shown in Fig. 2.8.

25

(a) (b)

Fig. 2.8 Electric field contour plots upon breakdown with (a) n-drift dose of 11012

cm2

and (b) n-drift dose of 21012

cm2

.

To provide an extra degree of design freedom, the double implanted RESURF structure is

implemented. This structure could achieve better trade-off between Ron,sp and the

breakdown voltage. At the same time, bulk breakdown becomes possible. The p-buried

layer (PBL) is obtained through ion-implantation and it shares the same masking layer as

n-drift region. The PBL could also be realized in the form of an epi layer with higher

doping than the p-substrate. However, the ion-implantation approach is more cost

effective. The device structure is as illustrated in Fig. 2.9.

Fig. 2.9 A double implanted RESURF EDMOS structure.

26

The idea of inserting the PBL layer was previously introduced to fully deplete the upper

n-drift layer and thus increase the n-drift doping concentration in a 7-30V EDMOS

application [31]. By optimizing the RESURF charge, the Ron,sp could be greatly reduced.

However, with the increase of the PBL dose, the breakdown voltage will be degraded.

As shown in Fig. 2.10, when the PBL dose is increased to 21012

cm2

, the maximum

breakdown voltage achievable is only 56V. When compared to the case where the PBL

dose is 51011

cm2

, the highest breakdown voltage could be 72V. As can be seen from

Fig. 2.12, the addition of PBL layer would make the expansion effect more obvious.

Fig. 2.10 Breakdown voltage vs. n-drift dose with varying PBL dose. Here the

implantation energy for n-drift is 300keV and for PBL is 800keV.

However, when compared with the single RESURF condition, as shown in Fig. 2.2 where

the n-drift dose is selected to be 11012

cm2

to avoid surface breakdown under the gate,

the suppression on the expansion effect is greatly improved with double implanted

RESURF structure. The on-state current is also greatly increased, indicating a lower on-

state resistance at the same time. In addition, the existence of PBL layer ensures bulk

27

breakdown even with n-drift implant dose greater than 1.51012

cm2

as shown in Fig.

2.10. Therefore, it can be concluded that the double implanted RESURF structure is

superior to the single RESURF structure in this case from the aspect of breakdown

voltage, Ron,sp and expansion effect control.

Ron,sp vs. PBL implant dose

PBL dose (cm-2

)

0.00 5.00e+11 1.00e+12 1.50e+12 2.00e+12 2.50e+12 3.00e+12

Ro

n,

sp

(mm

m2)

100

150

200

250

N-drift dose is 1.5e12cm-2




Fig. 2.11 Ron,sp vs. PBL dose with varying n-drift dose. Here the implantation energy for

n-drift is 300keV and for PBL is 800keV.

Fig. 2.11 illustrates the trend of Ron,sp with PBL and n-drift implant dose variations. It can

be seen that the PBL dose does not have significant impact on Ron,sp and the higher the n-

drift dose, the smaller the Ron,sp. This can be easily understood since higher n-drift dose

basically provides more conducting electrons, lowering the resistance of the drift region.

Based on this conclusion, the optimized combination of n-drift and PBL would be

31012

cm2

and 1.51012

cm2

, respectively. The resulting breakdown voltage is 68.5V

with bulk breakdown. The IV characteristics at Vgs = 6V can be found in Fig. 2.12 (the

line with red square symbol). The control of expansion effect is much better but still

needs to be improved. The Ron,sp obtained based on this selection is 95mΩmm2, which is

28

still a bit high. Therefore, a new structure will be proposed in the next section to further

improve the device performance.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

PBL dose is 1.5e12cm-2



Without PBL implant

Fig. 2.12 Ids vs. Vds curves with different PBL implant doses (n-drift dose = 21012

cm2

at

300keV. The PBL implantation energy is 800keV).

2.3 Additional N-drift Enhanced Layer and N-buffered Layer

Fig. 2.13 Double implanted RESURF EDMOS structure with an n-drift enhanced layer

and an n-type buffered drain layer.

29

The new proposed structure is as shown in Fig. 2.13. A shallow n-drift enhanced (NDE)

layer and n-type buffered drain (NBD) layer are added to the n-drift region.

2.3.1 N-Drift Enhanced (NDE) Layer

The main purpose of adding the NDE layer is to alleviate the expansion effect and

meanwhile to further reduce the on-state resistance.

The NDE layer is designed to be under the field oxide throughout the n-drift region, thus

it is sharing the same masking layer as n-drift implant and PBL implant. Ideally, the NDE

layer should be shallow and with high doping concentration (The implantation angle of

the NDE layer is chosen to be 45° and implantation energy is set to be only 50keV).

However, since it has to be implanted before the field oxidation step, the subsequent

thermal budget, which includes the oxidation, annealing etc., would make shallow NDE

layer difficult to obtain. The optimized n-type doping profile of the n-drift region can be

found in Fig. 2.14. Instead of forming an abrupt junction, the NDE and n-drift doping

profiles merge into a steep profile.

Phosphorus doping profile along the center of n-drift region


1 2 3 4

Co

nce

ntr

atio

n (

cm

-3)

0

2e+16

4e+16

6e+16

8e+16

1e+17

Without the NDE implant

With NDE implant of 3e12cm-2

and 60keV

Fig. 2.14 Phosphorus doping profile along the cutline at x = 5µm (around the center of

the n-drift region) with and without the NDE implantation.

30

With the properly designed NDE implantation, the expansion effect could be further

alleviated, as shown in Fig. 2.15. The reason for this is that the NDE layer greatly

increases the doping concentration along the surface of the n-drift region. This alters the

surface electric field distribution. As it can be seen from Fig. 2.16, with the insertion of

the NDE layer, the peak electric field at the drain edge is reduced while the electric field

at the channel edge is slightly increased; the effect is the same as the one shown in

Fig.1.16 when the n-drift layer dose is varied for the RESURF condition optimization.

Here in this case, the drain edge is the location where the electric field and the impact

ionization rate are highest. Therefore, the NDE effectively reduced the electric field at

this hot spot and the impact ionization effect is suppressed. In addition, this NDE layer

mainly alters the charge distribution at the surface, thus the breakdown voltage of the

vertical diode will not be degraded significantly.

Fig. 2.17 illustrates the electron and hole concentrations at high Vgs and Vds condition

with and without NDE implantation. It is clearly shown that the impact ionization

generated hole concentration is decreased by more than 40% with the addition of NDE

layer, which means that the impact ionization rate at the drain edge is greatly reduced.

From Fig. 2.15 it can be inferred that the higher the NDE implant dose, the greater

suppression on the impact ionization effect could be achieved. However, there is an upper

limit for the NDE dose for any fixed combination of PBL and n-drift implantation

condition based on the charge balance theory. When the NDE dose is too high it might

cause surface breakdown which is detrimental to the device. As shown in Fig. 2.18, when

the NDE dose reaches 41012

cm2

, the breakdown location will shift from bulk to the

surface region at the channel edge. Therefore, the NDE implantation dose should be

carefully controlled to avoid surface breakdown.

31

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

NDE dose is 1e12cm-2



Without NDE implant

Fig. 2.15 Ids vs. Vds curves for different NDE dose conditions (implantation energy for

NDE layer = 50keV).


0 2 4 6 8

Ele

ctr

ic F

ield

(V

/cm

)

0

1e+5

2e+5

3e+5

4e+5

Without NDE implant

With NDE implant of 4e12cm-2

Fig. 2.16 Electric field along the x-direction with Vgs = 6V. The cutline is under the

LOCOS as shown in Fig. 1.11.

32

Fig. 2.17 Electron and hole concentration along x = 5µm (center of the n-drift region)

cutline with NDE (dose = 31012

cm2

at 50keV) and without NDE.

Breakdown Voltage & Ron,sp vs. NDE Dose

NDE Dose (cm-2

)

0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12

Bre

akd

ow

n V

olta

ge

(V

)

45

50

55

60

65

70

75

Ro

n,

sp

(mm

m2)

80

100

120

140

Breadkown location is at bulk


Ron,sp

Fig. 2.18 Breakdown voltage and Ron,sp vs. NDE implantation dose (implantation energy

for NDE layer = 50keV, n-drift implant is 21012

cm2

at 300keV, and PBL implant is

1.51012

cm2

at 800keV).

Vgs=6V and Vds=50V


0.5 1.0 1.5 2.0 2.5

Conce

ntr

atio

n (

cm-3

)

0.0

2.0e+16

4.0e+16

6.0e+16

8.0e+16

1.0e+17

1.2e+17

Electron concentration for device w/o NDE

Hole concentration for device w/o NDE

Electron concentration for device with NDE

Hole concentration for device with NDE

33

Another benefit of adding the NDE layer is that it could reduce the Ron,sp. This can be

easily understood since the increase in the concentration of the n-type dopants could

increase the conductivity of the drift region. This is in fact the largest contribution to the

total resistance as demonstrated in Fig. 2.19. However, when the NDE dose is increased

beyond a certain limit (41012

cm2

, from Fig. 2.18), Ron,sp could not be further reduced.

This is due to the fact that when the free carrier concentration is too high, the carrier

mobility will be greatly degraded. According to the equation below, conductivity is

proportional to the product of mobility and carrier concentration.

(2.2)

Therefore, the NDE dose needs to be carefully selected to suppress the expansion effect,

as well as to optimize the breakdown condition and Ron,sp.

L-drift (m)

2 3 4 5 6

Ro

n, sp (

mm

m2)

0

20

40

60

80

100

120

140





Without NDE implant

Fig. 2.19 Specific on-resistance profile along the surface of the EDMOS during on-state

(Vgs = 5V and Vds = 5V).

34

2.3.2 N-type Buffered Drain (NBD)

The region under the LOCOS bird’s beak near the drain contact always has very high

electrical field at high Vds condition due to the triangular shape of the oxide. This high

electrical field is the origin of the detrimental impact ionization effect. The N-type

Buffered Drain (NBD) layer is basically a buffered layer around the drain region with

moderate increase in the doping concentration under the bird’s beak. This enhances the

conductivity and the E-field under the bird’s beak is decreased. This could alleviate the

expansion regime to some extent, as can be seen from the Fig. 2.20.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

Without NBD implant

NBD dose is 1e13cm-2

Fig. 2.20 Ids vs. Vds curves with and without NBD implant at Vgs = 6V. The NBD implant

is performed at an angle.

Distance along the cut line (m)

0.0 0.1 0.2 0.3 0.4 0.5 0.6

Ele

ctr

ic fie

ld (

V/c

m)

0.0

5.0e+4

1.0e+5

1.5e+5

2.0e+5

2.5e+5

3.0e+5

3.5e+5

Without NBD doping

NBD dose 1e12cm-2

NBD dose 1e13cm-2

Fig. 2.21 Electrical field along the specified cut line for different NBD implants.

35

The NBD layer could be implemented after the NDE implant to achieve a graded doping

profile through the thermal annealing process. It can also be implemented after the n+

source/drain implant with a much higher dose since there is not much thermal budget

afterwards. The NBD layer has its own lithography mask which is slightly larger than the

drain region. The implantation angle of NBD is designed to be 45° and the implant

energy is only 100keV to make it a shallow layer. The higher the NBD dose, the lower

the Ron,sp and the lower the breakdown voltage. In addition, heavier NBD dose does not

necessarily provide better control of the expansion effect. Therefore, the NBD layer dose

needs to be carefully designed through numerous simulations.

Breakdown Voltage & Ron,sp vs. NBD Dose

NBD Dose (cm-2

)

0.0 5.0e+12 1.0e+13 1.5e+13 2.0e+13 2.5e+13 3.0e+13 3.5e+13

Bre

akd

ow

n V

olta

ge

(V

)

45

50

55

60

65

70

75

Ro

n, sp

(mm

m2)

80

100

120

140

Breadkown voltage

Ron,sp

Fig. 2.22 Breakdown voltage and Ron,sp vs. NBD implantation dose (NBD implantation

energy = 100keV).

2.4 Chapter Summary

This chapter presented some of the key design methods to control the expansion effect in

the conventional EDMOS.

Inserting the p-body enhancement (PBE) layer was mentioned in some previous work to

effectively suppress the turn on of the parasitic BJT and the subsequent impact ionization

effect. It is demonstrated that increasing the PBE dose or decreasing the PBE implant

36

energy could have better suppression of the expansion effect. However, the PBE dose

cannot be too high in order to prevent the unwanted out diffusion of the boron. This

would cause the threshold voltage to be extremely high and breakdown location to be

moved to be under the gate. The decrease in the PBE implant energy will also increase

the threshold voltage and decrease the on-state current flow.

A double implanted RESURF structure is implemented to achieve the best trade-off

between breakdown voltage and Ron,sp. The inserted P-buried layer (PBL) shifts the

breakdown location to be in the bulk under the drain.

The n-type drift enhanced (NDE) layer is introduced to further suppress the expansion

effect as well as to decrease Ron,sp. The simulation results demonstrated that this method

is very effective. The NDE layer is designed to be a very thin and highly doped layer

under the field oxide which is sharing the same masking layer as the n-drift. The dose of

the NDE layer should be carefully chosen to achieve the optimized breakdown voltage

and Ron,sp.

Another possible way to alleviate the expansion effect is to add the n-type buffered drain

(NBD) layer around the drain region to reduce the electrical field under the bird’s beak of

the LOCOS field oxide. As a result the impact ionization rate is reduced and the

expansion effect is alleviated. However, this method is not as effective as the NDE layer.

37

Chapter 3

Device Optimization with Expansion Regime

Suppression

In the previous chapter, several effective ways to suppress the expansion regime in the IV

characteristics of the EDMOS are discussed and a new structure is proposed. However,

there are many other factors in this device structure which could affect the expansion

effect. This chapter will provide a systematic approach to complete the design of the

EDMOS. Various device parameters will be taken into consideration to suppress the

expansion effect.

3.1 P-body Region Design

The formation of the p-body region includes the p-body implant, PBE implant,

HV_NLDD implant and LV_NLDD implant. In the previous chapter, the effect of adding

the PBE implant has already been discussed. In this section, the design methodology of

the three remaining implantation steps will be introduced.

Fig. 3.1 Illustration of the p-body region in the EDMOS.

3.1.1 P-body Implant

The main purpose of p-body implant is to avoid punch-through between the n+ source

and n-drift region and also to achieve proper threshold voltage. The implantation energy

38

selected for the p-body layer is 80 to 100 keV which is much shallower when compared

to the energy for the PBE implant (200keV~300keV).

Vgs (V)

0 1 2 3 4 5 6

Ids (

A/

m)

0

2e-6

4e-6

6e-6

8e-6

P-body dose is 1e13cm-2




Fig. 3.2 Ids vs. Vgs curves for different p-body dose conditions (Vds = 0.1V).

In Fig. 3.2, the p-body implant energy is fixed at 100keV, the dose is varied from

11013cm

2 to 110

14cm2

. The threshold voltage increases with the dose at first due to the

increased p-type doping concentration near surface. However, when the dose increases

further, the threshold voltage decreases since the heavier dose drives the peak doping

concentration to be deeper. This results in a decrease of dopants near the surface where

the majority n-type carriers flow through.

Breakdown Voltage & Ron,sp vs. P-body Dose

P-body Dose (cm-2

)

0.0 2.0e+13 4.0e+13 6.0e+13 8.0e+13 1.0e+14 1.2e+14

Bre

akd

ow

n V

olta

ge

(V

)

45

50

55

60

65

70

75

Ro

n,

sp

(mm

m2)

80

100

120

140

Breadkown location is at bulk

Ron,sp

Fig. 3.3 Breakdown voltage and Ron,sp vs. p-body implantation dose (implantation energy

for p-body is 100keV).

39

From Fig. 3.3 it can be observed that the dose of p-body implant will not affect the

breakdown voltage when it is controlled within a reasonable range. Ron,sp varies slightly

with the implant dose due to the variation of threshold voltage.

In general, the higher the p-body dose, the better control of the expansion effect due to

the suppression of the parasitic BJT. As shown in Fig. 3.4, this observation is similar to

the effect of varying the PBE implantation. In this case, the lower the implant energy, the

better control of the expansion effect and the higher the threshold voltage.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020




Fig. 3.4 Ids vs. Vds curves at different p-body dose condition (Vgs = 6V).

3.1.2 LDD Implant

There are two LDD implantation steps: LV_NLDD implant and HV_NLDD implant. The

LV_NLDD implant is applied at the same time as for the low voltage CMOS devices, and

it takes place after the gate electrode formation. While the HV_NLDD implant shares the

same masking layer with the p-body/PBE implant and occurs before the poly gate

formation. It diffuses deeper into the channel region and therefore has much more impact

on the device characteristics (see Fig. 3.1).

As discussed in Section 2.1, the location of the peak of the PBE implant has significant

influence on the expansion effect. As can be seen from Fig. 3.5, when the implant energy

40

of PBE is reduced from 300keV to 160keV, the expansion regime is greatly supressed,

but the on-state current and Ron,sp are sacrificed at the same time. Therefore, the

HV_NLDD implant dose needs to be increased in order to maintain the device

performance. Although the heavier doping of HV_NLDD would worsen the expansion

effect, it is still better when compared to the condition with higher PBE implant energy.

Meanwhile, a comparable on-state current could still be achieved.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

HV_NLDD dose is 2e13cm-2

, PBE implant energy is 300KeV







Fig. 3.5 Ids vs. Vds curves for different HV_NLDD dose and PBE implant energy

conditions (Vgs = 6V, PBE dose = 41014

cm2

and HV_NLDD implant energy = 40keV).

Breakdown Voltage & Ron,sp vs. HV_NLDD Dose

HV_NLDD Dose (cm-2

)

1e+13 2e+13 3e+13 4e+13 5e+13 6e+13 7e+13

Bre

akd

ow

n V

olta

ge

(V

)

45

50

55

60

65

70

Ro

n,

sp

(mm

m2)

50

100

150

200

250

Breadkown voltage

Ron,sp

Fig. 3.6 Breakdown voltage and Ron,sp vs. HV_NLDD implantation dose (implant energy

for HV_NLDD = 40keV).

41

As shown in Fig. 3.5, when the HV_NLDD dose increases, the IV characteristics

becomes worse due to the higher current drive which would raise the impact ionization

rate near the drain edge. However, the higher the HV_NLDD dose, the lower the Ron,sp.

As illustrated in Fig. 3.6 and Fig. 3.7, higher HV_NLDD doping could reduce the

resistance in the source side LDD region as more carriers are readily available for

conduction. However, the threshold voltage is lowered, resulting in higher on-state

current. In such case, the design of the HV_NLDD implantation needs consideration with

regard to the trade-off between the expansion effect control and on-state current drive.

L-drift (m)

2 3 4 5 6

Ro

n, sp

(mm

m2)

0

20

40

60

80

100

120





Fig. 3.7 Specific on-resistance profile along the drift region of the EDMOS structure

during on-state for different HV_NLDD implant dose conditions (Vgs = 5V and Vds = 5V).

The energy and tilt angle of HV_NLDD implant only have minor impact on the device

IV characteristics when compared to the implant dose. As for the LV_NLDD implant, it

closely resembles the effect of the HV_NLDD implant, and also with minor impact.

However, since the LV_NLDD implant is already fixed for the low voltage CMOS

device, only HV_NLDD implant can be varied for our design.

42

For a properly designed device, the breakdown voltage is dominated by the drift region. It

can be seen from Fig. 3.6 that within a certain range, the variation of the HV_NLDD dose

will not affect the breakdown voltage.

In conclusion, the design of the p-body region involves the optimization of the PBE, p-

body and NLDD dose, as well as the trade-off between the depth of the PBE implant and

NLDD implant dose. It is possible that there are many different combinations for these

implants to achieve optimized control on suppressing the parasitic BJT and the threshold

voltage values.

3.2 Device Dimensions

In this section, the device dimensions and geometries will be adjusted in order to further

optimize the device. All the dimension parameters are as shown in Fig 3.8.

Fig. 3.8 Device structure with labeled dimensions.

Ldrift represents the drift region length of the n-drift region. Decreasing Ldrift could reduce

Ron,sp but the breakdown voltage will be sacrificed at the same time. In this case, the Ldrift

length must at least 2µm in order to achieve a breakdown voltage of 65V. The effects of

Ldrift variation are as illustrated in Fig. 3.9 and Fig. 3.10. All other device dimensions and

process conditions remain the same as Ldrift is varied. The optimized Ldrift is found to be

2.3µm.

43

Breakdown Voltage & Ron,sp vs. Ldrift Length

Ldrift Length (m)

1.0 1.5 2.0 2.5 3.0

Bre

akd

ow

n V

olta

ge

(V

)

40

50

60

70

80

Ro

n, sp

(mm

m2)

60

80

100

120

140


Breakdown location is at bulk

Ron,sp

Fig. 3.9 Breakdown voltage and Ron,sp vs. Ldrift.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

0.0025

0.0030

Ldrift=1.5m

Ldrift=2.0m

Ldrift=2.3m

Ldrift=2.5m

Fig. 3.10 Ids vs. Vds curves with varying Ldrift (Vgs = 6V).

Lbody indicates the window opening under the gate electrode region where HV_NLDD/p-

body/PBE doses are implanted. This is an important parameter which determines the

channel length as well as the junction between the p-body region and the n-drift region.

From Fig. 3.11 and Fig. 3.12 it can be seen that the smaller the Lbody, the smaller Ron,sp

and the higher on–state current. However, the expansion regime would become worse. In

44

addition, smaller Lbody may also cause surface breakdown at the channel edge due to the

increased n-type doping concentration at the bird’s beak.

Breakdown Voltage & Ron,sp vs. Lbody

Length

Lbody

Length (m)

0.0 0.1 0.2 0.3 0.4 0.5

Bre

akd

ow

n V

olta

ge

(V

)

40

50

60

70

80

Ro

n, sp

(mm

m2)

60

80

100

120

140Breakdown location is at channel edge near surface

Breakdown location is at bulk

Ron,sp

Fig. 3.11 Breakdown voltage and Ron,sp vs. Lbody.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

0.0025

0.0030

Lbody=0.1m

Lbody=0.2m

Lbody=0.3m

Lbody=0.4m

Fig. 3.12 Ids vs. Vds curves with varying Lbody (Vgs = 6V).

45

When Lbody is increased from 0.1µm to 0.4µm, the impact ionization rate at the drain edge

is greatly decreased, as it can be seen in Fig. 3.13. This is confirmed by the amount of

electron-hole pairs generated as illustrated in Fig. 3.14.

Fig. 3.13 Impact ionization rate spatial distribution with Vgs = 6V and Vds = 50V (a) Lbody

= 0.1µm (b) Lbody = 0.4µm.

Vgs=6V and Vds=50V


0.5 1.0 1.5 2.0 2.5

Co

nce

ntr

atio

n (

cm

-3)

0.0

2.0e+16

4.0e+16

6.0e+16

8.0e+16

1.0e+17

1.2e+17

1.4e+17

Electron concentration when Lbody=0.1m

Hole concentration when Lbody=0.1m

Electron concentration when Lbody=0.4m

Hole concentration when Lbody=0.4m


cutline with Lbody = 0.1µm and Lbody = 0.4µm.

In fact, as shown in Fig 3.15, the longer Lbody length shifts the p-body and n-drift junction

to the right and makes the channel length to become longer. As a consequence, the on-

state current is reduced and the IV curve hump is alleviated. In addition, the longer Lbody

makes the doping profile at the p-body/n-drift junction to be steeper, and the average p-

46

type doping concentration at the p-body region is also increased. This results in better

suppression of the parasitic BTJ due to the reduced shunting base-emitter resistance.

Net doping concentration along Y=0.4m cutline


2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

Co

nce

ntr

ation

(cm

-3)

1e+15

1e+16

1e+17

1e+18

1e+19

Lbody=0.1m

Lbody=0.4m

Fig. 3.15 Net doping concentration along y = 0.4µm cutline when Lbody = 0.1µm and Lbody

= 0.4µm.

Lac is the accumulation length of the overlap between n-drift region and the gate

electrodes. Fig. 3.16 and Fig. 3.17 describe the effect of varying Lac on the device

performance based on previous optimized condition. It is clear that the breakdown

voltage remains relatively unchanged as Lac is varied while Ron,sp fluctuates a bit with the

changes in Lac. This demonstrates good stability for this design. As observed before, the

Ron,sp always decreases when Lac increases and the sensitivity is really high.

Nevertheless, the expansion control would be better when the Lac is increased as it can be

seen in Fig. 3.17. In fact, the increase in Lac could make the n-type doping concentration

at the p-body and n-drift junction to be higher. In such case, the electric field at the p-

body and n-drift junction is reduced the impact ionization effect will be suppressed.

However, Lac could not be overly long otherwise the actual channel length would be too

small ( ). There should also be some design margin in

consideration of possible misalignment in the real fabrication process.

47

Breakdown Voltage & Ron,sp vs. Lac Length

Lac Length (m)

0.0 0.2 0.4 0.6

Bre

akd

ow

n V

olta

ge

(V

)

40

50

60

70

80

Ro

n, sp

(mm

m2)

60

80

100

120

140Breakdown location is at bulk

Ron,sp

Fig. 3.16 Breakdown voltage and Ron,sp vs. Lac length (all the other dimension parameters

and process conditions remain the same, and Lbody = 0.3µm, and Lg = 1.2µm).

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

0.0025

0.0030

Lac=0.2m

Lac=0.4m

Lac=0.6m

Fig. 3.17 Ids vs. Vds curves with varying Lac length (Vgs = 6V).

48

3.3 Summary

This chapter first described the p-body region design, which mainly includes the p-body

implant and the LDD implant, as well as the PBE implant which was introduced in the

previous chapter. It is found that the effect of the p-body implantation resembles that of

the PBE implantation. For example, the larger the dose or the shallower the implant

energy, the better the suppression of the parasitic BTJ. The variation of both the PBE and

p-body implant steps do not have any significant impact on the breakdown voltage or

Ron,sp of the device. While for the LDD implant, the higher the implant dose, the smaller

the Ron,sp. Meanwhile the expansion effect becomes worse with increased LDD dose.

For the optimized design of the p-body region, the desired threshold voltage, the

appropriate on-state current and Ron,sp, as well as suppression of the parasitic BTJ should

all be taken into consideration. Trade-off between the p-type implantation depth and the

LDD dose should be proper managed according to the specific design requirement.

This chapter also documents the impacts of the variation of the device dimensions, which

also serves as a sensitivity check for the so far optimized design. It turns out that the

sensitivity is well under control, within a reasonable range.

In the next chapter, the device fabrication design and the experimental results will be

presented and analyzed.

49

Chapter 4

Device Fabrication and Experimental Results

This chapter focuses on the process development for the designed EDMOS with

suppressed expansion effect as well as optimized device performance. The detailed

fabrication schemes for the optimized EDMOS will be described. In addition, the

experimental electrical measurement results will be presented, and the performance

advantage of the proposed EDMOS structure over the conventional EDMOS will also be

verified experimentally.

4.1 Low Side Device Fabrication Design

The process design for the low side device is based on a 0.35µm CMOS technology

developed by AKPD (Asahi Kasei EMD). The fabrication steps are compatible with the

standard CMOS flow.

Fig. 4.1 illustrates a condensed flow chart for the conventional n-channel EDMOS

process. While the proposed n-EDMOS fabrication process needs just one extra masking

layer for the NBD implantation, and a few more implantation steps (PBL implant and

NDE implant share the same mask with the n-drift implant, PBE implant and HV_NLDD

implant share the same mask with the p-body implant). Originally, there was no

HV_NLDD implant, only LV_NLDD implant step is implemented. The device structure

is as shown in Fig. 4.2 (a). Although the LV_NLDD implant is self-aligned to the gate

electrode, it is verified by experimental results that this structure would cause large

variation of the threshold voltage over the wafer, especially when the dimension of Lbody

is small. However, when HV_NLDD implant step is added, the variation of the threshold

voltage is narrowed even with shorter channel. Another reason for introducing the

HV_NLDD, as explained in Section 3.2, is the fact that the LV_NLDD is already fixed

for the low voltage CMOS devices. Since the threshold voltage of the n-EDMOS would

be too low with only the LV_NLDD implant due to the high PBE implant dose, the

addition of a HV_NLDD step is essential to achieve proper Vth and Ron,sp.

50

Fig. 4.1 Process steps for n-EDMOS fabrication in 0.35µm CMOS technology.

51

(a) (b)

Fig. 4.2 Device structures with (a) LV_NLDD implant only and (b) both LV_NLDD

implant and HV_NLDD implant.

4.1.1 Thermal Budget Control

Thermal budget is defined as the total amount of thermal energy applied to the wafer

during a given elevated temperature treatment. It is proportional to the temperature and

the duration of the thermal process. Low thermal budget is desired in deep sub-micron

and nanometer scale VLSI manufacturing to prevent dopant redistribution, and to reduce

excessive stress between various deposited layers which may cause wafer warp.

The dopant redistribution is one of the major concerns in the EDMOS fabrication process.

In this design, the PBE implant dose is very high (41014

cm2

). Any excessive thermal

budget would cause the boron’s out-diffusion to become un-predictable. Therefore, the

thermal budget needs to be precisely controlled in this case. In addition, the detailed

thermal budget design should be based on experimental trials and extensive process

simulations.

4.1.2 Calibration of the Diffusion Model

The process simulation tool used in this thesis is Tsuprem4. The simulation model needs

to be calibrated based on experimental SIMS data. By adjusting the diffusion and

segregation coefficients for specific dopants in Tsuprem4, we can fit the simulation

doping profile to the experimental SIMS data very well. This procedure is essential in

improving the accuracy of process simulation. The parameters which were modified to fit

52

the actual boron diffusion profile are listed in Table 4.1; and the simulation results before

and after model calibration comparing to the SIMS data for the boron implantation are

illustrated in Fig. 4.3. The original diffusion model for phosphorus is already good

enough to fit the actual SIMS data as shown in Fig. 4.4, therefore nothing is changed for

phosphorus.

Table 4.1 Parameters Modified for Boron Diffusion Model Calibration.

Depth (um)

0.5 1.0 1.5 2.0 2.5

Bo

ron

Co

nce

ntr

ation

(a

tom

s/c

m3)

1e+14

1e+15

1e+16

1e+17

1e+18

1e+19

SIMS

Simulation data before model calibrarion

SImulation data after model calibrarion

Fig. 4.3 Boron implantation SIMS and simulation data (before and after calibration).

Parameter Calibrated Value Definition

DIX.0 2108 (µm

2/min)

The pre-exponential constant for diffusion with

neutral interstitials

DIX.E 2.98 (µm2/min)

The activation energy for diffusion with neutral

interstitials

SEG.0 1.13103

The pre-exponential factor for segregation at

Si/SiO2 interface

SEG.E 0.96 The activation energy for segregation at Si/SiO2

interface

53

Depth (um)

0 2 4 6 8 10 12 14 16

Ph

osp

hu

rus C

on

ce

ntr

atio

n (

ato

ms/c

m3)

1e+14

1e+15

1e+16

1e+17

SIMS

Simulation

Fig. 4.4 Phosphorus implantation SIMS and simulation data (The model is accurate

without calibration).

In practice, the diffusion model should be calibrated based on different dose conditions

(i.e., in the order of 11012

cm2

, 11013

cm2

or 11014

cm2

) to ensure the accuracy.

4.1.3 Simulation Results

Table 4.2 and Table 4.3 list all the detailed implantation conditions and the key device

dimension parameters for one of the optimized device designs. The target here is to

design an EDMOS with breakdown voltage higher than 65V and threshold voltage is

around 1.3V. At the same time, the Ron,sp should be minimized and the expansion regime

is suppressed as much as possible.

‘Q’ in the last column indicates quad implant. A quad implant is done by dividing the

desired dose into four equal portions, and then repositioning the wafer between each

implantation segment (rotate by 90o every time). This could alleviate the shadowing

effects resulting from implantation with large tilt angles. It also features giving the

symmetry of the zero tilt implant without the associated axial channeling [33].

54

Table 4.2 Ion Implant Conditions of the designed EDMOS.

Table 4.3 Key Dimensions of the designed EDMOS.

unit Ldrift Lg Lbody Lac Lfp

(µm)

Fig. 4.5 Ids vs. Vds curves for different Vgs conditions.

Vds (V)

0 20 40 60 80

Ids (

A/

m)

0.0000

0.0005

0.0010

0.0015

0.0020

Vgs=2V

Vgs=4V

Vgs=6V

Process Dopant Dose (cm2

) Energy (keV) Tilt/Rotation Angle (o)

PBL Boron

n-drift Phosphorus

NDE Phosphorus

NBD Phosphorus

p-body Boron

PBE Boron

HV_NLDD Arsenic

LV_NLDD Phosphorus

N+ source/drain Arsenic

p+ contact BF2

55

Fig. 4.5 to Fig. 4.8 shows the simulation results for the proposed design using Tsuprem4

and Medici. It can be seen that the threshold voltage is 1.3V (Fig. 4.6), and the

breakdown voltage is 72V (Fig. 4.8). The breakdown location is in the bulk, as shown in

Fig. 4.9, the peak E-field upon breakdown is at the junction of the n-drift and PBL. The

Ron,sp is calculated from Fig. 4.7: The on state current is 3.8104

A/µm at Vds = 0.5V and

Vgs = 5V, the area is 5.1µm 1µm (In the 2-D simulation the width of the device is

always 1µm and the length measured from the center of the body contact to the center of

the drain contact is equal to 5.1µm). The simulated Ron,sp is calculated to be 67mΩmm2.

Fig. 4.6 Ids vs. Vgs curve with Vds =0.1V.

Fig. 4.7 Ids vs. Vds curve for Vgs =5V.

Vds=0.1V

Vgs (V)

0 1 2 3 4 5 6

Ids (

A/

m)

0

2e-6

4e-6

6e-6

8e-6

1e-5

Vgs=5V

Vds (V)

0.0 0.1 0.2 0.3 0.4 0.5

Ids (

A/

m)

0.0000

0.0001

0.0002

0.0003

0.0004

56

Fig. 4.8 Ids vs. Vds curve with Vgs =0V.

Fig. 4.9 Electric field contour plot upon breakdown at Vds = 72V.

Vgs=0V

Vds (V)

0 20 40 60 80

Ids (

A/

m)

1e-16

1e-15

1e-14

1e-13

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

Breakdown

Location

57

4.2 Experimental Results and Discussion

The experiment data for the simulated design will be presented in Section 4.2.1. The

effect of varying the Ldrift will be demonstrated in Section 4.2.2. Finally, Section 4.2.3

will describe the impact of variation of selected implant doses on the expansion effect.

4.2.1 Threshold Voltage and IV Characteristics

Fig. 4.10 to Fig. 4.12 shows the output characteristics of the fabricated EDMOS with Ldrift

= 2.3µm. The comparison between the measured device performance data and the

simulation results are summarized in Table 4. 4.

Fig. 4.10 Measured Ids vs. Vgs curve.

Fig. 4.11 Measured Ids vs. Vds characteristic with Vgs varied from 2V to 6V.

Vgs increases

58

Fig. 4.12 Measured breakdown voltage with Vgs =0V.

Table 4.4 Key Device Performance Parameters Comparison.

Vth (V) (V) Ron,sp ( )

Simulation 1.3 72 67

Experiment 2 75 54.8

From Table 4.4, it can be seen that the experimentally obtained breakdown voltage is

comparable to the simulation result. However, the threshold voltage is still too high. It is

suspected that the excessive out-diffusion of the PBE implant dopants maybe the main

cause for this discrepancy. During the model calibration, only SIMS data for relative

lower implantation dose are available. Therefore, the SIMS calibration may not be

suitable for heavy implant dose condition. One possible solution is to add a Vth

adjustment implantation step to reduce Vth.

The measured Ron,sp value is lower than the simulated data. This is mainly due to the

layout configuration implemented as shown in Fig. 4.13. In this experiment, the finger

length (or gate channel width) is 40µm and single finger structure is used. The half pitch

size is reduced by putting source and drain contact in an alternating arrangement.

Therefore, the effective device area is reduced. Another reason that may cause higher

simulated resistance is the inaccurate diffusion model for the heavy boron implant dose

condition, which would make it difficult to properly predict the actual IV characteristics.

59

Fig. 4.13 Layout design for the proposed EDMOS.

The IV characteristics up until the breakdown voltage for different Vgs conditions are as

shown in Fig. 4.14. It can be observed that there is no sign of the expansion regime till

Vgs = 5.5V. When Vgs = 6V, a slight hump appears as Vds exceeds 30V. The starting point

of the expansion regime is in agreement with the simulation results shown in Fig. 4.5.

However, the experimental result is much better than the simulation results regarding the

expansion regime suppression due to self-heating. This effect is not modelled in the

simulation.

60

(a) (b)

Fig. 4.14 Ids vs. Vds curves with (a) Ldrift = 2µm and (b) Ldrift = 2.3µm.

4.2.2 Effect of Ldrift Variations

The Ldrift length is varied in the experiment without changing any other device

dimensions and process conditions. Some of the electrical measurement results, including

the breakdown voltage, Ron,sp, Vth as well as the IV characteristics are as shown in Fig.

4.15 to Fig. 4.17.

Breakdown Voltage & Ron,sp vs Ldrift length

Ldrift Length (m)

1.0 1.5 2.0 2.5 3.0

Bre

akd

ow

n V

olta

ge

(V

)

40

50

60

70

80

90R

on

, sp

(mm

m2)

30

40

50

60

70

80

Breadkown Voltage

Ron,sp

Fig. 4.15 Measured breakdown voltage and Ron,sp vs. Ldrift variation.

61

Ldrift Length (m)

1.0 1.5 2.0 2.5 3.0

Th

resh

old

Vo

lta

ge

(V

)

1.7

1.8

1.9

2.0

2.1

2.2

Fig. 4.16 Measure threshold voltage vs. Ldrift variation.

Fig. 4.17 Ids vs. Vds with Vgs = 5.5V as Ldrift is varied.

The breakdown voltage and Ron,sp are found to decrease as Ldrift is reduced. The decrease

of breakdown voltage with Ldrift follows a rate of 20V/µm. This is in agreement with the

simulation results in Section 3.2. Other than this, the threshold voltage and the control of

the expansion effect almost hold the same when Ldrift is scaled. Since the design target is

only 65V for the breakdown voltage, smaller Ldrift length could be used to achieve smaller

Ron,sp. In this case, Ldrift = 2µm could be selected, with = 70V and Ron,sp of only

48mΩmm2, while there is no expansion regime till Vgs = 5.5V.

62

4.2.3 Effect of Implant Dose Variations

Fig. 4.18 Ids vs. Vds curves for varying PBE implant dose.

Fig. 4.19 Ids vs. Vds curves for varying n-drift dose and NDE dose.

The effect of dose variations for key implantation steps were verified experimentally. As

shown in Fig. 4.18, the increase in PBE dose would result in better suppression of the

expansion effect due to the decrease in the base-emitter resistance of the parasitic BJT, as

predicted by simulation in Section 2.1. In this design, the PBE dose must be at least

4 1014

cm-2

to completely eliminate expansion regime up to Vgs = 5.5V. However, when

the PBE dose is increased, the current drive is decreased due to the increased Vth.

Fig. 4.19 shows that if either n-drift or NDE dose is increased, the expansion effect could

also be alleviated, this is because of the increase in the n-type dopants concentration

improves the charge balance in this case and the peak electric field at the drain edge is

reduced. Therefore the impact ionization effect is suppressed.

63

4.4 Summary

This chapter provides the fabrication process flow, as well as the simulated electrical

characteristics for the optimized low side EDMOS.

The optimized design for the low side EDMOS is verified experimentally. A 70V

EDMOS with Ron,sp of 48 and no expansion effect until Vgs = 5.5V is

successfully fabricated. However, the threshold voltage is higher than expected due to the

excessive boron out-diffusion. This could be solved by adding a Vth adjustment

implantation step.

The effect of Ldrift variation and dose variation for key implantation steps are also verified

by experiment. The measured results are in good agreement with the simulation.

64

Chapter 5

Conclusions and Future Work

In this thesis, the origin of the expansion effect in the HV EDMOS is investigated, and

effective ways to suppress the expansion effect are introduced and experimentally

verified. In this chapter, a brief summary of the thesis and suggestions for future work are

presented.

5.1 Conclusions

The expansion effect, which refers to the sudden increase of the drain current at high Vds

and Vgs conditions in a EDMOS, is originated from the parasitic BJT structure turning on

due to impact ionization effect. There are several effective ways to suppress the

expansion effect. These include inserting a p-body enhancement (PBE) layer under the

source/body contact; implement the n-drift enhanced (NDE) layer in the drift region and

the n-buffered drain layer (NDB) around the drain contact. The PBE layer is the most

effective way since it could greatly suppress the parasitic BJT structure; followed by the

NDE layer which is also very effective in suppressing the expansion regime as well as in

decreasing Ron,sp. The effect of the NBD layer may not be very obvious but it is effective

in decreasing the electric field around the LOCOS bird’s beak beside the drain region.

The expansion effect would greatly degrade the SOA of the device and may cause

breakdown at lower than expected drain voltage. Therefore, for a proper EDMOS device

design, the expansion effect should be minimized. At the same time, the traditional

requirements such as breakdown voltage and Ron,sp should also be optimized. A double

implanted RESURF structure can be used for the drift region design to achieve the best

trade-off between breakdown voltage and Ron,sp; as well as to ensure bulk breakdown to

avoid reliability issues. In addition, the p-body region design is very important for

supressing the expansion regime. The effects of varying various key device dimensions

should also be taken into consideration to achieve desired device performance.

65

The design procedures for the proposed EDMOS with suppressed expansion regime are

summarized in Table 5.1 below.

Table 5.1 Design Procedures for EDMOS with Expansion Regime Suppression.

The designed process flow for this EDMOS is highly compatible with the conventional

CMOS technology. In this experiment, the low side EDMOS was successfully fabricated

with a 0.35µm process flow. A breakdown voltage of 70V, Ron,sp of 48mΩmm2 and no

expansion effect until Vgs is greater than 5.5 V are observed. Fig. 5.1 compares the results

for this work with some previous published EDMOS structures. It can be seen that the

obtained Ron,sp and BV are very competitive for below 100V applications. Furthermore,

Design Steps Purpose

1 Construct the basic EDMOS structure

2 Insert and optimize PBE layer Eliminate snapback and suppress

parasitic BJT

3 Insert and optimize PBL under n-drift layer

to make double RESURF structure

Achieve bulk breakdown as well

as the best trade-off between

Ron,sp and BV

4 Insert and optimize NDE layer Reduce Ron,sp and suppress the

expansion effect

5 Insert and optimize NBD layer

Reduce the E-field under bird’s

beak of LOCOS and alleviate

expansion effect

6 NLDD / p-body / PBE layer optimization

Achieve proper Vth , and the best

trade-off between on-state

current and suppression of the

parasitic BTJ

7 Device dimensions tuning ( Ldrift, Lac, Lbody ) Device optimization and

sensitivity check

8 Thermal budget design

Avoid unpredictable dopants

redistribution such as the

excessive boron out-diffusion of

the PBE layer

9 Design iteration and optimization Further refinements

66

when compared to the previous work, the proposed design has much better control on the

expansion effect.

Breakdown Voltage (V)

10 100

Ro

n,s

p (

mm

m2)

1

10

100

1000

10000

Previous EDMOS

This work

Si-limit

Fig. 5.1 Ron,sp vs. BV curves for this work and other recently published results [14, 34-37].

5.2 Future Work

Future work may take advantage of new structures or new layout configurations to

further optimize the low side device with suppressed expansion effect at higher Vgs

conditions. New techniques could be explored to achieve better trade-of between the PBE

implantation and the desired threshold voltage. In addition, proper modeling of the boron

diffusion with heavy dose and the self-heating effect could also be taken into

consideration to enable more aggressive fine-tuning of the process.

With the successful design and process development of the low side device, the design of

a high side device that can be integrated onto the same chip could be carried out for

future work. Instead of developing a whole new set of masks and process conditions for a

high side p-channel EDMOS, a floating source high side n-channel EDMOS could share

most of the masks and process conditions with the low side n-EDMOS. This reduces the

process complexity and provides more cost saving. The proposed high side device

67

structure is as shown in Fig. 5.2. Based on the experimental results of the low side device,

the characteristics for the complementary high side device should be very promising.

Fig. 5.2 Proposed high side EDMOS structure.

68

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