ESE570 Fall 2021

University of PennsylvaniaDepartment of Electrical and System Engineering

Digital Integrated Cicruits AND VLSI Fundamentals

ESE570, Fall 2021 HW5: Delay and Layout Sunday, October 3

Due: Sunday, October 10th, 11:59pm

• Problems:

• All problems should use the AMI 0.60u C5N (3M,2P,high-res) technology setup inprevious homeworks.

• For extra Cadence help refer to http://www.seas.upenn.edu/~ese570/manual/manual_1.htm and Piazza. This manual is for the older version of Cadence, but most steps aresimilar to what we are currently using with a different GUI.

1. Using Cadence simulation, we can create a first-order resistive model of a MOS-FET. What is the equivalent source-drain resistance Rds for a W = L = 1.5µmtransistor with Vgs = Vds = Vdd = 5V (NMOS) or Vgs = Vds = −Vdd = −5V(PMOS)? Answer for both NMOS and PMOS transistors.

– Include description of test circuit, circuit schematics, and simulation resultsin homework turnin. Part of the question is designing and understandingyour test setup.

NOTE:

– Circuit schematic: This is a cell of a digital circuit block with defined inputsand outputs.

– Test schematic: This is a cell where the inputs are being set by voltage sourcesto run a simulation testing some functional or performance specificationsof your circuit. (Eg. a transient simulation measuring delay, a transientsimulation measuring power, or a dc simulation generating a VTC, etc.).

– Simullation results: These are the results obtained from the simulation test

– Descriptions: Each of these schematics/results should be accompanied by de-scriptions to explain them. (Eg. What test is being run to measure what?What do the results specify). Annotating the figures/screen shots from ca-dence is highly recommended to show results.

2. From a Cadence simulation, what is the RC time-constant for:

(a) one transistor (W = L = 1.5µm) charging another transistor’s gate input ofthe same size?

(b) a transistor (W = L = 1.5µm) charging the gates of 4 transistors of the samesize?

1

ESE570 Fall 2021

(c) a transistor (W = L = 1.5µm) charging the gate of a single transistor 4 timesthe size of the driving transistor?

(d) How do your answers to (a), (b), and (c) relate?

– Include description of test circuit, circuit schematics, and simulation resultsin homework turnin. Part of the question is designing and understandingyour test setup.

3. Consider our MOS technology with the following parameters:

– VDD = 5V

– −VT0p = VT0n = VT0 = 0.8V

– µn = 530cm2/(V · s) and µp = 200cm2/(V · s)– tox = 14.1nm

– λ = 0

– εox = 3.9ε0.

(a) Using Cadence, design a CMOS inverter (i.e. size the transistors) such thatthe switching voltage, Vth = 1/2VDD. Submit both the schematic and VTCverifying your design.

(b) Using the Vpulse design a test schematic to measure the propagation delayand rise/fall times of your inverter from part (a) with a rail-to-rail input wave-form with a period of 4ns, pulse width of 2ns, and rise/fall times of 10ps. Loadyour inverter with an identical inverter for your delay measurement. Submitthe test schematic, input/output transient waveforms, and your delay mea-surements (propagation and rise/fall times).

Left click Add → Instance select vpulse from NCSU Analog Parts li-brary. Fill the rest of the boxes. The figure below shows the input pulse thatwe have specified is bounded between 0 and 5V. It has an initial delay of 1ns,rise and fall time of 1ps and high/low duration of 2ns.

2

ESE570 Fall 2021

In the Analog Design Environment go to Analyses → Choose... Setthe transient analysis with Stop Time as 8n. We have specified a transientanalysis from 0 to 8ns. Left click Outputs → To be Plotted → Selecton Schematic. Select the input and output of the inverter. Refer to theprevious section, DC analysis, for the necessary steps. The ADE windowshould look like the picture shown below. Run the simulation by pressing onthe green traffic light icon. After few seconds you should be able to see theresults of the transient analyses.

3

ESE570 Fall 2021

Note: Make sure to save your schematic every time before simulation, or youwill get an error.

(c) Design a test schematic to measure the propagation delay of your inverter us-ing a more realistic input. The input should be created by passing the Vpulsefrom part (b) through your inverter from part (a). Your inverter should stillbe loaded with an identical inverter. Submit the test schematic, input/outputtransient waveforms, and your delay measurements (propagation and rise/falltimes).

(d) Measure the avg power over 4 periods using the calculator to plot the averagecurrent through your inverter.

4. Cadence Symbols and Layout This problem is to complete the flow from schematicto layout and verification of your inverter from the previous problem.

(a) For the inverter you designed above, create a corresponding symbol. Submityour drawn symbol and schematic with your homework.

The schematic is almost the same as before. But you need to add pins forthe schematic. Left click Create → Pin. In the Pin Names box type thefollowing pin names: in, out, vdd, gnd. Also change the direction of thepins to input for in, output for out, Input/Output for vdd and gnd. Agood example of schematic is show below. You can define the pin names asyou wish.

4

ESE570 Fall 2021

The symbol editor lets you create a ”black box” description of a cell usinglabels, pins, shapes, notes, and a selection box. Symbols make your designmore readable, as you can use them in more complex designs, instead of indi-vidual transistors. In the Library Manager click once on your own library.Then left click File → New → Cell View. Select schematicSymbol andthe View Name box will be automatically filled with symbol.

Then the Viutuoso Symbol Editor should show up. Then click Create →Shape to build the symbol for your schematic. A good example of symbolis shown below. Then we need to add pins to the symbol. Left click Create

5

ESE570 Fall 2021

→ Pin. In the Pin Names box type the following pin names: in, out, vdd,gnd. Also change the direction of the pins to input for in, output for out,Input/Output for vdd and gnd. Change the type to actHi. You are goingto start placing the pins in the symbol in the order specified in the Pin Namesbox, i.e. first you will place the in pin, then out pin. The pins look a littledifferent from the ones in the schematic, so be careful. You will notice thatit is a box with a line attached. The end of the line will have the pin name.The box is the actual pin, so it must point AWAY from the rest of the symbol.

Next we want to add label to the symbol. Left click Create → Label... Thelast thing to add is a selection box. This will tell the software how much ofthe symbol is actually used. Create → Selection box → automatic. Thesymbol is now finished.

(b) For your inverter, create the corresponding layout. Submit your layout withyour homework.

In Library Manager click File → New → Cell View, select Type to belayout and view will be filled with layout automatically.

6

ESE570 Fall 2021

After you create the layout cellview, Virtuoso Layout Suite L windowshould show up as below. On the left side, you can see a list of all the layersyour can build your mask in and can select between them.

Since we are using the AMI 0.6u technology, we only have an nwell process touse. Thus, the substrate will be a p-type substrate. We can always assume

7

ESE570 Fall 2021

that the background is a p-subtrate. Now we will create a pmos transistorfirst. To do that, we need an nwell layer in which the pmos transistor will beformed.

Note: You may adjust the minimum distance between the grids. In orderto do it, in the Virtuoso Layout Editing window select Options → Dis-play. A new window will open. On that window, change ”Minor Spacing”to a value that you want. In order to work efficiently, you can adjust it to 1lambda which is 0.3 (it is actually 0.3u but in that window it will be writtenas 0.3).

Here are some hotkeys that I have found to be very useful whendesigning layouts:Move about the layout view screen — keyboard arrows (up, down, left, right)Fit entire layout onto screen — fZoom in/out — Ctrl/Shift zCancel previous command — EscReveal all mask layers within each layout cell — Shift f (Use Ctrl f to hidethese layers)Properties — qCreate path — p (Convenient for making interconnections between I/O pinsof layout cell; need to select mask layer first from LSW window)Create rectangle of mask layer — r (Select mask layer first from LSW)Create pin — Ctrl p (Select mask layer first from LSW)Instantiate layout cell — iSelect more than one mask layer simultaneously — Hold down Shift and clickon each layer (Use Ctrl to deselect a particular layer)Undo — uCopy — cDelete — dMove — mStretch — s (Point to edge of mask layer first using mouse cursor)Ruler — k (Erase ruler Shift k)

Select nwell in LSW window, and move cursor to layout window. Type r,just click on the left mouse button to draw the rectangle of n-well region.If you want to change the dimension after drawing, move your cursor to theside where you want to extend or shorten such that the side is highlightedand then type s (stretch). The side will move with your cursor.

Note: The ruler shown below can be invoked by typing k, the numbers rep-resent the length in um (micrometers). You do not have to necessarily followthe dimensions shown below. In fact, it is probably a good idea to play aroundwith the lengths and widths in order to see how small a mask layer you cancreate without violating any of the design rules.

8

ESE570 Fall 2021

Likewise, draw the nselect and pselect layers as shown in the figure below.The pselect is where you are creating the pmos transistor since this is wherethe p+ diffusion is going to be formed. Draw the p+ active layer on yourlayout as shown in the figure below. The orange shaded rectangle is the p+active regions. The green shaded rectangle is the n+ active region. Next,draw the poly layer to form the gate of the transistor. The size of the pmostransistor shown below has W=1.5um and L=0.6um.

Next we need to connect the active regions to metal lines so that they canbe routed. The figure below shows the metal1 layer (blue line-shaded poly-gons) is connected to the active region by an active contact (cc, which issolid black). Remember that the design rule usually restricts the size of thecontact to be 2lambda * 2lambda, which is 0.6u * 0.6u. The nselect createsan n+ diffusion in the nwell. This is the body pin of the pmos transistor,which should be connected to power (vdd). We’ll touch on how to connectto the power supply later.

9

ESE570 Fall 2021

Next, you can proceed to create the nmos transistor but this time your nmosneeds to be created in the nselect layer while the p+ diffusion of the nmosis in the pselect. The size of the nmos chosen in this design has the samedimension as the pmos (channel length 0.6um, width 1.5um). Note that sincewe are using an nwell technology, we don’t need an explicit well for the nmostransistor (the pwell) since the background is p-substrate. The figure belowshows the inverter.

10

ESE570 Fall 2021

The region between the two transistors would be used for pin definitions andfor routing signals from one layout cell to another. The more the distance be-tween the nmos and the pmos transistor, the more connections can be routed

11

ESE570 Fall 2021

and less problems to worry about in the future when designing big cells. How-ever, a large distance may be inefficient and result in a very big layout. Butfor the sake of learning, we would rather choose to go with a large distanceof around 15um.

The gate of the transistors needs to be connected to the metal1 lines for it tobe accessed. To do that there are some ready-to-use macros available for mak-ing contacts. To access a macro cell which has a poly-metal1 combo with asingle contact, instantiate the cell M1 POLY (note capital letters) from thelibrary NCSU TechLib ami06. Similarly, to access a metal1-metal2 combowith a via, instantiate the cell M1 M2 from the NCSU TechLib ami06library. These cells will appear as a black box. To see through the cell, type”Shift -f”. This will make the cell visible. Remember that you cannot updatethis cell, since it is a standard library cell. The figure below shows the con-nection. The red-shaded polygon with a black square at the center and blueborderline is the M1 POLY contact. The blue-shaded polygon with a pinksquare at the center and pink borderline is the M1 M2 contact.

12

ESE570 Fall 2021

For simulation purposes and standard cell design rules, it is necessary to addthe pin layer. They are identical in purpose to the input/output and vdd/gndpins in the schematic view. Power and ground rail pins should be declaredas Input/output. It would not be a bad idea to label your pins with thetext layer, but make sure to name the labels the same as the pins in yourschematic and put them on top of the labeled wires. Click on metal2 in theLSW window. Then press Ctrl-p in the layout editor window. A window

13

ESE570 Fall 2021

will pop up. Enter the name ’in’ for labeling input. Choose ”Display pinname ” option and define the pin as input. Then click on the left mousebutton with the cursor placed at the top left corner of the metal2 square tobe labeled. Then drag the mouse to the right bottom corner of the samemetal2 square to be labeled. Click one more time inside the metal2 square toplace the text. Do the same steps for placing an ”out” pin except for the factthat you declare the pin as ”output”. Next, select metal1 in LSW window,and type Ctrl-p. Type ”vdd” for ’Temrinal Names’ and select ”I/O Type”as ”Input/Output”. The rest is the same as before.

14

ESE570 Fall 2021

(c) Perform a DRC and LVS on your inverter layout to ensure it passes the designrules and matches your scehmatic. Submit proof of passing both the DRCand LVS with your homework.

Our next step in the Design Process is to perform a Design Rule Check, morecommonly known as DRC on the layout. The DRC is a step taken to promptus of any violations. To run the DRC, choose DRC... from the Verify menuin the layout view window. A pop-up menu will appear as below. Click okto run DRC.

Cadence then runs the DRC and reports the errors or warnings, if any, in theCIW window.

A successful DRC ensures that the layout passes through the rules designedfor faultless fabrication. However, it does not guarantee if it really representsthe circuit you desire to fabricate. In our case, for an inverter, we reallyneed a tool that can compare the connectivities of our layout with that ofthe schematic and ensure that it is really a layout for an inverter. One way

15

ESE570 Fall 2021

Cadence does this is by generating an Hspice netlist file from the layout andcomparing it with the netlist for the schematic. This is the essence of theLVS tool.

The first step is to extract all the connectivities and parasitic capacitancesfrom your layout design. From the layout view window, choose Extract...under Verify menu. A window will pop-up. Make sure that the entries areas given below. For the entry in Switch Names, click on Set Switches.A window will pop-up. Choose the option for Extract parasitic caps. Fi-nally, click on OK. The beauty of this extraction tool is that Cadence willrecognize not only all the connections but also more importantly, if you havedesigned the layout correctly, it will also recognize all the nmos and pmostransistors.

Your layout will then be extracted and while Cadence is doing so, the in-termediary steps will be displayed in the CIW. It will tell you whether theextraction is successful or not.

Open the extracted view of the cell from the Library Manager window.Press Shift-f to see the symbols for the active and passive devices appear in

16

ESE570 Fall 2021

the extraction view window. This is just symbolic to associate the portionsof the layout with different devices. The extracted view will look somethinglike this:

The next step is to perform LVS. Since we generated a layout with certaina W and L for the transistors (for the case discussed here, both nmos andpmos W = 1.5u and L = 0.6u), the layout versus schematic operation willgive you an error if the schematic against which the layout is compared has adifferent W and L for its pmos and nmos transistors. You need to make surethat Cadence is checking for certain LVS rules. To do so, click on NCSU

17

ESE570 Fall 2021

→ Modify LVS Rules from the layout view window of your inverter. Awindow should pop-up with a number of LVS options available for you tochoose. For our purposes, you should verify that the following 4 items areselected: Allow FET Series Permutations, Combine Parallel FETs,Combine Parallel Capacitors, Compare FET Parameters. This checkshould be performed every time you are about to start an LVS.

From the extracted layout window, choose Verify → LVS. A pop-up menuwill appear like below. If you already had an LVS directory, a window willpop-up which might say ” The selected LVS rule directory does not matchthe run form”. Just select Form Contents and click OK. Run the LVS youcan get the following result if it succeeds.

18

ESE570 Fall 2021

If there are any errors, click on Error Display in the LVS menu to viewwhat went wrong. Click output from LVS window, you will see the followinglog file. It is very beneficial if you click on output window shown below. Itwill explain each of the terms in the above window in great detail. The si.logwill also explain to you all the errors that it detected in both the schematicand layout views during the LVS comparison.

One should realize that almost no one designs a perfect layout on the firstattempt so do not expect to pass the LVS check on your first try. In mostcases, there will be many errors reported by both the si.log file and the ErrorDisplay window. You should not be intimidated by all these errors. Manyof these are, in fact, related to each other. Hence, once you fix one of theseerrors, many of the other errors should disappear. The idea is to concentrateon one error at a time, change the layout design accordingly and repeat theextraction and LVS steps until the layout and schematic views match perfectlywith each other.

(d) Using your test schematic for measuring the inverter delay, run a simulationof the analog extracted schematic generated from your layout to measure the

19

ESE570 Fall 2021

dynamic performance of your layout. You should use your inverter to drivethe input and your inverter should still be loaded with an identical inverter.Submit the test schematic, input/output transient waveforms, and your delaymeasurements (propagation and rise/fall times). Here are the instructions forpost layout simulation.

Open up the test schematic for the inverter. Select Launch → ADE L. Thesame steps that you run simulation in previous homeworks. However, the onechange that needs to be made is: goes to Setup → Environment... andyou will see the Environment Options window open up. Originally, theSwitch View List should contain the following items:spectre cmos sch cmos.sch schematic veriloga

In order for Cadence to simulate through the extracted view of the layoutdesign instead of the schematic view, you will include an additional item (ex-tracted) in the Switch View List such that it now contains the following:spectre cmos sch cmos.sch extracted schematic veriloga

20