hw5 - university of marylandnewcomb/courses/fall2015/303h/hw5solutions.pdf · hw5 i did a...
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HW5
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1. (60 points; OTA integrator design)
a) For the above connection give the nonlinear differential equation for the voltage output versus the voltage input using an MOS OTA.
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Design an OTAC circuit to give this differential equation using a MOS OTA made of 4007 transistors (with one tail current setting resistor). Use two 6V power supply batteries, set the tail current at 5mA, and use a 10nFd capacitor.
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Rb
1.0 3.0 10 30 100 300 1.0K 3.0K 10K
I(Rbias)
-25mA
-20mA
-15mA
-10mA
-5mA
0mA
I ran a sweep for {Rb}, the value of the bias resistor. The sweep intersects 5mA (the desired current) at about 1.142 kΩ.
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b) Sketch (by hand) the low frequency output current versus input differential voltage that you expect for this integrator with small signal sine wave inputs.
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Correction: 𝑣𝑜 would be a negative cosine wave, because it is the integration of 𝑖𝑐, and 𝑖𝑐 = −𝑖𝑜
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Determine the small signal gm and run Spice to check the integrator operation.
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Do a frequency response to determine over what frequency range it will work.
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Frequency plot of the current amplitude through the output capacitor. No significant current goes through the transistor until around 1GHz, this seems really high…
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2. (40 points; current sources, mirrors)
a) Compare NMOS current sources made with one input/output pair of transistors versus a circuit using a cascode of two input/output pairs.
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One-pair:
Voltage sweep on {Vds1}. Measure the current into the drain of OP2.
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V_Vds1
0V 2V 4V 6V 8V 10V 12V 14V 16V 18V 20V
I(OP2:d)
0A
1.0mA
2.0mA
3.0mA
4.0mA
One-pair plot of 𝑉𝐷𝑆 across the mirror NMOS, vs the current through its drain. The saturation region still has a rising slope, which is undesirable.
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Two-pair (cascode):
Voltage sweep on {Vo}, measure current through the transistors (same through both) on the mirrored side).
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V_Vo
0V 2V 4V 6V 8V 10V 12V 14V 16V 18V 20V
I(Ca4:d)
0A
50uA
100uA
150uA
200uA
250uA
300uA
Two-pair cascode plot of 𝑉𝑜𝑢𝑡 across the both mirror transistors, vs the current through those mirror transistors. The saturation is now flat with a constant current, but that current is much lower than the one-pair.
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b) Design a 4 transistor CMOS bidirectional current mirror (that is, one which will work with input currents of any sign). Note that this will require a bias offset current. Check your design in Spice.
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For the bidirectional mirror, I could not figure out how to get the proper behavior in pspice with just 4 transistors. I used an NMOS cascode sink and a PMOS cascodesource in parallel, both of which connect to the load resistor (in the middle).
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HW5
I did a bias-point simulation with a positive 20V source, which should have let current run through the NMOS cascode, but not through the PMOS cascode. But the bulk terminal on P_cas1 was drawing -18.34mA. I don’t know why this happened.