“GIGABIT ETHERNET OPTOELECTRONIC LINK”

GROUP 7 DESIGN TEAMCasey BristerThee Kong

Charles A. Lewis IIMuhammad Qayyum

My TranBounsysavanh Vongsamphanh

ECE4006-BCapstone Design ClassMAJOR DESIGN PROJECT

Instructors: Dr. Jokerst & Dr. Brooke

Paper#1THURSDAY, October 24, 2002

Georgia Institute of TechnologySchool of Electrical and Computer Engineering

ATLANTA, GEORGIA

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TABLE OF CONTENTS

I. Abstract 3

II. Design Team Organization 4

III. Background 4

IV. Testing theory 9

V. Procedure (for provided Pre-fab board) 11

VI. Results (for provided Pre-fab board) 12

VII. Conclusions (for provided Pre-fab board 15

VIII. Designing a Gigabit Ethernet Receiver and Transmitter 16

A. Introduction 16

B. Component Analysis and Selection 16

C. Receiver Board (RX design) 24

D. Transmit Board #1 (TX1 design) 26

E. Transmit Board #2 (TX2 design) 28

IX. Outlook / Paper2 preview 30

Reference 32

APPENDIX A 34

APPENDIX B 35

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I. ABSTRACT

This paper provides a general introduction to Gigabit Ethernet theory and serves as a

comprehensive summery summary of the work to date of the ECE4006-B G7 major design team.

That includes the theory, design, build, testing, and analysis of a Gigabit Ethernet optoelectronic

(OE) link. The OE device will include both optical transmit and receive structures that transfer

data at 1.25Gb/sec and operate within the specifications stated in the IEEE 802.3z standard.

Results will be tested using 8B/10B encoded random data inputs. Performance assessment will

be based upon bit error rate (BER) of the data, eye diagram clarity, and other parameters.

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II. Design Team Organization

In order to ensure efficient and timely completion of this project, the Group 7 design

team established an internal operating structure. Charles A. Lewis II was appointed design team

leader. Then the team was divided into Transmit (TX) and Receive (RX) specialization teams.

The group them conducted extensive independent research on Gigabit Ethernet and related

topics, with each member paying additional attention to there assigned area of specialization. A

management plan was then developed as a production guide for the project. Done in Gantt chart

format, it is regularly updated as serves as the most recent version of that management plan is

shown in APPENDIX B.

III. Background

The purpose of this project is to design a gigabit optoelectronic data communication link.

This system would be capable of transferring the data at a rate of 1 gigabit per second with low

errors. It is important to understand the importance and mechanics of gigabit Ethernet before

getting into design details

Gigabit Ethernet is the new dimension in the world of Ethernet. Ethernet is an extremely

successful technology for the fact that it is simple, yet produces reliable and low-cost, low-

maintenance networks. Gigabit Ethernet incorporates all of the qualities of an already stable

system, plus gives the advantage of increased speed. At 1000 Mbps, Gigabit Ethernet is 100

times faster than Ethernet, and 10 times faster than Fast Ethernet.

However, with faster data rates the probability of errors increases as well. So, the issue of

delivering data without corruption is an important issue when it is being delivered at faster data

rates. The adaptability of Ethernet structure was used to avoid this problem. With the

development of IEEE 802.3 Media Access Controller (MAC) the problem of the deliverance of

uncorrupted data was taken care of.

The purpose of this project is to design, build, and test a Gigabit Ethernet optoelectronic

(OE) link. That link will include both a transmitter (TX) and receiver (RX).

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Gigabit Ethernet is explicitly defined in IEEE Standard 802.3z. Within the standard

8B/10B is listed as the block coding scheme to be used for Gigabit Ethernet data transfer. (See

IEEE Standard 802.3z 1.4.24 and 36.2.4) 8B/10B is the scheme used by the gigabit Ethernet so

that the data can be interpreted correctly at the receiver. It is a DC balanced octet orientated data

encoding format. In this encoding scheme, eight bits of data are sent along with two extra bits.

The transmission rate of these ten bits is 1 GP/s. The extra bits are needed for control

information like the start of the packet, end of the packet, and idle. If invalid bits are received

then a transmission error occurs. This encoding scheme is useful because it makes bit

synchronization easy and it insures that incoming bit stream has frequent transitions for

performing clock recovery. (The 8B/10B encoding scheme is more completely explained in the

Testing Theory section of this paper.)

In order to confirm the transfer rate of 1 GP/s, the physical layer uses Fiber Channel

modifications. Fiber Channel uses long wave lengths to transfer data over a fiber optic cable.

These wavelengths known as1000Base-X standard are given below. The 1000BASE-X family

contains 1000Base-SX, 1000Base-LX, and 1000Base-CX. 1000Base-SX, for Short wavelength

850 nm laser on multi-mode fiber, is the one that will be used for this design project.

1 2 3 4

Figure 1 - Gigabit Ethernet physical Layers.

(Fiber Channel is discussed further in the Testing Theory section of this paper. For a

complete explanation of Fiber Channel, please refer to ANSI X3.230 Standard.)

The MAC layer for the gigabit Ethernet has all the capabilities used for other Ethernet

technologies. In addition to old capabilities, the two additions are carrier extension and frame

bursting which will be discussed later.

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In the IEEE standard 802.3z, MAC layer can perform operations in half and full duplex

modes. In case of half duplex mode, a channel can transmit and receive data but not at the same

time. However, in full duplex mode, packets can be received and sent at the same time. In full

duplex mode, flow control is used, however, in half duplex mode, CSMA/CD access method is

employed. In this method, a frame is only sent when the transmission medium is clear. The

network listens for a collision of the frames. Now, if the transmission had been clear for a while,

then both end of the network might transmit frames at the same time and that would result in a

collision. CSMA/CD detects these collisions and discards the damaged frames, and the frames

are retransmitted after the transmission medium is clear.

CSMA/CD is effective in the network but it has a timing problem because of the frame

length. This problem is solved by employing carrier extension mechanism. . The carrier extended

frame is shown in Figure 1.

Figure 2 - Carrier-extended frame.

Carrier extension technique increases the frame length from 64 bytes to 512 bytes. If a

frame is sent into the transmission medium with a length less than 512 bytes then non-data

extension bytes are added. CSMA/CD access method is further improved with the introduction

of frame bursting mechanism. This mechanism has the ability to send multiple frames of small

sizes so that bandwidth does not go to waste. Figure 2 gives an overall picture as to how this

method works.

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Figure 3 - Illustration of CSMA/CD methodIn short, the purpose of the IEEE standard 802.3z is to provide essential specifications for

the Media Access Control (MAC) and Physical Layer of the gigabit Ethernet. It also provides

half duplex and full duplex operations. The standard 802.3z depends on 802.3 Ethernet frame

format and Carrier Sense Multiple Access / Collision Detection (CSMA/CD) access method. As

this standard is compatible with 10MPS and 100MPS technologies, so this provides a less

complex and more stable technological advancement.

The Group optoelectronic link will have two active components. They are a Vertical

Cavity Surface Emitting Laser (VCSEL) on the transmit side and on the receive side it would be

a photodiode (PD).

Vertical Cavity Surface Emitting Laser (VCSEL) is a key component in the TX design.

The differential input coming into an integrated circuit and comes out as current which drives the

VCSEL to produce a laser. This laser enters an optic fiber leading up to the photodetector on the

RX side.

VCSELs are composed of several layers of mirrors that are produced by semi-conductors

with varying compositions. These mirrors reflect a narrow range of wavelengths back into the

cavity which in return caused the light emission of just one wavelength. Figure 3 demonstrates

this description.

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Figure 4- Structure of a VCSEL. Figure 5. Images of the two types of VCSELS to be used in this project. (On the left, an “unconnectorized” VCSEL, and on the

right an SC Connectorized VCSEL.)

VCSELs are used because they give high performance and are cost effective. They also

tend to have other advantages including low threshold currents, low temperature sensitivity, high

transmission speed with low power consumption, and easy alignment and production packaging

due to same geometry as the photodetectors (PDs) used. (Photodetectors are explained below).

VCSELs can be connectorized or unconnectorized. Connectorized components are pre-

aligned and factory-tested to ensure minimal insertion-loss. The outside connectorized end will

generally have a protective shroud that prevents damage to the connectors during installation.

For this project VCSELs will be assessed by divergence angle, threshold current, and

slope efficiency. Beam divergence angle is defined as the light intensity full width at the 1/e2

intensity level. Threshold current is the minimum current that turns the VCSEL on. Slope

efficiency is the ratio of the output power (micro watts) to input current (mA).

Photodetectors be selected based upon their sensitivity at the required wavelength,

responsivity, divergence angle, (preferably large), speed, and capacitance (preferably low).

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Responsivity of a photodetector is the ratio of current (A) produced to the input power

(W). Photodetectors are also available as either connectorized or unconnectorized.

Table 1 - Gigabit Ethernet over Fiber.

VCSELs are composed of several layers of mirrors that are produced by semi-conductors

with varying compositions. These mirrors reflect a narrow range of wavelengths back into the

cavity which in return caused the light emission of just one wavelength. Figure 3 demonstrates

this description.

IV. Testing Theory

For this project system performance will be assessed through the use of “eye diagrams”.

The eye diagram is a plot of data points repetitively sampled from a pseudo-random bit sequence

and displayed by an oscilloscope. Each data clock pulse triggers the oscilloscope sweep. An eye

diagram allows the user to visualize how the waveforms used to send multiple bits of data can

potentially lead to errors in the interpretation of those bits.

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Figure 6 - Example of an eye diagram

The "eye diagram" gives a visual representation of the “jitter” and output driver quality of

the output signal. (Jitter is a measure of signal quality and is defined as the measure of variance

in signal characteristics. A zero jitter measurement indicates that the signal transition occurs at

exactly the same point in time for each transition. The wide transitions in the eye pattern are the

result of extensive jitter within the signals, implying that the signals are not consistently

transitioning at the required time. Small eye width implies a large variance in signal transition

time.) Horizontal eye closure is due to jitter, while vertical eye closure is due to signal

attenuation or noise. Therefore, a larger "eye", also referred to as an “open” eye is considered an

indication of a better performance. During analysis we will be assessing the quality of eye

diagrams in these terms. Transition times can be measured using the slope of the transitioning

signals in the eye diagram. A 90 degree slope implies a rise and fall time of 0 ns. In reality,

however, there is a certain transition time associated with rising and falling signals. The closer

the slope is to 90 degrees, the smaller the transition time. A smaller transition time indicates that

the signal is valid for a longer time at the next time period. It can thus be said that eye diagram

interpretation is and indication of jitter measurement and comparison. Therefore, a known data

pattern is required.

The components of the optoelectronic link being designed and built for this project will

be tested using random input data. The two test pattern formats to be used will be K28.5 and

PRBS7. K28.5 is a mixed frequency test pattern for testing deterministic jitter. Generally it is a

continuously repeating sequence of 0011111010 followed by logical inverse 1100000101. This

pattern is a special character in the 8B/10B-coding table and often marks the beginning or end of

a frame. A repeating K28.5 sequence (composed of alternating K28.5+ and K28.5-) contains the

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symbols 0011111010110000010. This pattern contains five consecutive 1's and five consecutive

0's, (the longest consecutive identical digits found in 8B/10B coded data). It also contains an

isolated 1-010-and an isolated 0-101. These isolated points serve as excellent markers. PRBS7,

or Pseudo-random bit sequence 7, which is equivalent to 27-1, is used for common bit error rate

and pseudo random bit stream (PRBS) testing. In industry, PRBS has become the choice as a

test signal because it is easy to generate, convenient to implement, and specifically for Gigabit

Ethernet it is a more robust and stringent test signal format.

Both test patterns to be used are forms of 8B/10B encoding. Developed by IBM, 8B/10B

is a coding procedure with which 8 bits long user information is converted to serially into 10 bits

long groups of codes. It provides a useful connection mechanism to deliver data, clock and

control over a single differential pair. The 8B/10B-encoding is used with both the fiber Channel

(Fiber Channel is a transmission technique used for point-to-point connections between

computers and peripheral units. It is known for achieving extremely high transmission rates) and

with 1000BaseX. (1000BaseX is the name given to the family of Gigabit Ethernet types

including 1000BaseCX, 1000BaseLX and 1000BaseSX. 1000BaseX is standardized within IEEE

802.3z.)

For gigabit Ethernet, the Fiber Channel FC-1 layer describes the synchronization and the

8B/10B-encoding scheme. Gigabit Ethernet utilizes the same 8B/10B encoding/decoding as

specified in the FC-1 layer of Fiber Channel. Fiber Channel uses 8B/10B because of its DC

balance. The lack of DC balance can potentially result in data-dependent heating of lasers, (in

this project that could result in burning out the VCSELs) because a transmitter sends more 1s

than 0s, resulting in higher error.

V. ProcedureAssembling the receiver board was a fairly straightforward procedure. The TIA

(MAX3266), the limiting amplifier (MAX3264), the board, and all the other necessary

components (capacitors, resistors, B/C connectors, etc.) were supplied by professors Jokerst and

Brook. Professor Brook also supplied a schematic clearly detailing the structure of the receiver

board. The schematic of the pre-fabricated receiver board is displayed in Figure 7.

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Figure 7 - Pre-fabricate Receiver Board Schematic.

Professor Brook provided further guidance with a lecture on properly assembling and

soldering the boards. Proper care should be used in assembling the input and output routes as

these were the most sensitive to noise and other interference. Soldering should also be

completed according to proper form to insure complete connections between all solder joints.

Soldering with such sensitive and small components can be a daunting task. Guidelines

for a proper soldering are to use a hot soldering iron, make quick solder joints to limit the

internal heat of the components, and to check for shiny joints representing a well connected joint.

Figure 8 shows proper solder joints made for the power connector and the SMA RF connecter.

Figure 8 - Proper Solder connections for a Power connector and a SMA RF connector.

Despite the beneficial lecture from Professor Brook, soldering is still closer to an art form

than an exact science. It requires a great deal of practice to become adept at making proper

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joints. Everyone in the design group was encouraged to practice with the soldering iron to gain a

feel for the task. The actual assembly was completed by the two most experienced members of

the design team.

Figure 9- Pre-fabricated Receiver Board Layout.For reference, a layout of the receive board can be found in Figure 9. The receiver was

tested according to the guidelines discussed in class and an eye-diagram was generated. The

resulting eye-diagram can be seen in figure 10a. The eye-diagram was less than satisfactory due

to the excessive amount of noise causing data points to appear outside the acceptable tracks. The

joints on the receiver board were re-soldered to guarantee that there were no “cold” or bad joints

creating the problem. The board was retested and produced a very satisfactory eye-diagram that

can be seen in Figure 10b.

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(a) (b)Figure 10-Eye diagram from prefabricated receiver board (a)with bad joints and (b)correctly soldered.

VI. Results

The setup for testing the pre-fabricated receiver board consisted of a pattern generator,

attenuator, and the digital oscilloscope. The pattern generator produces different bit streams

such as PRBS7 and K28.5. An attenuator is then used to vary the signal to different levels and

then it is outputted to the oscilloscope. The oscilloscope uses an eye diagram to determine if the

signal has low error rate. If the eye is distorted or there are many data points within the eye, then

the signal has too much noise. A good eye indicates that there is a low signal-to-noise ratio.

Figure 11 displays eye diagrams generated by the PRBS7 bit stream. A good eye is consistently

produced from 10dB to 30dB of attenuation. Around 40dB to 50dB of attenuation, there is a lot

of jitter due to semi-random displacement of a signal from its ideal location. These

displacements can occur in amplitude, phase, and pulse width and are generally categorized as

random. At 60 dB of attenuation, the eye diagram is completely distorted.

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PRBS-7

10 dB 30 dB

50 dB 60 dB

Figure 11 - Eye diagrams generated by the PRBS7 bit stream.(Click on the individual images to view a larger image.)

In Figure 12 below are the results for the K28.5 bit stream. From 10dB to 20dB of

attenuation, the eye diagram looks great except the dipping phenomenon. However, from 30dB

to 40dB, there is a gradual increase of jitter. At 50 dB of attenuation, the transition region of the

eye is distorted and at 60dB the signal is completely lost.

K28.5

10 dB 30 dB

50 dB 40 dB

Figure 12 - Eye diagrams generated by the K28.5 bit stream.

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(Click on the individual images to view a larger image.)VII. Conclusions

After building and testing the provided pre-fabricated receiver board, the group members

became familiar with soldering components and setting up test equipment. In the beginning of

the semester, only one group member was familiar with soldering surface mount parts. The task

of soldering the passives and Maxim chips was a great soldering experience for the team as a

whole because the components were extremely small and difficult to work with. Working

continuously, each group member gained valuable experience with soldering surface mount

parts. The initial testing of the pre-fabricated receiver board was a failure due to bad solder

joints. After refinishing the bad solder joints, the group learned that good solder joints are

smooth and shiny compared to the rough and dull joints. In addition, the important problem of

possible overheating of the chip was overcome by not soldering joints continuously. After

building the pre-fabricated receiver board, the initial testing equipment consisted of a pattern

generator, attenuator, and oscilloscope. The group became familiar with the testing equipment

after multiple tests with different bit patterns such as PRBS7 and K28.5. The pattern generator

was used to transmit a bit stream and the receiver outputted the data onto the oscilloscope. The

oscilloscope displayed an eye diagram, which is a useful tool to indicate good data transmission.

A near perfect open eye indicates very low signal-to-noise ratio. The attenuator was used to

adjust the input signal to different levels and it was connected between the pattern generator and

the receiver. The testing of the pre-fabricated board resulted in a good eye from 10dB to 30dB

for the PRBS7 pattern. For the K28-5 pattern, a good eye was produce within 10dB to 40dB.

However at 50dB, the K28-5 pattern had more jitter, which is caused by the difference in the

differential paths. Overall, the pre-fabricated receiver board produced a good eye for various

levels of attenuation. That prefabricated receiver board, having thus been shown to function

correctly, can therefore be used in the future as a reference board to establish if the test setup is

working correctly.

VIII. Designing a Gigabit Ethernet Receiver and Transmitter

A. Introduction

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The purpose of assembling the prefabricated receiver board discussed in the previous

sections was to familiarize the design group with the components, processes, assembly, and

testing procedure to be used during this project. Having acquired that experience, the design of

both the optoelectronic link’s receiver and transmitter boards could begin.

One of the purposes of this course is to prepare the members of the design team for work

in a professional environment. This means doing efficient work and producing a quality product

that recognizes the established guidelines of the various governing bodies in industry. As such,

the groups design is developed and constructed to conform to gigabit optoelectronic standards,

such as IEEE 802.3z, etc. The design is also intended to maintaining maximum functionality at a

low cost. This left design group 7 with a great deal of freedom to be as creative and innovative

in their design as possible. This required that the team to choose the best optical and passives

components, correctly design their printed circuit boards (PCBs), and assemble and test the

boards. System performance is to be evaluated using the generated eye diagrams, as well as the

bit error rate measurements.

B. Component Analysis and Selection

To begin the design of the boards, one must first determine which components to use. To

better understand the criteria behind choosing the optical components, one must first understand

the path by which a signal travels in going from the transmitter to the receiver. A logical

flowchart of this signal path is represented below in Figure 13.

Figure 13 - Top-level design of optoelectronic link.

As indicated by the figure above, the path begins with the laser driver. The electrical

signal then runs through the VCSEL and is converted to an optical signal. The optical signal is

passed through the optical fiber and is finally received by the photodetector. The photodetector

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converts the optical signal back to an electrical signal. The current from the photodetector is

passed through the Transimpedance Amplifier and then to the Limiting Amplifier.

As implied by its name, the MAXIM MAX3287 LAN Laser Driver, which is optimized

for Gigabit Ethernet (1.25 Gbps) applications, is used to drive the laser (VCSEL). By controlling

a potentiometer in the laser driver’s circuitry, one can control the current driving the VCSEL.

This is advantageous in that if there is not power coming from the VCSEL, one can adjust the

modulation current to amplify the intensity of the laser.

Figure 14 – MAXIM MAX3287 Laser driver Pin out diagramFrom the VCSEL, the light travels through an optical fiber and reaches a photodetector,

which converts the optical signal back into an electrical signal. When the signal leaves the PD, it

enters the Transimpedance Amplifier (TIA). The TIA used in the design was the MAXIM

MAX3266, which is also optimized for 1.25 Gbps applications.

Figure 15 – MAXIM MAX3266 TIA Pin out diagramThe purpose of the MAX3266 is to amplify the small current from the PD while also

converting the current to a voltage to drive the Limiting Amplifier that follows it. The MAXIM

MAX3264 Limiting Amplifier then amplifies the voltage by 55 dB and converts the analog

signal to a digital one.

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Figure 16 – MAXIM MAX3264 Limiting Amplifier Pin out diagram

Since the same three Maxim ICs are used in every design, the optical components, the

VCSEL and PD, are the only components that determine whether signal integrity is maintained

in the conversion between optical and electrical signals and in the transmittance of the signal in

the transfer. The main specification to look for when searching for VCSELs and PDs is that they

must be able to support 1.25 Gbps data transfer. Another criterion to look for in searching for

components is whether the parts are connectorized or unconnectorized. Connectorized parts are

already pre-aligned and linked to a connector, while unconnectorized are not. The advantage of

an unconnectorized part is that, since they are not fixed to a connector, the optical fiber can be

manually aligned with each part for optimal data transfer (see Figure 17for illustration).

Connectorized parts, on the other hand, do not require any alignment on the part of the end-user.

One simply needs to attach the fiber to the VCSEL or PD.

Figure 17 - Alignment Tolerance of Fiber/Component Connection

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As one can see from the figure above, a misalignment between fiber and optoelectronic

components may result in a loss of data/signal. If transverse alignment is off, the light emitted or

received may not be completely detected. Likewise, if longitudinal alignment is off and the fiber

is too far away from the component, then there may be leakage of light in the transfer. While the

connectorized components may seem convenient, their disadvantage lies in the fact that they are

usually more expensive and also cannot be manually adjusted for better alignment. Both

connectorized and unconnectorized parts will be utilized and tested, in this project. The former

are used to test the test connection, while the latter are used to test the range of the parts.

Once the potentially suitable parts are found, their specifications must be inspected to

determine how good they are. The best parts are those that would best maintain signal integrity.

To assist in determining whether the strength and integrity of the signal is maintained, an optical

link power budget is used. A flow diagram of this power budget can be seen in Figure 18 below.

Figure 18 - Optical Link Power Budget.

An explanation of these design specifications, as well as the other main criteria used in

determining which components are good, is listed below in Table 2.

Table 2Units Explanation

VCSELsThreshold Current, ITH mA The minimum current required for lasing. This number should be

minimized. A higher threshold current would require more current from the laser driver circuitry and thus, more power.

Slope Efficiency, ŋ mW/mA The power (mW) of the light emitted for every milliamp of current passed through the laser. This number should be maximized. A higher slope efficiency would require less current from the laser driver and thus, less power in.

DC bias of laser, IBIAS mA The DC current passing through the laser.Divergence angle, θ Degrees The degree to which the light emitted from the VCSEL spreads.

A lower divergence angle represents less scattering and a more concentrated, better signal.

Series Resistance, RS Ohms The resistance of the VCSEL. This value needs to be matched by the laser driver circuitry.

PhotodetectorsResponsivity, R A/W The amount of current (A) for every W of power coming into the

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photodetector. This number should be maximized to reduce the amount of power needed as input to the PD.

Dark Current, ID nA The current passing through the PD when not detecting light. A high dark current could cause noise and should thus be minimized.

Capacitance, C pF A low capacitance is favorable for high speed signals.Peak Response Wavelength, λ

nm This wavelength should match the wavelength of the VCSEL. If not matched correctly, the PD will not work since it will not detect any light of the desired frequency. This value should be ~850nm for the1000Base-SX standard.

Field of View Degrees The range of view where the photodetector can detect light. The higher this value, the bigger the area that the PD can detect light and generate current.

Of these conditions, the most important properties for VCSELs are slope efficiency and

threshold current, and the responsivity for the PDs. The importance of these properties becomes

clear when looking at the optical link budget. Larger values of slope efficiency and responsivity

simply make the link more efficient. With larger values, one does not need as high an input

current or power input to the VCSEL and PD, respectively.

Despite the apparent simplicity of the optical link power budget, it is more than a simple

process of substituting numbers and calculating values. Other considerations must be taken. For

instance, there are minimum, typical, and maximum values for each of the specifications for the

parts. Consequently, when determining the power budget, one must consider all “four corners.”

That is, one must compute the link budget for all possible combinations of ITH and slope

efficiency. In other words, one must determine the link budget for min. ITH and min. , min. ITH

and max. , max. ITH and min. , and lastly, max. ITH and max. .

Another factor is the current coming from the photodetector. According to the

specifications sheet for the MAX3266, the minimum current required to operate the TIA is 30

A, while the maximum before overload is 1 mA. Hence, one must adjust the modulation

current of the laser driver such that the power yielded from the VCSEL and received by the PD

results in a current greater than 30 A and also less than 1 mA. Otherwise, the TIA, and

consequently, the receiver, would not operate correctly. Before the light is received by the

photodetector, however, it must first travel through a length of fiber and connectors. Thus, since

the fibers are not lossless and connectors not perfect, one must take into account losses that may

occur. For the calculations used for this design, a loss of 8 dB (~82%) was assumed. This

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assumption is actually greater than the worst-case 1000BASE-SX link power budget penalties of

7.5 dB as stated in IEEE 802.3z subsection 38.3.3.

One final issue in dealing with the optical link budget and Gigabit Ethernet standards

compliance is safety. According to IEEE 802.3 standards, Section 3, page 116 (Clause 38.7.2),

“transceivers shall be certified to be in conformance with IEC 60825-1.” The IEC 60825-1 is the

International Engineering Consortium’s safety standards for Class 1 optical devices. Although

many of the VCSELs chosen were Class IIIb lasers, the IEEE 802.3z standards only require that

the transceivers follow Class I device conditions. While the actual IEC 60825-1 document could

not be located as to be used as a reference, two sources which reference the standards were found

that provide the eye safety levels for 850 nm Class I lasers. According to the Lightpointe White

Paper on Free-Space Optical Laser Safety (Table 1, page 7), which referenced the IEC and

Center for Device and Radiological Health (CDRH) standards, the maximum power emitted for

Class I and Class IM lasers for an aperture size of 7 mm, the average size of a human pupil, is

0.78 mW (see Figure 19 below).

Figure 19 - Eye safety data for 850 nm Class I lasers. [9]

This value is further confirmed by the calculations found in the Laser Safety Standards

Update and the “…Impact on 850 nm Serial PMD” presentation given by Paul Kolesar and Jane

Ehrgott of Lucent Technologies[10]. If one uses the formulas given in the presentation, which

are referenced from the IEC standards, and substitute 850 nm instead of the 840 nm used, one

obtains 0.787 mW as the maximum Accessible Emission Limit for Class I lasers. While the said

presentation is for 802.ae (10Gbps Ethernet), this is irrelevant since the same safety standards

apply for 802.3z as long as Class I lasers are used. These two references should provide

sufficient support of the claim that eye safety is 0.78 mW for 850 nm Class I lasers despite the

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numerous claims to the contrary. Nevertheless, if this value is incorrect, it would still be less

than the more prevalent value of 1 mW. Hence, it is better to be safe than sorry, despite the fact

that the lower power coming from the VCSEL would require more precise alignment of the

optical components in order to achieve a better signal.

Using the above criteria, four unconnectorized and one connectorized VCSELs were

found. All of the VCSELs acquired were common anode. Hence, the PCB layout for the

transmitter had to be designed to meet these requirements. For the photodiodes, all three found

were unconnectorized. This was due to the difficulty in locating connectorized PDs that meet the

specifications of the design. The search continues, however, and it is possible that a suitable PD

has already been found. The specifics of this particular PD are not detailed here because the

vendors must first be contacted about the availability of the product. Until then, the PD may be

of no use to this project.

As for the optoelectronic components chosen, free samples of each have been received

from the respective vendors. Due to the small number of components needed and the large

minimum order required for each of the parts by the vendors, many of the vendors opted to

supply the components for free. While the components were acquired at no cost, their cost must

still be taken into account when designing the boards to better simulate a professional work

situation. This factor, along with the performance of each of the parts, will be taken into account

when the boards are assembled and tested. To better predicate which parts will work best, a

four-corners optical link budget was determined for each of the VCSEL/PD combinations. A

sample of this link budget is found in the table below. For a complete optical link budget, please

visit http://www.ece.gatech.edu/academic/courses/ece4006/fall2002/group7/data.html.

Table 3- Sample of optical link budget calculations for components selected

  HFE-4085-321 HFE-4383-521           

  min max min maxIth (mA)   1.5 6 3.5 6

 DC bias of laser (mA)   7.2 7.2 7.2 7.2

 Minimum Slope Efficiency (mW/mA)   0.1 0.1 0.02 0.02Modulation Current (mA)   2.1 6.6 35.3 37.8Range of Power (mW)   0.78 0.78 0.78 0.78Range of Power Output w/ loss (mW)   0.123621669 0.123622 0.123621669 0.12362167Responsivity of BPX63 (A/W)   0.5 0.5 0.5 0.5

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Responsivity of OPF420 (A/W)   0.55 0.55 0.55 0.55Responsivity of S5973 (A/W)   0.47 0.47 0.47 0.47Range of current of BPX63 (µA)   61.81083451 61.81083 61.81083451 61.8108345Range of current of OPF420 (µA)   67.99191796 67.99192 67.99191796 67.991918Range of current of S5973 (µA)   58.10218444 58.10218 58.10218444 58.1021844

 Maximum Slope Efficiency (mW/mA)   0.4 0.4 0.1 0.1Modulation Current (mA)   -3.75 0.75 4.1 6.6Range of Power (mW)   0.78 0.78 0.78 0.78Range of Power Output w/ loss (mW)   0.123621669 0.123622 0.123621669 0.12362167Responsivity of BPX63 (A/W)   0.5 0.5 0.5 0.5Responsivity of OPF420 (A/W)   0.55 0.55 0.55 0.55Responsivity of S5973 (A/W)   0.47 0.47 0.47 0.47Range of current of BPX63 (µA)   61.81083451 61.81083 61.81083451 61.8108345Range of current of OPF420 (µA)   67.99191796 67.99192 67.99191796 67.991918Range of current of S5973 (µA)   58.10218444 58.10218 58.10218444 58.1021844

The above link budget is for two VCSELs (one connectorized and one unconnectorized) and the

three photodetectors. As discussed previously, the eye safety level was assumed to be 0.78 mW

and the power loss 8 dB. Using these values and the specifications of the parts, the above optical

link budget was computed. To obtain an idea of what range of modulation current will be

required, the power emitted from each of the four corners of the two VCSELs was set at eye

safety. The modulation current required to yield this power was then calculated (see Figure 18

above for formulas to calculate). With the range of modulation currents known, the

potentiometer values for the laser driver circuit could be determined using equation 1 below

IMOD = 51*[1.15/(RMOD + 250) + 1.06*(1+4.010-3(T—25C)) /(RTC + 250)] Eq. 1

Assuming RTC to be open, this equation reduces to

IMOD = 51*[1.15/(RMOD + 250)] Eq. 2

Due to the varying properties of the components chosen, a wide range of RMOD was required.

Thus, to be able to test all of the different components, it was decided that 10kΩ, 20kΩ, 50kΩ,

and 100kΩ potentiometers would be purchased. For the other passives used in the transmitter

design, the values were determined by referencing the MAX3287 Laser Driver specifications

sheet. [7]

C. Receiver Board (RX Design)

The optical receiver board is adapted from the pre-fabricated board provided. As

explained previously, the receiver intercepts the signal from the transmitter. The signal current is

25

amplified by the Transimpedance Amplifier (TIA) and then converted to voltage. The Limiting

Amplifier boosts the TIA output voltage from approximately 30mV to around 100mV. The

signal is then passed through differential outputs to, in this case, the Textronix TDS 694C digital

oscilloscope.

The difference between this design and the pre-fabricated receiver board is that this

design uses a photodetector to receive the signal from the transmitter instead of an electrical

receiver. In Figure 20, the anode of the photodiode is connected to pin 3 or Input, and the

cathode side of the photodiode is connected to pin 4 or “Filter”. It is very important that the

photodiode is placed close to the TIA to eliminate any possible EMI or transmission line

reflections and harmonics. Next to every power supply input to the board, a decoupling

capacitor is used to separate high frequency sensitive signals from that of noisy analog signals.

The two resistors act as a terminator to the two output lines. This ensures a high frequency

return path. Finally, the two differential outputs should be designed so that they mirror each

other. This means that they both should have the same length. If not, this might cause jitter in

the signals due to the two signals arriving at different times.

Figure 20 - PCB Layout of Receiver Designed

26

Figure 21- Schematic of Receiver Design

D. Transmit Board #1 (TX1 design)

In order to design the Transceiver a schematic was produced first. The lectures provided

by Dr. Brook were a great help in building a correct schematic, particularly the lecture on the

laser driver needs in Figure 22 provided the essential heart of the final design.

Figure 22 - Laser Driver Lecture with essential schematicAn interesting incident occurred during the design process that exemplifies the exacting

nature of this highly detailed process. The final schematic design (Figure 23) included an

incorrect capacitor breaking the red line in the schematic. This capacitor remained unnoticed

27

despite the multiple of design reviews carried out by the design team and the peer reviews done

by Dr. Brook. The mistake was finely noticed during a layout review with Dr. Brook. The

mistake had gone through the entire schematic design process and was only noticed during a

completely different stage of the project.

Decoupling capacitors were placed on the power lines to prevent any outside frequencies

entering the circuit as well as any internal frequencies traveling around the chip using these lines.

The laser driver, along with the circuit powering it, can be seen in the far right hand side of the

design.

Figure 23 - Transceiver schematic

Capacitors were added to the inputs immediately after the input pins to insure there were

no DC components in the signal. Similarly capacitors and inductors were added to the outputs of

the chip to stop and drain away any DC voltages in the lines.

The next step was to complete a layout design based on our transceiver schematic. Dr.

Brook provided some key lectures on transmission line avoidance and signal protection to insure

that our designs were as robust as possible. Figure 24 shows a collection of possible layout

architectures that should and should not be used.

Figure 24 -Layout architectures.

28

At high frequencies, wires start behaving in strange ways that can interrupt the

performance of a circuit. Long lines though which high frequency signals must pass can begin to

look like large resistors degrading any signal. Sharp turns can also act more like breaks in the

line. High frequencies lines can also act as radios, sending and receiving any adjacent signals.

The key lines needing protection from other signals and from becoming transmission

lines were the input and output lines from the chip. These lines needed to be as short as possible

with as few sharp turns as possible to limit the chance of them behaving like transmission lines.

These lines cam be traced in the final layout design in Layout 2 from the input on the connectors,

through a capacitor and resister combination, through the chip, and out through another capacitor

and resister network to the laser diode. These lines are matched as much as possible and are kept

away from other lines such as power and ground as much as possible. Their relative short length

is evident when you compare them to other lines in the schematic such as the power line along

the bottom of the design. Despite the care taken, there is room for improvement in a second

design.

Figure 25- First transceiver design.

E. Transmit Board #2 (TX2 design)

After completing the first transmitter design, a second design was created to reduce the

length of the signal path and also, to establish only forty-five degree angles in the signal path.

The first transmitter design as illustrated in Figure 26could have some potential flaws with the

incoming signal making a ninety degree angle turn. The incoming signals at high speed have a

tendency to be deflected causing a loss in the signal. With the second transmitter design, the

resistors and capacitors are arranged in a position where the signal path makes only forty-five

degree angle turns. The signals encountering forty-five degree angle turns are fully transmitted

29

and there are negligible losses. The overall signal path in the second transmitter design was

shortened enormously by making the passive components and VCSEL adjacent to each other.

From Figure 26, the closeness of the components in the second transmitter layout can be

observed. In the first transmitter design the passive components and VCSEL have significant

spacing between them. By reducing the signal path, the transmission line effects can be

neglected. At high frequencies, transmission lines are major factors of noise.

Figure 26- First and Second Transmitter Design Comparison.Another important implementation that was design for the second transmitter layout is the

capability to use common anode VCSEL. Originally, the first transmitter layout was designed

only for common cathode configuration. Through the complications of ordering VCSELs,

common anode components became an alternative. Many of the VCSELs that arrived early were

common anode such as the Honeywell HFE 4085-321 and OPV 2000 Optic. The schematic for

the common anode and common cathode is displayed in Figure 27. For common cathode

configuration, the VCSEL is grounded and the potentiometer is tied to the power supply. And

for common anode, the VCSEL is connected to the power supply and the potentiometer is

grounded. A group decision was made to revise the first transmitter design to be able to utilize

the common anode VCSEL configuration. By enabling the first transmitter design to use

common anode VCSELs, a comparison of the two designs could be determined.

30

Figure27a. Common Cathode TX Schematic

Figure 27b Common Anode TX Schematic

In Figure 28, jumpers were added to certain locations in the layout in order to

accommodate the use common anode VCSELs. The jumpers allow the VCSEL or potentiometer

to be shorted to ground or the power supply depending on the desired configuration. In the

second transmitter design, the spacing for the surface mount potentiometers were increase

because there might be a potential problem with soldering components that are so close to each

other. By observing the Maxim evaluation boards, the potentiometer is the largest component

that was soldered onto the printed circuit board. The overall design of the second transmitter

layout seems promising because it takes in account of all the problems that can occur when

gigabit data transmission is implemented.

31

Figure 28 - Transmitter 2 Layout.

After the modification of the circuit, a layout for the optical receiver board was performed using

the ExpressPCB software, a free program that was proprietary to that vendor. The ExpressPCB

vendor was chosen to make the printed circuit boards (PCB) because it was less expensive than

other vendors. The provided software was simple, but highly efficient for a novice designer. A

helpful lecture was presented on using the software that provided the good foundation to begin

layouts. Through further experimentation, the layouts for the receiver and the transmitter circuit

were completed.

IX. Outlook/Paper 2 Preview

As of October 23, 2002, the G7 design team is moving ahead as planned. We currently

are awaiting the arrival of our ordered PCBs and various components. We are monitoring the

delivery pathways and expect the majority, if not all necessary parts to be in-house very soon.

Upon arrival of the printed circuit boards containing our TX and RX designs we will attach the

laser driver, TIA, and the limiting amp. This will be followed by the attachment of all passive

components. After the active component selection process is completed for all VCSELs and PDs

that are in our possession, they will be attached the boards, thus completing the assembly

process. The team will then conduct test on the receiver and transmit apparatuses, at varying

32

attenuation levels. If time permits we would also like to do a second assembly, utilizing the

components we deemed to have had lower typical performance values than those of the ones

used in the first build, but that could provide a more economically viable option. This will allow

for a meaningful comparison of “cost-VERSUS-performance” that should prove very

informative.

In the next paper we intend to present the procedures, results, data, and analysis

associated with the final build and testing of our completed transmit and receiver boards.

Provided along with the performance results will be a comprehensive production cost analysis.

This will help determine the feasibility of mass production of the teams designed optoelectronic

link, and will likely be accompanied by suggestions and opinions on ways in which the link

could be improved to better insure the profitability of any such undertaking.

33

REFERENCES

[1] Tanenbaum, Andrew S., Computer Networks. New Jersey: Prentice Hall. 1996

[2] “Gigabit_Ehternet”, August 9, 1999.

http://www.syskonnect.com/syskonnect/technology/Gigabit_Ethernet.PDF

[3] “Gigabit Ethernet”, December 2, 2000.

http://www.comm.toronto.edu/~karen/projects/21.GbEthernet-802.3/overview.html

[4] “Ethernet Web”, January 31, 2000.

http://www.ots.utexas.edu/ethernet

[5] “Gigabit Ethernet: Your Pipe Dream Come True?”, Netware Connection. April 1998.

http://www.nwconnection.com/apr.98/gigbit48/

[6] “A Brief Introduction to Jitter in Optical Receivers”, December 8, 2000.

http://pdfserv.maxim-ic.com/arpdf/AppNotes/4hfan401.pdf

[7] Gigabit Ethernet Background Info from Cisco

http://www.cisco.com/warp/public/cc/techno/media/lan/gig/tech/gigbt_tc.htm

[8] Redd, Justion. “Synch and clock recovery- an analog guru looks at jitter,” Planet Analog.

August 31, 2001. http://www.planetanalog.com/features/OEG20010827S0037

[9] “White Paper: Free-Space Optical Laser Safety”,

http://www.essentia.it/documenti/WP_Articoli_Tecnici/LigthPointe-

WhitePaper_FSO_Human_Safety.pdf

[10] Kolesar, Paul and Jane Ehrgott. “Laser Safety Standards Update and Impact on 850 nm

Serial PMD”, http://grouper.ieee.org/groups/802/3/ae/public/mar00/kolesar_1_0300.pdf

[11] IEEE Std 802.3, 2000 Editionhttp://standards.ieee.org/reading/ieee/std/lanman/restricted/802.3-2000.pdf

[12] Maxim 3264 Limiting Amplifier datasheethttp://pdfserv.maxim-ic.com/arpdf/MAX3264-MAX3765.pdf

[13] Maxim 3266 TIA datasheethttp://pdfserv.maxim-ic.com/arpdf/MAX3266-MAX3267.pdf

[14] Maxim 3287 Laser Driver datasheethttp://pdfserv.maxim-ic.com/arpdf/MAX3286-MAX3299.pdf

34

[15] Honeywell HFE4085-321 VCSEL datasheethttp://content.honeywell.com/vcsel/pdf/4085-321.pdf

[16] Honeywell HFE4383-521 VCSEL datasheethttp://content.honeywell.com/vcsel/pdf/HFE4380,4381.pdf

[17] Optek OPV200 VCSELhttp://www.optekinc.com/pdf/OPV200.pdf

[18] Optek OPV210 VCSELhttp://www.optekinc.com/pdf/OPV210.pdf

[19] Infineon BPX63 Photodiodehttp://www-soem.ecu.edu.au/units/scp3313/bpx63.pdf

[20] Optek OPF420 Photodiodehttp://www.optekinc.com/pdf/OPF420.pdf

[21] Hammamatsu S5973 Photodiodehttp://www.hpk.co.jp/eng/products/ssd/PDF/3/S5971,S5972,S5973_series_KPIN1025E02.pdf

[22] Figure 6 (From http://www.planetanalog.com/features/OEG20010827S0037)

[]

35

APPENDIX A:Parts List of Vendors used in research

Vendors UsedVendor Website- Contacts info Components

1 Kyosemi www.yosemi-usa.com (408-946-8836) VCSEL2 Laser Mate 909-718-0999 VCSEL3 Honeywell 1-800 MY VCSEL or 972-470-4660 VCSEL/PD4 Optek Technology 972 323 2200 Photodiode5 Hamamatsu www.hamamatsu.com (1 800 524 0504 or

908 231 0960)Photodiode

6 Mouser Electronics www.mouser.com POT: 328-42 series, Inductor: 801-Bl11HA102SG

POT/Inductors

7 Maxim www.maxim.com Laser driver /TIA/Limiting Amp

8 Metrodyne Microsystem Corp.

www.metrodyne.com.tw VCSEL/PD

9 Express PCB www. expresspcb.com PCBoard Manufacturer

36

APPENDIX B

Management Plan

ECE 4006-B GIGABIT ETHERNETGROUP #7

Update Presentation #7ECE 4006b Gigabit Ethernet Group #7 Management Plan (-Ver. 6.5)

Week34 Week35 Week36 Week37 Week38 Week39 Week40 Week41 Week42 Week43 Week44 Week45 Week46 Week47 Week48 Week49

Aug.20 Aug.27 Sept.3 Sept.10 Sept. 19 Sept.24 Oct.1 Oct.8 Oct.15 Oct. 24 Oct.29 Nov.5 Nov.12 Nov.19 Nov.26 Dec. 3EXAM1 PAPER1

TASK X X X X X X X X X X PAPER2

PHA

SE 1

Research

X Pre-fab practice

X TX Design Verfication

PHA

SE 2

Vendor Contact

Board Design(parallel TX designs)

Order Componets

Order Receipt verification

PHA

SE 3

Component/board Assembly"BUILD1" -Primary

Testing

Repair

Final Testing(or Scrap and move to BUILD2)

Component/board Assembly"BUILD2" - Secondary

B2_Testing & Repair

B2_Final Testing

Analysis

PHA

SE 4

Draft of paper

Paper rewriteFinal Paper Writing Period

Upload final version

LEGENDindicates projected task/timeindicates completed taskindicates professor review dates/times

X task/week check off symbolindicated possible schedule shiftindicates behind scheduleindicates work progress

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