i c and pulse and digital circuits lab
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No:1
LINEAR WAVE SHAPING
AIM :
a) To study the response of RC Low pass circuit and to determine rise time for a square wave input for different time constants.
i)
RC>>T
ii) RC
=Tiii)
RC<<T b) To study the response of RC Hih pass circuit and to determine percentae ti!t for a square input for different time constants.
i)
RC>>Tii)
RC
=T
iii)
RC<<T.
Components Required :
1. Resistors - 1!"# 1 !"# 1M" $. Ca%acitor - .1&' Apparatus Required :
1. (read (oard.$. CR)
*. 'unction +enerator.
,. Connecting ires.THEOR:
LINEAR WAVE SHAPING
e %rocess o0 ere b2 te 0orm o0 a non-sinusoidal signal is altered b2
transmission troug a linear netor! is called 3 L"#$%R &%'$ (H%"#*+.
a! RC Lo" Pass Cir#uit :
R
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Vi
C
V$
'igure 1: RC Lo Pass Circuit.
e circuit %asses lo 0re4uencies readil2 but attenuates ig 0re4uencies because tereactance o0 te ca%acitor decreases it increasing 0re4uenc2. 5t 6er2 ig 0re4uencies teca%acitor acts as a 6irtual sort circuit and te out%ut 0alls to 7ero. is circuit also or!s asintegrating circuit. 5 circuit in ic te out%ut 6oltage is %ro%ortional to te integral o0 tein%ut 6oltage is !non as integrating circuit. e condition 0or integrating circuit is RC 6aluemust be muc greater tan te time %eriod o0 te in%ut a6e 8RC99 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No:1
LINEAR WAVE SHAPING
AIM :
a) To study the response of RC Low pass circuit and to determine rise time for a square wave input for different time constants.
i)
RC>>Tii)
RC
=T
iii)
RC<<T b) To study the response of RC Hih pass circuit and to determine
percentae ti!t for a square input for different time constants.
i)
RC>>Tii)
RC=
T
iii) RC<<T.
Components Required :
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1. Resistors - 1!"# 1 !"# 1M" $. Ca%acitor - .1&' Apparatus Required :
1. (read (oard.$. CR)
*. 'unction +enerator.,. Connecting ires.THEOR:
LINEAR WAVE SHAPING
e %rocess o0 ere b2 te 0orm o0 a non-sinusoidal signal is altered b2
transmission troug a linear netor! is called 3 L"#$%R &%'$ (H%"#*+.
a! RC Lo" Pass Cir#uit :
R
Vi
C
V$ 'igure 1: RC Lo Pass Circuit.
e circuit %asses lo 0re4uencies readil2 but attenuates ig 0re4uencies because tereactance o0 te ca%acitor decreases it increasing 0re4uenc2. 5t 6er2 ig 0re4uencies teca%acitor acts as a 6irtual sort circuit and te out%ut 0alls to 7ero. is circuit also or!s asintegrating circuit. 5 circuit in ic te out%ut 6oltage is %ro%ortional to te integral o0 tein%ut 6oltage is !non as integrating circuit. e condition 0or integrating circuit is RC 6aluemust be muc greater tan te time %eriod o0 te in%ut a6e 8RC99 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Let Vi alternating in%ut 6oltage.
i resulting current
5%%l2ing irco00ps Voltage La to RC lo %ass circuit 80ig.1.
T 1 ' iR
i dt .
i q
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C o
Multi%l2ingtrougout b2
C#eget
T C'
iRC
i dt .
i q o T
5s RC >> T # te term i dt .ma2 be neglected
o
∴
C' iRC
i
Integratingitres%ect
to T on bot sides# e get T
T C' dt .
RC i dt .
i
T t 1 1 i dt .
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' dt
.i
C
RC
T 1 '
.
i dt C t ∴
1 ' .
' dt i
RC
e out%ut 6oltage is %ro%ortional to te integral o0 te in%ut 6oltage.E(PECTE) GRAPH:
Vi
t *$+,!V$
*$+-!V
RC.T
$
t
tr
RC//T
V$
t
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Let
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Vi alternating in%ut 6oltage.i resulting current
5%%l2ing irco00ps Voltage La to RC lo %ass circuit 80ig.1.T
1 '
iR i dt .
i q C o
Multi%l2ingtrougout
b2C#eget
T
C' iRC i dt
.i
q o
T 5s RC >> T # te term i dt .
ma2 be neglected o ∴
C' iRC i
Integratingitres%ectto T on bot sides# e get
T T
C' dt .
RC i dt
.
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i
T t
1 1 i dt
.
' dt .
i C
RC T
1 ' .
i dt C t
∴
1 ' .
' dt i RC
e out%ut 6oltage is %ro%ortional to te integral o0 te in%ut 6oltage.E(PECTE) GRAPH:
Vi
t
*$+,!V$
*$+-!V
RC.T
$
t
tr
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RC//T
V$
t
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 0! RC Hi12 Pass
Cir#uit+
C
Vi
R
V$ 'igure: $. RC ig Pass Circuit.
e iger 0re4uenc2 com%onents in te in%ut signal a%%ears at te out%ut it less attenuation tan te loer 0re4uenc2 com%onents because te reactance o0 te ca%acitordecreases it increase in 0re4uenc2. is circuit or!s as a di00erential circuit. 5 circuit inic te out%ut 6oltage is %ro%ortional to te deri6ati6e o0 te in%ut 6oltage is !non asdi00erential circuit. e condition 0or di00erential circuit is RC 6alue must be muc smaller tente time %eriod o0 te in%ut a6e ,RC<<T).
5%%l2ing irco00ps Voltage La to RC ig %ass circuit 80ig.$
T 1 ' i dt .
iR .i
q C o
Di6ide
trougout b2R
T
' 1 i i dt
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.q i . R
RC o
5s RC << T # te abo6e e4uation is modi0ied as
T '
1 i i dt
. R
RC o
Di00erentiatingabo6e
e4uationitres%ectto T .1 d
1 ' i
. R dt i
RC
d RC ' iR
dt i
' iR d
d
ere0ore ' .
' ∝ '
RC 'i
dt i dt
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T
' 1 i i dt
. R RC o
Di00erentiatingabo6ee4uationitres%ectto T .1 d
1 ' i .
R dt i
RC d RC
' iR dt i ' iR
d d ere0ore '
.' ∝
'
RC 'i dt
i
dt
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
GRAPHS:
Vi
t
V- V t
RC3T
-
V
RC..T
t
)ESIGN:
1.Coose 1msec.
$.velect C .1 &'.*.'or RC w select R.,.'or RC 99 w select R.x.'or RC yy w select R.z.I0 RC yy # te ig %ass circuit or!s as a di00erentiator.{.I0 RC 99 # te Lo %ass circuit or!s as an integrator.PROCE)%RE:
1.Connect te circuit as son in te 0igure1 |$.$.Connect te 0unction generator at te in%ut terminals and CR) at te out%ut
terminals o0 te circuit.*.5%%l2 a s4uare a6e signal o0 0re4uenc2 17 at te in%ut. 8 1
msec. ,.
)bser6e te out%ut a6e0orm o0 te circuit 0or di00erent time constants.x.Calculate te rise time 0or lo %ass 0ilter and tilt 0or ig %ass 0ilter and com%are it te
teoretical 6alues.z.'or lo %ass 0ilter select rise time 8tr $.$ RC 8teoretical. e rise time is
de0ined as te time ta!en b2 te out%ut 6oltage to rise 0rom .1 to .= o0 its 0inal 6alue.{.
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} tilt , T-RC ) ~ /00 8 teoretical } tilt = 1 , ' / 2 '/ ) - , ' - ) 3 ~ /00 8 %ractical INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
GRAPHS:
Vi
t
V- V t
RC3T
-
V
RC..T
t
)ESIGN:
1.Coose 1msec.
$.velect C .1 &'.*.'or RC w select R.,.'or RC 99 w select R.x.'or RC yy w select R.z.I0 RC yy # te ig %ass circuit or!s as a di00erentiator.{.
I0 RC 99 # te Lo %ass circuit or!s as an integrator.PROCE)%RE:
1.Connect te circuit as son in te 0igure1 |$.$.Connect te 0unction generator at te in%ut terminals and CR) at te out%ut
terminals o0 te circuit.*.
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5%%l2 a s4uare a6e signal o0 0re4uenc2 17 at te in%ut. 8 1 msec. ,.
)bser6e te out%ut a6e0orm o0 te circuit 0or di00erent time constants.x.
Calculate te rise time 0or lo %ass 0ilter and tilt 0or ig %ass 0ilter and com%are it teteoretical 6alues.z.'or lo %ass 0ilter select rise time 8tr $.$ RC 8teoretical. e rise time is
de0ined as te time ta!en b2 te out%ut 6oltage to rise 0rom .1 to .= o0 its 0inal 6alue.{.} tilt , T-RC ) ~ /00 8 teoretical
} tilt = 1 , ' / 2 '/ ) - , ' - ) 3 ~ /00 8 %ractical INSTIT%TE O& ENGINEERING ' TECHNOLOG
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II RES%LT:
1. Rise time 0or lo%ass 0ilter en RC yy eoretical
Practical
$. } tilt 0or ig%ass 0ilter en RC .eoreticalPractical
Res%onse o0 RC Lo %ass circuit is obser6ed and rise time calculated.Res%onse o0 RC ig %ass circuit is obser6ed and %ercentage tilt is
calculated.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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•
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II RES%LT:
1. Rise time 0or lo%ass 0ilter en RC yy eoretical
Practical
$. } tilt 0or ig%ass 0ilter en RC .eoreticalPractical
Res%onse o0 RC Lo %ass circuit is obser6ed and rise time calculated.Res%onse o0 RC ig %ass circuit is obser6ed and %ercentage tilt is
calculated.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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k?SF NO?k ?JGK
€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No:2
NON LINEAR WAVE SHAPING 4 CLIPPERS
AIM :
To study the c!ippin circuits for the fo!!owin reference vo!taes and
to verify the responses.Components Required:
1. Resistors - 1" $. I,{ Diode ‚ $o.
Apparatus Required :
1. (read board.$. 'unction generator
*. CR) ,. Poer su%%l2 -*V x. Connecting ires.
THEOR:
e non-linear semiconductor diode in combination it resistor can 0unction as cli%%er
circuit. Energ2 storage circuit com%onents are not re4uired in te basic %rocess o0 cli%%ing.ese circuits ill select %art o0 an arbitrar2 a6e0orm ic lies abo6e or belo some
%articular re0erence 6oltage le6el and tat selected %art o0 te a6e0orm is used 0or transmission.vo te2 are re0erred as 6oltage limiters# current limiters# am%litude selectors or slicers.
ere are tree di00erent t2%es o0 cli%%ing circuits.
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1Positi6eCli%%ingcircuit.
$ egati6e Cli%%ing.* Positi6e and egati6e Cli%%ing 8 slicer .
In %ositi6e cli%%ing circuit %ositi6e c2cle o0 vinusoidal signal is cli%%ed and negati6e %ortion o0 sinusoidal signal is obtained in te out%ut o0 re0erence 6oltage is added# instead o0com%lete %ositi6e c2cle tat %ortion o0 te %ositi6e c2cle ic is abo6e te re0erence 6oltage6alue is cli%%ed.
In negati6e cli%%ing circuit instead o0 %ositi6e %ortion o0 sinusoidal signal# negati6e %ortion is cli%%ed.
In slicer bot %ositi6e and negati6e %ortions o0 te sinusoidal signal are cli%%ed.I+ Positi5e C6ippin1
1 '
I ,{ ' i 0
'igure:1 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No:2
NON LINEAR WAVE SHAPING 4 CLIPPERS
AIM :
To study the c!ippin circuits for the fo!!owin reference vo!taes and
to verify the responses.Components Required:
1. Resistors - 1" $. I,{ Diode ‚ $o.
Apparatus Required :
1. (read board.$. 'unction generator
*. CR)
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,. Poer su%%l2 -*V x. Connecting ires.
THEOR:
e non-linear semiconductor diode in combination it resistor can 0unction as cli%%er
circuit. Energ2 storage circuit com%onents are not re4uired in te basic %rocess o0 cli%%ing.ese circuits ill select %art o0 an arbitrar2 a6e0orm ic lies abo6e or belo some %articular re0erence 6oltage le6el and tat selected %art o0 te a6e0orm is used 0or transmission.
vo te2 are re0erred as 6oltage limiters# current limiters# am%litude selectors or slicers.
ere are tree di00erent t2%es o0 cli%%ing circuits.
1Positi6eCli%%ingcircuit.
$ egati6e Cli%%ing.* Positi6e and egati6e Cli%%ing 8 slicer .
In %ositi6e cli%%ing circuit %ositi6e c2cle o0 vinusoidal signal is cli%%ed and negati6e %ortion o0 sinusoidal signal is obtained in te out%ut o0 re0erence 6oltage is added# instead o0com%lete %ositi6e c2cle tat %ortion o0 te %ositi6e c2cle ic is abo6e te re0erence 6oltage6alue is cli%%ed.
In negati6e cli%%ing circuit instead o0 %ositi6e %ortion o0 sinusoidal signal# negati6e %ortion is cli%%ed.
In slicer bot %ositi6e and negati6e %ortions o0 te sinusoidal signal are cli%%ed.I+ Positi5e C6ippin1
1 '
I ,{ '
i
0 'igure:1 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Vi V
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V„ t t
'igure: $8a. In%ut a6e0orm
'igure: $8b)ut%ut a6e0orm.'i is a in%ut sinusoidal signal as son in te 0igure $8a . 'or %ositi6e %ortion o0 tesinusoidal te diode I,{ gets 0orard biased. e out%ut 6oltages in te 6oltage across tediode under 0orard biased ic is cut-in-6oltage o0 te diode. ere0ore te %ositi6e %ortionabo6e te cut-in-6oltage is cli%%ed or not obser6ed in te out%ut ,'0) as son in 0igure $8b.
II+ Positi5e C6ippin1 "it2 Positi5e Re7eren#e Vo6ta1e
1 I ,{ '
' i
0 VR 'igure:*.
Vi V VR8 V„ t t 'igure:,8a. In%ut a6e0orm
'igure:,8b. )ut%ut a6e0orm.
ein%utsinusoidalsignal8 'i in 0igure ,8a can ma!e te diode to conduct en its
instantaneous 6alue is greater tan 'R. …% to tat 6oltage 8 'R) te diode is o%encircuited and te out%ut 6oltage is same as te in%ut 6oltage. 50ter tat 6oltage 8 'R te out%ut6oltage is 'R %lus te cut-in-6oltage 8 ' „ o0 te diode as son in 0igure ,8b.
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Vi V V„
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t t
'igure: $8a. In%ut a6e0orm'igure: $8b)ut%ut a6e0orm.
'i is a in%ut sinusoidal signal as son in te 0igure $8a . 'or %ositi6e %ortion o0 tesinusoidal te diode I,{ gets 0orard biased. e out%ut 6oltages in te 6oltage across tediode under 0orard biased ic is cut-in-6oltage o0 te diode. ere0ore te %ositi6e %ortionabo6e te cut-in-6oltage is cli%%ed or not obser6ed in te out%ut ,'0) as son in 0igure $8b.
II+ Positi5e C6ippin1 "it2 Positi5e Re7eren#e Vo6ta1e
1 I ,{ ' '
i 0
VR 'igure:*.Vi
V VR8 V„ t t 'igure:,8a. In%ut a6e0orm
'igure:,8b. )ut%ut a6e0orm.
ein%utsinusoidalsignal8 'i in 0igure ,8a can ma!e te diode to conduct en its
instantaneous 6alue is greater tan 'R. …% to tat 6oltage 8 'R) te diode is o%encircuited and te out%ut 6oltage is same as te in%ut 6oltage. 50ter tat 6oltage 8 'R te out%ut6oltage is 'R %lus te cut-in-6oltage 8 ' „ o0 te diode as son in 0igure ,8b.
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< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II III+ Positi5e C6ippin1
"it2 Ne1ati5e Re7eren#e Vo6ta1e
1 I ,{
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'
' i 0
VR
'igure: x.V V t i V„ 4VR
t
'igure:z8a.In%uta6e0orm
'igure:z8b)ut%uta6e0orm.
In tis circuit te diode conducts te out%ut 6oltage is same as in%ut 6oltage. e diodeconducts at a 6oltage less b2 'R 0rom cut-in-6oltage called as ' „. 'or 6oltage less tan ' „# tediode is o%en circuited and out%ut is same as in%ut 6oltage.
IV Ne1ati5e C6ippin1 Cir#uit
1 ' I ,{ '0 i 'igure:{.
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<
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II III+ Positi5e C6ippin1"it2 Ne1ati5e Re7eren#e Vo6ta1e
1 I ,{ ' ' i
0
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VR 'igure: x.
V V t
i V„ 4VR
t
'igure:z8a.In%uta6e0orm'igure:z8b)ut%uta6e0orm.
In tis circuit te diode conducts te out%ut 6oltage is same as in%ut 6oltage. e diodeconducts at a 6oltage less b2 'R 0rom cut-in-6oltage called as ' „. 'or 6oltage less tan ' „# tediode is o%en circuited and out%ut is same as in%ut 6oltage.
IV Ne1ati5e C6ippin1 Cir#uit
1 ' I ,{ '0
i 'igure:{.
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† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Vi V t t
-V „
'igure:‡8a.In%uta6e0orm'igure:‡8b.
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)ut%uta6e0orm.
'or tis %ortion o0 te in%ut sinusoidal signal ,'i)# te diode gets re6erse biased and it iso%en. en te out%ut 6oltage is same as in%ut 6oltage. 'or te negati6e %ortion o0 te signal te
diode gets 0orard biased and te out%ut 6oltage is te cut-in-6oltage 8 4' „ ) o0 te diode. ente in%ut sinusoidal 6ariation is not seen in te out%ut. ere0ore te negati6e %ortion o0 te in%utsinusoidal signal ,'i) is cli%%ed in te out%ut signal , '0 ).
V+ Ne1ati5e C6ippin1 "it2 Ne1ati5e Re7eren#e Vo6ta1e
1 I ,{ 'i '0 VR 'igure:= Vi
V t t 4VR4V„
'igure:18a.In%uta6e0orm.'igure:18b)ut%uta6e0orm.
In tis circuit# te diode gets 0orard biased 0or te in%ut sinusoidal 6oltage is less tan 8 2'R. 'or in%ut 6oltage greater tan 8 2'R# te diode is non-conducting and it is o%en. en teout%ut 6oltage is same as in%ut 6oltage.
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† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Vi V t t -V „
'igure:‡
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8a.In%uta6e0orm'igure:‡8b.
)ut%uta6e0orm.
'or tis %ortion o0 te in%ut sinusoidal signal ,'i)# te diode gets re6erse biased and it iso%en. en te out%ut 6oltage is same as in%ut 6oltage. 'or te negati6e %ortion o0 te signal tediode gets 0orard biased and te out%ut 6oltage is te cut-in-6oltage 8 4' „ ) o0 te diode. ente in%ut sinusoidal 6ariation is not seen in te out%ut. ere0ore te negati6e %ortion o0 te in%utsinusoidal signal ,'i) is cli%%ed in te out%ut signal , '0 ).
V+ Ne1ati5e C6ippin1 "it2 Ne1ati5e Re7eren#e Vo6ta1e
1 I ,{
'i '0 VR 'igure:= Vi V t t 4VR4V„
'igure:18a.In%uta6e0orm.'igure:18b)ut%uta6e0orm.
In tis circuit# te diode gets 0orard biased 0or te in%ut sinusoidal 6oltage is less tan 8 2'R. 'or in%ut 6oltage greater tan 8 2'R# te diode is non-conducting and it is o%en. en teout%ut 6oltage is same as in%ut 6oltage.
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ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II VI+ Ne1ati5e C6ippin1
"it2 Positi5e Re7eren#e Vo6ta1e
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1 I ,{ 'i '0
VR
'igure:11.Vi V VR4V„ t t
'igure:1$8aIn%uta6e0orm'igure:1$8b
)ut%uta6e0orm.
'or in%ut sinusoidal signal 6oltage less tan 'R# te diode is sorted and te out%ut6oltage is 0i‰ed ar 'R. 'or in%ut sinusoidal 6oltage greater tan 'R te diode is re6erse biasedand o%en circuited. en te out%ut 6oltage is same as in%ut 6oltage.
VII+ S6i#er
1 I ,{ I ,{ VR1 VR$ 'igure:1*.
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ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II VI+ Ne1ati5e C6ippin1
"it2 Positi5e Re7eren#e Vo6ta1e 1 I ,{ 'i
'0 VR 'igure:11.
Vi
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V VR4V„ t t
'igure:1$8aIn%uta6e0orm'igure:1$8b)ut%uta6e0orm.
'or in%ut sinusoidal signal 6oltage less tan 'R# te diode is sorted and te out%ut6oltage is 0i‰ed ar 'R. 'or in%ut sinusoidal 6oltage greater tan 'R te diode is re6erse biasedand o%en circuited. en te out%ut 6oltage is same as in%ut 6oltage.
VII+ S6i#er
1 I ,{ I ,{ VR1 VR$ 'igure:1*.
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II V Vi t V„8VR
t V„4VR
'igure:1,8a.In%ut
a6e0orm'igure1,8b.)ut%uta6e0orm.)ESIGN:
1. 'or %ositi6e cli%%ing at ŠVp 6olts re0erence select VR V.$. 'or negati6e cli%%ing at ŠVp 6olts re0erence select VR V.*. 'or cli%%ing at to inde%endent le6els at V1|V$ re0erence 6oltages select
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VR1 V1# VR$ V$ and VR$ 9 VR1.PROCE)%RE:
1. Connect te circuit as son in te 0igure 1.$. Connect te 0unction generator at te in%ut terminals and CR) at te out%ut
terminals o0 te circuit.
*. 5%%l2 a sine a6e signal o0 0re4uenc2 17 at te in%ut and obser6e te out%ut a6e0orms o0 te circuits.,. Re%eat te %rocedure 0or 0igure *# x# {# =# 11 and 1*.RES%LT:
V„
Cli%%ing circuits 0or di00erent re0erence 6oltages are studied.9%ESTIONS:
1. at is a cli%%er‹ Describe 8i Positi6e cli%%er 8ii (iased cli%%er 8iii Combinationcli%%er.
$. Discuss te di00erences beteen sunt and series cli%%er.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II V Vi
t V„8VR
t V„4VR
'igure:1,8a.In%uta6e0orm'igure1,8b.)ut%uta6e0orm.)ESIGN:
1. 'or %ositi6e cli%%ing at ŠVp 6olts re0erence select VR V.$. 'or negati6e cli%%ing at ŠVp 6olts re0erence select VR V.*. 'or cli%%ing at to inde%endent le6els at V1|V$ re0erence 6oltages select
VR1 V1# VR$ V$ and VR$ 9 VR1.PROCE)%RE:
1. Connect te circuit as son in te 0igure 1.$. Connect te 0unction generator at te in%ut terminals and CR) at te out%ut
terminals o0 te circuit.
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*. 5%%l2 a sine a6e signal o0 0re4uenc2 17 at te in%ut and obser6e te out%ut a6e0orms o0 te circuits.
,. Re%eat te %rocedure 0or 0igure *# x# {# =# 11 and 1*.RES%LT:
V„ Cli%%ing circuits 0or di00erent re0erence 6oltages are studied.9%ESTIONS:
1. at is a cli%%er‹ Describe 8i Positi6e cli%%er 8ii (iased cli%%er 8iii Combinationcli%%er.
$. Discuss te di00erences beteen sunt and series cli%%er.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No:3
NON LINEAR WAVE SHAPING CLAMPERS
AIM :
To et positive and neative c!ampin for sinusoida! and (quare wave inputs.
Components Required:
1.Resistors - 1!"
$. I,{ Diode *. Ca%acitor -1&' Apparatus Required:
1. (read board $. 'unction generator *. CR) ,. Poer su%%l2 -*V x. Connecting ires.
THEOR:
C6ampin1 Cir#uit “A clampin circ!it i" one t#at ta$e" an inp!t %a&e'orm an( pro&i(e" an o!tp!t t#at i"
a 'ait#'!l replica o' it" "#ape )!t #a" one e(e ti#tl* clampe( to t#e +ero &oltae
re'erence
point,
ere are 6arious t2%es o0 Clam%ing circuits# ic are mentioned belo: 1. Positi6e Clam%ing Circuit.
$. egati6e Clam%ing Circuit.
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*. Positi6e Clam%ing it %ositi6e re0erence 6oltage.,. egati6e Clam%ing it %ositi6e re0erence 6oltage.x. Positi6e Clam%ing it negati6e re0erence 6oltage.z. egati6e Clam%ing it negati6e re0erence 6oltage.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No:3
NON LINEAR WAVE SHAPING CLAMPERS
AIM :
To et positive and neative c!ampin for sinusoida! and (quare wave inputs.
Components Required:
1.Resistors - 1!"
$. I,{ Diode *. Ca%acitor -1&' Apparatus Required:
1. (read board $. 'unction generator *. CR)
,. Poer su%%l2 -*V x. Connecting ires.
THEOR:
C6ampin1 Cir#uit
“A clampin circ!it i" one t#at ta$e" an inp!t %a&e'orm an( pro&i(e" an o!tp!t t#at i"
a 'ait#'!l replica o' it" "#ape )!t #a" one e(e ti#tl* clampe( to t#e +ero &oltae
re'erence
point,
ere are 6arious t2%es o0 Clam%ing circuits# ic are mentioned belo: 1. Positi6e Clam%ing Circuit.
$. egati6e Clam%ing Circuit.
*. Positi6e Clam%ing it %ositi6e re0erence 6oltage.,. egati6e Clam%ing it %ositi6e re0erence 6oltage.x. Positi6e Clam%ing it negati6e re0erence 6oltage.z. egati6e Clam%ing it negati6e re0erence 6oltage.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Ne1ati5e C6ampin1
Cir#uit
V5 8
8
4
C
'
)
i '0
4 'igure:1
e in%ut signal is a sinusoidal ic begins at t. e ca%acitor C is carged at t = 0.e a6e0orm across te diode at 6arious instant is studied.
During te 0irst 4uarter c2cle te in%ut signal rises 0rom 7ero to te ma‰imum 6alue 'm.e diode being ideal# no 0orard 6oltage ma2 a%%ear across it. During tis 0irst 4uarter
c2cle te ca%acitor 6oltage '% = 'i. e 6oltage across C rises sinusoidall2# te ca%acitor iscarged troug te series combination o0 te signal source and te diode. rougout tis 0irst4uarter c2cle te out%ut '0 as remained 7ero. 5t te end o0 tis 4uarter c2cle tere e‰ists across
te ca%acitor a 6oltage '% = 'm.
50ter te 0irst 4uarter c2cle# te %ea! as been %assed and te in%ut signal begins to 0all#te 6oltage '% across te ca%acitor is no longer able to 0ollo te in%ut 6oltage. 'or in order todo so# it ould be re4uired tat te ca%acitor discarge# and because o0 te diode# suc adiscarge is not %ossible. e ca%acitor remains carged to te 6oltage '% = 'm# and# a0ter te0irst 4uarter c2cle te out%ut is '0 = 'i ‚ 'm. During succeeding c2cles te %ositi6e e‰cursiono0 te signal Œust barel2 reaces 7ero. e diode need ne6er again conduct# and te %ositi6ee‰tremit2 o0 te signal as been clam%ed to 7ero. e a6erage 6alue o0 te signal is ‚ 'm.
Positi5e C6ampin1 Cir#uit:
'm
8 8
8
4
C
' )
i
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Positi5e C6ampin1 Cir#uit:
'm 8
8
8
4 C
' )
i
'0
4
4
'igure:$
It is also called as negati6e %ea! clam%er# because tis circuit clam%s at te negati6e
%ea!s o0 a signal.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Let
te
in%utsignal be 'i = 'm sin t. en 'i goes negati6e# diode gets 0orard biased and conducts. e
ca%acitor carges to 6oltage 'm# it %olarit2 as son. …nder stead2 state condition# te %ositi6e clam%ing circuit is gi6en as#
' ' Ž 8 ' Ž i
m
'
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E4.1 ' q '
i
m Duringtenegati6eal0c2cleo0 'i# te diode conducts and C carges to ‚ 'm 6olts# i.e.#te negati6e %ea! 6alue. e ca%acitor cannot discarge since te diode cannot conduct in
te re6erse direction. us te ca%acitor acts as a batter2 o0 2'm 6olts and te out%ut 6oltage isgi6en b2 e4uation.1 abo6e. It is seen 0or 0igure $# tat te negati6e %ea!s o0 te in%ut signal are
clam%ed to 7ero le6el. Pea!-to-%ea! am%litude o0 out%ut 6oltage 'm# ic is te same as tato0 te in%ut signal.Ne1ati5e C6ampin1 "it2 Positi5e Re7eren#e Vo6ta1e
C
)
'i '0 'R
'igure:$ vince 'R is in series it te out%ut o0 negati6e clam%ing circuit# no te a6erage 6alueo0 te out%ut becomes ,4'm 5 'R ).
vimilarl2# te a6erage o0
i egati6e clam%ing it negati6e re0erence 6oltage is ,4'm 5 'R ).
ii Positi6eclam%ing is q 'm.
iii Positi6e clam%ing it %ositi6e re0erence 6oltage is 'm 5 'R.
i6 Positi6e clam%ing it negati6e re0erence 6oltage is 'm 4 'R.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Let
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tein%utsignal be 'i = 'm sin t. en 'i goes negati6e# diode gets 0orard biased and conducts. e
ca%acitor carges to 6oltage 'm# it %olarit2 as son. …nder stead2 state condition# te
%ositi6e clam%ing circuit is gi6en as#' ' Ž 8 '
Ž i
m
'
E4.1 ' q '
i m
Duringtenegati6eal0c2cleo0 'i# te diode conducts and C carges to ‚ 'm 6olts# i.e.#te negati6e %ea! 6alue. e ca%acitor cannot discarge since te diode cannot conduct in
te re6erse direction. us te ca%acitor acts as a batter2 o0 2'm 6olts and te out%ut 6oltage isgi6en b2 e4uation.1 abo6e. It is seen 0or 0igure $# tat te negati6e %ea!s o0 te in%ut signal areclam%ed to 7ero le6el. Pea!-to-%ea! am%litude o0 out%ut 6oltage 'm# ic is te same as tato0 te in%ut signal.
Ne1ati5e C6ampin1 "it2 Positi5e Re7eren#e Vo6ta1e
C
)
'i '0
'R
'igure:$ vince 'R is in series it te out%ut o0 negati6e clam%ing circuit# no te a6erage 6alue
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II C6ampin1 Cir#uit
T2eorem:
It states tat 0or an2 in%ut a6e0orm te ratio o0 te areas under te out%ut 6oltage cur6e
in 0orard direction to tat in te re6erse direction is e4ual to te ratio 8 Rf - R). %
R f f
.
% R
r ere %f area o0 te out%ut a6e in 0orard direction.
%r area o0 te out%ut a6e in re6erse direction. Rf and R are 0orard and re6erse resistances o0 te diode.I+ Ne1ati5e C6ampin1
1&' C
1 ' )
R
i '0
I ,{ 'igure:* Vi
V.
Vm
t
t
-Vm
-2Vm
'igure:,8a.In%uta6e0orm'igure:,8b)ut%uta6e0orm.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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k?SF NO?k ?JGK
• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II C6ampin1 Cir#uit
T2eorem:
It states tat 0or an2 in%ut a6e0orm te ratio o0 te areas under te out%ut 6oltage cur6e
in 0orard direction to tat in te re6erse direction is e4ual to te ratio 8 Rf - R). %
R
f
f .
%
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R
r ere %f area o0 te out%ut a6e in 0orard direction.
%r area o0 te out%ut a6e in re6erse direction. Rf and R are 0orard and re6erse resistances o0 te diode.
I+ Ne1ati5e C6ampin1 1&' C
1 '
)
R
i '0
I ,{ 'igure:*
Vi V.
Vm
t
t
-Vm
-2Vm
'igure:,8a.In%uta6e0orm'igure:,8b)ut%uta6e0orm.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II II+ Ne1ati5e C6ampin1
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1 'R 'igure:x Vi
V.
'R t
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t
'igure:z8a.In%uta6e0orm
'igure:z8b)ut%uta6e0orm.III+ Ne1ati5e C6ampin1 "it2 Ne1ati5e Re7eren#e Vo6ta1e+
1&' C
)
I ,{ ' R
i '0 1 'R
'igure:{ INSTIT%TE O& ENGINEERING ' TECHNOLOG
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t
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'igure:z8a.In%uta6e0orm'igure:z8b)ut%uta6e0orm.III+ Ne1ati5e C6ampin1 "it2 Ne1ati5e Re7eren#e Vo6ta1e+
1&' C
)
I ,{
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'
R
i '0
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'R 'igure:{ INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Vi
V.
t
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4'R
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1&' C
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1 ' )
R
i
'0 I ,{ 0igure:= 'm Vi
'm
V.
t
t
4'm
'igure:18a.In%uta6e0orm'igure:18b)ut%uta6e0orm.V+ Positi5e C6ampin1 "it2 Ne1ati5e Re7eren#e Vo6ta1e+
1&' C
)
I ,{ ' R
i
'0 1 'R
'igure: 11 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II
Vi V.
t
t
4'R
'igure:‡8a.In%uta6e0orm'igure:‡8b)ut%uta6e0orm.IV+ Positi5e C6ampin1+
1&' C
1 '
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I ,{ 0igure:= 'm
Vi
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t
t
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4'm
'igure:18a.In%uta6e0orm
'igure:18b)ut%uta6e0orm.V+ Positi5e C6ampin1 "it2 Ne1ati5e Re7eren#e Vo6ta1e+
1&' C
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i '0 1 'R
'igure: 11 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 4' V
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R
i
V.
t
t
'igure:1$8a.In%uta6e0orm'igure:1$8b)ut%uta6e0orm.VI+ Positi5e C6ampin1 "it2 Positi5e re7eren#e Vo6ta1e+
1&' C
) I ,{ ' R
i
'0 1 'R
'igure: 1* Vi
V.
'R t
t
'igure:1,8a.In%uta6e0orm'igure:1,8b)ut%uta6e0orm.PROCE)%RE:
1. Connect te circuit as son in te 0igure *.$. Connect te 0unction generator at te in%ut terminals and CR) at te out%ut
terminals o0 te circuit.*. 5%%l2 a sine a6e and s4uare a6e signal o0 0re4uenc2 1!7 at te in%ut and
obser6e te out%ut a6e0orms o0 te circuits in CR).,. Re%eat te abo6e %rocedure 0or te di00erent circuit diagram as son in0 0igure x# {# =#
11 and 1*.
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< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 4' V
R
i
V.
t
t
'igure:1$8a.In%uta6e0orm'igure:1$8b)ut%uta6e0orm.VI+ Positi5e C6ampin1 "it2 Positi5e re7eren#e Vo6ta1e+
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1&' C
)
I ,{ '
R i
'0 1 'R
'igure: 1* Vi
V.
'R
t
t
'igure:1,8a.In%uta6e0orm'igure:1,8b)ut%uta6e0orm.PROCE)%RE:
1. Connect te circuit as son in te 0igure *.$. Connect te 0unction generator at te in%ut terminals and CR) at te out%ut
terminals o0 te circuit.*. 5%%l2 a sine a6e and s4uare a6e signal o0 0re4uenc2 1!7 at te in%ut and
obser6e te out%ut a6e0orms o0 te circuits in CR).,. Re%eat te abo6e %rocedure 0or te di00erent circuit diagram as son in0 0igure x# {# =#
11 and 1*.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II RES%LT: e clam%ing6oltages 0or %ositi6e and negati6e clam%ing circuits are noted.
9%ESTIONS:
1. E‰%lain te o%eration o0 a clam%ing circuit 0or a s4uare a6e in%ut.$. Di00erentiate te cli%%ers it clam%ers.*. +i6e te a%%lications o0 clam%ers.
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† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II RES%LT: e clam%ing6oltages 0or %ositi6e and negati6e clam%ing circuits are noted.
9%ESTIONS:
1. E‰%lain te o%eration o0 a clam%ing circuit 0or a s4uare a6e in%ut.$. Di00erentiate te cli%%ers it clam%ers.*. +i6e te a%%lications o0 clam%ers.INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK
k?SF NO?k ?JGK
ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II
E;periment
No:<
ST%) O& LOGIC GATES AIM :
To study the various !oic ates by usin discrete components.
Component Required :
1. Resistors - 1!" -1# 1 !" -$ $. I,{ Diode ‚ $ no *. ransistor $$*z= Apparatus Required:
1. Poer su%%l2 -*V $. (read board *. Connecting ires
THEOR: R…5(LE
5(
5
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5.(
1
( vM()L 1
1
1 1 AN/ GA0E:
e 5D gate as a ig out%ut en all te in%uts are ig te 0igure 1 sos one a2 to build te 5D gate b2 using diodes.
Case 1: en bot 5 and ( are lo ten te diodes are in te saturation region ten tesu%%l2 0rom VCC ill 0lo to te diodes ten te out%ut is lo.
Case $: en 5 is lo and ( is ig ten diode D1 ill be in te saturation region andD$ ill be in te Cut-o00 region# ten te su%%l2 0rom VCC ill 0lo troug diode D1 ten teout%ut ill be lo.
Case *: en 5 is ig# ( is lo te diode D1 ill be in te Cut-o00 region and diode D$ill be in saturation region ten te su%%l2 0rom VCC ill 0lo troug te diode D$# tere0orete out%ut ill be lo.
Case ,: en bot te 5 and ( are ig ten te to diodes ill be in Cut-o00 regiontere0ore te su%%l2 0rom VCC ill 0lo troug 'out ten 'out is ig.
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ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II
E;periment
No:<
ST%) O& LOGIC GATES
AIM :
To study the various !oic ates by usin discrete components.Component Required :
1. Resistors - 1!" -1# 1 !" -$ $. I,{ Diode ‚ $ no *. ransistor $$*z= Apparatus Required:
1. Poer su%%l2 -*V $. (read board
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*. Connecting ires THEOR:
R…5(LE
5( 5 5.(
1 ( vM()L
1 1
1 1 AN/ GA0E:
e 5D gate as a ig out%ut en all te in%uts are ig te 0igure 1 sos one a2 to build te 5D gate b2 using diodes.
Case 1: en bot 5 and ( are lo ten te diodes are in te saturation region ten tesu%%l2 0rom VCC ill 0lo to te diodes ten te out%ut is lo.
Case $: en 5 is lo and ( is ig ten diode D1 ill be in te saturation region andD$ ill be in te Cut-o00 region# ten te su%%l2 0rom VCC ill 0lo troug diode D1 ten teout%ut ill be lo.
Case *: en 5 is ig# ( is lo te diode D1 ill be in te Cut-o00 region and diode D$ill be in saturation region ten te su%%l2 0rom VCC ill 0lo troug te diode D$# tere0orete out%ut ill be lo.
Case ,: en bot te 5 and ( are ig ten te to diodes ill be in Cut-o00 regiontere0ore te su%%l2 0rom VCC ill 0lo troug 'out ten 'out is ig.
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II R GA0E:
R…5(LE
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5(
5
5 q ( (
1 1 vM()L 1
1 1
1 1 5n )R gate as to or more in%uts but onl2 one out%ut signal. It is called )R gate
because te out%ut 6oltage is ig i0 an2 or all te in%uts are ig.e 0igure $ sos one a2 to build )R gate 8to in%uts b2 using diodes.Case 1: en 5 and ( are lo ten te to diodes D1 and D$ are in Cut-o00 region. en
te 'out is lo.Case $: en 5 is lo and ( is ig ten te diode D1 is in Cut-o00 region and diode D$
is in saturation region# ten te 'out is ig.Case *: en 5 is ig and ( is lo ten te diode D$ is in saturation region and diode
D1 is in Cut-o00 region# ten te 'out is ig.Case ,: en bot 5 and ( are ig te diodes D1 and D$ are in saturation region ten
te out%ut 'out is ig. NR GA0E:
R…5(LE
5(
5 q ( q 5 6
% 7
1
(
1 1
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5 1
1 6 % q 7
(
v2mbol )R gate is re0erred to a ) )R gate because te out%ut is 6 % q 7 . Read tis as
) 5 )R ( or com%liment o0 te 5 )R (. te circuit is in an )R gate 0olloed b2 a ) gate )R in6erter. e onl2 to get ig out%ut is to a6e bot in%uts lo.
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II R GA0E:
R…5(LE
5(
5
5 q ( (
1 1 vM()L 1
1 1
1 1
5n )R gate as to or more in%uts but onl2 one out%ut signal. It is called )R gate because te out%ut 6oltage is ig i0 an2 or all te in%uts are ig.
e 0igure $ sos one a2 to build )R gate 8to in%uts b2 using diodes.Case 1: en 5 and ( are lo ten te to diodes D1 and D$ are in Cut-o00 region. en
te 'out is lo.Case $: en 5 is lo and ( is ig ten te diode D1 is in Cut-o00 region and diode D$
is in saturation region# ten te 'out is ig.
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Case *: en 5 is ig and ( is lo ten te diode D$ is in saturation region and diodeD1 is in Cut-o00 region# ten te 'out is ig.
Case ,: en bot 5 and ( are ig te diodes D1 and D$ are in saturation region tente out%ut 'out is ig.
NR GA0E:
R…5(LE
5(
5 q ( q 5 6
% 7
1 (
1 1
5 1
1 6 % q 7
( v2mbol
)R gate is re0erred to a ) )R gate because te out%ut is 6 % q 7 . Read tis as ) 5 )R ( or com%liment o0 te 5 )R (. te circuit is in an )R gate 0olloed b2 a ) gate )R in6erter. e onl2 to get ig out%ut is to a6e bot in%uts lo.
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II NAN/ GA0E:
R…5(LE
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5.( 5 6
%. 7
5( (
1
1 1 5 1
1 6 %. 7
( 11
v2mbol 5D gate is re0erred to as ) 5D +5E because te out%ut is 6 %. 7 read tis as ) 5 5D ( or Com%liment o0 5 5D (. (2 tis gate te out%ut is lo en allte in%uts are ig.
N0 GA0E:
R…5(LE
5 5 % 1 1 v2mbol
e In6erter or ) gate is it onl2 one in%ut and onl2 one out%ut. It is called in6erter because te out%ut is ala2s o%%osite to te in%ut.
e 0igurex sos te one a2 to build in6erter circuit b2 using transistor 8CE modeen te Vin is lo ten te transistor ill be in te Cut-o00 region. en te su%%l2 0rom VCC ill 0lo to Vout. en te Vout is ig. en Vin is ig ten te transistor is in tesaturation region ten te su%%l2 0rom VCC ill 0lo troug te transistor to te ground# tente Vout is lo.
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II NAN/ GA0E:
R…5(LE
5.( 5
6 %. 7 5
( (
1
1 1 5 1
1 6 %. 7 ( 1
1 v2mbol 5D gate is re0erred to as ) 5D +5E because te out%ut is 6 %. 7 read tis as ) 5 5D ( or Com%liment o0 5 5D (. (2 tis gate te out%ut is lo en allte in%uts are ig.
N0 GA0E:
R…5(LE
5 5 %
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1 1 v2mbol
e In6erter or ) gate is it onl2 one in%ut and onl2 one out%ut. It is called in6erter because te out%ut is ala2s o%%osite to te in%ut.
e 0igurex sos te one a2 to build in6erter circuit b2 using transistor 8CE modeen te Vin is lo ten te transistor ill be in te Cut-o00 region. en te su%%l2 0rom VCC ill 0lo to Vout. en te Vout is ig. en Vin is ig ten te transistor is in tesaturation region ten te su%%l2 0rom VCC ill 0lo troug te transistor to te ground# tente Vout is lo.
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II CIRC%IT
)IAGRAM :
D1 I,{ D1 I,{ 5
5 1 1 ( ( D$ I,{ D$ I,{ AN) GATE
OR GATE
qx
qx
'igure 1'igure $
qx 1 D1 I,{
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1 5 =N=>?,
1 (
D$ I,{ NOR GATE
'igure * VCC 8@V
1 1 D1 I,{ 5 =N=>?,
1
( D$ I,{ NAN) GATE
'igure , INSTIT%TE O& ENGINEERING ' TECHNOLOG
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II CIRC%IT
)IAGRAM :
D1 I,{ D1 I,{ 5 5 1 1
( ( D$ I,{ D$ I,{ AN) GATE
OR GATE
qx qx
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'igure 1'igure $
qx 1
D1 I,{ 1 5 =N=>?,
1 ( D$ I,{ NOR GATE
'igure * VCC 8@V
1 1 D1 I,{ 5 =N=>?,
1 ( D$ I,{ NAN) GATE
'igure , INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II qx 1
1 5 =N=>?,
NOT GATE
'igure x PROCE)%RE:
1. Connect te circuit as son in 0igure 1
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$. Veri02 te trut tables o0 6arious gates 0or di00erent conditions o0 in%uts.*. Re%eat te ste%s 1|$ 0or 0igures $# *# , | x.TR%TH TALES
AN) GATE OR GATE
NAN) GATE
NOR GATENOT GATE
A A A A A
$
$
$
$
$
$
$
$
$
$
-
$
-
$
-
$
-
-
$
-
$
-
$
-
$
-
-
-
-
-
-
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-
-
-
W2ere @V is represented 0B 6o1i# -+
RES%LT:
)i77erent 6o1i# 1ates are studied and t2eir trut2 ta06es are 5eri7ied +
9%ESTIONS:
1. Reali7e 5D# )R# ) gates using 5D | )R gates $. 2 5D | )R gates are called uni6ersal gates.
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II qx 1 1 5 =N=>?,
NOT GATE
'igure x
PROCE)%RE: 1. Connect te circuit as son in 0igure 1 $. Veri02 te trut tables o0 6arious gates 0or di00erent conditions o0 in%uts.
*. Re%eat te ste%s 1|$ 0or 0igures $# *# , | x.TR%TH TALES
AN) GATE OR GATE
NAN) GATE
NOR GATE
NOT GATE
A A A A A
$
$
$
$
$
$
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$
$
$
$
-
$
-
$
-
$
-
-
$ -
$
-
$
-
$
-
-
-
-
-
-
-
-
-
W2ere @V is represented 0B 6o1i# -+
RES%LT:
)i77erent 6o1i# 1ates are studied and t2eir trut2 ta06es are
5eri7ied +
9%ESTIONS:
1. Reali7e 5D# )R# ) gates using 5D | )R gates $. 2 5D | )R gates are called uni6ersal gates.
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:@
5STALE M%LTIVIRATOR
AIM : a) To desin and test performance of an %stab!e 8u!tivibrator to
enerate c!oc9 pu!se for a iven frequency.
COMPONENTS RE9%IRE): 1. Resistors $. Ca%acitors .1 &0 - $ *. ransistors $$*z= ‚ $ APPARAT%S :
1. CR) $. Poer su%%l2 -*V *. (read board ,. Connecting ires THEOR:
An A"ta)le m!lti&i)rator #a" t%o !a"i-"ta)le "tate" an( it $eep" on "%itc#in
)et%een t#e"e t%o "tate" )* it"el' No external trierin "inal i" nee(e( 0#e a"ta)le
m!lti&i)rator
cannot remain in(e'initel* in an* o' t#e"e t%o "tate" 0#e t%o ampli'ier" o' an a"ta)le
m!lti&i)rator are reenerati&el* cro""-co!ple( )* capacitor
Prin#ip6e:
5 collector-cou%led astable multi6ibrator using n-%-n transistor in 0igure 1. e or!ing
o0 an astable multi6ibrator can be studied it res%ect to te 0igure1.VCC -=V
RC-
R=
R-
RC=
C
)
C=
C-
9-
9=
=N=>?,
=N=>?,
A
&i1ure:-
Let it be assumed tat te multi6ibrator is alread2 in action and is oscillating i.e.#
sitcing beteen te to states. Let it be 0urter assumed tat at te instant considered# 9= is ON and 9- is O&&.
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:@
5STALE M%LTIVIRATOR
AIM : a) To desin and test performance of an %stab!e 8u!tivibrator to enerate c!oc9 pu!se for a iven frequency.
COMPONENTS RE9%IRE):
1. Resistors $. Ca%acitors .1 &0 - $ *. ransistors $$*z= ‚ $ APPARAT%S :
1. CR) $. Poer su%%l2 -*V *. (read board ,. Connecting ires THEOR:
An A"ta)le m!lti&i)rator #a" t%o !a"i-"ta)le "tate" an( it $eep" on "%itc#in
)et%een
t#e"e t%o "tate" )* it"el' No external trierin "inal i" nee(e( 0#e a"ta)le
m!lti&i)rator
cannot remain in(e'initel* in an* o' t#e"e t%o "tate" 0#e t%o ampli'ier" o' an a"ta)le
m!lti&i)rator are reenerati&el* cro""-co!ple( )* capacitor
Prin#ip6e:
5 collector-cou%led astable multi6ibrator using n-%-n transistor in 0igure 1. e or!ingo0 an astable multi6ibrator can be studied it res%ect to te 0igure1.
VCC -=V
RC-
R=
R-
RC=
C
)
C= C-
9-
9=
=N=>?,
=N=>?,
A
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&i1ure:-
Let it be assumed tat te multi6ibrator is alread2 in action and is oscillating i.e.#
sitcing beteen te to states. Let it be 0urter assumed tat at te instant considered# 9= is ON and 9- is O&&.
INSTIT%TE O& ENGINEERING ' TECHNOLOG 1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II i vince $ is )#ca%acitor C$ carges troug resistor RC1. e 6oltage across C$ is VCC.
ii Ca%acitor C1discarges troug resistor R1# te 6oltage across C1 en it is about to
start discarging is VCC.8Ca%acitor C1 gets carged to VCC en 1 is ).
5sca%acitorC1 discarges more and more# te %otential o0 %oint 5 becomes more and
more %ositi6e 8or less and less negati6e# and e6entuall2 V5 becomes e4ual to V„# te cutin 6oltage o0 1. 'or V5 9 V„# transistor 1 starts conducting. en 1 is ) $ becomes)''.
vimilaro%erations
re%eaten1 becomes ) and $ becomes )''.
usit 9- ON and 9= O&& ca%acitor C1 carges troug resistor RC$ and ca%acitor C$
discarges troug resistor R$. 5s ca%acitor C$ discarges more and more # it is seen tat te %otential o0 %oint ( becomes less and less negati6e 8or more and more %ositi6e# and e6entuall2V( becomes e4ual to V„# te cut in 6oltage o0 $. en V( 9 V„# transistor $ startsconducting.
en $ becomes )n# 1 becomes )''.
It is tus seen tat te circuit !ee%s on sitcing continuousl2 beteen te to 4uasi-stable states and once in o%eration# no e‰ternal triggering is needed. v4uare a6e 6oltage aregenerated at te collector terminals o0 1 and $ i.e.# at %oints C and D.
)ESIGN:
IC ma‰ x m5 w VCC 1$ Vw VCE 8v5 .$V RC 8VCC - VCE8v5 / IC M5‘ Let C .1 &0 and R 1"
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.z= 8R1C1qR$C$ .z=8$RC 8 R1R$ w C1C$
3)q)'' PROCE)%RE:
1. Connect te circuit as son in 0igure 1.
$. )bser6e te a6e0orms at V(E1# V(E$# VCE1# VCE$ and 0ind 0re4uenc2.*. Var2 C 0rom .1 to .1&' and measure te 0re4uenc2 at eac ste%.,. ee% te DC- 5C control o0 te )scillosco%e in DC mode.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II i vince $ is )#ca%acitor C$ carges troug resistor RC1. e 6oltage across C$ is VCC.
ii Ca%acitor C1discarges troug resistor R1# te 6oltage across C1 en it is about tostart discarging is VCC.8Ca%acitor C1 gets carged to VCC en 1 is ).
5sca%acitorC1 discarges more and more# te %otential o0 %oint 5 becomes more and
more %ositi6e 8or less and less negati6e# and e6entuall2 V5 becomes e4ual to V„# te cutin 6oltage o0 1. 'or V5 9 V„# transistor 1 starts conducting. en 1 is ) $ becomes)''.
vimilaro%erationsre%eaten1 becomes ) and $ becomes )''.
usit 9- ON and 9= O&& ca%acitor C1 carges troug resistor RC$ and ca%acitor C$
discarges troug resistor R$. 5s ca%acitor C$ discarges more and more # it is seen tat te %otential o0 %oint ( becomes less and less negati6e 8or more and more %ositi6e# and e6entuall2
V( becomes e4ual to V„# te cut in 6oltage o0 $. en V( 9 V„# transistor $ startsconducting.
en $ becomes )n# 1 becomes )''.
It is tus seen tat te circuit !ee%s on sitcing continuousl2 beteen te to 4uasi-stable states and once in o%eration# no e‰ternal triggering is needed. v4uare a6e 6oltage aregenerated at te collector terminals o0 1 and $ i.e.# at %oints C and D.
)ESIGN:
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IC ma‰ x m5 w VCC 1$ Vw VCE 8v5 .$V RC 8VCC - VCE8v5 / IC M5‘ Let C .1 &0 and R 1" .z= 8R1C1qR$C$ .z=8$RC
8 R1R$ w C1C$
3)q)'' PROCE)%RE:
1. Connect te circuit as son in 0igure 1.$. )bser6e te a6e0orms at V(E1# V(E$# VCE1# VCE$ and 0ind 0re4uenc2.*. Var2 C 0rom .1 to .1&' and measure te 0re4uenc2 at eac ste%.,. ee% te DC- 5C control o0 te )scillosco%e in DC mode.INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
WAVE&ORMS:
9- O&& 9= ON 9- O&& 9= ON
VCC 9- ON 9= O&& 9- ON 9= O&&
VC-
VCE 8v5 t
VCC VC=
VCE 8v5 t
V
V „ -
t
V
V „ =
t I.R C 'igure $ RES%LT:
TON
3
TO&& 3 T*TON 8 TO&&! 3
5stable multi6ibrator is designed and its %er0ormance is tested.
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9%ESTIONS: 1. at is a sitcing circuit‹
$. ’usti02 tat te 5stable Multi6ibrator is a to stage RC cou%led 5m%li0ier using negati6e 0eedbac!. o does it generate s4uare a6e.
*. at is te di00erence beteen a sitcing transistor and an ordinar2 transistor‹
,. at is te e00ect o0 sle rate on te or!ing o0 an )%-am% Multi6ibrator‹INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
WAVE&ORMS:
9- O&& 9= ON 9- O&& 9= ON VCC 9- ON 9= O&& 9- ON 9= O&&
VC-
VCE 8v5 t
VCC VC=
VCE 8v5 t
V
V „ -
t
V
V „ =
t
I.R C 'igure $ RES%LT:
TON
3TO&& 3 T*TON 8 TO&&! 3
5stable multi6ibrator is designed and its %er0ormance is tested.9%ESTIONS:
1. at is a sitcing circuit‹$. ’usti02 tat te 5stable Multi6ibrator is a to stage RC cou%led 5m%li0ier using
negati6e 0eedbac!. o does it generate s4uare a6e.*. at is te di00erence beteen a sitcing transistor and an ordinar2 transistor‹
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,. at is te e00ect o0 sle rate on te or!ing o0 an )%-am% Multi6ibrator‹INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:?
MONOSTALE M%LTIVIRATOR
AIM :
a o design and test %er0ormance o0 a monostable multi6ibrator to generate cloc! %ulse 0or a gi6en 0re4uenc2. 5nd obtain te a6e0orms.
Components Required:
1. Resistors
$. Ca%acitors.*. ransistors $$*z= ‚ $
Apparatus Required:
1. CR) $. Poer su%%l2 -*V *. (read board ,. Connecting ires CIRC%IT )IAGRAM:
VCC -=V
RC-
R3-$D
RC= R-
C3$+-&&
=N=>?, 9-
9=
=N=>?,
R=
4V 4-+@V
'igure 1 THEOR :
Š5 monostable multi6ibrator as onl2 one stable state# te oter state being 4uasi-
stable. ormall2 te multi6ibrator is in te stable state# and en an e‰ternal triggering %ulse is a%%lied# it sitces 0rom te stable to te 4uasi-stable state. It remains in te 4uasi-stablestate INSTIT%TE O& ENGINEERING ' TECHNOLOG
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< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:?
MONOSTALE M%LTIVIRATOR
AIM :
a o design and test %er0ormance o0 a monostable multi6ibrator to generate cloc! %ulse 0or a gi6en 0re4uenc2. 5nd obtain te a6e0orms.
Components Required:
1. Resistors $. Ca%acitors.
*. ransistors $$*z= ‚ $ Apparatus Required:
1. CR)
$. Poer su%%l2 -*V *. (read board ,. Connecting ires CIRC%IT )IAGRAM:
VCC -=V
RC-
R3-$D
RC=
R-
C3$+-&&
=N=>?, 9-
9= =N=>?,
R=
4V 4-+@V
'igure 1 THEOR :
Š5 monostable multi6ibrator as onl2 one stable state# te oter state being 4uasi- stable. ormall2 te multi6ibrator is in te stable state# and en an e‰ternal triggering %ulse is a%%lied# it sitces 0rom te stable to te 4uasi-stable state. It remains in te 4uasi-stablestate INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK
k?SF NO?k ?JGK
† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 0ro a sort duration# but
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automaticall2 re6erts i.e. sitces bac! to its original stable state# itout an2 triggering %ulsep.Prin#ip6e o7 operation
5 collector-cou%led Monostable multi6ibrator o0 te to transistors 1 and $# 1 is
normall2 )'' and $ is ormall2 ). Resistor R1 and R$ are connected to te normall2 )''
transistor# and te ca%acitor C is connected to te normall2 ) transistor.It is seen 0rom te circuit o0 te monostable multi6ibrator tat# under normal conditions#
te su%%l2 6oltage VCC %ro6ides enoug base dri6e to te transistor $ troug resistor R# itte result tat $ goes into saturation. it $ )# 1 goes )''# as alread2 studied in teconte‰t o0 binar2 o%eration.
it$ ) and 1 )''# te ca%acitor 0inds a carging %at. e 6oltage across te
ca%acitor is VCC it %olarit2. It is ob6ious tat in te stable state o0 te multi6ibrator#$ is )
and 1 is )''.I0 te negati6e triggering %ulse is a%%lied to te collector o0 1# it is transmitted to te
base o0 $ troug te ca%acitor# and ence ma!es te base o0 $ negati6e. Immediatel2 $goes )'' and 1 becomes ). oe6er# tis is onl2 a 4uasi-stable state as is ob6ious 0orm te0olloing obser6ation.
it1 ) and $ )''# te ca%acitor C 0inds a discarging %at. 5s te ca%acitor
discarges# it is seen tat te %otential at te base o0 te transistor $ becomes less andless negati6e# and a0ter a time# e a6e V( V„# te cut-in-6oltage o0 $.
5ssoonasV( crosses te le6el o0 V„# $ starts conducting and gets saturated.en $ becomes )# 1 becomes )''. us te original stable state o0 te
multi6ibrator is restored. In quasi4sta06e state: 9- is ON and 9= is O&&F
e inter6al during ic te 4uasi-stable state o0 te multi6ibrator %ersists i.e.# $
remains )'' is de%endent u%on te rate at ic te ca%acitor C discarges. isduration o0 te 4uasi-stable state is termed as dela2 time or %ulse idt or gate time. It is denotedas . e a6e 0orms o0 te 6oltage at base o0 te transistor $ and C 8Collector o0 1 DEvI+: VCE x.xz6# VCC z6# VCE8sat .*6# V(E8sat# .{6# IC zm5#V' -.*6 Rc 8VCC‚VCE8sat/IC.
Ž ' R
' R
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' R
' R C$ 8
$ 77
1 q 7$ 8 sat C ' sat
CC '
1 q :
C$
R q R R q R R
1 $ 1 $ 1 q R R 1 q R
C
C 'ind te 6alues o0 R1 and R$ PROCE)%RE:
1. Connect te circuit as son in 0igure.$. it te el% o0 a triggering circuit and using te condition 8trig 98uasi a %ulse a6e0orm is generated.*. e out%ut o0 te triggering circuit is connected to te base o0 te o00
transistor.,. e )00 transistor goes into ) state.x. )bser6e te a6e0orms at V(E1# V(E$# VCE1# VCE$
z. ee% te DC- 5C control o0 te )scillosco%e in DC mode.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 0ro a sort duration# butautomaticall2 re6erts i.e. sitces bac! to its original stable state# itout an2 triggering %ulsep.
Prin#ip6e o7 operation
5 collector-cou%led Monostable multi6ibrator o0 te to transistors 1 and $# 1 is
normall2 )'' and $ is ormall2 ). Resistor R1 and R$ are connected to te normall2 )'' transistor# and te ca%acitor C is connected to te normall2 ) transistor.
It is seen 0rom te circuit o0 te monostable multi6ibrator tat# under normal conditions#te su%%l2 6oltage VCC %ro6ides enoug base dri6e to te transistor $ troug resistor R# itte result tat $ goes into saturation. it $ )# 1 goes )''# as alread2 studied in te
conte‰t o0 binar2 o%eration.
it$ ) and 1 )''# te ca%acitor 0inds a carging %at. e 6oltage across te
ca%acitor is VCC it %olarit2. It is ob6ious tat in te stable state o0 te multi6ibrator#$ is ) and 1 is )''.
I0 te negati6e triggering %ulse is a%%lied to te collector o0 1# it is transmitted to te base o0 $ troug te ca%acitor# and ence ma!es te base o0 $ negati6e. Immediatel2 $goes )'' and 1 becomes ). oe6er# tis is onl2 a 4uasi-stable state as is ob6ious 0orm te
0olloing obser6ation.
it1 ) and $ )''# te ca%acitor C 0inds a discarging %at. 5s te ca%acitor
discarges# it is seen tat te %otential at te base o0 te transistor $ becomes less andless negati6e# and a0ter a time# e a6e V( V„# te cut-in-6oltage o0 $.
5ssoonasV( crosses te le6el o0 V„# $ starts conducting and gets saturated.
en $ becomes )# 1 becomes )''. us te original stable state o0 temulti6ibrator is restored.
In quasi4sta06e state: 9- is ON and 9= is O&&F
e inter6al during ic te 4uasi-stable state o0 te multi6ibrator %ersists i.e.# $
remains )'' is de%endent u%on te rate at ic te ca%acitor C discarges. isduration o0 te 4uasi-stable state is termed as dela2 time or %ulse idt or gate time. It is denotedas . e a6e 0orms o0 te 6oltage at base o0 te transistor $ and C 8Collector o0 1
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DEvI+: VCE x.xz6# VCC z6# VCE8sat .*6# V(E8sat# .{6# IC zm5#V' -.*6 Rc 8VCC‚VCE8sat/IC.
Ž ' R
'
R ' R
' R C$ 8 $ 77 1 q
7$ 8 sat C ' sat
CC
' 1 q : C$
R q R R q R R
1 $ 1 $ 1 q R R 1 q R C
C 'ind te 6alues o0 R1 and R$ PROCE)%RE:
1. Connect te circuit as son in 0igure.$. it te el% o0 a triggering circuit and using te condition 8trig 98uasi a %ulse a6e0orm is generated.*. e out%ut o0 te triggering circuit is connected to te base o0 te o00
transistor.,. e )00 transistor goes into ) state.
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x. )bser6e te a6e0orms at V(E1# V(E$# VCE1# VCE$ z. ee% te DC- 5C control o0 te )scillosco%e in DC mode.
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;ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
WAVE&ORMS:
9= O&& 9- ON 9- O&& 9= ON
VCC
9= ON 9- O&&
VC
V =
CE *SAT!
t
V „ V=
t
I+R C
VCC
V
VC
CE *SAT! -
t
V „ V-
t
'igure $ RES%LT:
)
)''
otal8) q )''
Monostable multi6ibrator is designed and studied.9%ESTIONS:
1. E‰%lain te o%eration o0 collector cou%led Monostable Multi6ibrator‹
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$. Deri6e te e‰%ression 0or te gate idt o0 a transistor Monostable Multi6ibrator‹*. +i6e te a%%lication o0 a Monostable Multi6ibrator.INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
;ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
WAVE&ORMS:
9= O&& 9- ON 9- O&& 9= ON
VCC
9= ON 9- O&&
VC
V =
CE *SAT!
t
V „ V=
t
I+R C
VCC
V
VC
CE *SAT! -
t
V „ V-
t
'igure $ RES%LT:
)
)''
otal8) q )''
Monostable multi6ibrator is designed and studied.9%ESTIONS:
1. E‰%lain te o%eration o0 collector cou%led Monostable Multi6ibrator‹
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$. Deri6e te e‰%ression 0or te gate idt o0 a transistor Monostable Multi6ibrator‹*. +i6e te a%%lication o0 a Monostable Multi6ibrator.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II
Experiment No:4
ISTALE M%LTIVIRATOR
AIM:
To desin a fi;ed bias 7istab!e 8u!tivibrator and to measure the stab!e state vo!taes and after trierin.
COMPONENTS RE9%IRE): 1. Resistors $. Ca%acitors.
*. ransistors $$*z= ‚ $ APPARAT%S:
1. (read board $. Poer su%%l2 -*V *. CR) ,. Connecting ires THEOR:
A 0ista06e mu6ti5i0rator 2as t"o sta06e output states+ It can remain inde0initel2 in an2
one o0 te to stable states# and it can be induced to ma!e an abru%t transition to te oter stablestate b2 means o0 suitable e‰ternal e‰citation. It ould remain inde0initel2 in tis stable state#until it is again induced to sitc into te original stable state b2 e‰ternal triggering.
(istable multi6ibrators are also termed as Š(inar2ps or 'li%-0lo%sp+ 5 binar2 is sometimesre0erred to as 5Eccle"-6or(an 7irc!it8 .
8VCC
I-
I=
RC-
RC=
R-
R- C
)
9
A
-
9=
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R=
R=
4V
&i1ure -
Prin#ip6e o7 Operation o7 0ista06e mu6ti5i0rator+
Consider te circuit as son in te 0igure.1. e transistor 1 and $ are n-%-n transistors. e2 are cou%led to eac oter as son in 0igure 1. It is e6ident tat teout%ut o0 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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;
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No:4
ISTALE M%LTIVIRATOR
AIM:
To desin a fi;ed bias 7istab!e 8u!tivibrator and to measure the stab!e state vo!taes and after trierin.
COMPONENTS RE9%IRE):
1. Resistors $. Ca%acitors.
*. ransistors $$*z= ‚ $ APPARAT%S:
1. (read board $. Poer su%%l2 -*V *. CR) ,. Connecting ires THEOR:
A 0ista06e mu6ti5i0rator 2as t"o sta06e output states+ It can remain inde0initel2 in an2one o0 te to stable states# and it can be induced to ma!e an abru%t transition to te oter stablestate b2 means o0 suitable e‰ternal e‰citation. It ould remain inde0initel2 in tis stable state#until it is again induced to sitc into te original stable state b2 e‰ternal triggering.
(istable multi6ibrators are also termed as Š(inar2ps or 'li%-0lo%sp+ 5 binar2 is sometimesre0erred to as 5Eccle"-6or(an 7irc!it8 .
8VCC I-
I=
RC-
RC=
R-
R-
C
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VCC -=V
RC-
RC=
=+=D
=+=D
R- -@D R- -@D
=N=>?,
=N=>?,
9
9
=
-
$D
-$
=
= R
-$$D
R
4V 3 4-+@V
'igure: $ PROCE)%RE:
1. Connect te circuit as son in 0igure $.$. )bser6e te a6e0orms at V(E1# V(E$# VCE1# VCE$
*. )bser6e ic transistor is in ) state and ic transistor is in )'' state.,. 5%%l2 ‚6e triggering at te base o0 te ) transistor and obser6e te 6oltages VC1#
VC$# V(1# and V($.x. 5%%l2 q 6e triggering at te base o0 te )'' transistor and obser6e te
Voltages VC1# VC$# V(1# V($.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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;
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II eac transistor iscou%led to te in%ut o0 te oter transistor. vince te transistors are identical# tere 4uiescentcurrents ould be te same# unless te loo% gain is greater tan unit2. en "/ increases sligtl2# te 6oltage dro% across te collector resistance RC/ increases. vince'CC is 0i‰ed# te 6oltage o0 %oint C decreases. is as te e00ect o0 decreasing te base currento0 .
is# in turn# decreases te collector current o0 6i7. " decreases# te 6oltage dro% "RC
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decreases. ence te 6oltage o0 %oint increases.
Duetoincrease
o0 '# te base current o0 / increases. is increases te collector current o0 / 6i7 "/.us "/ 0urter increases. "/RC/ dro% 0urter increases# 'C 0urter decreases# te base current o0 0urter decreases# it te result tat " 0urter decreases. us it can easil2 seen tat i0 tecollector current "/ increases e6en marginall2# " ould go on %rogressi6el2 decreasing and as aresult# "/ ould %rogressi6el2 increase. E6entuall2 " ould become %racticall2 7ero# cutting o00te transistor # at te same time transistor / ould conduct ea6il2 it te result tat itould be dri6en into saturation. us becomes )'' and / becomes ). It can similarl2 be son tat i0 " increases e6en marginall2 similarse4uence o0 o%eration ould result and ultimatel2 ould be ) and / )''. us en / is )# is )'' and en / is )'' is ).
CIRC%IT )IAGRAM:
VCC -=V RC-
RC=
=+=D
=+=D
R- -@D
R- -@D
=N=>?,
=N=>?,
9
9
=
-
$D
-$
=
=
R
-$$D
R
4V 3 4-+@V
'igure: $ PROCE)%RE:
1. Connect te circuit as son in 0igure $.$. )bser6e te a6e0orms at V(E1# V(E$# VCE1# VCE$
*. )bser6e ic transistor is in ) state and ic transistor is in )'' state.,. 5%%l2 ‚6e triggering at te base o0 te ) transistor and obser6e te 6oltages VC1#
VC$# V(1# and V($.x. 5%%l2 q 6e triggering at te base o0 te )'' transistor and obser6e te
Voltages VC1# VC$# V(1# V($.
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;; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
WAVE&ORMS:
VC1 VC$ Voltage Voltage VC$ VC1
t t (e0ore riggering 50ter riggering RES%LT:
V(E1V(E$VCE1VCE$
vtable state Voltages 9%ESTIONS:
1. at is Multi6ibrator‹ E‰%lain te %rinci%le on ic it or!s‹ 2 is it called a binar2‹
$. E‰%lain te role o0 commutating ca%acitors in a (istable Multi6ibrator‹*. +i6e te 5%%lication o0 a (inar2.INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
;; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E(PECTE)
WAVE&ORMS:
VC1 VC$
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Voltage Voltage VC$ VC1
t t (e0ore riggering 50ter riggering RES%LT:
V(E1V(E$VCE1VCE$
vtable state Voltages
9%ESTIONS: 1. at is Multi6ibrator‹ E‰%lain te %rinci%le on ic it or!s‹ 2 is it called a binar2‹
$. E‰%lain te role o0 commutating ca%acitors in a (istable Multi6ibrator‹*. +i6e te 5%%lication o0 a (inar2.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No: 9
SCHMITT TRIGGER
AIM:
To desin and ana!ye (chmitt trier and to observe the waveforms.
COMPONENTS RE9%IRE):
1. Resistors $. ransistors $$*z= ‚ $ *.
APPARAT%S:
1. (read board $. Poer su%%l2 -*V *. vignal generator ,. CR)
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x. Connecting ires.CIRC…I DI5+R5M:
VCC 3 -=V
RC-
RC=
R- R
9
=N=>?,
9
=N=>?,
=
-
q Si1na6
V$
Vi Generator
RE
- R=
'igure:1 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Experiment No: 9
SCHMITT TRIGGER
AIM:
To desin and ana!ye (chmitt trier and to observe the waveforms.
COMPONENTS RE9%IRE): 1. Resistors $. ransistors $$*z= ‚ $ *.
APPARAT%S:
1. (read board $. Poer su%%l2 -*V *. vignal generator
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,. CR) x. Connecting ires.
CIRC…I DI5+R5M: VCC 3 -=V
RC-
RC= R-
R
9
=N=>?,
9
=N=>?,
=
-
q Si1na6
V$ Vi
Generator
RE
- R=
'igure:1 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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;• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
e most im%ortant a%%lication o0 vcmitt rigger circuit are am%litude com%arator ands4uaring circuit are am%litude com%arator and s4uaring circuit. e circuit is used to obtain as4uare a6e0orm 0rom an2 arbitrar2 in%ut a6e0orm. e loo% gain is to be less tan unit2.
I0 is conducting tere ill be 6oltage dro% across R? ic ill ele6ate te emitter o0/. Conse4uentl2 i0 ' is small enoug in 6oltage# / ill be cut-o00 it / conducting# tecircuit am%li0ies and since te gain is %ositi6e# te out%ut to rise# ' continues to 0all and ?
continues to rise. ere0ore a 6alue o0 ' ill be reaced ere is turned )''. 5t te %oint te out%ut no longer res%onds to te in%ut.
ere te in%ut signal is arbitrar2 e‰ce%t tat it as large enoug e‰cursion to carr2 in%ut be2ond te limits o0 2steresis range# 'H = ,'/ 2 ').
e out%ut is a s4uare a6e ose am%litude is inde%endent o0 te am%litude o0 te in%uta6e0orm.
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DEvI+: IC$ xm5 8Rc$ q RE VCC / IC$ …..P VE$ xV V
~ E$ 8RE VCC / 8Rc$qRE I$ .1~IC$ L..P VE1 *V R$ ER$i / I$ VE1 / I$ L..P / I$ Rc ~ 1 “8RE VCC / VE1” ‚RE I($ IC$ / 0e8min 8VCC - VE$ / 8R1qRL1 8VE$/R$qI($
R ~ ( 80e RE / 1 'ind R1# R$# RE# Rc1and Rc$ 0rom te abo6e e4uations PROCE)%RE:
1. Connect te circuit as son in 0igure 1 it designed 6alues.$. 5%%l2 VCC o0 1$V and an in%ut 0re4uenc2 o0 17 it an am%litude more tan te
designed …P.*. o note don te out%ut a6e 0orms
,. )bser6e tat te out%ut comes to ) state en in%ut e‰ceeds …P and it comes to)'' state en in%ut comes belo LP x. )bser6e te a6e0orms at VC1# VC$# V($ and VE and %lot gra%s.
z. ee% te DC- 5C control o0 te )scillosco%e in DC mode.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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;•
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR: e most im%ortant a%%lication o0 vcmitt rigger circuit are am%litude com%arator ands4uaring circuit are am%litude com%arator and s4uaring circuit. e circuit is used to obtain as4uare a6e0orm 0rom an2 arbitrar2 in%ut a6e0orm. e loo% gain is to be less tan unit2.
I0 is conducting tere ill be 6oltage dro% across R? ic ill ele6ate te emitter o0/. Conse4uentl2 i0 ' is small enoug in 6oltage# / ill be cut-o00 it / conducting# tecircuit am%li0ies and since te gain is %ositi6e# te out%ut to rise# ' continues to 0all and ?
continues to rise. ere0ore a 6alue o0 ' ill be reaced ere is turned )''. 5t te
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%oint te out%ut no longer res%onds to te in%ut.
ere te in%ut signal is arbitrar2 e‰ce%t tat it as large enoug e‰cursion to carr2 in%ut be2ond te limits o0 2steresis range# 'H = ,'/ 2 ').
e out%ut is a s4uare a6e ose am%litude is inde%endent o0 te am%litude o0 te in%uta6e0orm.DEvI+:
IC$ xm5 8Rc$ q RE VCC / IC$ …..P VE$ xV V ~ E$ 8RE VCC / 8Rc$qRE I$ .1~IC$
L..P VE1 *V R$ ER$i / I$ VE1 / I$ L..P / I$ Rc ~ 1 “8RE VCC / VE1” ‚RE I($ IC$ / 0e8min 8VCC - VE$ / 8R1qRL1 8VE$/R$qI($ R ~ ( 80e RE / 1 'ind R1# R$# RE# Rc1and Rc$ 0rom te abo6e e4uations PROCE)%RE:
1. Connect te circuit as son in 0igure 1 it designed 6alues.$. 5%%l2 VCC o0 1$V and an in%ut 0re4uenc2 o0 17 it an am%litude more tan te
designed …P.*. o note don te out%ut a6e 0orms
,. )bser6e tat te out%ut comes to ) state en in%ut e‰ceeds …P and it comes to)'' state en in%ut comes belo LP x. )bser6e te a6e0orms at VC1# VC$# V($ and VE and %lot gra%s.
z. ee% te DC- 5C control o0 te )scillosco%e in DC mode.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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;€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II MO)EL GRAPHS:
…P
In%ut sin a6e VM5‘9…P LP vcmitt rigger VC$ out%ut VC1 V($ RES%LT:
vcmitt rigger circuit is designed and studied.9%ESTIONS:
1. E‰%lain o a vcmitt trigger acts as a com%arator‹$. Deri6e its e‰%ressions 0or …P | LP.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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;€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II MO)EL GRAPHS:
…P In%ut sin a6e VM5‘9…P LP vcmitt rigger VC$ out%ut VC1 V($ RES%LT:
vcmitt rigger circuit is designed and studied.9%ESTIONS:
1. E‰%lain o a vcmitt trigger acts as a com%arator‹$. Deri6e its e‰%ressions 0or …P | LP.
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;ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:,
A))ER S%TRACTOR ' COMPARATOR
AIM: o 6eri02 te o%eration o0 te 5dder# vubtractor and com%arator using {,1 o%am%.
APPARAT%S:
1. )%erational 5m%li0ier &5 {,1 IC ‚1o.$. Resistors 1" - x# $$"
*. Poer su%%l28 -*V
,. Multi meter x. (read board z. CR) 8$M7/*M7 CIRC%IT )IAGRAM:
-+ A))ER:
Ra1 V$ R qVa 0 1 Ia
I R ' b 1 qVcc qVb I $ { b Rc1
- qV z c I ≅ ($ V R
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R
R
1 {,1
: :
: Ic ' Ž ' ' '
a q b q
c q R R
R
I ≅ a b
c
(1
* , -V R EE )M 8Ra Rb Rc R' RL &i1 -a! In5ertin1 Con7i1uration
R1 V$ R' Vcc - R
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'
' ' :
a q b q c R V {,1 ' 1 q
1
q qV 1 R
* a R qV V RL b EE R qVc &i1 -0!Non In5ertin1 Con7i1uration
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;ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:,
A))ER S%TRACTOR ' COMPARATOR
AIM: o 6eri02 te o%eration o0 te 5dder# vubtractor and com%arator using {,1 o%
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am%.APPARAT%S:
1. )%erational 5m%li0ier &5 {,1 IC ‚1o.$. Resistors 1" - x# $$"
*. Poer su%%l28 -*V
,. Multi meter x. (read board z. CR) 8$M7/*M7 CIRC%IT )IAGRAM:
-+ A))ER:
Ra1 V$ R qVa 0 1 Ia
I R ' b 1 qVcc qVb I $ { b Rc1 - qV z c I ≅ ($ V R R R
1 {,1 :
: : Ic ' Ž
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'
' ' a q b q
c q R R R
I ≅ a b c
(1
* , -V R EE )M 8Ra Rb Rc R' RL
&i1 -a! In5ertin1 Con7i1uration R1 V$ R' Vcc -
R ' '
'
:
a q b q c
R V {,1 ' 1
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&i1 =: Su0tra#tor
>+ASIC COMPARATOR:
q1xV - {
$ LM{, z 1 * q , R 1" -1xV RL 1" R 1" V RE'
V I &i1+>*a! In5ertin1 #omparator
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;< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II =+ S%TRACTOR:
R R qVa qVcc - R {,1 V Vb-Va q qVb -VEE
R RL &i1 =: Su0tra#tor
>+ASIC COMPARATOR:
q1xV - { $
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LM{, z 1 * q ,
R 1" -1xV RL 1" R 1" V RE' V I &i1+>*a! In5ertin1 #omparator
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;† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II MO)EL GRAPH:
Vin Vin V% V% - Vre0 V
t V t -VRE' - V% - V% V V Vin 9VRE' Vin 9VRE' qVv5
Vin 9VRE' qVv5 V t V -V t v5
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-V V V in yVRE' Vin yVRE'
in yVRE' v5 &i1+>*0! i7 Vre7
is
positi5e
&i1+>*#!
i7
Vre7 is ne1ati5e
THEOR:
-+Summin1 amp6i7iers
*A!In5ertin1 #on7i1uration
'ig81a sos te in6erting con0iguration it tree in%uts Va# Vb# and Vc .…sing in%utresistors Ra# Rb# and Rc. e circuit can be used as eiter a summing am%li0ier# scalingam%li0ier# or a6eraging am%li0ier. e circuitps 0unction can be 6eri0ied b2 e‰amining tee‰%ression 0or te out%ut 6oltage Vo# ic is obtained 0rom irco00ps current e4uation rittenat node V$.
Re0erring to 0ig81# Ia q Ib q Ic I( q I' vince Ri and 5 o0 te o%-am% are ideall2 in0init2# I( 5 and V1 V$≅ V.
ere0ore#'
'
' ' a b
c o q q Ž R
R
R
R a
b c :
R R
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R
' Ž : ' ' ---- 1 o
q : a
q : b
R
R R a
b c
Summin1 amp6i7ier: I0 in te circuit o0 'ig81a# Ra Rb Rc R# 0or e‰am%le# ten e4uation 81 can bereritten as INSTIT%TE O& ENGINEERING ' TECHNOLOG
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;† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II MO)EL GRAPH:
Vin Vin V% V% - Vre0 V t V t -VRE' - V%
- V% V V Vin 9VRE' Vin 9VRE' qVv5 Vin 9VRE' qVv5
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V t V -V t
v5 -V V V in yVRE' Vin yVRE' in yVRE' v5 &i1+>*0! i7 Vre7
is
positi5e
&i1+>*#!i7
Vre7 is ne1ati5e
THEOR:
-+Summin1 amp6i7iers
*A!In5ertin1 #on7i1uration
'ig81a sos te in6erting con0iguration it tree in%uts Va# Vb# and Vc .…sing in%ut
resistors Ra# Rb# and Rc. e circuit can be used as eiter a summing am%li0ier# scalingam%li0ier# or a6eraging am%li0ier. e circuitps 0unction can be 6eri0ied b2 e‰amining tee‰%ression 0or te out%ut 6oltage Vo# ic is obtained 0rom irco00ps current e4uation rittenat node V$.
Re0erring to 0ig81# Ia q Ib q Ic I( q I' vince Ri and 5 o0 te o%-am% are ideall2 in0init2# I( 5 and V1 V$≅ V.
ere0ore#'
' '
' a b
c
o
q q Ž R R
R R
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a
b c :
R
R R
' Ž : ' ' ---- 1 o
q : a q :
b
R R R a
b
c Summin1 amp6i7ier:
I0 in te circuit o0 'ig81a# Ra Rb Rc R# 0or e‰am%le# ten e4uation 81 can bereritten as INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II R: ' Ž ' q ' q '
o
8 a b c R
is means tat te output 5o6ta1e is equa6 to t2e neati&e sum o7 a66 t2e inputs timeste gain o0 te circuit R'/R: ence te circuit is called a "!mmin ampli'ier
*!Non in5ertin1 Con7i1uration:
I0 in%ut 6oltages sources and resistors are connected to te non in6erting terminal as
son in 0ig 81b# te circuit can be used eiter as a summing or a6eraging am%li0ier trougselection o0 a%%ro%riate 6alues o0 resistors# tat is# R1 and R'.
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…sing te su%er%osition teorem# te 6oltage V1 at te non in6erting terminal is R R R
'
$ ' $ q '
$ q '
1 a
b c R R
R
R q R q R q $ $ $ ' ' '
' q ' q '
a b
c
a b c
' q q ---- $ 1 * * *
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* R
ence te out%ut 6oltage is Vo 1 :
q ' 1 R
1
R ' q ' q 'c
1 :
q a b
R * 1 Summin1 amp6i7ier:
5 close e‰amination o0 e4uation 8$ re6els tat i0 te gain 81qR'/R1 is e4ual to te
number o0 in%uts# te out%ut 6oltage becomes e4ual to te sum o0 all in%ut 6oltages. at is# i081qR'/R1 *. 8'rom e4uation 81#
Vo Va q Vb qVc ence te circuit is called a non invertin summin amp!ifier.
=+ Su0tra#tor:
5 basic di00erential am%li0ier can be used as a subtractor as son in 0igure $. In tis
0igure# in%ut signals can be scaled to te desired 6alues b2 selecting a%%ro%riate 6alues 0or tee‰ternal resistorsw en tis is done# te circuit is re0erred to as scaling am%li0ier. oe6er# in
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0igure * all e‰ternal resistors are e4ual in 6alue# so te gain o0 te am%li0ier is e4ual to 1. 'romINSTIT%TE O& ENGINEERING ' TECHNOLOG
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ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II R: ' Ž ' q ' q '
o
8 a b c R is means tat te output 5o6ta1e is equa6 to t2e neati&e sum o7 a66 t2e inputs times
te gain o0 te circuit R'/R: ence te circuit is called a "!mmin ampli'ier*!Non in5ertin1 Con7i1uration:
I0 in%ut 6oltages sources and resistors are connected to te non in6erting terminal as
son in 0ig 81b# te circuit can be used eiter as a summing or a6eraging am%li0ier trougselection o0 a%%ro%riate 6alues o0 resistors# tat is# R1 and R'.
…sing te su%er%osition teorem# te 6oltage V1 at te non in6erting terminal is R R
R
' $ ' $ q ' $ q ' 1
a b c R
R R R q R q
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R q $ $ $ '
' '
' q ' q ' a b
c
a b c
' q
q ---- $ 1 * * * * R
ence te out%ut 6oltage is Vo 1 : q ' 1
R
1
R ' q ' q 'c
1 :
q a b
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R *
1 Summin1 amp6i7ier:
5 close e‰amination o0 e4uation 8$ re6els tat i0 te gain 81qR'/R1 is e4ual to te
number o0 in%uts# te out%ut 6oltage becomes e4ual to te sum o0 all in%ut 6oltages. at is# i081qR'/R1 *. 8'rom e4uation 81#
Vo Va q Vb qVc ence te circuit is called a non invertin summin amp!ifier.
=+ Su0tra#tor:
5 basic di00erential am%li0ier can be used as a subtractor as son in 0igure $. In tis
0igure# in%ut signals can be scaled to te desired 6alues b2 selecting a%%ro%riate 6alues 0or tee‰ternal resistorsw en tis is done# te circuit is re0erred to as scaling am%li0ier. oe6er# in0igure * all e‰ternal resistors are e4ual in 6alue# so te gain o0 te am%li0ier is e4ual to 1. 'romINSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II te 0igure# te out%ut
6oltage o0 te di00erential am%li0ier it a gain o0 1 is R8 ' Ž '
a
'
b Ž R at is#
' ' Ž ' b a
us te out%ut 6oltage V is e4ual to te 6oltage a%%lied to te non in6erting terminal
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8Vb minus te 6oltage a%%lied to te in6erting terminal8Vawence te circuit is called asubtractor.
>+asi# #omparator:
'igure 8* sos an o%-am% used as a com%arator. 5 0i‰ed re0erence 6oltage Vre0
o0 1V is a%%lied to te 8- in%ut# and te oter time-6ar2ing signal 6oltage Vin is a%%liedto te 8q in%ut. (ecause o0 tis arrangement# te circuit is called te nonin6erting com%arator.en Vin is less tan Vre0# te out%ut 6oltage V is at ‚Vsat8≅-VEE because te
6oltage at te 8- in%ut is iger tan tat at te 8q in%ut. )n te oter and# en Vin is greatertan Vre0# te 8q in%ut becomes %ositi6e it res%ect to te 8- in%ut# and V goes to qVsat8≅qVcc. us V ≅
canges 0rom one saturation le6el to anoter ene6er Vin Vre0# as son in 0igure *8b.
In sort# te com%arator is a t2%e o0 analog-to-digital con6erter. 5t an2 gi6en time te V a6e0orm sos eter Vin is greater or less tan Vre0. e com%arator is sometimes
also called a 6oltage-le6el detector because# 0or a desired 6alue o0 Vre0# te 6oltage le6el o0 tein%ut Vin can be detected .e resistance R in series it Vin is used to limit te current troug D1 and D$.o reduce o00set %roblems# a resistance R
≅
)M R is connected beteen 8- in%ut and Vre0.I0 te re0erence 6oltage Vre0 is negati6e it res%ect to ground# it sinusoidal signal
a%%lied to te 8q in%ut# te out%ut a6e0orms ill be as son in 'igure*8c.en Vin9Vre0# V is at qVsatw on te oter and# en VinyVre0# V is at ‚Vsat.)b6iousl2# te am%litude o0 Vin must be large enoug to %ass troug Vre0 i0 te
sitcing action is to ta!e %lace.
'igure 8* sos an in6erting com%arator in ic te re0erence 6oltage Vre0 is a%%liedto te 8q in%ut and Vin is a%%lied to te 8- in%ut. In tis circuit# Vre0 is obtained b2 using a1" %otentiometer tat 0orms a 6oltage di6ider it te dc su%%l2 6oltage qVcc and ‚VEEand te i%er connected to te 8q in%ut.
5s te i%er is mo6ed toard ‚VEE# Vre0 becomes more negati6e# ile i0 it is mo6edtoards qVcc# Vre0 becomes more %ositi6e. us a Vre0 o0 a desired am%litude and %olarit2 can be INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II te 0igure# te out%ut
6oltage o0 te di00erential am%li0ier it a gain o0 1 is R8 ' Ž ' a
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' b Ž R
at is#' ' Ž '
b a us te out%ut 6oltage V is e4ual to te 6oltage a%%lied to te non in6erting terminal8Vb minus te 6oltage a%%lied to te in6erting terminal8Vawence te circuit is called asubtractor.
>+asi# #omparator:
'igure 8* sos an o%-am% used as a com%arator. 5 0i‰ed re0erence 6oltage Vre0 o0 1V is a%%lied to te 8- in%ut# and te oter time-6ar2ing signal 6oltage Vin is a%%lied
to te 8q in%ut. (ecause o0 tis arrangement# te circuit is called te nonin6erting com%arator.en Vin is less tan Vre0# te out%ut 6oltage V is at ‚Vsat8≅-VEE because te6oltage at te 8- in%ut is iger tan tat at te 8q in%ut. )n te oter and# en Vin is greatertan Vre0# te 8q in%ut becomes %ositi6e it res%ect to te 8- in%ut# and V goes to qVsat8≅qVcc. us V ≅
canges 0rom one saturation le6el to anoter ene6er Vin Vre0# as son in 0igure *8b.
In sort# te com%arator is a t2%e o0 analog-to-digital con6erter. 5t an2 gi6en time te V a6e0orm sos eter Vin is greater or less tan Vre0. e com%arator is sometimesalso called a 6oltage-le6el detector because# 0or a desired 6alue o0 Vre0# te 6oltage le6el o0 te
in%ut Vin can be detected .e resistance R in series it Vin is used to limit te current troug D1 and D$.o reduce o00set %roblems# a resistance R
≅
)M R is connected beteen 8- in%ut and Vre0.I0 te re0erence 6oltage Vre0 is negati6e it res%ect to ground# it sinusoidal signal
a%%lied to te 8q in%ut# te out%ut a6e0orms ill be as son in 'igure*8c.en Vin9Vre0# V is at qVsatw on te oter and# en VinyVre0# V is at ‚Vsat.)b6iousl2# te am%litude o0 Vin must be large enoug to %ass troug Vre0 i0 te
sitcing action is to ta!e %lace.'igure 8* sos an in6erting com%arator in ic te re0erence 6oltage Vre0 is a%%lied
to te 8q in%ut and Vin is a%%lied to te 8- in%ut. In tis circuit# Vre0 is obtained b2 using a1" %otentiometer tat 0orms a 6oltage di6ider it te dc su%%l2 6oltage qVcc and ‚VEEand te i%er connected to te 8q in%ut.
5s te i%er is mo6ed toard ‚VEE# Vre0 becomes more negati6e# ile i0 it is mo6edtoards qVcc# Vre0 becomes more %ositi6e. us a Vre0 o0 a desired am%litude and %olarit2 can be INSTIT%TE O& ENGINEERING ' TECHNOLOG
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k?SF NO?k ?JGK
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II obtained b2 sim%l2adŒusting te 1" %otentiometer. it te sinusoidal in%ut a6e0orm# te out%ut V as tea6e0orm son in 'igure *8a or *8b# de%ending on eter Vre0 is negati6e# res%ecti6el2.
PROCE)%RE:
Part -: A))ER:
1. Connect te circuit as son in 0igure81.$. 5%%l2 di00erent DC in%ut 6oltages at Va# Vb# and Vc and
measure te out%ut 6oltage Vo using a multi meter
It sould be Vo Va q Vb q Vc Part =: S%TRACTOR:
1. Connect te circuit as son in 0igure8$.$. 5%%l2 di00erent DC in%ut 6oltages at Va# and Vb and
measure te out%ut 6oltage Vo using a multi meter .It sould be Vo Vb ‚ Va.
Part >: COMPARATOR:
1. Connect te circuit as son in 0igure8*a.$. 5%%l2 a re0erence 6oltage o0 8sa2 1V# to in6erting terminal o0 o%-am%.
*. 5%%l2 a sinusoidal a6e it a %ea! 6oltage more tan Vre0 to )P-5MPs on-in6erting terminal.
,. )bser6e te out%ut at %in number z# ic ill be a s4uare a6e it %ea! to %ea!6oltage o0 8Vsat to ‚Vsat.
x. )bser6e tat en Vre0 is less tan Vin# ten te out%ut goes to qVsat#en Vre0 is greater tan Vin ten out%ut goes to ‚Vsat.z. o set anoter re0erence 6oltage and re%eat te ste%s , and x.{. Dra te obser6ed a6e0orms on gra% seet and obtain te %ractical re0erence
6oltage.Resu6t:
ence te o%eration o0 5dder# vubtractor# and com%arator 8using {,1 o% am% is 6eri0ied.Con#6usions:
It is obser6ed tat te out %ut Values are 6er2 muc nearer to te gi6en in%uts. vo e canconclude tat 5dder# vubtractor# and com%arator are 0unctioning %ro%erl2.
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:-$
INTEGRATOR AN) )I&&ERENTIATOR %SING <- OP4AMP
AIM:
o obser6e te out%ut o0 an acti6e integrator and di00erentiator using {,1o%-am% 0or agi6en in%ut signal and to %lot teir 0re4uenc2 res%onse b2 6ar2ing te in%ut signal 0re4uenc20rom 17 to 18or $ 7.
–ote: ere te in%ut signal is a v4uare a6e or a vine a6e it a s%eci0ic 5m%litude81VP-P and a %articular 0re4uenc28va2 17— APPARAT%S:
1. )%erational 5m%li0ier &5 {,1 IC ‚$o.$. Resistors 1" - x# $$"
*. Poer su%%l28 -*V ,. Multi meter x. (read board z. CR) 8$M7/*M7 + Ca%acitors CIRC%IT )IAGRAM:
&i1 -: Inte1rator
6 R1 $ R0
i C0 Vi 1 I( i' 1V q { vignal
$ q1xV
V .x 1 1.x +enerator - z LM -1V {,1 qq
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Vo t8msec * -1xV 5-
, V 4
CR) RomR1 RL .xV t8msec INSTIT%TE O& ENGINEERING ' TECHNOLOG
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; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:-$
INTEGRATOR AN) )I&&ERENTIATOR %SING <- OP4AMP
AIM:
o obser6e te out%ut o0 an acti6e integrator and di00erentiator using {,1o%-am% 0or agi6en in%ut signal and to %lot teir 0re4uenc2 res%onse b2 6ar2ing te in%ut signal 0re4uenc20rom 17 to 18or $ 7.
–ote: ere te in%ut signal is a v4uare a6e or a vine a6e it a s%eci0ic 5m%litude81VP-P and a %articular 0re4uenc28va2 17— APPARAT%S:
1. )%erational 5m%li0ier &5 {,1 IC ‚$o.$. Resistors 1" - x# $$"
*. Poer su%%l28 -*V ,. Multi meter x. (read board z. CR) 8$M7/*M7 + Ca%acitors CIRC%IT )IAGRAM:
&i1 -: Inte1rator 6 R1 $ R0 i C0 Vi
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1 I( i' 1V q { vignal
$ q1xV V .x 1 1.x +enerator - z LM -1V {,1 qq
Vo t8msec * -1xV 5-
, V 4
CR) RomR1 RL .xV t8msec INSTIT%TE O& ENGINEERING ' TECHNOLOG
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II &i1 =: )i77erentiator
DI''EREI5)R 6$ R1 R'
ic i' C'
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1V i($ V { q
$ q1xV -1V vignal - z LM +enerator 6 {,1
1 $V q * -1xV , V RomR1 i(1 CR) RL $V &i1 >: OP AMP
PI DI5+R5M: )''vE …LL 1 ‡ C IV i/% $ { Vq ) IV i/% * z o/% V - , x )''vE …LL &i1 <
&requen#B Response:
Voltage gain in d( R: d7 R 1 5' 0a 0b 8,a Integrator 0re4uenc2 res%onse INSTIT%TE O& ENGINEERING ' TECHNOLOG
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k?SF NO?k ?JGK
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II &i1 =: )i77erentiator
DI''EREI5)R 6$ R1 R'
ic i' C' 1V
i($ V { q
$ q1xV -1V vignal - z
LM +enerator 6 {,1 1 $V q * -1xV , V
RomR1 i(1 CR) RL $V &i1 >: OP AMP
PI DI5+R5M: )''vE …LL 1 ‡ C IV i/% $ { Vq
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) IV i/% * z o/% V - , x )''vE …LL &i1 <
&requen#B Response:
Voltage gain in d( R: d7
R 1 5' 0a 0b 8,a Integrator 0re4uenc2 res%onse INSTIT%TE O& ENGINEERING ' TECHNOLOG
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II +ain d( 0 0a 0b <0! Di00erentiator 0re4uenc2 res%onse THEOR:
A!INTEGRATOR: 5 circuit in ic 3te out%ut 6oltage a6e0orm is te integral o0 te in%ut 6oltagea6e0orm˜ is te integrator or te integration am%li0ier.
vuc a circuit is obtained b2 using a basic in6erting am%li0ier con0iguration# i0 te 0eed bac! resistor R' is re%laced b2 a ca%acitor C'.
Ana6Bsis o7 Inte1rator Cir#uit:
e e‰%ression 0or te out%ut 6oltage 6 can be obtained b2 riting irco00ps currente4uation at node 6$: i1 I( q i' vince I( is negligibl2 small#
i ≅ 1 i' Recall tat te relationsi% beteen current troug and 6oltage across te ca%acitor is dv
i c C C dt
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v Ž v
d ere0ore#
1 $ C
Ž :
8 v v 1 R
dt 1 oe6er# 6 ≅
1 6$
because 5 is 6er2 large. ere0ore#v d
in C Ž :
8 v R dt
1 e out%ut 6oltage can be obtained b2 integrating bot sides it res%ect to time:
t v t
d in dt C Ž : 8 v dt R
dt 1
C' 8-6 q v t
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II +ain d( 0 0a 0b <0! Di00erentiator 0re4uenc2 res%onse THEOR:
A!INTEGRATOR:
5 circuit in ic 3te out%ut 6oltage a6e0orm is te integral o0 te in%ut 6oltagea6e0orm˜ is te integrator or te integration am%li0ier.
vuc a circuit is obtained b2 using a basic in6erting am%li0ier con0iguration# i0 te 0eed bac! resistor R' is re%laced b2 a ca%acitor C'.
Ana6Bsis o7 Inte1rator Cir#uit: e e‰%ression 0or te out%ut 6oltage 6 can be obtained b2 riting irco00ps currente4uation at node 6$: i1 I( q i' vince I( is negligibl2 small#
i ≅ 1 i' Recall tat te relationsi% beteen current troug and 6oltage across te ca%acitor is dv
i c C C dt
v Ž v
d ere0ore#
1 $ C Ž :
8 v v
1 R
dt 1 oe6er# 6 ≅
1 6$
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because 5 is 6er2 large. ere0ore#v
d in C
Ž
: 8 v R dt 1 e out%ut 6oltage can be obtained b2 integrating bot sides it res%ect to time: t v t d
in dt C Ž
: 8 v dt R dt
1
C' 8-6 q v t
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II t
1 ere0ore# 6
v dt C ------- 1 in q R C 1 : ere C is integration constant and is %ro%ortional to te 6alue o0 te out%ut 6oltage 6
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at time t seconds.E4uation 1 indicates tat te out%ut 6oltage is directl2 %ro%ortional to te negati6e
integral o0 te in%ut 6oltage and in6ersel2 %ro%ortional to te time constant R1C'.I0 te in%ut to te integrator is a sine a6e# te out%ut ill be a cosine a6e# or i0 te
in%ut is a s4uare a6e# te out%ut ill be a triangular a6e.
In te circuit son in 0igure te stabilit2 and te lo 0re4uenc2 roll-o00 %roblems can becorrected b2 te addition o0 a resistor R$ 8R'. e term stabilit2 re0ers to a constant gain as0re4uenc2 o0 an in%ut signal is 6aried o6er a certain range. Lo 0re4uenc2 roll-o00 re0ers to terate o0 decrease in gain at loer 0re4uencies. e in%ut signal ill be integrated %ro%erl2 i0 tetime %eriod o0 te signal is larger tan or e4ual to R'C'.
™ 1 e 0re4uenc2 at ic gain is d( is gi6en b2 0b $ R š C
1 f
™ 1 e gain limiting 0re4uenc2 is gi6en b2 0a R
š $ C f
f ™ e Values o0 0a and in turn R1C0 and R0C0 Values sould be selected suc tat 0ay0b.
™ E‰: I0 0a.10b# ten R01R1.™ e in%ut signal ill be integrated %ro%erl2# i0 te ime %eriod o0 te signal R0C0.App6i#ations:
e integrator is most commonl2 used in analog com%uters and analog to digital con6erters and signal a6e sa%ing circuits.
!)I&&ERENTIATOR:
e circuit son in 0igure %er0orms te matematical o%eration o0 di00erentiation tat iste out%ut a6e0orm is te deri6ati6e o0 te in%ut a6e0orms.
e di00erentiator ma2 be constructed 0rom a basic in6erting am%li0ier i0 an in%ut resistorR1 is re%laced b2 a ca%acitor C1.
Ana6Bsis o7 )i77erentiator Cir#uit:
e e‰%ression 0or te out%ut 6oltage 6 can be obtained b2 riting irco00ps currente4uation at node 6$ as 0ollos: INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II t 1 ere0ore# 6
v dt C ------- 1 in q R C
1 : ere C is integration constant and is %ro%ortional to te 6alue o0 te out%ut 6oltage 6at time t seconds.
E4uation 1 indicates tat te out%ut 6oltage is directl2 %ro%ortional to te negati6eintegral o0 te in%ut 6oltage and in6ersel2 %ro%ortional to te time constant R1C'.
I0 te in%ut to te integrator is a sine a6e# te out%ut ill be a cosine a6e# or i0 tein%ut is a s4uare a6e# te out%ut ill be a triangular a6e.In te circuit son in 0igure te stabilit2 and te lo 0re4uenc2 roll-o00 %roblems can be
corrected b2 te addition o0 a resistor R$ 8R'. e term stabilit2 re0ers to a constant gain as0re4uenc2 o0 an in%ut signal is 6aried o6er a certain range. Lo 0re4uenc2 roll-o00 re0ers to terate o0 decrease in gain at loer 0re4uencies. e in%ut signal ill be integrated %ro%erl2 i0 tetime %eriod o0 te signal is larger tan or e4ual to R'C'.
™ 1 e 0re4uenc2 at ic gain is d( is gi6en b2 0b $ R š C
1 f ™ 1 e gain limiting 0re4uenc2 is gi6en b2 0a R
š $ C f
f ™ e Values o0 0a and in turn R1C0 and R0C0 Values sould be selected suc tat 0ay0b.
™ E‰: I0 0a.10b# ten R01R1.™ e in%ut signal ill be integrated %ro%erl2# i0 te ime %eriod o0 te signal R0C0.App6i#ations:
e integrator is most commonl2 used in analog com%uters and analog to digital con6erters and signal a6e sa%ing circuits.
!)I&&ERENTIATOR:
e circuit son in 0igure %er0orms te matematical o%eration o0 di00erentiation tat is
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te out%ut a6e0orm is te deri6ati6e o0 te in%ut a6e0orms.e di00erentiator ma2 be constructed 0rom a basic in6erting am%li0ier i0 an in%ut resistor
R1 is re%laced b2 a ca%acitor C1.Ana6Bsis o7 )i77erentiator Cir#uit:
e e‰%ression 0or te out%ut 6oltage 6 can be obtained b2 riting irco00ps current
e4uation at node 6$ as 0ollos: INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II iC I( q i' vince I ≅
( #
iC i' d Ž C Ž 1 8 v
v v v
$ in $ dt R: (ut 6 ≅
1 6$ V# because 5 is 6er2 large. ere0ore#
dv v
in C Ž
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1 dt R: dv
)r v Ž R C
in : 1 dt
us te out%ut 6 is e4ual to R'C1 times te negati6e instantaneous rate o0 cange o0te in%ut 6oltage 6in it time.
vince te di00erentiator %er0orms te re6erse o0 te integrators 0unction# a cosine a6ein%ut ill %roduce a sine a6e out%ut# or triangular a6e in%ut ill %roduce a v4uare a6eout%ut.
e stabilit2 and te ig 0re4uenc2 noise %roblems can be corrected b2 te addition o0
to com%onents R1 and C'.™ 1 e 0re4uenc2 at ic gain is d( is gi6en b2 0a $ R
š C
f 1 ™ 1 e gain limiting 0re4uenc2 is gi6en b2 0b ere R1C1R0C0 $ R š C 1 1 ™ e in%ut signal ill be di00erentiated %ro%erl2# i0 te ime %eriod o0 te signal R0C1.
™ 'rom te 0re4uenc2 0 to 0b#te gain increases at $d(/decade.oe6er#a0ter 0b te gaindecreases at $ d(/decade.
App6i#ations:
e di00erentiator is most commonl2 used in a6e sa%ing circuits to detect ig 0re4uenc2 com%onents in an in%ut signal and also as a rate-o0-cange detector in 'Mmodulator.
)ESIGN :
Part -:)esi1n o7 Inte1rator
Design an Integrator to Integrate an in%ut signal# tat 6aries in 0re4uenc2 0rom 17 to 17.
1 –ote:velect R0 C0# ere R0 C0 8 in%ut signal time %eriod—
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f
š $ a 1. velect 0a 1 7. 5ssume a 6alue o0 C0 y 1 &0. 8Let C0 .1 &0 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II iC I( q i' vince I ≅ ( #
iC i' d
Ž C Ž 1 8 v v v
v $ in
$ dt R:
(ut 6 ≅
1 6$ V# because 5 is 6er2 large. ere0ore#
dv v in C
Ž 1 dt
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R:
dv )r v Ž R C in
: 1 dt us te out%ut 6 is e4ual to R'C1 times te negati6e instantaneous rate o0 cange o0te in%ut 6oltage 6in it time.
vince te di00erentiator %er0orms te re6erse o0 te integrators 0unction# a cosine a6ein%ut ill %roduce a sine a6e out%ut# or triangular a6e in%ut ill %roduce a v4uare a6eout%ut.
e stabilit2 and te ig 0re4uenc2 noise %roblems can be corrected b2 te addition o0to com%onents R1 and C'.
™
1 e 0re4uenc2 at ic gain is d( is gi6en b2 0a $ R š C f
1 ™ 1 e gain limiting 0re4uenc2 is gi6en b2 0b ere R1C1R0C0 $ R š C
1 1 ™ e in%ut signal ill be di00erentiated %ro%erl2# i0 te ime %eriod o0 te signal R0C1.
™ 'rom te 0re4uenc2 0 to 0b#te gain increases at $d(/decade.oe6er#a0ter 0b te gaindecreases at $ d(/decade.
App6i#ations:
e di00erentiator is most commonl2 used in a6e sa%ing circuits to detect ig 0re4uenc2 com%onents in an in%ut signal and also as a rate-o0-cange detector in 'Mmodulator.
)ESIGN :
Part -:)esi1n o7 Inte1rator
Design an Integrator to Integrate an in%ut signal# tat 6aries in 0re4uenc2 0rom 17 to 17.
1 –ote:velect R0 C0# ere R0 C0 8 in%ut signal time %eriod— f š
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$ a
1. velect 0a 1 7. 5ssume a 6alue o0 C0 y 1 &0. 8Let C0 .1 &0 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 8 0a is te gain limiting0re4uenc2 1 $.Calculate te 6alue o0 R0 using te 0ormula R0 f š
$ C a
f *. let 0b10a 8 0b is te 0re4uenc2 at ic gain is d( 1 ,.Calculate R1 using te 0ormula R1 .
f š $
C b
f z.Coose Rom R1.
z. a!e load resistor RL 1" Part =: )esi1n o7 )i77erentiator
Design a Di00erentiator to Di00erentiate an in%ut signal# tat 6aries in 0re4uenc2 0rom 17 to $7.
1. velect 0a 1 7. 5ssume a 6alue o0 C1 y 1 &0. 8Let C1 .1 &0 8 0a is te 0re4uenc2 at ic gain is d( 1 $.Calculate te 6alue o0 R0 using te 0ormula R0 $ f š C a 1 8Result: R01.x= *. let 0b $0a # 0b is te gain limiting 0re4uenc2 1
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Calculate R1 using te 0ormula R1 .
$ f š C
b
1 8Result: R1{=.x ,. 'rom R1C1 R0C0 calculate C0 8Result: C1.x&0 x.Coose Rom R0.
z. a!e load resistor RL 1" PROCE)%RE:
Part -
1. (2 using te com%onent 6alues as %er te abo6e s%eci0ied design#Connect te circuit asson in te 0igure.
$. 5%%l2 te 1VP-P# 17 vinea6e or v4uarea6e as in%ut
*. )bser6e te out%ut on CR).,. Dra te in%ut and out%ut vignals on te +ra% %a%er.Part =
x. Var2 te in%ut signal 8Pre0erabl2 vine a6e 0re4uenc2 0rom 1 7 to18or $7and notedon te am%litude o0 te out%ut signal 8V.
'
z. Claculate +ain o at eac 6alue o0 te in%ut signal 0re4uenc2.
'i
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< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 8 0a is te gain limiting0re4uenc2 1
$.Calculate te 6alue o0 R0 using te 0ormula R0 f š $ C
a f *. let 0b10a 8 0b is te 0re4uenc2 at ic gain is d(
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1 ,.Calculate R1 using te 0ormula R1 .
f
š
$ C
b f z.Coose Rom R1.
z. a!e load resistor RL 1" Part =: )esi1n o7 )i77erentiator
Design a Di00erentiator to Di00erentiate an in%ut signal# tat 6aries in 0re4uenc2 0rom 17 to $7.
1. velect 0a 1 7. 5ssume a 6alue o0 C1 y 1 &0. 8Let C1 .1 &0
8 0a is te 0re4uenc2 at ic gain is d( 1 $.Calculate te 6alue o0 R0 using te 0ormula R0 $ f š C a
1 8Result: R01.x= *. let 0b $0a # 0b is te gain limiting 0re4uenc2 1 Calculate R1 using te 0ormula R1 .
$ f
š C b 1 8Result: R1{=.x ,. 'rom R1C1 R0C0 calculate C0 8Result: C1.x&0 x.Coose Rom R0.
z. a!e load resistor RL 1" PROCE)%RE:
Part -
1. (2 using te com%onent 6alues as %er te abo6e s%eci0ied design#Connect te circuit as
son in te 0igure.$. 5%%l2 te 1VP-P# 17 vinea6e or v4uarea6e as in%ut
*. )bser6e te out%ut on CR).,. Dra te in%ut and out%ut vignals on te +ra% %a%er.
Part =
x. Var2 te in%ut signal 8Pre0erabl2 vine a6e 0re4uenc2 0rom 1 7 to18or $7
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and notedon te am%litude o0 te out%ut signal 8V.'
z. Claculate +ain o at eac 6alue o0 te in%ut signal 0re4uenc2.
'i
INSTIT%TE O& ENGINEERING ' TECHNOLOG 1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II ' 5lso Calculate d( Value o0 +ain $log o .
'i
{. Plot te gra% beteen 0re4uenc2 8on ‘-5‰is and ' d( Value o0 +ain $log o 8on -5‰is 'i ‡. Identi02 te Practical Values o0 0aand 0b 0rom te +ra%s.
8ote: e Practical Values o0 0aand 0b obser6ed 0rom te +ra%s must e4ual to te eoritical 6alues Resu6t: ence te out%ut o0 an acti6e integrator and di00erentiator using o%-am% {,1 0or agi6en in%ut signal is obser6ed and %lotted teir 0re4uenc2 res%onse b2 6ar2ing te in%ut signal0re4uenc2 0rom 17 to 18or $ 7.
Con#6usions: e Practical Values o0 0aand 0b obser6ed 0rom te +ra%s are e4ual to te
eoritical 6alues. 'rom tis e can conclude tat te Integrator and Di00erentiator using {,1 )P-5MP are satis02ing teir 0unction %ro%erl2.
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†
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II ' 5lso Calculate d( Value o0 +ain $log o .'i
{. Plot te gra% beteen 0re4uenc2 8on ‘-5‰is and '
d( Value o0 +ain $log o 8on -5‰is 'i ‡. Identi02 te Practical Values o0 0aand 0b 0rom te +ra%s.
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8ote: e Practical Values o0 0aand 0b obser6ed 0rom te +ra%s must e4ual to te eoritical 6alues Resu6t: ence te out%ut o0 an acti6e integrator and di00erentiator using o%-am% {,1 0or agi6en in%ut signal is obser6ed and %lotted teir 0re4uenc2 res%onse b2 6ar2ing te in%ut signal0re4uenc2 0rom 17 to 18or $ 7.
Con#6usions: e Practical Values o0 0aand 0b obser6ed 0rom te +ra%s are e4ual to teeoritical 6alues. 'rom tis e can conclude tat te Integrator and Di00erentiator using {,1 )P-5MP are satis02ing teir 0unction %ro%erl2.
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•ˆ
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II
E;periment
No+--
ACTIVE &ILTER APPLICATIONS LP& HP& *&IRST OR)ER!
AIM: o Plot te 0re4uenc2 res%onse o0 0irst order lo %ass and ig %ass 0ilters using{,1 )P-5MP and to 0ind iger and Loer Cut-o00 0re4uencies.
APPARAT%S:
1. vignal generator8-1M7 $. )scillosco%e8$/*M7 *. (read board
,. Poer su%%l28-*V x. Resistors 1x" 81 o.# 1"8* o.s z. Ca%acitors .1&' -1o.
{. )%-am% {,1 IC ‚ 1o.CIRC%IT )IAGRAM:
-+ Lo" Pass &i6ter
R1 V R $ '
Voltage gain qVcc 1" 1" q1x - -$d(/decade {,1
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V R q 5'
$ %ot at -V R EE L Passband vto%band Vin 1x.=" .1&' C
1" .{{5' 're4uenc2 q -1x6 0 8b 8a 'ig.1 'irst-order lo-%ass (utterort 0ilters. 8a Circuit. 8b 're4uenc2 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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•ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II
E;periment
No+--
ACTIVE &ILTER APPLICATIONS LP& HP& *&IRST OR)ER!
AIM: o Plot te 0re4uenc2 res%onse o0 0irst order lo %ass and ig %ass 0ilters using{,1 )P-5MP and to 0ind iger and Loer Cut-o00 0re4uencies.
APPARAT%S:
1. vignal generator8-1M7 $. )scillosco%e8$/*M7 *. (read board ,. Poer su%%l28-*V x. Resistors 1x" 81 o.# 1"8* o.s
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z. Ca%acitors .1&' -1o.{. )%-am% {,1 IC ‚ 1o.CIRC%IT )IAGRAM:
-+ Lo" Pass &i6ter
R1
V R $ ' Voltage gain qVcc 1" 1" q1x - -$d(/decade
{,1 V R q 5' $ %ot at -V R EE L Passband vto%band Vin 1x.=" .1&' C 1" .{{5' 're4uenc2 q -1x6 0 8b 8a 'ig.1 'irst-order lo-%ass (utterort 0ilters. 8a Circuit. 8b 're4uenc2 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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•
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II =+ Hi12 Pass &i6ter
R1 V R $ ' Voltage gain qVcc 1" 1" q1x
-$d(/decade - C {,1 V 1 5 -V ' EE .1&'
-1x6 RL 1" .{{5 $ %ot at R ' Vin sto%band 1x.=" Pass band
dd 0L 're4uenc2 'ig.$ 'irst-order ig-%ass (utterort 0ilters. 8a Circuit. 8b 're4uenc2 res%onse THEOR:
'ILER 55LvIv: -+LP&:
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'igure1 sos a 0irst-order lo-%ass (utterort 0ilter tat uses an RC netor! 0or0iltering.
ote tat te o%-am% is used in te non in6erting con0igurationwence it does not load don te RC netor!. Resistors R1 and R' determine te gain o0
te 0ilter.
5ccording to te 6oltage-di6ider rule# te 6oltage at te non in6erting terminal 8across ca%acitor C is Ž @Ac v E4uation 81 1 vin R Ž @Ac ere 1 Œ›8-1 and -Œ‘c @ fC
š $ vim%li02ing E4uation 81# e get v
v
in 1 1 q @ fRC š $ INSTIT%TE O& ENGINEERING ' TECHNOLOG
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II =+ Hi12 Pass &i6ter
R1
V R $ ' Voltage gain qVcc 1" 1"
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q1x -$d(/decade - C {,1
V 1 5 -V ' EE .1&' -1x6 RL 1" .{{5
$ %ot at R ' Vin sto%band 1x.=" Pass band dd 0L 're4uenc2 'ig.$ 'irst-order ig-%ass (utterort 0ilters. 8a Circuit. 8b 're4uenc2 res%onse THEOR:
'ILER 55LvIv: -+LP&:
'igure1 sos a 0irst-order lo-%ass (utterort 0ilter tat uses an RC netor! 0or0iltering.
ote tat te o%-am% is used in te non in6erting con0igurationwence it does not load don te RC netor!. Resistors R1 and R' determine te gain o0
te 0ilter.5ccording to te 6oltage-di6ider rule# te 6oltage at te non in6erting terminal
8across ca%acitor C is Ž @Ac
v
E4uation 81 1 vin
R Ž @Ac
ere 1
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Œ›8-1 and -Œ‘c @ fC
š $ vim%li02ing E4uation 81# e get v
v in
1 1 q @
fRC
š $ INSTIT%TE O& ENGINEERING ' TECHNOLOG
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 5nd te out%ut 6oltage R
v 1 8 :
q
v 1 R 1 R
v : at is#
v
in 1
8 q R
1q @ fRC 1 š
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$ v % :
- E4uation 8$ v 1 q @8 f / f in
H
v ere gain o0 te 0ilter as a 0unction o0 0re4uenc2 vin R
% 1 8 :
q %ass band gain o0 te 0ilter : 1 R 0 0re4uenc2 o0 te in%ut signal 1 f ig cuto00 0re4uenc2 o0 te 0ilter H
RC š $ e gain magnitude and %ase angle e4uations o0 te lo-%ass 0ilter can be obtained b2con6erting E4uation-8$ into its e4ui6alent %olar 0orm# as 0ollos: ' % - E4uation-8* 'in › 8 :
$ 1 q 8 f / f H
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œ f
-tan-1
fH ere œ is te %ase angle in degrees.e o%eration o0 te lo-%ass 0ilter can be 6eri0ied 0rom te gain magnitude e4uation 8*:
1. 5t 6er2 lo 0re4uencies# tat is# 0y0#'
≅ 5' 'in ' %
$. 5t 00 :
{{ .
%:
'in › $ ' *. 5t 090 y
#
5' 'in us te lo-%ass 0ilter as a constant gain 5' 0rom 7 to te ig cuto00 0re4uenc20.
5t 0 te gain is .{{ 5'# and a0ter 0 it decreases at a constant rate it an increase in0re4uenc2 see 'ig1b. at is# en te 0re4uenc2 is increased to ten0old 8one decade# te6oltage gain is di6ided b2 1.
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II 5nd te out%ut 6oltage R
v 1 8
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:
q v 1
R 1 R
v : at is#
v
in 1 8 q
R 1q @ fRC 1 š $ v %
: - E4uation 8$ v 1 q @8 f / f in
H v
ere gain o0 te 0ilter as a 0unction o0 0re4uenc2 vin R
% 1 8 : q %ass band gain o0 te 0ilter :
1 R
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0 0re4uenc2 o0 te in%ut signal 1 f ig cuto00 0re4uenc2 o0 te 0ilter
H RC
š $ e gain magnitude and %ase angle e4uations o0 te lo-%ass 0ilter can be obtained b2con6erting E4uation-8$ into its e4ui6alent %olar 0orm# as 0ollos: ' % - E4uation-8* 'in
› 8 : $ 1 q 8 f / f H
œ f
-tan-1
fH
ere œ is te %ase angle in degrees.e o%eration o0 te lo-%ass 0ilter can be 6eri0ied 0rom te gain magnitude e4uation 8*:
1. 5t 6er2 lo 0re4uencies# tat is# 0y0#'
≅ 5' 'in ' % $. 5t 00 :
{{ .
%: 'in › $ ' *. 5t 090
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y#5'
'in
us te lo-%ass 0ilter as a constant gain 5' 0rom 7 to te ig cuto00 0re4uenc2
0. 5t 0 te gain is .{{ 5'# and a0ter 0 it decreases at a constant rate it an increase in0re4uenc2 see 'ig1b. at is# en te 0re4uenc2 is increased to ten0old 8one decade# te6oltage gain is di6ided b2 1.
INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
•; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II In oter ords# te gaindecreases $db 8$ log 1 eac time te 0re4uenc2 is increased b2 1.
ence te rate at ic te gain rolls o00 a0ter 0 is $ db/decode or z db/octa6e# ereocta6e signi0ies a to0old increase in 0re4uenc2.
e 0re4uenc2 0 0 is called te iger cuto00 0re4uenc2 because te gain o0 te 0ilter attis 0re4uenc2 is don b2 * db 8$ log .{{ 0rom 7. )ter e4ui6alent terms 0or cuto000re4uenc2 are -*db 0re4uenc2# brea! 0re4uenc2# or corner 0re4uenc2.
HP&:
ig-%ass 0ilters are o0ten 0ormed sim%l2 b2 intercanging 0re4uenc2-determining
resistors and ca%acitors in lo-%ass 0ilters. at is# a 0irst-order ig-%ass 0ilter is 0ormed0rom a 0irst-order lo-%ass t2%e b2 intercanging com%onents R and C. vimilarl2# a second-order ig%ass 0ilter is obtained 0rom a second-order lo-%ass 0ilter i0 R and C are intercanged# andso on.
'igure$ sos a 0irst-order ig-%ass (utterort 0ilter it a lo cuto00 0re4uenc2 o00L. is is te 0re4uenc2 at ic te magnitude o0 te gain is .{{ times its %ass band 6alue.)b6iousl2# all 0re4uencies iger tan 0L are %ass band 0re4uencies# it te igest 0re4uenc2determined b2 te closed-loo% bandidt o0 te o%-am%.
ote tat te ig-%ass 0ilter o0 0igure$8a and te lo-%ass 0ilter o0 0igure81a are tesame circuits# e‰ce%t tat te 0re4uenc2-determining com%onents 8R and C are intercanged.
'or te 0irst-order ig-%ass 0ilter o0 'igure# te out%ut 6oltage is R @ š $ fRC : ' 1 8 q
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' in
R
1 q @ 1 š $ fRC or '
@ 8 f / fL %: 'in
1q @8 f / fL R ere % 1 8 :
q %ass band gain o0 te 0ilter :
1 R 0 0re4uenc2 o0 te in%ut signal 87 1 0L $ š RC lo cuto00 0re4uenc2 87 ence te magnitude o0 te 6oltage gain is INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
•; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II In oter ords# te gaindecreases $db 8$ log 1 eac time te 0re4uenc2 is increased b2 1.
ence te rate at ic te gain rolls o00 a0ter 0 is $ db/decode or z db/octa6e# ereocta6e signi0ies a to0old increase in 0re4uenc2.
e 0re4uenc2 0 0 is called te iger cuto00 0re4uenc2 because te gain o0 te 0ilter attis 0re4uenc2 is don b2 * db 8$ log .{{ 0rom 7. )ter e4ui6alent terms 0or cuto000re4uenc2 are -*db 0re4uenc2# brea! 0re4uenc2# or corner 0re4uenc2.
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HP&:
ig-%ass 0ilters are o0ten 0ormed sim%l2 b2 intercanging 0re4uenc2-determining
resistors and ca%acitors in lo-%ass 0ilters. at is# a 0irst-order ig-%ass 0ilter is 0ormed0rom a 0irst-order lo-%ass t2%e b2 intercanging com%onents R and C. vimilarl2# a second-order
ig%ass 0ilter is obtained 0rom a second-order lo-%ass 0ilter i0 R and C are intercanged# andso on.'igure$ sos a 0irst-order ig-%ass (utterort 0ilter it a lo cuto00 0re4uenc2 o0
0L. is is te 0re4uenc2 at ic te magnitude o0 te gain is .{{ times its %ass band 6alue.)b6iousl2# all 0re4uencies iger tan 0L are %ass band 0re4uencies# it te igest 0re4uenc2determined b2 te closed-loo% bandidt o0 te o%-am%.
ote tat te ig-%ass 0ilter o0 0igure$8a and te lo-%ass 0ilter o0 0igure81a are tesame circuits# e‰ce%t tat te 0re4uenc2-determining com%onents 8R and C are intercanged.
'or te 0irst-order ig-%ass 0ilter o0 'igure# te out%ut 6oltage is
R @ š $ fRC :
' 1 8 q '
in R
1 q @ 1 š $ fRC
or '
@
8 f / fL %:
'in 1q @8 f / fL R
ere % 1 8 :
q %ass band gain o0 te 0ilter :
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1 R 0 0re4uenc2 o0 te in%ut signal 87 1 0L $ š RC
lo cuto00 0re4uenc2 87 ence te magnitude o0 te 6oltage gain is INSTIT%TE O& ENGINEERING ' TECHNOLOG
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II '
%: 8 f / f L 'in
› 81q 8 f / fL $ vince ig-%ass 0ilters are 0ormed 0rom lo-%ass 0ilters sim%l2 b2 intercanging Rps andCps# te design %rocedure o0 te lo-%ass 0ilter is also a%%licable to te ig-%ass 0ilters &ILTER
)ESIGN:
A!LP& )esi1n:
Design a LP' a6ing Cuto00 0re4uenc2 o0 17 it a Passband gain o0 $.5 lo-%ass 0ilter can be designed b2 im%lementing te 0olloing ste%s:
1. Coose a 6alue o0 ig cuto00 0re4uenc2 0 8let us ta!e 17
$. velect a 6alue o0 C less tan or e4ual to 1&0. 8 let us ta!e C.1&0 . 1 *. Calculate te 6alue o0 R using te 0ormula R 8It ill become 1x.= f
š $ C
H
,. 'inall2# select 6alues o0 R1 and R' de%endent on te desired %ass band gain 5' using R
% 1 8 :
q –vince 5 :
'$#ten R1 R'. Let R1 R' 1
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— 1 R x.Let RL1 .
A!HP& )esi1n:
Design a P' a6ing Cuto00 0re4uenc2 o0 17 it a Passband gain o0 $.5 ig-%ass 0ilter can be designed b2 im%lementing te 0olloing ste%s: 1. Coose a 6alue o0 lo cuto00 0re4uenc2 0L 8let us ta!e 17 $. velect a 6alue o0 C less tan or e4ual to 1&0. 8 let us ta!e C.1&0 . 1 *. Calculate te 6alue o0 R using te 0ormula R 8It ill become 1x.= f š $ C
L ,. 'inall2# select 6alues o0 R1 and R' de%endent on te desired %ass band gain 5' using R %
1 8 : q –vince 5 : '$#ten R1 R'. Let R1 R' 1 — 1 R
x.Let RL1 .INSTIT%TE O& ENGINEERING ' TECHNOLOG
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• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II ' %: 8 f / f L 'in › 81q 8 f / fL $ vince ig-%ass 0ilters are 0ormed 0rom lo-%ass 0ilters sim%l2 b2 intercanging Rps andCps# te design %rocedure o0 te lo-%ass 0ilter is also a%%licable to te ig-%ass 0ilters &ILTER
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)ESIGN:
A!LP& )esi1n:
Design a LP' a6ing Cuto00 0re4uenc2 o0 17 it a Passband gain o0 $.5 lo-%ass 0ilter can be designed b2 im%lementing te 0olloing ste%s:
1. Coose a 6alue o0 ig cuto00 0re4uenc2 0 8let us ta!e 17
$. velect a 6alue o0 C less tan or e4ual to 1&0. 8 let us ta!e C.1&0 . 1 *. Calculate te 6alue o0 R using te 0ormula R 8It ill become 1x.= f
š $ C H
,. 'inall2# select 6alues o0 R1 and R' de%endent on te desired %ass band gain 5' using R
% 1 8 :
q –vince 5 : '$#ten R1 R'. Let R1 R' 1 — 1 R
x.Let RL1 .A!HP& )esi1n:
Design a P' a6ing Cuto00 0re4uenc2 o0 17 it a Passband gain o0 $.5 ig-%ass 0ilter can be designed b2 im%lementing te 0olloing ste%s:
1. Coose a 6alue o0 lo cuto00 0re4uenc2 0L 8let us ta!e 17 $. velect a 6alue o0 C less tan or e4ual to 1&0. 8 let us ta!e C.1&0 . 1 *. Calculate te 6alue o0 R using te 0ormula R 8It ill become 1x.= f
š $ C
L ,. 'inall2# select 6alues o0 R1 and R' de%endent on te desired %ass band gain 5' using R
%
1 8
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:
q –vince 5 :
'$#ten R1 R'. Let R1 R' 1
— 1 R x.Let RL1 .
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•• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Note:
It is better to ta!e a Ca%acitor o0 a standard80i‰ed6alue#not a Variable Ca%acitor.I0 e ta!e Variable Ca%acitor Value# some times# te 'ilter ma2 gi6e bad
Res%onse8out%ut.vo in te abo6e Design Procedure#e a6e Cosen a 0i‰ed 6alue 0or te Ca%acitor#not a Variable Ca%acitor#and ten Calculated te 6alue o0 Resistor 0or a desired 0re4uenc2.
PROCE)%RE:
L) P5vv 'ILER| I+ P5vv 'ILER 'RE…EC REvP)vE 1.Connect te circuit as son in 0igure $.a!e a signal generator and obser6e its out%ut 8sinusoidal signal on CR).
5dŒust te 5m%litude o0 te sinusoidal signal8Vi as 1V%-%.ee% its 0re4uenc2 as 17.$.Connect te signal generator to te in%ut o0 te LP'.…sing CR) obser6e te in%ut and out%ut a6e0orms simultaneousl2.* Var2 te 0re4uenc2 o0 in%ut signal 0rom 17 to 17
,. Measure te out%ut 6oltage 5m%litude8Vo 0or e6er2 in%ut 0re4uenc2 usingoscillosco%e.
' x.Claculatete +ain o0 te 'ilter o . 5lso Calculate its d( Value.
'i
x. Dra te gra% beteen 0re4uenc2 87 on ‘-5‰is and te +ain on ‚a‰is on semi -log seet.
z.Calculate te cut o00 0re4uenc2 0rom te gra%.is is te Practical 6alue o0 Cut o000re4uenc2.
–0rom te gra% 0ind te 6alue o0 Cut o00 0re4uenc2#at ic te +ain is .{{ times tat o0 Pass band gain85'—.
{.Com%are te Practical 6alues it eoritical 6alues.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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•• IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Note:
It is better to ta!e a Ca%acitor o0 a standard80i‰ed6alue#not a Variable Ca%acitor.I0 e ta!e Variable Ca%acitor Value# some times# te 'ilter ma2 gi6e bad
Res%onse8out%ut.vo in te abo6e Design Procedure#e a6e Cosen a 0i‰ed 6alue 0or te Ca%acitor#not a Variable Ca%acitor#and ten Calculated te 6alue o0 Resistor 0or a desired 0re4uenc2.
PROCE)%RE:
L) P5vv 'ILER| I+ P5vv 'ILER 'RE…EC REvP)vE 1.Connect te circuit as son in 0igure $.a!e a signal generator and obser6e its out%ut 8sinusoidal signal on CR).
5dŒust te 5m%litude o0 te sinusoidal signal8Vi as 1V%-%.ee% its 0re4uenc2 as 17.
$.Connect te signal generator to te in%ut o0 te LP'.…sing CR) obser6e te in%ut and out%ut a6e0orms simultaneousl2.* Var2 te 0re4uenc2 o0 in%ut signal 0rom 17 to 17
,. Measure te out%ut 6oltage 5m%litude8Vo 0or e6er2 in%ut 0re4uenc2 usingoscillosco%e.
'
x.Claculatete +ain o0 te 'ilter o . 5lso Calculate its d( Value.'i
x. Dra te gra% beteen 0re4uenc2 87 on ‘-5‰is and te +ain on ‚a‰is on semi -log seet.
z.Calculate te cut o00 0re4uenc2 0rom te gra%.is is te Practical 6alue o0 Cut o00
0re4uenc2.–0rom te gra% 0ind te 6alue o0 Cut o00 0re4uenc2#at ic te +ain is
.{{ times tat o0 Pass band gain85'—.{.Com%are te Practical 6alues it eoritical 6alues.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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•€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II OSERVATIONS:
In%utvignal5m%litude8Vin 1V%-%
're4uenc2
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)ut%ut +ain Vo/Vin
+ain8ind(
87 6oltage8Vo $log 8Vo/Vin 17 $7 ,7 z7 ‡7 =7 =x7 =‡7
17 1.17 1.$7 1.,7 $7 .
.
.
.17
Resu6t:
ence te 0re4uenc2 res%onse o0 0irst order lo %ass and ig %ass 0ilters using {,1 )P-5MP ere %lotted#and Claculated te iger and Loer Cut-o00 0re4uencies#
'rom +ra%s.Con#6usions:
e Practical 6alues are same as te teoritical 6alues in bot te cases8ie.#LP'|P' Inte 'irst case#0or te 0re4uencies belo 17 te 'ilterps +ain is Constant and a0ter 17 tereis a decrease in te +ain. vo it is Called as LoPass 'ilter.
In te vecond case#0or te 0re4uencies abo6e 17 te 'ilterps +ain is Constant and belo 17 tere is a decrease in te +ain. vo it is Called as ig Pass 'ilter.
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•€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II OSERVATIONS:
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In%utvignal5m%litude8Vin 1V%-%
're4uenc2 )ut%ut
+ain Vo/Vin+ain8ind(
87 6oltage8Vo $log 8Vo/Vin 17 $7 ,7 z7
‡7 =7 =x7 =‡7 17 1.17 1.$7 1.,7 $7 .
.
.
.17
Resu6t:
ence te 0re4uenc2 res%onse o0 0irst order lo %ass and ig %ass 0ilters using {,1 )P-5MP ere %lotted#and Claculated te iger and Loer Cut-o00 0re4uencies#
'rom +ra%s.Con#6usions:
e Practical 6alues are same as te teoritical 6alues in bot te cases8ie.#LP'|P' Inte 'irst case#0or te 0re4uencies belo 17 te 'ilterps +ain is Constant and a0ter 17 tereis a decrease in te +ain. vo it is Called as LoPass 'ilter.
In te vecond case#0or te 0re4uencies abo6e 17 te 'ilterps +ain is Constant and belo 17 tere is a decrease in te +ain. vo it is Called as ig Pass 'ilter.
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•ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment4-=
&%NCTION GENERATOR %SING <- OP4AMP
AIM: o generate triangular a6e0orm using {,1 )%-5m% 0unction generator.APPARAT%S: )%-am%{,1-$o#
Ca%acitor ‚.1&0 ‚ 1o#
ener
diode ‚x1 ‚$o#
Resistors ‚1-$#1x-1#1x-1#1M-1#
‡.$"-1 CIRC%IT )IAGRAM:
C .x&' R$$‡ q1xV Ri 1, { R11 q1xV $ *
{ z {,1 z * { {,1 ,
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$ V5 , -1xV V(
-1xV O%TP%T WAVE&ORMS
1x V( qVsat x V… t8ms 1 $
* -x VL - 1 -Vsat - 1x INSTIT%TE O& ENGINEERING ' TECHNOLOG
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•ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment4-=
&%NCTION GENERATOR %SING <- OP4AMP
AIM: o generate triangular a6e0orm using {,1 )%-5m% 0unction generator.APPARAT%S: )%-am%{,1-$o#
Ca%acitor ‚
.1&0 ‚ 1o#
enerdiode ‚x1 ‚$o#
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Resistors ‚1-$#1x-1#1x-1#
1M-1#‡.$"-1 CIRC%IT )IAGRAM:
C .x&' R$$‡ q1xV Ri 1, { R11 q1xV $
* { z {,1 z * { {,1 , $ V5 , -1xV V( -1xV O%TP%T WAVE&ORMS
1x V( qVsat x V… t8ms 1 $ * -x VL - 1 -Vsat
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- 1x INSTIT%TE O& ENGINEERING ' TECHNOLOG
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•< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Pin out dia1ram o7 LM
<- IC
)''vE …LL 1 ‡ C IV I/P $ { V q ) IV I/P * z )/P V - , x )''vE …LL THEOR:
5 basic bi%olar triangle a6e generator circuit is %resented in 0ig 1 . e triangle a6eV5 # is a6ailable at te out%ut o0 te {,1 integrator circuit . e s4uare a6e signal V(# isa6ailable at te out%ut o0 te {,1 com%arator . 5ssume tat V( is ig at qVsat. is 0orces aconstant current 8Vsat/Ri troug C 8le0t to rigt to dri6e V5 negati6e 0rom V… to VL. enV5 reaces VL# Pin * o0 te com%arator goes negati6e and V( sna%s to ‚Vsat. 5nd t 1msec.
en V( is at -Vsat # it 0orces a constant current8 rigt to le0t troug C to dri6e V5 %ositi6e 0rom VL toard V… 8 te time inter6al 1 to $ msec . en V5 reaces V… at t $msec # %in * o0 te com%arator goes %ositi6e and V( sna%s to qVsat. is initiates tene‰t c2cle o0 oscillation .
&requen#B o7 Operation
e %ea! 6alues o0 te triangular a6e are establised b2 te ratio o0 resistor R$ to R and
te saturation 6oltages .Ž ' R
e2 are gi6en b2 1 '
sat BT
R $ ' R 1 '
sat LT R $ I0 te saturation 6oltages are reasonable e4ual # te 0re4uenc2 o0 oscillation 80 is gi6en b2 R f
$
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, R R C
i 1 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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k?SF NO?k ?JGK
•< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II Pin out dia1ram o7 LM
<- IC
)''vE …LL 1 ‡ C IV I/P $ { V q ) IV I/P * z )/P
V - , x )''vE …LL THEOR:
5 basic bi%olar triangle a6e generator circuit is %resented in 0ig 1 . e triangle a6eV5 # is a6ailable at te out%ut o0 te {,1 integrator circuit . e s4uare a6e signal V(# isa6ailable at te out%ut o0 te {,1 com%arator . 5ssume tat V( is ig at qVsat. is 0orces aconstant current 8Vsat/Ri troug C 8le0t to rigt to dri6e V5 negati6e 0rom V… to VL. enV5 reaces VL# Pin * o0 te com%arator goes negati6e and V( sna%s to ‚Vsat. 5nd t 1msec.
en V( is at -Vsat # it 0orces a constant current8 rigt to le0t troug C to dri6e V5 %ositi6e 0rom VL toard V… 8 te time inter6al 1 to $ msec . en V5 reaces V… at t $msec # %in * o0 te com%arator goes %ositi6e and V( sna%s to qVsat. is initiates tene‰t c2cle o0 oscillation .
&requen#B o7 Operation e %ea! 6alues o0 te triangular a6e are establised b2 te ratio o0 resistor R$ to R andte saturation 6oltages .
Ž ' R e2 are gi6en b2 1 ' sat
BT R $
' R 1 ' sat LT R $ I0 te saturation 6oltages are reasonable e4ual # te 0re4uenc2 o0 oscillation 80 is gi6en b2 R
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f
$ , R R C i
1
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•† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
1. Connect te circuit as son in te 0igure.$. )bser6e te out%ut a6e0orms on CR) and note don necessar2 readings and
a6e0orms.*. Calculate te time %eriod and am%litude o0 te a6e0orm teoreticall2.,. Com%are te teoretical 6alues it te e‰%erimental results.RES%LT:
ence triangular a6e0orm is generated using {,1 )%-5m% 0unction generator.CONCL%SIONS:
It can be concluded tat te {,1 integrator as %roduced a triangle a6e 8V5 and te {,1 com%arator as %roduced a s4uare a6e8 V( it am%litude le6els ‚Vsat to qVsat.eout%ut o0 te {,1 com%arator as gi6en to te integrators in%ut . at means integration o0s4uare a6e gi6es te triangle a6e.
INSTIT%TE O& ENGINEERING ' TECHNOLOG 1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
•† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
1. Connect te circuit as son in te 0igure.
$. )bser6e te out%ut a6e0orms on CR) and note don necessar2 readings and a6e0orms.*. Calculate te time %eriod and am%litude o0 te a6e0orm teoreticall2.,. Com%are te teoretical 6alues it te e‰%erimental results.RES%LT:
ence triangular a6e0orm is generated using {,1 )%-5m% 0unction generator.CONCL%SIONS:
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It can be concluded tat te {,1 integrator as %roduced a triangle a6e 8V5 and te {,1 com%arator as %roduced a s4uare a6e8 V( it am%litude le6els ‚Vsat to qVsat.eout%ut o0 te {,1 com%arator as gi6en to te integrators in%ut . at means integration o0s4uare a6e gi6es te triangle a6e.
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€ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:->
MONOSTALE M%LTIVIRATOR %SING @@@ IC
AIM: o obser6e te out%ut a6e0orm o0 Monostable multi6ibrator using xxx IC.APPARAT%S:
(read (oard CR)8$/*M7 Connecting ires COMPONENTS:
@xx IC# Resistors and Ca%acitors as %er te Design CIRC%IT )IAGRAM:
MONOSTALE M%LTIVIRATOR
V V CCxV i
R ‡ , , $ time { rigger i/% Vo xxx LM @@@
z z * C 1 x CR) time
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.1&0 ) 81.1 RC Pin dia1ram
+D 1 ‡ VCC
rigger $ { Discarge @
)ut%ut * z resold LM @@
Reset , x Control Voltage INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:->
MONOSTALE M%LTIVIRATOR %SING @@@ IC
AIM: o obser6e te out%ut a6e0orm o0 Monostable multi6ibrator using xxx IC.APPARAT%S:
(read (oard CR)8$/*M7 Connecting ires
COMPONENTS: @xx IC# Resistors and Ca%acitors as %er te Design CIRC%IT )IAGRAM:
MONOSTALE M%LTIVIRATOR
V V CCxV i R ‡ ,
, $ time { rigger i/% Vo xxx LM @@@
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z z * C 1
x CR) time .1&0 ) 81.1 RC Pin dia1ram
+D 1 ‡ VCC rigger $ { Discarge @
)ut%ut *
z resold LM @@
Reset , x Control Voltage INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
E xxx 5v 5 M))v5(LE M…LIVI(R5)R: 5 Monostable multi6ibrator is also called as a one-sot multi6ibrator is a %ulse- generating circuit in ic te duration o0 te %ulse is determined b2 te RC netor!connected e‰ternall2 to te xxx timer. In a stable state te out%ut o0 te circuit is 7ero or at logic-lo le6el.
en an e‰ternal trigger %ulse is a%%lied# te out%ut is 0orced to go ig 8≅Vcc. etime te out%ut remains ig is determined b2 te e‰ternal RC netor! connected to te timer.
5t te end o0 te timing inter6al# te out%ut automaticall2 re6erts bac! to its logic lostable state. e out%ut sta2s lo until te trigger %ulse is again a%%lied. en te c2cle re%eats.
e monostable multi6ibrator as onl2 te stable state.e a%%lications 0or te monostable multi 6ibrator are 0re4uenc2 di6ider and %ulse
stretcer )ESIGN:
Dersign a MMV using xxxIC to %roduce an )ut%ut Pulse idt o0 1msec.1.Let R1
T $.Claculate te 6alue o0 C using te 0ormula C
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p
R 1 .
1 PROCE)%RE:
1.Connect te circuit as son in te 0igure# b2 using te com%onent as %er design.$. 5%%l2 te rigger %ulse at Pin no $. )bser6e te out%ut a6e0orm at %in no *.*.Calculate te time during ic te out%ut remains ig8t% or tonor %
,.Com%are it it te teoritical 6alue+
RES%LT:
e out%ut o0 Monostable multi6ibrator using xxxIC is obser6ed. It is also obser6ed tat %ractical 6alue o0 te time during ic te out%ut remains ig is same as teoritical 6alue.
CONCL%SIONS:
It can be concluded tat#i0 te MMV is once triggered#its out%ut ill remain in te ig
state until te set time ela%ses.e out%ut ill not cange its state e6en i0 an in%ut trigger isa%%lied again during tis time inter6al %.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
E xxx 5v 5 M))v5(LE M…LIVI(R5)R: 5 Monostable multi6ibrator is also called as a one-sot multi6ibrator is a %ulse- generating circuit in ic te duration o0 te %ulse is determined b2 te RC netor!connected e‰ternall2 to te xxx timer. In a stable state te out%ut o0 te circuit is 7ero or at logic-lo le6el.
en an e‰ternal trigger %ulse is a%%lied# te out%ut is 0orced to go ig 8≅Vcc. etime te out%ut remains ig is determined b2 te e‰ternal RC netor! connected to te timer.
5t te end o0 te timing inter6al# te out%ut automaticall2 re6erts bac! to its logic lostable state. e out%ut sta2s lo until te trigger %ulse is again a%%lied. en te c2cle re%eats.e monostable multi6ibrator as onl2 te stable state.
e a%%lications 0or te monostable multi 6ibrator are 0re4uenc2 di6ider and %ulse
stretcer )ESIGN:
Dersign a MMV using xxxIC to %roduce an )ut%ut Pulse idt o0 1msec.1.Let R1
T $.Claculate te 6alue o0 C using te 0ormula C
p
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R
1 .
1 PROCE)%RE:
1.Connect te circuit as son in te 0igure# b2 using te com%onent as %er design.$. 5%%l2 te rigger %ulse at Pin no $. )bser6e te out%ut a6e0orm at %in no *.*.Calculate te time during ic te out%ut remains ig8t% or tonor %
,.Com%are it it te teoritical 6alue+
RES%LT:
e out%ut o0 Monostable multi6ibrator using xxxIC is obser6ed. It is also obser6ed tat %ractical 6alue o0 te time during ic te out%ut remains ig is same as teoritical 6alue.
CONCL%SIONS:
It can be concluded tat#i0 te MMV is once triggered#its out%ut ill remain in te igstate until te set time ela%ses.e out%ut ill not cange its state e6en i0 an in%ut trigger isa%%lied again during tis time inter6al %.
INSTIT%TE O& ENGINEERING ' TECHNOLOG 1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment:-<
ASTALE M%LTIVIRATOR %SING @@@ IC
AIM: o obser6e te out%ut a6e0orm o0 5stable multi6ibrator using xxx IC.APPARAT%S:
(read (oard CR)8$/*M7 Connecting ires COMPONENTS:
@xx IC# Resistors and Ca%acitors as %er te Design CIRC%IT )IAGRAM:
ASTALE M%LTIVIRATOR
VCCxV .z=8R5qR(C ‡
R , 5 C * { R( R
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x xxx ( * z
D CR) C $ .1&0 .z=R(C 1 x Pin dia1ram
+D 1 ‡ VCC @
rigger $ { Discarge )ut%ut * LM @@
z resold Reset , x Control Voltage INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment:-<
ASTALE M%LTIVIRATOR %SING @@@ IC
AIM: o obser6e te out%ut a6e0orm o0 5stable multi6ibrator using xxx IC.APPARAT%S:
(read (oard CR)8$/*M7 Connecting ires COMPONENTS:
@xx IC# Resistors and Ca%acitors as %er te Design CIRC%IT )IAGRAM:
ASTALE M%LTIVIRATOR
VCCxV .z=8R5qR(C ‡ R ,
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%ositi6e %ulse idt8c.,$1msec and a a negati6e %ulse idt 8d.$z=msec.Let c .z= 8R5qR( C ---1# ere c is te time during ic te out%ut is ig.Let d .z= R(C------------$# ere d is te time during ic te out%ut is lo
Calculate cqd 1.velect C .1 &'.
$.calculate R( using E4uation $ *.using te results in ste%s1#$#calculate R5 using E4uation 1 PROCE)%RE:
-+ Connect te circuit as son in te 0igure.$.velect te com%onent 6alues as %er design.*. )bser6e te out%ut a6e0orm at %in no *.,.Calculate te time during ic te out%ut is ig and out%ut is lo.Com%are it it teoritical 6alues+
x.Calculate te } dut2 c2cle using te 0ormula 8c / ž1. Com%are it it teoritical6alue+
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€; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
5n 5stable multi6ibrator# o0ten called as 0ree-running multi6ibrator# is a rectangular-a6e-generating circuit. is circuit does not re4uire an e‰ternal trigger to cange te stable o0te out%ut# ence te name 0ree-running. oe6er te time during ic te out%ut is eiter ig
or lo is determined b2 to resistors and a ca%acitor. ic are e‰ternall2 connected to te xxx timer.
e a%%lications 0or astable multi6ibrator are 81 v4uare-a6e oscillator 8$ 'ree-runningram% generator.
)ESIGN:
Design an 5stable Multi6ibrator using xxxIC to %roduce an out%ut %ulse it a %ositi6e %ulse idt8c.,$1msec and a a negati6e %ulse idt 8d.$z=msec.
Let c .z= 8R5qR( C ---1# ere c is te time during ic te out%ut is ig.Let d .z= R(C------------$# ere d is te time during ic te out%ut is lo
Calculate cqd 1.velect C .1 &'.
$.calculate R( using E4uation $ *.using te results in ste%s1#$#calculate R5 using E4uation 1 PROCE)%RE:
-+ Connect te circuit as son in te 0igure.$.velect te com%onent 6alues as %er design.*. )bser6e te out%ut a6e0orm at %in no *.,.Calculate te time during ic te out%ut is ig and out%ut is lo.Com%are it it teoritical 6alues+
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x.Calculate te } dut2 c2cle using te 0ormula 8c / ž1. Com%are it it teoritical6alue+
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II RES%LT:
e out%ut o0 5stable Multi6ibrator using xxxIC is obser6ed.It is also obser6ed tat %ractical 6alue o0 te time during ic te out%ut remains ig
and out%ut is lo is same as teoritical 6alue.CONCL%SIONS:
It can be concluded tat b2 canging te 6alues o0 te Com%onents 8i.e.# R5# R( and
C#te Pulse idts ill be canged.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II RES%LT:
e out%ut o0 5stable Multi6ibrator using xxxIC is obser6ed.It is also obser6ed tat %ractical 6alue o0 te time during ic te out%ut remains igand out%ut is lo is same as teoritical 6alue.
CONCL%SIONS:
It can be concluded tat b2 canging te 6alues o0 te Com%onents 8i.e.# R5# R( andC#te Pulse idts ill be canged.
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ۥ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment:-@
SCHMITT TRIGGER
AIM: o obser6e te out%ut o0 te vcmitt trigger using {,1 | xxx ICpv APPARAT%S:1. )scillosco%e8$/*M $. Poer su%%l28-*V
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*. vignal generator8-1M7 ,. (read (oard x. Resistors 1"-$o.s#xz"#1" z. Resistors 1 #x" {. )%-am% {,1IC ‚ 1o.
CIRC%IT )IAGRAM: qVC R)M ≅ R ŸŸ 1 R $ q1xV $ { - z V
q q - * , V -V 1xV EE in RL
Vlt 1" R$x" R11 " &i1*-a! vcmitt rigger using {,1 )P-5m% V cc R1 1!om ‡ , z * )ut%ut Vi Vcc/$ xxx In%ut $
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R$ x 1 1!om .1micro 0arad
&i1*-0! vcmitt rigger using xxxIC INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ۥ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment:-@
SCHMITT TRIGGER
AIM: o obser6e te out%ut o0 te vcmitt trigger using {,1 | xxx ICpv APPARAT%S:1. )scillosco%e8$/*M $. Poer su%%l28-*V *. vignal generator8-1M7 ,. (read (oard x. Resistors 1"-$o.s#xz"#1" z. Resistors 1 #x" {. )%-am% {,1IC ‚ 1o.
CIRC%IT )IAGRAM:
qVC R)M ≅ R ŸŸ
1 R $ q1xV $ { - z V q q -
* , V -V 1xV EE in RL
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Vlt 1" R$x" R11 "
&i1*-a! vcmitt rigger using {,1 )P-5m% V cc R1 1!om ‡ , z * )ut%ut Vi Vcc/$
xxx In%ut $ R$ x 1 1!om .1micro 0arad &i1*-0! vcmitt rigger using xxxIC INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II MO)EL
WAVE&ORMS:
Vin V% - Vut
V
Vlt t - V% V qVv5 V
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t -Vv5 &i1*-C!In%ut and out%ut a6e 0orms Vo qVsat
qVut qVIt Vin 2steresis 6oltage 8Vut-Vit -Vsat &i1*-d!Vo 6ersus Vin Plot o0 te 2sterisis Voltage INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II MO)EL
WAVE&ORMS:
Vin V% - Vut V
Vlt t - V% V qVv5 V t -Vv5 &i1*-C!In%ut and out%ut a6e 0orms Vo qVsat
qVut qVIt Vin 2steresis 6oltage 8Vut-Vit -Vsat &i1*-d!Vo 6ersus Vin Plot o0 te 2sterisis Voltage INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
A!SCHMITT TRIGGER %SING <-IC:
'igure 81a sos an in6erting com%arator it %ositi6e 0eedbac!. is circuit
con6erts an irregular ‚sa%ed a6e0orm to a s4uare a6e or %ulse. e circuit is !nonas te vcmitt trigger or s4uaring circuit.
e in%ut 6oltage Vin triggers 8canges te state o0 te out%ut V e6er2 time it e‰ceedscertain 6oltage le6els called te u%%er tresold 6oltage Vut and loer tresold 6oltage Vlt# asson in 'igure 81c.
In 'igure 81a# tese tresold 6oltages are obtained b2 using te 6oltage di6ider R1-R$#ere te 6oltage across R1 is 0ed bac! to te 8q in%ut. e 6oltage across R1 is a 6ariablere0erence tresold 6oltage tat de%ends on te 6alue and %olarit2 o0 te out%ut 6oltage V.
en V qVsat# te 6oltage across R1 is called te u%%er tresold 6oltage# Vut. ein%ut 6oltage Vin must be sligtl2 more %ositi6e tan Vut in order to cause te out%ut Vo tositc 0rom qVsat to ‚Vsat. 5s long as Vin y Vut# Vo is at qVsat. …sing te 6oltage-di6ider rule# R ' 1
q 1a ut 8 'sat R 1 q R $
)nteoterand#en
V -Vsat# te 6oltage across R1 is re0erred to as te loer tresold 6oltage# Vlt. Vin must be sligtl2 more negati6e tan Vlt in order to cause Vto sitc 0rom ‚Vsat to qVsat. In oter ords# 0or Vin 6alues greater tan Vlt# V is at ‚Vsat.Vlt is gi6en b2 te 0olloing e4uation: R ' 1 Ž
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1 q 1a ut
8 'sat R 1 q R $
)nteoterand#enV -Vsat# te 6oltage across R1 is re0erred to as te loer
tresold 6oltage# Vlt. Vin must be sligtl2 more negati6e tan Vlt in order to cause Vto sitc 0rom ‚Vsat to qVsat. In oter ords# 0or Vin 6alues greater tan Vlt# V is at ‚Vsat.
Vlt is gi6en b2 te 0olloing e4uation: R ' 1 Ž 1b !t 8 'sat R 1 q R $
us#i0tetresold6oltageVut and Vlt are made larger tan te in%ut noise 6oltages#te %ositi6e 0eedbac! ill eliminate te 0alse out%ut transitions. 5lso# te %ositi6e
0eedbac!# because o0 its regenerati6e action# ill ma!e V sitc 0aster beteen qVsat and ‚ Vsat. In 'igure 8a# resistance R ≅ )M R1 R$ is used to minimi7e te o00set %roblems.
'igure 81c sos tat te out%ut o0 te vcmitt trigger is a s4uare a6e en te in%utis a sine a6e. 5 nonin6erting com%arator is used as a vcmitt trigger. en te in%ut is atriangular INSTIT%TE O& ENGINEERING ' TECHNOLOG
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€< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II a6e# te out%ut o0 tevcmitt trigger is a s4uare a6e# ere as i0 te in%ut is a satoot a6e# te out%ut is a %ulsea6e0orm.
e com%arator it %ositi6e 0eedbac! is said to e‰ibit 2steresis# a dead-band condition. at is# en te in%ut o0 te com%arator e‰ceeds Vut# its out%ut sitces0rom qVsat to ‚Vsat and re6erts bac! to its original state# qVsat# en te in%ut goes belo Vlt.8vee 'igure 1d e 2steresis 6oltage is e4ual to te di00erence beteen Vut and Vlt.
ere0ore#V2 Vut -Vlt. R
1 –q ' Ž Ž '
sat 8 sat — R
----------$
1 q R $ ANALSIS O& THE CIRC%IT -A:
'or {,1#te ma‰imum out%ut 6oltage sing is 1,V.at is qVsat1,V and -Vsat -1,V. 'rom e4uation 1a|1b#
1 ' q1, ${ x .
ut 8 m'
x1 1
' Ž1, ${ Ž x .
!t 8 m'
x1
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e 2sterisis VoltagexxmV.! SCHMITT TRIGGER %SING @@@:
e use o0 xxx timer as a vcmitt rigger is son in 'igure81b. ere te to internal ' com%arators are tied togeter and e‰ternall2 biased at CC troug R1 and R$. vince te u%%er
$ $ 1 com%arator ill tri% at VCC and loer com%arator at VCC# te bias %ro6ided b2 R1 and R$ is * * centered itin tese to tresolds. us# a sine a6e o0 su00icient am%litude ' $
' 89 CC CC ' Ž to e‰ceed te re0erence le6els causes te internal 0li%-0lo% to alternatel2 z * CC $ set and reset# %ro6iding a s4uare a6e out%ut as son in 'ig1c. It ma2 be noted tat unli!e con6entional multi 6ibrator# no 0re4uenc2 di6ision ista!ing %lace and te 0re4uenc2 o0 s4uare a6e remains te same as tat o0 in%ut signal.
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€< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II a6e# te out%ut o0 tevcmitt trigger is a s4uare a6e# ere as i0 te in%ut is a satoot a6e# te out%ut is a %ulse
a6e0orm.
e com%arator it %ositi6e 0eedbac! is said to e‰ibit 2steresis# a dead-band condition. at is# en te in%ut o0 te com%arator e‰ceeds Vut# its out%ut sitces0rom qVsat to ‚Vsat and re6erts bac! to its original state# qVsat# en te in%ut goes belo Vlt.8vee 'igure 1d e 2steresis 6oltage is e4ual to te di00erence beteen Vut and Vlt.
ere0ore#V2 Vut -Vlt.
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R
1 –q ' Ž Ž '
sat
8 sat — R
----------$
1 q R $ ANALSIS O& THE CIRC%IT -A:
'or {,1#te ma‰imum out%ut 6oltage sing is 1,V.at is qVsat1,V and -Vsat -1,V. 'rom e4uation 1a|1b#
1 '
q1, ${ x .ut
8 m'
x1 1 ' Ž1, ${ Ž x .
!t 8 m'
x1 e 2sterisis VoltagexxmV.
! SCHMITT TRIGGER %SING @@@:
e use o0 xxx timer as a vcmitt rigger is son in 'igure81b. ere te to internal '
com%arators are tied togeter and e‰ternall2 biased at CC troug R1 and R$. vince te u%%er $ $ 1 com%arator ill tri% at VCC and loer com%arator at VCC# te bias %ro6ided b2 R1 and R$ is * * centered itin tese to tresolds. us# a sine a6e o0 su00icient am%litude '
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$ ' 89 CC CC
' Ž
to e‰ceed te re0erence le6els causes te internal 0li%-0lo% to alternatel2 z * CC $ set and reset# %ro6iding a s4uare a6e out%ut as son in 'ig1c. It ma2 be noted tat unli!e con6entional multi 6ibrator# no 0re4uenc2 di6ision ista!ing %lace and te 0re4uenc2 o0 s4uare a6e remains te same as tat o0 in%ut signal.
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۠ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
1. Connect te circuit as son in 0igure.$. 5%%l2 a sinusoidal a6e it %ea! 6oltage greater tan te designed 6oltage 8…t.*. )bser6e te a6e0orm on CR).,. ote tat# en in%ut sinusoidal 6oltage is more tan V8…t# te out%ut canges
0rom ‚Vsat to qVsat..
en Vin is less tan V8Lt te out%ut canges 0rom qVsat to ‚Vsat.x.)bser6e te out%ut a6e0orm on CR).z.Put te CR) in ‘ Mode–In%ut signal on Cannel1| out%ut signal on Cannel$—.en e can obser6e te 2sterisis Voltage Cur6e on te CR).'rom tis ote don V… and VL.ese are te e‰treme %oints o0 te cur6e on ‘-a‰is.8E‰treme Le0t and E‰treme rigt
{.Dra te a6e0orms on gra% seets.z. )btain te V8…t and V8Lt 0rom gra% and com%are tem it te 0olloing
teoretical 6alues.
R
V8… 1 t ž8qVsat
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8 R
R 1 q $
R
V8L 1 t ž8-Vsat 8 R
R 1 q $
{. ote don te 2sterisis 6oltage V2 Vut ‚ VLt.RES%LT: ence te out%ut o0 vcmitt trigger using {,1 | xxx ICps is obser6ed.CONCL%SIONS:
'rom te 2sterisis 6oltage cur6e# it can be obser6ed tat# te to% and bottom e‰tremesare qVsat and ‚Vsat.
vo e can conclude tat te 2sterisis 6oltage cur6e is e‰isting# in beteen qVsat and ‚ Vsat on -a‰is.
)n ‘-a‰is 2sterisis 6oltage cur6e is e‰isting in beteen Vut and VLt.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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۠ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
1. Connect te circuit as son in 0igure.$. 5%%l2 a sinusoidal a6e it %ea! 6oltage greater tan te designed 6oltage 8…t.*. )bser6e te a6e0orm on CR).,. ote tat# en in%ut sinusoidal 6oltage is more tan V8…t# te out%ut canges
0rom ‚Vsat to qVsat..en Vin is less tan V8Lt te out%ut canges 0rom qVsat to ‚Vsat.x.)bser6e te out%ut a6e0orm on CR).z.Put te CR) in ‘ Mode–In%ut signal on Cannel1| out%ut signal on Cannel$—.
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en e can obser6e te 2sterisis Voltage Cur6e on te CR).'rom tis ote don V… and VL.ese are te e‰treme %oints o0 te cur6e on ‘-a‰is.8E‰treme Le0t and E‰treme rigt
{.Dra te a6e0orms on gra% seets.z. )btain te V8…t and V8Lt 0rom gra% and com%are tem it te 0olloing
teoretical 6alues.
R
V8… 1 t ž8qVsat
8 R R 1 q $
R
V8L 1 t ž8-Vsat 8 R R
1 q $
{. ote don te 2sterisis 6oltage V2 Vut ‚ VLt.RES%LT: ence te out%ut o0 vcmitt trigger using {,1 | xxx ICps is obser6ed.CONCL%SIONS:
'rom te 2sterisis 6oltage cur6e# it can be obser6ed tat# te to% and bottom e‰tremesare qVsat and ‚Vsat.
vo e can conclude tat te 2sterisis 6oltage cur6e is e‰isting# in beteen qVsat and ‚ Vsat on -a‰is.
)n ‘-a‰is 2sterisis 6oltage cur6e is e‰isting in beteen Vut and VLt.INSTIT%TE O& ENGINEERING ' TECHNOLOG
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Err
Constant Amp
current source
IV V4
V4
're4. Com%.vection-1
vection-$ 'ig1 b: 'unctional (loc! diagram o0 {$* IC INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No:-?
VOLTAGE REG%LATOR %SING LM => IC
AIM: o %lot te regulation caracteristics o0 te gi6en IC LM {$* APPARAT%S: Resistors {.x " - $# *.=" - 1# Ca%acitor 1 &' ‚ 1# IC LM {$* ‚1#DR(# Voltmeter -*V# 5mmeter -1m5.
PIN )IAGRAM ' &%NCTIONAL LOCD )IAGRAM:
C
C Current limit 're4. Com%ensation Current vense Vq IV-erminal VCC ) IV-erminal LM {$* Vout Voltage RE'
V +nd C 'ig.18a Pin diagram o0 LM{$* VC V CL 1
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8
Vq V7 D $
4 Cv V Vq Re7
re08-{V Amp
I Err
Constant Amp
current source IV V4
V4
're4. Com%.vection-1
vection-$ 'ig1 b: 'unctional (loc! diagram o0 {$* IC INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II CIRC…I DI5+R5M:
Part4- : In%ut Voltage 6ersus )ut%ut Voltage 1$ 11 z
1 $ *.= {.x {$* * x LM
V
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, -*V RL 1* {
.x 1&' 'ig 8$-a Circuit diagram 0or In%ut Voltage 6ersus )ut%ut Voltage Part4= Load Resistance RL 6ersus )ut%ut Voltage 8Vo Line Voltage 8'rom DC %oer su%%l2 R 1$ 11 z 1
$ *.= {.x 5 {$* * x LM , RL 1* { {.x V -*V 1&' 'ig 8$-b Circuit diagram 0or Load Resistance RL 6ersus )ut%ut Voltage }R 'ig8$-c RL 6ersus } Regulation cur6e INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II CIRC…I DI5+R5M: Part4- : In%ut Voltage 6ersus )ut%ut Voltage 1$ 11 z
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1 $ *.= {.x {$* *
x LMV
, -*V RL 1* { .x 1&' 'ig 8$-a Circuit diagram 0or In%ut Voltage 6ersus )ut%ut Voltage
Part4= Load Resistance RL 6ersus )ut%ut Voltage 8Vo Line Voltage 8'rom DC %oer su%%l2 R 1$ 11 z 1 $ *.= {.x 5 {$* * x LM , RL 1* { {.x V -*V 1&' 'ig 8$-b Circuit diagram 0or Load Resistance RL 6ersus )ut%ut Voltage }R 'ig8$-c RL 6ersus } Regulation cur6e INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
it te ad6ent o0 Micro-electronics# it is %ossible to incor%orate te com%lete circuit on
a monolitic silicon ci%. is gi6es lo cost# ig reliabilit2# reduction in si7e and e‰cellent %er0ormance.
E‰am%les o0 Monolitic regulators are {‡‰‰/{=‰‰ series8ree terminal regulators and{$* general %ur%ose regulators.
e tree terminal regulators a6e te limitations 81 o sort circuit %rotection. 8$ )ut%ut 6oltage 8%ositi6e or negati6e is 0i‰ed.
ese limitations a6e been o6er come in te {$* general %ur%ose regulators# ic can be adŒusted o6er a ide range o0 bot %ositi6e and negati6e regulated 6oltage. is IC isinerentl2 lo current de6ice# but can be boosted to %ro6ide xam%s or more current b2connecting e‰ternal com%onents.
e limitations o0 {$* are tat it as no in built termal %rotection. It also as no sortcircuit current limits. {$* regulator IC is a6ailable in a 1,-%in# dual-in-line %ac!age.
'ig.1-b sos te 0unctional bloc! diagram o0 a {$* regulator IC. It as to se%aratesections.
e 7ener diode# a constant current source and re0erence am%li0ier %roduce a 0i‰ed6oltage o0 about { 6olts at te terminal Vre0. e constant current source 0orces te 7ener to
o%erate at a 0i‰ed %oint so tat te 7ener out%uts a 0i‰ed 6oltage.e oter section o0 te IC consists o0 an error am%li0ier# a series %ass transistor 1 and a
current limit transistor limit transistor $. e error am%li0ier com%ares a sam%le o0 te out%ut6oltage a%%lied at te 1V in%ut terminal to te re0erence 6oltage Vre0 a%%lied at te I in%utterminal.
e error signal controls te conduction o0 1. ese to sections are not internall2connected but te 6arious %oints are brougt out on te IC %ac!age. {$* Regulated IC isa6ailable in 1, Pin Dual ‚ in ‚ line %ac!age or 1 %in metal can.
e im%ortant 0eatures o0 {$* Regulated IC are as 0ollos: 1 In%ut 6oltage ,V ma‰ $ )ut%ut 6oltage adŒustable 0rom $V to *{V
* 1xm5 out%ut current itout e‰ternal %ass transistor , )ut%ut currents in e‰cess o0 15 %ossible b2 adding e‰ternal transistors INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
it te ad6ent o0 Micro-electronics# it is %ossible to incor%orate te com%lete circuit on
a monolitic silicon ci%. is gi6es lo cost# ig reliabilit2# reduction in si7e and e‰cellent %er0ormance.
E‰am%les o0 Monolitic regulators are {‡‰‰/{=‰‰ series8ree terminal regulators and{$* general %ur%ose regulators.
e tree terminal regulators a6e te limitations 81 o sort circuit %rotection. 8$ )ut%ut 6oltage 8%ositi6e or negati6e is 0i‰ed.
ese limitations a6e been o6er come in te {$* general %ur%ose regulators# ic can be adŒusted o6er a ide range o0 bot %ositi6e and negati6e regulated 6oltage. is IC isinerentl2 lo current de6ice# but can be boosted to %ro6ide xam%s or more current b2connecting e‰ternal com%onents.
e limitations o0 {$* are tat it as no in built termal %rotection. It also as no sortcircuit current limits. {$* regulator IC is a6ailable in a 1,-%in# dual-in-line %ac!age.
'ig.1-b sos te 0unctional bloc! diagram o0 a {$* regulator IC. It as to se%aratesections.
e 7ener diode# a constant current source and re0erence am%li0ier %roduce a 0i‰ed6oltage o0 about { 6olts at te terminal Vre0. e constant current source 0orces te 7ener to
o%erate at a 0i‰ed %oint so tat te 7ener out%uts a 0i‰ed 6oltage.e oter section o0 te IC consists o0 an error am%li0ier# a series %ass transistor 1 and a
current limit transistor limit transistor $. e error am%li0ier com%ares a sam%le o0 te out%ut6oltage a%%lied at te 1V in%ut terminal to te re0erence 6oltage Vre0 a%%lied at te I in%utterminal.
e error signal controls te conduction o0 1. ese to sections are not internall2connected but te 6arious %oints are brougt out on te IC %ac!age. {$* Regulated IC isa6ailable in 1, Pin Dual ‚ in ‚ line %ac!age or 1 %in metal can.
e im%ortant 0eatures o0 {$* Regulated IC are as 0ollos: 1 In%ut 6oltage ,V ma‰ $ )ut%ut 6oltage adŒustable 0rom $V to *{V
* 1xm5 out%ut current itout e‰ternal %ass transistor , )ut%ut currents in e‰cess o0 15 %ossible b2 adding e‰ternal transistors INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II x It Can be used aseiter a linear or a sitcing regulator.
e electrical caracteristics o0 {$* Regulated IC can be seen 0rom 5%%endi‰.e {$* IC can be used as Lo Voltage 8$V to {V and ig Voltage 89{V Regulators
Current Limit Prote#tion:
e {$* IC is %ro6ided it a current limit 0acilit2. Current limiting re0ers to te abilit2o0 a regulator to %re6ent te load current 0rom increasing abo6e a %resent 6alue. ecaracteristic cur6e o0 a current limited regulator is son in te 0olloing 0ig.
V I limit V Load
ILoad Caracteristic cur6e o0 a current limited regulator e out%ut 6oltage remains constant 0or load current belo I limit . 5s currenta%%roaces te limit te out%ut 6oltages dro%s . e current limit I limit is set b2 connecting ane‰ternal resistor Rsc beteen te terminals CL and Cv . e CL terminal is also connected to teout%ut terminal Vo and Cv terminal is connected to te load resistance .
I limit .xV/Rsc Current 7o6d 0a#:
In current limiting tecni4ue# te load current is maintained at a %resent 6alue and eno6erload condition occurs # te out%ut 6oltage Vo dro%s to 7ero . oe6er # i0 te load is sortcircuited # ma‰imum current does 0lo troug te regulator. o Protect te regulator one must
de6ise a metod ic ill limit te sort circuit current and 2et allo iger currents to teload . Current 0old bac! is te metod used 0or tis. e 0olloing 0igure sos te current 0old bac! caracteristic cur6e INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ; IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II x It Can be used aseiter a linear or a sitcing regulator.
e electrical caracteristics o0 {$* Regulated IC can be seen 0rom 5%%endi‰.e {$* IC can be used as Lo Voltage 8$V to {V and ig Voltage 89{V Regulators
Current Limit Prote#tion:
e {$* IC is %ro6ided it a current limit 0acilit2. Current limiting re0ers to te abilit2o0 a regulator to %re6ent te load current 0rom increasing abo6e a %resent 6alue. e
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caracteristic cur6e o0 a current limited regulator is son in te 0olloing 0ig.V
I limit V Load ILoad
Caracteristic cur6e o0 a current limited regulator e out%ut 6oltage remains constant 0or load current belo I limit . 5s currenta%%roaces te limit te out%ut 6oltages dro%s . e current limit I limit is set b2 connecting ane‰ternal resistor Rsc beteen te terminals CL and Cv . e CL terminal is also connected to teout%ut terminal Vo and Cv terminal is connected to te load resistance .
I limit .xV/Rsc Current 7o6d 0a#:
In current limiting tecni4ue# te load current is maintained at a %resent 6alue and eno6erload condition occurs # te out%ut 6oltage Vo dro%s to 7ero . oe6er # i0 te load is sortcircuited # ma‰imum current does 0lo troug te regulator. o Protect te regulator one mustde6ise a metod ic ill limit te sort circuit current and 2et allo iger currents to te
load . Current 0old bac! is te metod used 0or tis. e 0olloing 0igure sos te current 0old bac! caracteristic cur6e INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II V
Isc V Load I I !nee Load Current 7o6d 0a# #2ara#teristi# #ur5e
OSERVATIONS:
Ta06e:
1. Variation o0 Vout itVin $. Variation o0 } Regulation it RL VL
Line 6oltage )ut%ut
RL IL8m5 )ut%ut } Regulation 8Vin 6oltage
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6oltage ' Ž ' #L
:L
8Vout 8Vout ':L $111 1. 1111 $. =11 *. {11 ,.
x11 .,11
.*11
.$11
1$. 111 1*. 1 1,. = 1x. 1z. 1{. INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II V Isc V Load I I !nee
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Load Current 7o6d 0a# #2ara#teristi# #ur5e
OSERVATIONS:
Ta06e:
1. Variation o0 Vout itVin $. Variation o0 } Regulation it RL
VL Line 6oltage )ut%ut
RL IL8m5 )ut%ut } Regulation 8Vin 6oltage 6oltage '
Ž ' #L :L 8Vout 8Vout ':L $111 1. 1111 $. =11 *. {11 ,. x11 .
,11 .
*11 .
$11 1$. 111 1*. 1 1,. = 1x. 1z. 1{.
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INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ĥ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
Part 1: In%ut Voltage 6ersus )ut%ut Voltage 1. Connect te circuit as son in te 0ig$-a.
$. Connect te su%%l2 beteen 1$ | { terminals *. Connect te 6oltmeter to 1 | ground terminals ,. Increase te in%ut 6oltage and note don te corres%onding out%ut 6oltage x. Initiall2 te out%ut 6oltage is increasing it an increase in in%ut Voltage 5t some 6alue o0 in%ut Voltage # te out%ut 6oltage becomes constant
ote don all tese readings 0rom te multimeter.z. Dra te +ra% beteen te line 6oltage8Vin Versus out%ut 6oltage8 Vout
Part =: Load Resistance RL 6ersus )ut%ut Voltage 8Vo 1. Connect te circuit as son in te 0ig $-b.
$. ee% te 6oltage constant at ic %art 1 is obtained.*. ee% te load resistance 8DR( in te ma‰imum %osition
8 !ee% all te nobs o0 DR( in ma‰imum %osition ,. Decrease te load resistance 8RLoad and note don te out%ut current 8ILoadandout%ut 6oltage.
x. Decrease te load resistance till te out%ut current reaces ma‰imum rated current andnote don te corres%onding 6alues o0 te out%ut 6oltage.
z. Dra te +ra% beteen te load resistance8RLoad and } regulation RES%LT:
ence te out%ut 6oltage o0 {$* regulator is obser6ed 0or di00erent in%ut 6oltages . andte caracteristics o0 te IC LM {$* are %lotted.
CONCL%SIONS :
It is concluded tat te } regulation is decreased it an increase in te loadresistance8RLoad INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ĥ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
Part 1: In%ut Voltage 6ersus )ut%ut Voltage 1. Connect te circuit as son in te 0ig$-a.
$. Connect te su%%l2 beteen 1$ | { terminals
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*. Connect te 6oltmeter to 1 | ground terminals ,. Increase te in%ut 6oltage and note don te corres%onding out%ut 6oltage x. Initiall2 te out%ut 6oltage is increasing it an increase in in%ut Voltage 5t some 6alue o0 in%ut Voltage # te out%ut 6oltage becomes constant ote don all tese readings 0rom te multimeter.
z. Dra te +ra% beteen te line 6oltage8Vin Versus out%ut 6oltage8 Vout Part =: Load Resistance RL 6ersus )ut%ut Voltage 8Vo 1. Connect te circuit as son in te 0ig $-b.
$. ee% te 6oltage constant at ic %art 1 is obtained.*. ee% te load resistance 8DR( in te ma‰imum %osition
8 !ee% all te nobs o0 DR( in ma‰imum %osition ,. Decrease te load resistance 8RLoad and note don te out%ut current 8ILoadandout%ut 6oltage.
x. Decrease te load resistance till te out%ut current reaces ma‰imum rated current andnote don te corres%onding 6alues o0 te out%ut 6oltage.
z. Dra te +ra% beteen te load resistance8RLoad and } regulation
RES%LT: ence te out%ut 6oltage o0 {$* regulator is obser6ed 0or di00erent in%ut 6oltages . andte caracteristics o0 te IC LM {$* are %lotted.
CONCL%SIONS :
It is concluded tat te } regulation is decreased it an increase in te loadresistance8RLoad INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ€ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No: -
< IT )AC %SING OP AMP
AIM: o obser6e te out%ut o0 a Digital to analog con6erter using 81(inar2 eigted resistors 8$ R and $R resistors.
APPARAT%S: )%-am% {,1 ‚ 1# Resistors8R 1 " - ,# $"8$R- ,#,{" - 1# 1" - 1# $$"# Potentiometer ‚ 1 o# Multimeter
CIRC%IT )IAGRAM:
R' 1 b
q1xV R 1! - { b $ 1 R/$
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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II E;periment No: -
< IT )AC %SING OP AMP
AIM: o obser6e te out%ut o0 a Digital to analog con6erter using 81(inar2 eigted resistors 8$ R and $R resistors.
APPARAT%S: )%-am% {,1 ‚ 1# Resistors8R 1 " - ,# $"8$R- ,#
,{" - 1# 1" - 1# $$"# Potentiometer ‚ 1 o# Multimeter CIRC%IT )IAGRAM:
R' 1 b q1xV R 1! - { b $ 1
R/$ LM{,1 z V) * b$ R/, q , -1xV b* R/‡ qxV R' $$! q1xV R 1! R R - { $ Vo LM{,1 $R $R $R $R $R * z
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q , RL 1! b b1
b$ b * -1xV qxV INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
5 Digital-to-5nalog Con6erter is used en a (inar2 out%ut 0rom a digital s2stem must be con6erted to some e4ui6alent 5nalog 6oltage or Current.e (inar2 out%ut 0rom a digitals2stem is di00icult to inter%ret.oe6er a D5C ma!es te inter%retation easier.e 0unction o0D5C is e‰actl2 o%%osite to tat o0 5DC.
5d6antages:1It is sim%ler in construction en com%ared to 5DC $It can be used to0orm te 5DC.
2%es o0 D/5 Con6erters: ere are to t2%es o0 D5Cs a6ailable 1. D/5 con6erter it (inar2 ‚eigted Resistors
$. D/5 con6erter it R and $R resistors.i.e.#5 D/5 con6erter in its sim%lest 0orm uses an o%-am% and eiter binar2 eigted
resistors or R and $R resistors.-! )A #on5erter "it2 inarB "ei12ted Resistors
asi# )AC Te#2niques: e scematic o0 a D5C is son in 'ig1. e in%ut is an n-bit binar2 ord D and is combined it a re0erence 6oltage VR to gi6e an analog out%ut signal. eout%ut o0 a D5C can be eiter a 6oltage or current. eor2 o/% 6oltage
V V'v 8b1$-1qb$$-$q¡..qbn$-n E4-1 ere V out%ut 6oltage V'v 0ull scale out%ut 6oltage
scaling 0actor usuall2 adŒusted to unit2
b1b$¡..bn n-bit binar2 0ractional ord it te decimal %oint located at te le0t b1 most signi0icant bit 8Mv( it a eigt o0 V'v/$ bn least signi0icant bit 8Lv( it a eigt o0 V'v/$n INSTIT%TE O& ENGINEERING ' TECHNOLOG
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k?SF NO?k ?JGK
ƒƒ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II THEOR:
5 Digital-to-5nalog Con6erter is used en a (inar2 out%ut 0rom a digital s2stem must be con6erted to some e4ui6alent 5nalog 6oltage or Current.e (inar2 out%ut 0rom a digitals2stem is di00icult to inter%ret.oe6er a D5C ma!es te inter%retation easier.e 0unction o0D5C is e‰actl2 o%%osite to tat o0 5DC.
5d6antages:1It is sim%ler in construction en com%ared to 5DC $It can be used to0orm te 5DC.
2%es o0 D/5 Con6erters: ere are to t2%es o0 D5Cs a6ailable 1. D/5 con6erter it (inar2 ‚eigted Resistors
$. D/5 con6erter it R and $R resistors.i.e.#5 D/5 con6erter in its sim%lest 0orm uses an o%-am% and eiter binar2 eigted
resistors or R and $R resistors.-! )A #on5erter "it2 inarB "ei12ted Resistors
asi# )AC Te#2niques: e scematic o0 a D5C is son in 'ig1. e in%ut is an n-bit binar2 ord D and is combined it a re0erence 6oltage VR to gi6e an analog out%ut signal. eout%ut o0 a D5C can be eiter a 6oltage or current. eor2 o/% 6oltage
V V'v 8b1$-1qb$$-$q¡..qbn$-n E4-1 ere V out%ut 6oltage V'v 0ull scale out%ut 6oltage
scaling 0actor usuall2 adŒusted to unit2
b1b$¡..bn n-bit binar2 0ractional ord it te decimal %oint located at te le0t b1 most signi0icant bit 8Mv( it a eigt o0 V'v/$ bn least signi0icant bit 8Lv( it a eigt o0 V'v/$n INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II ¢ q VR 8Mv(
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I b 1 q
(inar2 D5C V b n-1 ord ( bn 8Lv( vcematic o0 a D5C )A #on5erter "it2 0inarB "ei12ted resistors
e abo6e 0igure$ sos D/5 con6erter using o%-am% and binar2 eigted resistors .5ltoug in tis 0igure te o%-am% is connected in te in6erting mode it can also beconnected in te non in6erting mode# vince te number o0 binar2 in%uts is 0our#te con6erter iscalled , bit 8binar2 digit con6erter .
(ecause tere are 1z8 $, combinations o0 binar2 in%uts 0or b troug b* an analogout%ut sould a6e 1z %ossible corres%onding 6alues .In 'ig$# 0our sitces8bto b* are used tostimulate te binar2 in%uts win %ractice # a , bit binar2 counter suc as {,=* ma2 be used instead . en sitc b is closed 8connected to qxV#te 6oltage across R is xV because V$V1 V. ere0ore R is xV/1!" .xm5 .oe6er # te in%ut bias current I( is negligiblewence te current troug 0eedbac! resistor R' is also .x m5 #ic #in turn %roduces an out%ut6oltage o0 ‚81!"8.xm5 -.xV.ote tat te o%-am% is or!ing as a current ‚to- 6oltagecon6erter .
o su%%ose tat sitc b1 is closed and b is o%ened .is action connects R/$ to te %ositi6e su%%l2 o0 qxV# causing tice as muc current 81m5 to 0lo troug R' ic in turndoubles te out%ut 6oltage .us te out%ut 6oltage Vo is -1V en b1 sitc is closed .
vimilarl2 #i0 bot sitces b and b1 are closed #te current troug R' ill be 1.x m5 #ic ill be con6erted to an out%ut 6oltage o0 ‚81!"81.xm5 -1.xV.
us# de%ending on eter sitces b to b* are o%en or closed # te binar2 eigtedcurrents ill be set u% in in%ut resistors .e sum o0 tese currents is e4ual to te current trougR' # ic in turn is con6erted to a %ro%ortional out%ut 6oltage .
INSTIT%TE O& ENGINEERING ' TECHNOLOG
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ƒ< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II ¢
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q VR 8Mv( I b
1 q (inar2 D5C V b n-1 ord ( bn 8Lv(
vcematic o0 a D5C )A #on5erter "it2 0inarB "ei12ted resistors
e abo6e 0igure$ sos D/5 con6erter using o%-am% and binar2 eigted resistors
.5ltoug in tis 0igure te o%-am% is connected in te in6erting mode it can also beconnected in te non in6erting mode# vince te number o0 binar2 in%uts is 0our#te con6erter iscalled , bit 8binar2 digit con6erter .
(ecause tere are 1z8 $, combinations o0 binar2 in%uts 0or b troug b* an analogout%ut sould a6e 1z %ossible corres%onding 6alues .In 'ig$# 0our sitces8bto b* are used tostimulate te binar2 in%uts win %ractice # a , bit binar2 counter suc as {,=* ma2 be used instead . en sitc b is closed 8connected to qxV#te 6oltage across R is xV because V$V1 V. ere0ore R is xV/1!" .xm5 .oe6er # te in%ut bias current I( is negligiblewence te current troug 0eedbac! resistor R' is also .x m5 #ic #in turn %roduces an out%ut6oltage o0 ‚81!"8.xm5 -.xV.ote tat te o%-am% is or!ing as a current ‚to- 6oltagecon6erter .
o su%%ose tat sitc b1 is closed and b is o%ened .is action connects R/$ to te %ositi6e su%%l2 o0 qxV# causing tice as muc current 81m5 to 0lo troug R' ic in turndoubles te out%ut 6oltage .us te out%ut 6oltage Vo is -1V en b1 sitc is closed .
vimilarl2 #i0 bot sitces b and b1 are closed #te current troug R' ill be 1.x m5 #ic ill be con6erted to an out%ut 6oltage o0 ‚81!"81.xm5 -1.xV.
us# de%ending on eter sitces b to b* are o%en or closed # te binar2 eigtedcurrents ill be set u% in in%ut resistors .e sum o0 tese currents is e4ual to te current trougR' # ic in turn is con6erted to a %ro%ortional out%ut 6oltage .
INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
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ƒ† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II en all te sitcesare closed #ob6iousl2 te out%ut ill be ma‰imum .e out%ut 6oltage e4uation is gi6en b2 b 1 b b $ b *
Vo
-R
q q q '
R R / $ R / , R / ‡
ere eac o0 te in%uts b* #b$ #b1 and b ma2 eiter be ig 8qxV or lo 8V.'ig b sos analog out%uts 6ersus %ossible combinations o0 in%uts .e out%ut is a
negati6e going staircase a6e0orm ill 1x ste%s o0 -.xV eac in %ractice # oe6er te ste%sma2 not all be te same si7e because o0 te 6ariations o0 te logic ig 6oltage le6el .otice tatte si7e i0 te ste%s de%ends on te 6alue o0 R' ere0ore a desired ste% can be obtained b2selecting a %ro%er 6alue o0 R' %ro6ided tat te ma‰imum out%ut 6oltage doesnot e‰ceed tesaturation le6els o0 an o%-am% .'or accurate o%eration o0 te D/5 con6erter %recision metal 0ilmresistors are recommended )ra" 0a#s: e %roblem it D/5 con6erter is tat it re4uires binar2 eigtedresistors ic ma2 not readil2 a6ailable #es%eciall2 i0 te number o0 in%uts more tan 0our .5nalternati6e is to use R and $R resistors 0or te D/5 con6erter since it re4uires onl2 to sets o0
%recision resistance 6alues )A #on5erter "it2 R and =R
'ig8 a sos D/5 con6erter it R and $R resistors . 5s be0ore# te binar2 in%uts aresimulated b2 sitces b troug b* and te out%ut is %ro%ortional to te binar2 in%uts .(inar2in%uts can be in eiter te ig 8qx6 or lo 86 state .5ssume tat te most signi0icant bit 8Mv( sitc b* is connected to qxV and oter sitces are connected to ground # as in 'ig 8a . e6eni7ingte circuit to te le0t o0 sitc b* .e6eninps e4ui6alent resistance R is
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R –“–8$R $R qR $R—qR” $R—qR
$R$"
e resultant circuit is son in 0ig8( .In tis 0ig te 8- in%ut is at 6irtual ground 8V≅ $ V w
tere0ore # te current troug R 8 $R is 7ero oe6er # te current troug $Rconnected ' x to qxV is .$xm5 .e same current 0los troug R' and in turn %roduces te out%ut
$ " 6oltage
Vo -8$!" 8.$xm5 - xV INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
ƒ† IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II en all te sitcesare closed #ob6iousl2 te out%ut ill be ma‰imum .e out%ut 6oltage e4uation is gi6en b2 b 1 b b $ b *
Vo-R
q q q '
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R R / $ R / , R / ‡
ere eac o0 te in%uts b* #b$ #b1 and b ma2 eiter be ig 8qxV or lo 8V.'ig b sos analog out%uts 6ersus %ossible combinations o0 in%uts .e out%ut is anegati6e going staircase a6e0orm ill 1x ste%s o0 -.xV eac in %ractice # oe6er te ste%sma2 not all be te same si7e because o0 te 6ariations o0 te logic ig 6oltage le6el .otice tatte si7e i0 te ste%s de%ends on te 6alue o0 R' ere0ore a desired ste% can be obtained b2selecting a %ro%er 6alue o0 R' %ro6ided tat te ma‰imum out%ut 6oltage doesnot e‰ceed tesaturation le6els o0 an o%-am% .'or accurate o%eration o0 te D/5 con6erter %recision metal 0ilmresistors are recommended )ra" 0a#s: e %roblem it D/5 con6erter is tat it re4uires binar2 eigtedresistors ic ma2 not readil2 a6ailable #es%eciall2 i0 te number o0 in%uts more tan 0our .5nalternati6e is to use R and $R resistors 0or te D/5 con6erter since it re4uires onl2 to sets o0
%recision resistance 6alues )A #on5erter "it2 R and =R
'ig8 a sos D/5 con6erter it R and $R resistors . 5s be0ore# te binar2 in%uts aresimulated b2 sitces b troug b* and te out%ut is %ro%ortional to te binar2 in%uts .(inar2in%uts can be in eiter te ig 8qx6 or lo 86 state .5ssume tat te most signi0icant bit 8Mv( sitc b* is connected to qxV and oter sitces are connected to ground # as in 'ig 8a . e6eni7ingte circuit to te le0t o0 sitc b* .e6eninps e4ui6alent resistance R is
R –“–8$R $R qR $R—qR” $R—qR
$R$"
e resultant circuit is son in 0ig8( .In tis 0ig te 8- in%ut is at 6irtual ground 8V≅ $ V w
tere0ore # te current troug R 8 $R is 7ero oe6er # te current troug $Rconnected '
x to qxV is .$xm5 .e same current 0los troug R' and in turn %roduces te out%ut $ " 6oltage
Vo -8$!" 8.$xm5 - xV INSTIT%TE O& ENGINEERING ' TECHNOLOG
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<ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II …sing te same anal2sis#te out%ut 6oltage corres%onding to all %ossible combinations o0 binar2 in%uts can becalculated .e ma‰imum or 0ull ‚scale out%ut o0 -=.*{x V is obtained en all te in%uts areig .e out%ut 6oltage e4uation can be ritten as b * b $ b 1 b V
q q q o - R' $ R , R ‡ R 1z R
ere eac o0 te in%uts b*# b$# b1 and b ma2 be eiter ig8qxV or lo 8V
e great ad6antage o0 te D/5 Con6erter is tat it re4uires onl2 to sets o0 %recisionresistance 6aluesw ne6erteless# it re4uires more resistors and is also more di00icult to anal27etan te binar2 ‚eigted resistor t2%e .5s te number o0 binar2 in%uts is increased be2ond 0our#
bot D/5 con6erter circuit get com%le‰ and teir accurac2 degenerates. ere0ore# in criticala%%lications an integrated circuit s%eciall2 designed as D/5 con6erter sould be used.
OSERVATIONS
v.o
Digital In%uts5nalog )ut%ut
1 $ 1 * 1 , 1 1
x 1 z 1 1 { 1 1 ‡ 1 1 1 = 1 1 1 1 11 1 1 1$ 1 1 1
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1* 1 1 1, 1 1 1 1x 1 1 1 1z 1 1 1 1 INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
<ˆ IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II …sing te same anal2sis#te out%ut 6oltage corres%onding to all %ossible combinations o0 binar2 in%uts can becalculated .e ma‰imum or 0ull ‚scale out%ut o0 -=.*{x V is obtained en all te in%uts areig .e out%ut 6oltage e4uation can be ritten as
b * b $ b 1 b V q q q o - R'
$ R , R ‡ R 1z R
ere eac o0 te in%uts b*# b$# b1 and b ma2 be eiter ig8qxV or lo 8V
e great ad6antage o0 te D/5 Con6erter is tat it re4uires onl2 to sets o0 %recisionresistance 6aluesw ne6erteless# it re4uires more resistors and is also more di00icult to anal27etan te binar2 ‚eigted resistor t2%e .5s te number o0 binar2 in%uts is increased be2ond 0our# bot D/5 con6erter circuit get com%le‰ and teir accurac2 degenerates. ere0ore# in criticala%%lications an integrated circuit s%eciall2 designed as D/5 con6erter sould be used.
OSERVATIONS
v.o
Digital In%uts
5nalog )ut%ut 1 $ 1 * 1 , 1 1 x 1 z 1 1 { 1 1
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‡ 1 1 1 = 1 1 1 1 11 1 1 1$ 1 1 1
1* 1 1 1, 1 1 1 1x 1 1 1 1z 1 1 1 1 INSTIT%TE O& ENGINEERING ' TECHNOLOG
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< IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
1. Connect te circuit as son in te diagram.$. Connect te out%ut o0 ladder to te in%ut o0 o%-am% {,1 #*. )bser6e te out%ut o0 o%-am% {,1 it DMM.,. 'or eac 6alue o0 in%ut 6ariation measure te out%ut 6oltage it DMM and tabulate
te 6alues.x. o remo6e DMM and obser6e te out%ut on CR).z. Cec! eter te out%ut o0 am%li0ier is a staircase a6e0orm.RES%LT: )%eration o0 digital to analog con6erter is 6eri0ied.INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK k?SF NO?k ?JGK
<
IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II PROCE)%RE:
1. Connect te circuit as son in te diagram.$. Connect te out%ut o0 ladder to te in%ut o0 o%-am% {,1 #
*. )bser6e te out%ut o0 o%-am% {,1 it DMM.,. 'or eac 6alue o0 in%ut 6ariation measure te out%ut 6oltage it DMM and tabulatete 6alues.
x. o remo6e DMM and obser6e te out%ut on CR).z. Cec! eter te out%ut o0 am%li0ier is a staircase a6e0orm.RES%LT: )%eration o0 digital to analog con6erter is 6eri0ied.INSTIT%TE O& ENGINEERING ' TECHNOLOG
1 ;<<-< =-$ >?@A B >F GHAJK NOGQSF TUW XYZ GA[\: [] ^_` GA f ThjK
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k?SF NO?k ?JGK