“i-v characteristics of a static random access memory cell
TRANSCRIPT
“I-V Characteristics of a Static Random Access Memory Cell
Utilizing Ferroelectric Transistors”
Crystal Laws, Cody Mitchell, Mitchell Hunt, Todd C. MacLeod, and Fat D. Ho
Presenting Author: Todd C. MacLeodInternational Symposium on Integrated Functionalities
2012 ConferenceJune 21, 2012
Introduction• SRAM utilizing Ferroelectric FETs may make high speed
memory possible with significant retention times without power (Retention times of 24 hours have been measured)
• Ferroelectric Field-Effect Transistor features polarization due to the ferroelectric layer between the substrate and the gate.
• After removal of the applied input voltage, the polarization still exists, thus the FeFET features unique I-V characteristics
• Current-Voltage (I-V) Characteristics Presented– FeFET– Resistive Load Static Random Access Memory (SRAM) Cell
• I-V FeFET Model Developed • Comparison
– Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and FeFET C. Laws et al. 2
FeFET Properties
• Ferroelectrics feature properties including– Polarization
• Positive and Negative – Hysteresis
• History dependence– Nonlinearity
• The ferroelectric layer gives FeFET unique I-V characteristics – Unlike the MOSFET, the I-V characteristics feature a
hysteresis trend
C. Laws et al. 3
FeFET I-V Characterization
• Ferroelectric Transistor was 10 µm wide and 10 µm long, provided by Radiant Technologies Inc.
• FeFET featured a PZT ferroelectric layer
• FeFET active current was measured with test circuit, shown left
• PZT ferroelectric layer was properly polarized
• The drain-to-source voltage (VDS) was varied for a range of gate-to-source voltages (VGS) and the drain current was measured
C. Laws et al. 4
ND1 Active Current for Various VDS
0.00E+00
5.00E‐06
1.00E‐05
1.50E‐05
2.00E‐05
2.50E‐05
3.00E‐05
3.50E‐05
4.00E‐05
4.50E‐05
5.00E‐05
‐8 ‐6 ‐4 ‐2 0 2 4 6 8
Act
ive
Cur
rent
(A)
Gate Voltage (V)
VDS = 1V
VDS =2 V
VDS = 3 V
VDS = 4V
VDS = 5 V
C. Laws et al. 5
SRAM Cell Operation
• A traditional resistive load SRAM cell was constructed as shown on the left
• The input voltage, Vin, is applied at drain of T1 and the output voltage , Vout, is read at drain of T2
• A couple different configurations were investigated– FeFETs for T1 and T2
– Various resistance values with FeFETs for T1 and T2
C. Laws et al. 6
ND1 SRAM I-V Characteristics at a Load Resistance of 51 kΩ
C. Laws et al. 7
0
5
10
15
20
25
30
‐0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Dra
in C
urre
nt (µ
A)
Gate Voltage (V)
ND1 SRAM I-V Characteristics at a Load Resistance of 105 kΩ
C. Laws et al. 8
0
5
10
15
20
25
‐0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Dra
in C
urre
nt (µ
A)
Gate Voltage (V)
ND1 SRAM I-V Characteristics at a Load Resistance of 275 kΩ
C. Laws et al. 9
0
2
4
6
8
10
12
‐0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Dra
in C
urre
nt (µ
A)
Gate Voltage (V)
ND1 SRAM I-V Comparison Chart
C. Laws et al. 10
0
5
10
15
20
25
30
‐0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Dra
in C
urre
nt (µ
A)
Gate Voltage (V)
R=100kΩ
R=275kΩ
R=50kΩ
Conclusion
• I-V characteristics for FeFET different than that of MOSFET• Ferroelectric layer features hysteresis trend whereas
MOSFET behaves same for both increasing and decreasing V GS
• FeFET I-V characteristics doesn’t show dependence on V DS
• A Transistor with different channel length and width as well as various resistance and input voltages give different results• As resistance values increased, the magnitude of the drain
current decreasedC. Laws et al. 11
References
1. C. Mitchell, C. L. McCartney, T. C. MacLeod, F. D. Ho, Characteristics of a Nonvolatile SRAM Cell Utilizing a Ferroelectric Transistor, Integrated Ferroelectrics, 132, 82-87 (2012).
2. A. K. Singh, Digital VLSI Design, New Delhi: Prentice Hall of India, 2011. 3. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,
New York: McGraw Hill, 2003.4. A. Pittet and A. Kandaswamy, Analog Electronics, New Delhi: Prentice Hall of India,
2005.5. J. Evans, Modeling Radiant Thin Ferroelectric Film Transistors, Radiant
Technologies Inc, 2011.6. T. C. MacLeod and F. D. Ho, I-V Characteristics of a Ferroelectric Field-Effect
Transistor, Integrated Ferroelectrics, 34, 21-26 (2001).7. Giuseppe Grosso and Giuseppe Pastori Parravicini, "Solid State Physics", 2nd ed. San
Diego: Academic Press, 2000.8. T. A. Phillips, T. C. MacLeod, F. D. Ho, Modeling of a Ferroelectric Field-Effect
Transistor Static Random Access Memory Cell. Integrated Ferroelectrics 96, 69-74 (2008).
C. Laws et al. 12
Acknowledgements
• University of Alabama in Huntsville for their support as well as providing the facilities to conduct the research
• Joe Evans and Radiant Technologies for supplying the transistors for the research
• NASA for providing some of the test equipment and lab facilities used for the research
C. Laws et al. 13