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IC Design/ Methodology Training-Overview

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•PD/Back-end

•-SemiTracks (Manufacturing training)•-Product Engg•-Reliability/FA•-Packaging…

•-RTL•-Synthesis

•-AnalogCircuitdesign

•-DV (systemVerilog, systemC)

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12/2/2010 catalyteIC 18

Custom Design Flow- Default To PowerTraining Manual

July 15, 2009Catalyte IC Design

1912/2/2010

Advanced Topics

Quantify Layout Utilization (QLU)Parasitic Extraction Validation Flow

QRC Techfile generation- 6lm/7lm/8lm, min/nom/max, TC0/TC25.. (7d -> 1d -> 6 hr)LVS deck (10k line -> 1k -> 50 line)LVS deck (Options/ Switches)Speed up DRC (deck split, design split, multi-CPU, LSF)spice- 1_page_viewParasitic extraction- 1_page_view

2012/2/2010 CatalyteIC 20

QLU Illustration- Area used by various devices inside module mod_analog

Area consumed by each types of devices

0102030405060708090

100

1

Device category

Are

a

NCH_RF

PCH_RF

NCH_TYPE_1

PCH_TYPE_1

NCH

PCH

DENMOS

DEPMOS

CAP_HV

CAP_LV

FLUXCAP

VARACTOR

• Overall utilization of area by different categories of devices

• DENMOS consumed most spaces for mod_analog

Area utilization by device category NCH_RF

PCH_RF

NCH_TYPE_1

PCH_TYPE_1

NCH

PCH

DENMOS

DEPMOS

CAP_HV

CAP_LV

FLUXCAP

VARACTOR

2112/2/2010 co@CatalyteIC

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Parasitic Extraction Validation Flow

•Option

•File•ext2Si_val

•Design input

•-Laff/cds.lib

•-pinFile

•-simulation testBench

•PDK input

•-lvs deck

•-rcx deck

•-spice model

•Parasitic simulation results

•DataWare•Silicon data

•-lot, wafer, parameters

•Measured data

•Inside Excel (Manual)

p7mncapv1a(BEOL): nomC- silicon, RCX, FS, startXt

0.00E+005.00E+011.00E+021.50E+022.00E+022.50E+023.00E+023.50E+024.00E+02

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DUTs

Cap

(fF)

si_nom rcx_nom FS_nom starXt

2212/2/2010

ext2Si_val

•Run LVS

•Run

RCX

•Parasitic

simulation

•Check input

•Create RSF

•Create Netlist

•Build Table

•Option File

•Exit if any invalid input

•module.rsf

•-layout

•-pinFile•-NO schematic

•-rcx.module.rsf

•-lvs output

•av_ext view

•Simulation netlist

•-testBench

•-RCX netList

•Simulation results

•-cap/res

2312/2/2010

Function Cadence Synopsys Mentor Magma IDM1 IDM2 Comments

Schematic Composer Galaxy - - - - -

Circuit simulation

spectre Hspice - - Powerspice

Spectre -

Fast Spice ultra-sim Nano-sim - finesim - - -

Layout (Manual)

VLE Galaxy IC-Station

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Automated custom layout

VXL,VCPVCR

Orion - - - - Laker

Physical Verification-DRC-LVS-ERC

Assura(PVS,Dracula, Diva, Vampire)

Hercules Calibre Quartz DRC/LVS

Niagara HerculesK2 (GV,SV)

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Parasitic Extraction(R, C, L, K)

QRC(RCX)

Star-RCXT

Xcalibre Quartz RC

Erie QRCStar-RCXT

-Raphael,QuickCap

Database

Tapeout - - - - RIT PG

Layout DB DFII/OA Milkyway - Volcano

DFM LPALEA

LCCCMP

-LFDyieldEnhancer

Yield-Analyzer

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•EDA Tools/Terminology- Simplified