ieee 1394 interface mn8644002 - panasonic...1394 interface to be provided for data storage devices...
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IEEE 1394 Interface
1
MN8644002SBP-2 IEEE 1394 IC
OverviewThe MN8644002 is a single-chip physical and link layer controller IC that conforms to the IEEE 1394-1995 serial
bus standard and includes on-chip protocol control circuits that conforms to the SBP2 standard. This IC allows an IEEE1394 interface to be provided for data storage devices such as DVD ROM/RAM drives, CD-ROM drives, and hard diskdrives.
Features• Conforms to the IEEE 1394-1995 serial bus standard.• Data transfer rate
Supports S100/S200Supports up to S400 with the use of an external physical layer circuit.
• Number of ports: 1 port• SBP2 conformance
High-speed transfers based on hardware data transfer processingReduced firmware overhead achieved by the use of hardware page table processing.
• Dedicated to asynchronous data transfersAsynchronous transmit FIFO: 48 4-byte wordsAsynchronous receive FIFO: 48 4-byte wordsData transmit/receive FIFO: 4 128 bytes (1 032 4-byte words)
• System controller interfaceAddress bus: 8 bits, data bus: 8 bitsSupports separate mode for address and data
• 16-bit transfer data interfaceSupports DMA burst transfer mode
Applications• IEEE 1394 interface with link and physical layers that support the SBP2 protocol.Main
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MN8644002 IEEE 1394 Interface
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Block Diagram
SY
S_M
OD
E[2
: 0]
SY
S_D
[7 :
0]
SY
S_A
[7 :
0]
SY
S_N
WE
SY
S_N
RE
SY
S_N
CS
SY
S_W
AIT
SY
S_A
LE
SY
S_I
NT
MCU interface Interruptcontrol
Register
Rxfilter
PHYTEST
LINKCORE
DM
A in
terf
ace
PHY
SYSCLK
PHYTEST[1 : 0]
LREQ
PCTL[1 : 0]
PHYDATA[7 : 0]
PC
[2 :
0]
CM
C
PH
YR
ES
ET
XO XI
DIR
EC
T
FIL
TE
R
CP
S
PD
LPS
R1
R0
CN
A
NT
PB
TP
B
NT
PA
TP
A
TP
BIA
S
TE
ST
M2
TE
ST
M1
LINKRESET
DD[15 : 0]
NIOWR
NIORE
RAMTEST
MINTEST
SCANTEST
DMARQDATAFIFO
Timer
Engine
DTRF
ARF
ATF
Txfilter
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IEEE 1394 Interface MN8644002
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Pin Arrangement
888990919293949596
565758596061626364
TP
A1
81T
PB
IAS
182
N.C
.83
AVS
S84
AVD
D85
PLL
VS
S86
PH
YV
ER
87F
ILT
ER
AVD
DX
OX
IP
LLV
DD
R0
R1
AVS
SN
STA
ND
BY
NT
PA
180
TP
B1
79N
TP
B1
78AV
SS
77N
.C.
76N
.C.
75N
.C.
74N
.C.
73AV
SS
72C
NA
71P
C2
70P
C1
69P
C0
68C
MC
67AV
DD
DD
11D
D10
DD
9D
D8
DV
SS
DD
7D
D6
DD
5D
D4
VR
EF
OD
CD
D3
DD
2D
D1
DD
0D
VS
SLD
VD
D
VR
EF
OD
CD
D12
DD
13D
D14
DD
15D
VS
SN
IOR
DN
IOW
RD
MA
RQ
TE
ST
IOV
RE
FO
DC
66
987654321 16151413121110 17 18 19 20 21 22 23 24 25 26 27
AVS
S
DV
SS
LDV
DD
LIN
KN
RS
TS
CA
NT
ES
TM
INT
ES
T65
28 29 30 31 32
PHYDATA049PHYDATA150DVSS51PHYDATA252PHYDATA353PDVDD54PHYDATA455PHYDATA5DVSSPHYDATA6PHYDATA7PDVDDSYSCLKDVSSPDCPS
PDVDD48PCTL047PCTL146DVSS45PHYNRST44LPS43LREQ42NISO41TESTM240
3938373635
TESTM1PDVDDPHYTEST1PHYTEST0TESTDVSSDIRECT
SYS_D7SYS_D6SYS_D5SYS_D4
VREFSYSSYS_D3SYS_D2SYS_D1SYS_D0
SYS_INTLDVDD
DVSS
SYS_MODE2SYS_MODE1SYS_MODE0
SYS_NWESYS_ALE
DVSS
VREFSYSSYS_A0SYS_A1SYS_A2SYS_A3
DVSSSYS_A4SYS_A5SYS_A6SYS_A7
VREFSYSSYS_NCSSYS_NRE 34
105104103102101100999897
112111110109108107106
113114115116117118119120121122123124125126127
SYS_WAIT 33128Mainten
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MN8644002 IEEE 1394 Interface
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Pin Functions
Pin No. Pin name I/O Function Notes
System controller interface (25 pins)
99 SYS_INT O Interrupt output to the system controller Active Low
SYS_A[7 : 0]*1 I Address inputs from the system controller in separateaddress and data mode
SYS_D[7 : 0]*1 I/O In separate address and data mode: data I/O to thesystem controller
In shared address and data mode: time division multi-
plexed address and data I/O to the system controller.
111 SYS_NWE I Write enable signal input from the system controller Active Low
127 SYS_NRE I Read enable signal input from the system controller Active Low
126 SYS_NCS I Chip select signal input from the system controller Active Low
128 SYS_WAIT O Signal output used to extend the external memory Active Lowaccess period when handshaking with external memory.
110 SYS_ALE I ALE signal input from the system controller in shared Fix Lowaddress and data mode
112 SYS_MODE0 I System controller interface mode 0 Fix High
113 SYS_MODE1 I System controller interface mode 1 Fix High
114 SYS_MODE2 I System controller interface mode 2 Fix Low
VREFSYS × 3 I Reference voltage (3 V or 5 V) used by the system controller interface
ODC DMA interface (19 pins)
DD[15 : 0] I/O Bidirectional data bus
24 NIORD I Read strobe signal input from the DMA interface Active Low
23 NIOWR I Write strobe signal input from the DMA interface Active Low
25 DMARQ O DMA transfer request signal output Active High
VREFODC ×3 I Reference voltage (3 V or 5 V) used by the ODC interface
Link test related (4 pins)
31 SCANTEN I Scan test mode setup input Fix Low
32 MINTEST I ASIC test input Fix Low
35 TEST I Test control Fix Low
26 TESTIO I/O Test I/O Open
Link interface (3 pins)
96 NSTANDBY I Internal link standby signal (0: Link stop, 1: link on)
33 DIRECT I Internal link isolation mode switching Fix High
30 LINKNRST I Internal link reset input Active Low
Note) *1: For the bus, 0 is the LSB
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IEEE 1394 Interface MN8644002
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Pin Functions (continued)
Pin No. Pin name I/O Function Notes
Interface between physical layer and link layer (13 pins)
PHYDATA I/O Data I/O between the internal link layer and the[7 : 0] external physical layer when an external physical layer
is used. (In monitor mode, monitoring the data between
the internal link layer and the internal physical layer.)
PCTL[1 : 0] I/O Control I/O between the internal link layer and theexternal physical layer when an external physical layer is
used. (In monitor mode, monitoring the control layer
between the internal link layer and the internal
physical layer.)
LREQ I/O LREQ signal I/O between the physicallayer and the link layer.
When the link layer is connected to an external
physical layer: output
When the physical layer is connected to an external
link layer: input
Other modes (e.g. monitoring): output
36 PHYTEST0 I Physical to link interface mode switching PHYTEST0 PHYTEST1
0 0 : Normal physical + link mode
37 PHYTEST1 0 1 :Link to external physical connection 1 0 :Physical to external link connection
1 1 : Monitoring mode
Physical 1394 cable interface (5 pins)
82 TPBIAS1 O Port1 TPBIAS
81 TPA1 I/O Port1 TPA
80 NTPA1 I/O Port1 NTPA
79 TPB1 I/O Port1 TPB
78 NTPB1 I/O Port1 NTPB
Link, ODC interface, and system controller interface power supplies (11 pins)
LVDD ×3 I Digital system VDD (3 V). Used for the link layer.
DVSS ×8 I Digital system ground
Physical layer power (18 pins)
AVDD ×3 I Analog system VDD
AVSS ×5 I Analog system ground
PDVDD ×4 I Digital system VDD(3 V)
DVSS ×4 I Digital system ground
PLLVDD I PLL VDD Provide power supplyon using external
physical layer
PLLGND I PLL GND
OPEN (On using
internal physical layer)
OPEN (On using
internal physical layer)
OPEN (On using
internal physical layer)Mainten
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MN8644002 IEEE 1394 Interface
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Pin Functions (continued)
Pin No. Pin name I/O FunctionNotes (on using internal
physical layer)
Physical layer and other pins (19 pins)
61 SYSCLK I/O 49.152 MHz clock
93 R0 External resistor (5.9 kΩ, tolerance: ±2%)
94 R1 External resistor (5.9 kΩ, tolerance: ±2%)
43 LPS I Link power status Fix High(See the IEEE 1394-1995 standard, section 4.3.4.1,
Self-ID Packet.)
63 PD I Power down: Internal functions are stopped when a Fix Low*2
high level is applied.
64 CPS I Cable power status: resistor (400 Ω, tolerance: ±10%) Fix High
71 CNA O Cable not active: A high level is output when no ports are connected to active ports. This output level
remains fixed during normal operation.
88 FILTER I/O External capacitor for the PLL circuit (open)
44 PHYNRST I Internal physical layer reset input Fix High
39 TESTM1 I Internal physical layer test mode setting 1 Fix High
40 TESTM2 I Internal physical layer test mode setting 2 Fix High
87 PHYVER O Internal physical layer version signal (currently unused)
90 XI I External oscillator element 25 MHz input
91 XO O External oscillator element 25 MHz output
41 NISO I Internal physical layer isolation setting Fix High(Low: isolation mode)
67 CMC I/O Configuration manager capable input or link-on output Fix Low(See the IEEE 1394-1995 standard, section 4.3.4.1,
Self-ID Packet.)
68 PC0 I/O Power class Any value69 PC1 I/O (See the IEEE 1394-1995 standard, section 4.3.4.1,
70 PC2 I/O Self-ID Packet.)
Note) *2: Hold this pin fixed at the high level if an external physical layer is used.
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IEEE 1394 Interface MN8644002
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Electrical Characteristics1. Absolute Maximum Ratings at VSS = 0 V
Parameter Symbol Rating Unit
Supply voltage VDD − 0.3 to +4.6 V
5 V reference voltage Vref5 − 0.3 to +5.7 V
Input Normal pins VI − 0.3 to VDD+0.3 V
voltage 5 V pins VI5 − 0.3 to +6.0 V
Output Normal pins VO − 0.3 to VDD+0.3 V
voltage Open-drain cells VO5 − 0.3 to 6.0 V
5 V pins − 0.3 to Vref5+0.3 V
Output current (Type HL4 pins) IO ±12 mA
Output current (Type HL8 pins) IO ±24 mA
Output current (Type HL16 pins) IO ±48 mA
Power dissipation PD 1.05 mW
Operating temperature Topr −40 to +70 °C
Storage temperature Tstg −55 to +150 °C
Type HL4 pins: DD0 to DD15, NIORD, NIOWR, DMARQ, TESTIO, SYS_INT, SYS_D0 to SYS_D7,
SYS_ALE, SYS_NWE, MODE0 to MODE2, SYS_A0 to SYS_A7, SYS_NCS, SYS_NRE,
SYS_WAIT
Type HL8 pins: PHYVER, LREQ, SYSCLK, CMC, PC0, PC1, CNA
Type HL16 pins: PCTL0, PCTL1, PHYDATA0 to PHYDATA7
Note) 1. The absolute maximum ratings are limiting values for applied stresses below which the chip will not be destroyed.
Operation is not guaranteed within these ranges.
2. All VDD pins (LDVDD, PDVDD, AVDD, and PLLVDD) and all VSS pins must be connected directly to external power supply
or ground, respectively.Mainten
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MN8644002 IEEE 1394 Interface
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Electrical Characteristics (continued)2. Recommended Operating Conditions
Parameter Symbol Conditions Min Typ Max Unit
Supply voltage LDVDD 3.0 3.3 3.6 V
PDVDD 3.0 3.3 3.6 V
AVDD 3.0 3.3 3.6 V
PLLVDD 3.0 3.3 3.6 V
5 V reference voltage VREFODC 4.75 5.0 5.25 V
VREFSYS 4.75 5.0 5.25 V
Ambient temperature Ta 0 70 °C
Input rise time tr 0 4 ns
Input fall time tf 0 4 ns
Oscillator frequency fOSC1 24.576 MHz Xtal 24.576 MHz
Recommended external CXI VDD = 3.3 V 33 pF
capacitor values CXO The feedback resistor is built in. 33
Note) 1. Since the oscillator characteristics differ depending on the type of the oscillator element, external capacitors, and other
conditions, we recommend consulting the oscillator element manufacturer to determine appropriate oscillator circuit
element values and conditions.
2. AVDD and PLLVDD must be the same.
XIXO
CXI
CXO
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IEEE 1394 Interface MN8644002
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Parameter Symbol Conditions Min Typ Max Unit
Operating LINK IDD0 VI = VDD or VSS 134 mAsupply current VI5 = 5.0 V or VSS
PHY_Digital IDD1 f = 50 MHz 30 mA
VDD = 3.3 V,
PHY_Analog IDD2 Vref5 = 5.0 V 40 mA
Outputs open
Oscillator circuit: XO
Internal feedback resistor Rf7 VI = VDD or VSS 313 940 2820 kΩVDD = 3.3 V
Input pins
CMOS level inputs: SCANTEST, DIRECT, TEST, PHYTEST0, PHYTEST1, TESTM0, TESTM1, NISO
High-level input voltage VIH VDD × 0.8 VDD V
Low-level input voltage VIL 0 VDD × 0.2 V
Input leakage current ILI VI = VDD or VSS −5 +5 µA
Input pins
CMOS level inputs with internal pull-down resistors: MINTEST
High-level input voltage VIH VDD × 0.8 VDD V
Low-level input voltage VIL 0 VDD × 0.2 V
Pull-down resistor RIL VI = VDD 10 30 90 kΩ
Input leakage current ILIPD VI = VSS −10 +10 µA
Input pins
LVTTL level inputs: PD
High-level input voltage VIH 2.0 VDD V
Low-level input voltage VIL 0 0.8 V
Input leakage current ILI VI = VSS −5 +5 µA
Input pins
5 V TTL level inputs: LINKNRST, LPS, PHYNRST, NSTANBY
High-level input voltage VIH 2.0 5.25 V
Low-level input voltage VIL 0 0.8 V
Input leakage current ILI5 VI = VSS −10 +10 µA
Output pins
N-channel open-drain outputs: SYS_WAIT
Low-level output voltage VOL IOL = 4.0 mA 0.4 VVI = VDD or VSS
Output leakage current IOZ5 VO5 = High-impedance state −10 +10 µAVO5 = 5.25 V or VSS
Electrical Characteristics (continued)
3. DC Characteristics
VDD = 3.0 V to 3.6 V, VSS = 0.00 V, fTEST = 50 MHz, Ta = 0°C to 70°C
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MN8644002 IEEE 1394 Interface
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Electrical Characteristics (continued)
3. DC Characteristics (continued)
VDD = 3.0 V to 3.6 V, VSS = 0.00 V, fTEST = 50 MHz, Ta = 0°C to 70°C
Parameter Symbol Conditions Min Typ Max Unit
I/O pins
CMOS level I/O: SYSCLK
High-level input voltage VIH VDD × 0.8 VDD V
Low-level input voltage VIL 0 VDD × 0.2 V
High-level output voltage VOH IOH = −8.0 mA VDD − 0.6 VVI = VDD or VSS
Low-level output voltage VOL IOL = 8.0 mA 0.4 VVI = VDD or VSS
Output leakage current IOZ VO = High-impedance state −5 +5 µAVI = VDD or VSS
VO = VDD or VSS
I/O pins
TTL level I/O: PHYVER, LREQ, CMC, PC0 to PC2, CNA
High-level input voltage VIH 2.0 VDD V
Low-level input voltage VIL 0 0.8 V
High-level output voltage VOH IOH = −8.0 mA 2.4 VVI = VDD or VSS
Low-level output voltage VOL IOL = 8.0 mA 0.4 VVI = VDD or VSS
Output leakage current IOZ VO = High-impedance state −5 +5 µAVI = VDD or VSS
VO = VDD or VSS
I/O pins
TTL level I/O: PCTL0, PCTL1, PHYDATA0 to PHYDATA7
High-level input voltage VIH 2.0 VDD V
Low-level input voltage VIL 0 0.8 V
High-level output voltage VOH IOH = −16.0 mA 2.4 VVI = VDD or VSS
Low-level output voltage VOL IOL = 16.0 mA 0.4 VVI = VDD or VSS
Output leakage current IOZ VO = High-impedance state −5 +5 µAVI = VDD or VSS
VO = VDD or VSS
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IEEE 1394 Interface MN8644002
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Electrical Characteristics (continued)3. DC Characteristics (continued)
VDD = 3.0 V to 3.6 V, VSS = 0.00 V, fTEST = 50 MHz, Ta = 0°C to 70°C
Parameter Symbol Conditions Min Typ Max Unit
I/O pins
TTL 5 V level and CMOS level I/O: DD0 to DD15, NIORD, NIOWR, DMARQ, DMAACK, SYS_INT, SYS_D0 to
SYS_ D7, SYS_ALE, SYS_NWE, MODE0 to MODE2, SYS_A0 to SYS_A7, SYS_NCS, SYS_NRE
High-level input voltage VIH 2.0 Vref5 V
Low-level input voltage VIL 0 0.8 V
High-level output voltage VOH IOH = −4.0 mA 2.4 VVI = VDD or VSS
Low-level output voltage VOL IOL = 4.0 mA 0.4 VVI = VDD or VSS
Output leakage current IOZ5 VO5 = High-impedance state −10 +10 µAVO5 = 5.25V or VSS
Physical layer block
Differential input voltage VID−100 Cable input (S100) 142 260 mV
Differential input voltage VID−200 Cable input (S200) 132 260 mV
Differential input voltage VID−ARB Cable input 171 262 mV(during arbitration)
TPBIAS output voltage VCMA 1.665 2.015 V
Differential output voltage VDO 172 265 mV
TPBIAS output current ICMA 4.84 mA
Speed signal output current ISS−200 During S200 transmission 2.52 4.84 mA
Speed signal input current ISS−200 During S200 reception 1.62 5.06 mA
Differential input voltage VIH+ Cable input "1" 89 168 mV(during arbitration)
Differential input voltage VIL− Cable input "0" −168 −89 mV(during arbitration)
4. AC Characteristics
Parameter Symbol Conditions Min Typ Max Unit
SYSCLK
Clock Period tcyc 49.152 MHz
waveform Clock duty dclk 50 %
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MN8644002 IEEE 1394 Interface
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twRD
trdrd
thdDD
tvDD
DD[15 : 0]Valid data Valid data Valid data
NIORD
DMARQ
trdrq
thd
VDD/2
thi
VclkVclk/2
tcyc
tsu
Input data
Clock
Output data
tod
VDD/2
dclk = thi/tcyc × 100
Electrical Characteristics (continued)4. AC Characteristics (continued)
Figure 1 I/O Timing
Timing Charts1. DMA Interface
1) Read Operation (Data: SBP2 → ODC)
Parameter Symbol Min Max Unit
DMARQ negate time trdrq 25 ns
DMARQ assert time trdrd 0 ns
NIORD "L" level pulsed width twRD 29 ns
Data output defined time tvDD 20 ns
Data output hold time thdDD 10 ns
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IEEE 1394 Interface MN8644002
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Timing Charts (continued)1. DMA Interface (continued)
1) Read Operation (Data: SBP2 → ODC) (continued)
t
DMARQ
NIORD
• When the IC applies a wait, the minimum negation period of DMARQ is t = 0 s.
2) Write Operation (Data: ODC → SBP2)
Parameter Symbol Min Max Unit
DMARQ negate time twrrq 25 ns
DMARQ assert time twrrd 0 ns
NIOWR "L" level pulsed width twWD 29 ns
Input data set up time tsuDD 10 ns
Input data hold time thdDD 10 ns
twWD
twrrd
thdDD
t
tsuDD
DD[15 : 0]Data Data Data
NIOWD
DMARQ
twrrq
DMARQ
NIOWD
• When the IC applies a wait, the minimum negation period of DMARQ is t = 0 s.
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MN8644002 IEEE 1394 Interface
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Timing Charts (continued)1. DMA Interface (continued)
3) Data register access cycle time
4) DMA Interface Direction Control
After a reset: input
From Rx start to data transfer completion: output
All other times: input
Parameter Symbol Min Max Unit Notes
Data register access cycle time (NIORD) tdcy_RD 58 ns Amount of data transferred:
64 Kbytes or less
91 ns Amount of data transferred:
64 Kbytes or more
Data register access cycle time (NIOWR) tdcy_WR 58 ns
Fall time (NIORD/NIOWR) td 10 ns
NIORD/NIOWR
tdcy
td
DD[15 : 0]OUTPUT
NIORD
OUTPUT
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IEEE 1394 Interface MN8644002
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Timing Charts (continued)2. External physical layer interface
Parameter Symbol Min Max Unit
SETUP(SYSYCLK → PHYDATA[3 : 0]) Tsu1 6.0 ns
SETUP(SYSYCLK → PCTL[1 : 0]) Tsu2 6.0 ns
HOLD(SYSYCLK → PHYDATA[3 : 0]) Thd1 6.0 ns
HOLD(SYSYCLK → PCTL[1 : 0]) Thd2 6.0 ns
SYSCLK
PHYDATA[3 : 0] Valid Valid
Tc1Tsu1
PCTL[1 : 0] Valid
PHY input from LINK
Valid
Tsu2
SYSCLK
PHYDATA[3 : 0] Valid Valid
Thd1
PCTL[1 : 0] Valid
PHY output to LINK
Valid
Thd2
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ance/
Discon
tinued
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ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
MN8644002 IEEE 1394 Interface
16
MCU(MN10200 Series)
MN8644002
SYSIF
ODC
DD[15 : 0]
[7 : 0]
NIOWRNIORD
DMARQ
DD[15 : 0]NIOWRNIORDDMARQ
NW
RN
RD
CP
UD
T[7
: 0]
CP
UA
DR
[17
: 0]
NC
SN
WA
ITO
DC
NIN
T[1
: 0]
NM
RS
TC
LKO
UT
1
MINI0300CORE MCU I/F
SY
S_M
OD
E1
SY
S_M
OD
E0
SY
S_I
NT
SY
S_W
AIT
SY
S_N
CS
SY
S_A
[7 :
0]S
YS
_D[7
: 0]
SY
S_N
RD
SY
S_N
WE
SY
S_M
OD
E2
Register
DM
A I/
F
DM
Aco
ntro
ller
[7 : 0]
[7 : 0]
Sample Application Systems• Separate address and data, 8-bit bus, and handshaking mode system
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
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four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
IEEE 1394 Interface MN8644002
17
Package Dimensions (Units: mm)• LQFP128-P-1818C
18.00±0.1096 65
1 32
64
33
97
128
20.00±0.20
(1.00)
0.50±0.200° to 10°
0.15
±0.0
5
18.0
0±0.
1020
.00±
0.20
1.70
max
0.10
±0.1
01.
40±0
.10
(1.2
5)
(1.25) 0.50 0.20±0.050.10 M
Seating plane0.10
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
Request for your special attention and precautions in using the technical information andsemiconductors described in this book
(1)If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2)The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book.
(3)The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support
systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod-ucts may directly jeopardize life or harm the human body. Any applications other than the standard applications intended.
(4)The products and product specifications described in this book are subject to change without notice for modification and/or im-provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements.
(5)When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6)Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7)This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)