MOSFET Technology as a Key for High PowerDensity Converters

Lutz Görgens, Ralf Siemieniec and Juan Miguel Martinez SanchezInfineon Technologies Austria AG, Villach, Austria

Abstract— The rapidly increasing computation-capability,data-density and functionality of electronic systems are thedriving forces for high-efficiency high power-density con-verters. Electronic systems are continuously increasing thedemand for power, while simultaneously available space andcooling capability stays constant. This requires smaller formfactors of the individual converter, higher efficiencies andhigher output powers. To meet these demands, new powerarchitectures, new converter-topologies and new MOSFETtechnologies are developed. In this paper we will reviewthe basic operational modes for low-voltage semiconductorsand mirror the resulting requirements with the capabilitiesof recent MOSFET technology developments.

I. INTRODUCTION

Even though the power-consumption of the individualfunctions or processes of an electronic system is de-creasing continuously, the power demand of the overallsystem is still growing. The complexity of electronicsystems outgrows the power-reduction of the individualfunctions. Telecommunication and data-networking sys-tems face exponentially growing data-volumes that needto be relayed and stored. Additionally, to process all thisdata, more capable computing systems are required. Otherelectronic systems show similar developments. Increasedfunctionality leads to higher power consumption. In afew years drive-by-wire systems, including electronicpower steering, power breaking and improved monitoringfunctions, i.e. tyre-pressure monitoring will be standard.In contradiction to this increase in power requirementstands the need for energy saving and limited space.

This challenge is met in several ways: new power-architectures as i.e. the IBA (intermediate bus archi-tecture) in telecom and data-networking systems arereducing losses on system level. Improving converter-level efficiency is usually realised by more complex andmore efficient topologies for AC/DC power-supplies andDC/DC converters. Now, new MOSFET technologies areavailable that allow the design of converters with higherpower-density and efficiency. In this paper we will focuson n-channel enhancement MOSFET technologies in therange of 20 V to 150 V. We review the requirementsfor new low-voltage MOSFET technologies according totheir different functions in power-conversion systems. Weevaluate the requirements for switches in isolated andnon-isolated converters, power-switches in or-ing circuitsand MOSFETs in synchronous rectification.

II. MOSFET OPERATION MODES

In the following, we will focus on the operation modesthat apply to the applications stated above. In all of those,the MOSFETs will be operated as switches. Operationin the linear region and its effects will be neglected. Forcontinuous conduction three states are important: forwardconduction (device fully turned on, current flowing fromdrain to source), reverse conduction (device fully turnedon, current flowing from source to drain) and diode-conduction (body diode active). Equally important are thetransitions from the conduction states to the off-state andvice versa.

MOSFETs in forward and reverse conduction modecan be modelled by their RDSon. The calculation ofthe respective losses is simple. However, for a giventechnology, the RDSon is linked to the Rth and Zth of thedevice. Combined with effects of packaging and cooling-concepts, the RDSon is the key-parameter of a MOSFETtechnology under static conditions. In opposite, the un-derstanding of the behaviour and loss-generation under

Fig. 1. Functional circuits of a buck-converter and a half-bridgeconverter with synchronous rectification. A,B,C mark the passes ofcurrent change during switching

1-4244-0121-6/06/$20.00 ©2006 IEEE EPE-PEMC 2006, Portorož, Slovenia1968

TABLE IMAIN APPLICATIONS FOR LOW VOLTAGE MOSFETS IN THE RANGE FROM 20 V TO 150 V

“+/0/-” INDICATE APPLICATIONS THAT ARE TYPICAL/SUITABLE/RARE

buck/boost control buck/boost sync. isol. DC/DC and prim. side switch isol. AC/DC and DC/DC sync. rect. power switch20 V + + - + +30 V + + - + +40 V + + 0 + -60 V 0 0 0 + 080 V 0 - + + +100 V 0 - + + +150 V - - + 0 -

transition proves to be difficult. The MOSFET interactswith the surrounding circuitry. Switching behaviour andlosses depend on MOSFET parameters as well as onthe circuit. This interaction results in different MOSFETrequirements for every type of transition. Additionally notonly the steady states of the MOSFETs are important butequally the way how the transition is controlled by theexternal circuit.

In the following, we will discuss which operationmodes are relevant in the application and what are therespective key parameters of the MOSFET. The findingsare then compared with recent MOSFET developmentsfor typical voltage classes.

Low voltage MOSFETs are used in a wide varietyof applications. Applications range from dc-brush andbrushless-dc motor-control over power-switches for powerdistribution to AC/DC and DC/DC SMPS. A volumegrowth of 10% worldwide is predicted for these devices[1]. The majority of the MOSFETs are used in power-management and power-supply applications. In this paper,we will focus on the requirements and possibilities of thebasic applications of low-voltage switches: non-isolatedand isolated dc/dc conversion, synchronous rectificationin AC/DC switched mode power-supplies (SMPS) andpower-switches as listed in Tab. I. The five applicationslisted in Tab. I can be further grouped according to thethree basic functions mentioned earlier. Power switchesare mainly characterised by their forward conductioncapability, including thermal aspects. Synchronous recti-fying switches and synchronous MOSFETs in buck/boostconverters act as switched active diodes and primary sideswitches in isolated converters as well as the controlMOSFETs of the buck/boost converters act as controlMOSFETs. Functional circuits of the latter two applica-tions are shown in Fig. 1.

A. Power Switches

Power switches are used to protect areas of the circuitryor for power distribution to turn parts of the power systemon and off. Devices are selected either to achieve targetefficiencies or to stay within the limits of the junctiontemperature Tj . In case the devices are also used as surgecurrent protection, certain ruggedness for linear operationis required, which is not discussed here in further detail.Conduction losses can be easily calculated as ohmiclosses I2 · RDSon, taking into account the RDSon at Tj

during operation. To estimate the junction temperature,

the knowledge of cooling capability in the system is vital.The Rth(j−a) (thermal resistance of junction to ambient)of the device is in series with the thermal resistance ofthe heatsink, PCB or another cooling path. The sum ofthe resistances limits the flow of the thermal energy fromthe silicon to the ambient. The Tj calculates then as:

Tj = Ta + I2· RDSon ·

(Rth(j−a) + Rth(heatsink)

)

with ambient temperature Ta and heatsink thermalresistance Rth(heatsink).

This equation shows that the overall performance of apower switch is a combination of the RDSon , RTH(j−a)

and the attached heatsink. As the die-size is usuallyshrunk from one MOSFET generation to the next, theRth(j−a) increases for a given RDSon. Fig. 2 shows theRDSon required by a technology that effectively reducesthe on-resistance by 50% compared to the referencetechnology (a 5mOhm device is used as an example) independence on the cooling capability. The common limitof both devices is Tj = Tjmax. It can be seen, that forvery good cooling conditions, as achievable with a largeheatsink, a substantially lower-ohmic device must be used.This is necessary to prevent the device from exceeding

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(new device)

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Fig. 2. RDSon required by a technology with a lower RDSon · Athan the reference technology, dependent on the heatsinking capabilityin the application

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0 1000 2000

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conduction lossesswitching losses

MO

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par

alle

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oss

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@12V [W]

Fig. 3. Efficiency loss in the synchronous rectifying stage of a SMPSwith 12V output voltage

the maximum allowed junction temperature Tjmax. ForSMD parts with an effective cooling of ∼ 30K/W , theRDSon can be identical for both technologies - withoutany significant change in Tj . From the above analysis,the RDSon in combination with the Rth can be derivedas the key parameters for power switches.

B. Switched Active Diodes

The replacement of diodes with MOSFETs to achievea lower forward voltage-drop during conduction is theinevitable step to reduce losses. For the conduction mode,all considerations done for the power switches are alsovalid. However, if the MOSFET is operated at highswitching frequencies, as it is the case for synchronousrectifying switches in SMPS or the low-side MOSFET ina buck-converter, switching losses and characteristics be-come important (Fig. 3). If the MOSFET technology usedis not sufficiently optimized for this type of operation, it iseven possible that no improvement whatsoever is achievedcompared to diodes. Often, losses are not the only issuewhen MOSFETs are used as active diodes. Ringing andovershoots during turn on and off become sometimesmore critical than the highest possible efficiency.

As the MOSFET is used instead of a diode, it ispossible to leave the device turned-off all the time. Theinternal body-diode of the MOSFET is, in principle,electrically sufficient. Consequently, the device is alwaysturned-on and -off while the body-diode is in an activestate (current flowing from source to drain). Thus allswitching of a synchronous MOSFET is therefore effec-tively zero-voltage switching. Switching losses are notrelated to simultaneous current and voltage across thedevice, but due to gate drive, reverse recovery of thebody-diode and the output capacitance COSS . The gatedrive losses are often small compared to the other losses.

Improved efficiency especially at light loads and lowerrequirements for the driving circuit are still advantages fora low gate-charge technology. The main switching lossesoccur during turn-off of the conducting body-diode [2].At first, the body-diode is conducting, then the externallycontrolled current changes polarity and the drain-sourcevoltage VDS across the device increases until the finalblocking voltage is reached. During these transitions, twocharges need to be removed by the MOSFET: the QRR,which is the stored charge in the body-diode, and theQOSS , the charge required to charge the COSS to theblocking voltage. The path of the current changing fromQ3 to Q4 is indicated in Fig. 1 as C. As shown in Fig.4, both QRR and QOSS do not completely contribute tothe switching losses. The QRR is removed during thezero-voltage phase (Fig. 4, t = 40ns) and does thereforenot directly generate losses. The QOSS stored in theCOSS is fed back to the power-circuit at the subsequentturn-on of the switch. Losses are instead related to thereverse-recovery current flow. Until the blocking voltageis reached, the QRR and QOSS feed the reverse current,limited only by the inductances in the loop. When theblocking voltage is reached for the first time (Fig. 4,t = 64ns), QRR and QOSS are completely removed.However, energy is now stored in the stray inductances inthe circuit which is approximately related to the reverse-recovery current peak IRRM :

Estray =1

2I2RRM Lstray

This dynamically stored energy appears as ringingafter the turn-off and is dissipated in snubber-circuits (ifpresent) and in the ohmic series-resistances. The max-imum reverse-recovery current IRRM depends stronglyon the circuitry, choice of components and also the wayhow the di/dt is controlled - either passively limitedby the inductances in the circuit, or actively by con-trolled switching. Fig. 3 shows the efficiency lost in

Fig. 4. VDS and ID at turn-off of body-diode(16V/div, 6A/div, 20ns)

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the synchronous rectifying stage. The switching lossesform the lower limit that cannot be improved withoutchanging MOSFET technology or improving the circuitry.The more MOSFETs are paralleled (lower RDSon) thebetter is the performance under high loads on the costof higher switching losses reducing efficiency under lightloads. Key parameters for the operation as switched activediodes are therefore: RDSon, Rth(j−a), QRR (ID, di/dt)and QOSS .

C. Control Switches

When used as a control switch, the original function ofcontrolling the current through the device is utilized. Thisis the key function for all kinds of switched-mode powerconversion and at least one device operating in this modeis required for this type of application. Loss generationdepends on the type of switch, currents, voltages andthe overall power-conversion concept. During on-time, allconsiderations from the power-switch section also applyto the control switch. For transitions, any losses additionalto those from the gate-drive strongly depend on theexternal circuitry and the exact operating conditions. Ba-sically, switching can be divided into hard-switching andsoft-switching. Under soft-switching conditions losses areminimized by reducing or even cancelling the voltage(ZVS: zero voltage switching) or current (ZCS: zerocurrent switching) across the device [3]. Hard-switching

Fig. 5. Current and voltage of control switch under A) MOSFETcontrolled switching and B) inductively limited switching

does solely control the current in the circuit by forcingthe gate (hard) on and off when required. This usuallyleads to switching losses, because voltage and currentare simultaneously non-zero across the device duringtransition. For the further evaluation, only hard-switchingtransitions are considered, as losses are highest underthese conditions.

MOSFET technologies to be used in SMPS have verylow gate-charges (Qg, Qgd) to switch very fast and havea very low RDSon [4]. This can lead to the situation thatthe device itself is able turn on and off significantly fasterthan it takes for the current to rise or drop (Fig. 5 B).Under these circumstances, the switching is inductivelylimited by the external circuit (including the source- anddrain-inductances of the package of the MOSFET). Ifinstead the time to turn the MOSFET on and off issignificantly larger than the commutation time for thecurrent, the switching is controlled by the device and isfurther referred to as MOSFET controlled switching (Fig.5 A).

The most common applications are the control switchesin buck/boost converters or the primary-side switchesin the various topologies of isolated DC/DC converters.We will discuss the effects for the half-bridge, similarconditions apply to most other topologies [5]. Examplesof the basic schematics are shown in Fig. 1. It is importantto understand where the current commutation happensand which inductances limit the switching speed. For thebuck/boost converter in discontinuous mode and the hard-switched half-bridge, the turn-on is limited by the outputinductor or the leakage inductance of the transformer,respectively. These are typically large compared to thestray inductances in the circuit and packages. The currentpath is indicated by A in Fig. 1. The turn-on of thebuck/boost in continuous conduction mode (CCM), aswell as the turn-off for both applications only see thelow-inductive loop through the input-capacitance [6]; thecurrent path is indicated by B in Fig. 1. While the typicalbuck/boost converter operating under CCM sees the sameinductance during turn on and off, the situation changesfor the half-bridge for turn-on and -off.

MOSFET controlled switching is the transition modethat is described in most textbooks. Losses are generatedin the channel region of the device, while voltage andcurrent across the device are non-zero (Fig. 5 A). Withthe latest low-Qg technologies available, this can beavoided even for very low-inductive circuits. Even witha di/dt ≥ 3000A/µs in a buck-converter operating at12 V, using the lowest inductive SMD packages and a low-inductive layout, it is possible to operate in the inductivelylimited regime. This greatly reduces the overall switchinglosses on the cost of a potentially stronger ringing andincreased EMI. MOSFET controlled switching is thepreferred choice in applications sensitive to these effects.For inductive switching, the turn-on losses are minimal,as the device switches under quasi zero-current conditions(Fig. 5 B). The turn-off losses usually exceed the turn-onlosses, as the energy stored in the inductances Estray =

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12 I2

RR Lstray of the circuit needs to be dissipated. Thismay occur in different ways:

• ringing after turn-off• device entering avalanche-mode• dynamic turn-on via coupling of the source induc-

tance in the gate circuit.

Furthermore, some or all of these mechanisms may occursimultaneously. A reduction of switching losses is mainlydriven by low gate charges Qg and Qgd combined with alow-inductive package and layout.

III. MOSFET TECHNOLOGY

Despite all efficiency improvements realized by ad-vanced power architecture concepts and improved con-verter topologies, power MOSFETs are the key compo-nent to achieve higher efficiencies in a power converters.Therefore, the performance of power MOSFETs did ad-vance at impressive rates over the past decade. Moderndevices in general have to offer a low on-resistance andlow switching-losses, but depending on the applicationa number of other parameters such as the body-diodesreverse-recovery charge or avalanche ruggedness are fromequal importance.

While it is essential for the achievement of a low on-resistance RDSon to employ a trench-gate concept, thereare nevertheless different competing device concepts indevelopment or already available on the market:

1) dense-trench MOSFETs [7]2) MOSFETs using shallow trenches with deep im-

plants and high cell density [8]3) field-plate trench MOSFETs [9]4) trench MOSFETs employing floating p-islands [10]

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Fig. 6. Device performance comparison chart for different 100 VMOSFET technologies of Infineon, Fairchild and International Rectifier(based on data-sheet values, package TO-220)

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Fig. 7. Evolution of Infineon’s low-voltage power MOSFET technolo-gies

Depending on the employed concept, some devicesbenefit from well-engineered manufacturing technologyand/or from newly-developed concepts using charge-compensation principles in different ways.

As an example, Fig. 6 gives a comparison of elder andup-to-date 100 V power MOSFET technologies of threesemiconductor manufacturers. As can be seen, all theirlatest technologies, although based on different deviceconcepts, show rather comparable performance in termsof FOM. Nevertheless there are differences leaving thedevices more or less optimized towards specific applica-tion fields.

Future technologies will continue to focus on on-resistance improvements, but probably spend more careon overall performance (in terms of FOM) in dependenceof the targeted application fields. Already now the deviceswith lowest per-area on-resistance not necessarily showthe best FOM. Especially, an increase in cell densityreduces the on-resistance, but in same time increasesthe total gate-charge. An improvement of both basicparameters needs more advanced cell concepts and highertechnological efforts. Another limiting factor is relatedto the thermal behaviour of the device. An increase incurrent density due to lower on-resistance leads to higherpower-densities. Simultaneously, the available area forcooling becomes smaller. Especially the performance un-der critical operation conditions, such as avalanche events,might suffer. Consequently there is a need for advancedpackaging concepts ensuring higher current capabilities,better cooling and lower package-related on-resistance.

For instance, Fig. 7 depicts the evolution of powerMOSFET technologies at Infineon Technologies, coveringthe last three generations and including some generallandmarks for the current developments. By employingcharge-balancing principles as explained in [9], the on-

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resistance is shifted below the so-called silicon-limit line(breakdown voltage of an ideal planar pn-junction). Notethat the values shown in Fig. 7 do not consider the sub-strate resistance which naturally becomes more significantas the blocking voltage decreases.

IV. PACKAGING

With silicon technology moving rapidly forward thepackage becomes an important part for low-voltage MOS-FETs. As discussed in the sections II and III, the packageinductance can play a major part in loss generation andfor the overall device performance. Additionally, the on-resistance of the latest technologies has become so lowspurring the need for low ohmic packages to avoid alimitation of the device by the package characteristics.30 V technologies from most vendors today allow forMOSFET dies in a TO-220 with a lower on-resistancethan the package resistance. Latest 55 V technologieson the market allow for devices with a package con-tribution of 30% and even for 100 V technologies thepackage can account for almost 20%, given a packageresistance of 1 mOhm. The package resistance not onlylimits the minimum on-resistance achievable in a package.Additionally, a larger die is required for a given RDSon

which increases the Qg and thus slowing down the device.Package contributions for devices with maximum die-size for the most common low-voltage MOSFET classesare shown in Fig. 8. To follow the route towards denserand more efficient power converter designs, new packagetypes, such as the SuperSO8, need to replace the leadedSMD or through-hole devices for low-voltage MOSFETs.

TO

-220

D²-

Pak

7-l

ead

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ntr

ibuti

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tance

package

30 V

60 V

100 V

Fig. 8. Package contribution to overall package resistance for deviceswith maximum die-size for state of the art technologies in 30 V, 60 Vand 100 V

It is easily possible to estimate the losses due topackage inductance for the turn-off. As example, a buck-converter with an output current of 30 A, operating at250 kHz, generates 0.7 W of losses in a D-Pak designdue to the total package inductance of 6nH. With alow inductive package like the SuperSO8, showing aninductance of just 0.5 nH, the losses drop below 0.1 W.

V. SUMMARY

In this paper we discussed the main operation modes oflow-voltage MOSFETs utilized in power conversion andpower management applications. It was shown that thecontinuing roadmap towards lower and faster switchingtechnologies has already brought many applications toa point where the limits are no longer the MOSFETsbut external components, the layout and the choice ofpackage. While this roadmap will still yield a benefitfor most applications, it comes at the cost of higherthermal resistances, diminishing the effect of the reducedRDSon and the expected cost-down. For future MOS-FET technologies a higher degree of specialisation forindividual applications is required, merging the siliconand packaging technology and layout guidelines into anoverall concept.

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[7] J. Zeng, G. Dolny, C. Kokon, R. Stokes, N. Kraft, L. Brush, T.Grebs, J. Hao, R. Ridely, J. Benjamin, L. Skurkey, S. Benczkowski,D. Semple, P. Wodarczyk and C. Rexer, “An Ultra DenseTrench-Gated Power MOSFET Technology Using A Self-AlignedProcess”, Proc. ISPSD, Osaka, 2001

[8] D. Kinzer, “Advances in power switch technology for 40V - 300Vapplications”, Proc. EPE, Dresden, 2005

[9] R. Siemieniec, F. Hirler, A. Schlögl, M. Rösch, N. Soufi-Amlashi,J. Ropohl and U. Hiller, “A new fast and rugged 100V powerMOSFET”, Proc. EPE-PEMC, Portoroz, 2006

[10] H. Takaya, K. Miyagi, K. Hamada, Y. Okura, N. Tokura and A.Kuroyanagi, “Floating Island and Thick Bottom Oxide TrenchGate MOSFET (FITMOS) - A 60V Ultra Low On-ResistanceNovel MOSFET with Superior Internal Body Diode”, Proc.ISPSD, Santa Barbara, 2005

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