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A Novel SEPIC Type Single-Stage Single SwitchElectronic Ballast with Very High Power Factor

and High EfficiencyJohn Lam[1], Member IEEE Praveen K. Jain[1], Fellow IEEE and Vineeta Agarwal[2], Member IEEE

Energy and Power Electronics Applied Research Laboratory (ePEARL) [1]

Queen’s University, Kingston, Canada, K7N 3N6 Tel: (613)-533-6984

Email: john.lam@ece.queensu.ca, praveen.jain@queensu.ca

Dept. of Electrical Engineering[2]

MN National Institute of Technology Allahabad, India

Email: vineeta@mnnit.ac.in

Abstract—A novel SEPIC type single-stage single switch electronic ballast with very high power factor is presented in this paper. The proposed lamp power circuit combines the SEPIC converter and a single switch resonant inverter to form a single-stage inverter to power the lamp. The resulting circuit provides a compact and cost-effective circuit configuration for electronic ballast designs. By operating the SEPIC power factor corrector in discontinuous conduction mode, the average line current is in phase with the line voltage and a very high power factor is achieved at the input. In the proposed design, zero-current switching (ZCS) is achieved at the turn-on of the MOSFET to maintain high efficiency for the overall circuit. The proposed topology also allows simple gate driver to be used without the use of any isolation devices. Simulation and experimental results are provided for a design example of a 26W compact fluorescent lamp to verify the feasibility of the proposed circuit.

I. INTRODUCTION

Compact fluorescent lamp (CFL) that was first introduced in the early 90’s, has now been using widely in a lot of household lightings, restaurants, offices, shops, and many other places where incandescent lamps were conventionally used. This is because a CFL consumes only one-third of the power that is dissipated in an incandescent lamp and its lifetime is 1000 times that of an incandescent lamp [1]. It provides a very valuable lighting source to conserve energy and reduce the energy cost. The key component inside each CFL is the high frequency electronic ballast that provides proper lamp ignition and lamp current stabilization. It is known that high frequency electronic ballasts operating at >25kHz provide more desirable performance than magnetic ballasts in fluorescent lightings as they are able to: (1) reduce the ballast volume; (2) increase the light efficacy by at least 20%; (3) eliminate light flickering; (4) implement advanced dimming control with great flexibility. However, like other electronic appliances, the harmonics of the line current drawn from the fluorescent lamp must comply with the IEC1000-3-2 standard [2] when the lamp power >25W.

The conventional way to connect a diode rectifier across a DC-link capacitor with resonant inverter as shown in Fig. 1(a) produces a poor power factor of less

than 0.6 and the harmonics content of the line current exceed the limits of the standard. To correct the power factor problem, the simplest way is to insert a power factor correction (PFC) circuit between the rectifier and the inverter as shown in Fig. 1(b) so that the shape of the line current follows the sinusoidal line voltage and a high power factor can be achieved at the input. However, this kind of circuit configuration usually results in a high cost and large size circuit that is almost impossible to be compatible with the size of a CFL.

Single-stage resonant inverters [3] have been studied extensively and discussed in works [4]-[6] to combine the PFC converter and the resonant inverter in one stage to provide a cost-effective design approach in T5 and T8 types fluorescent lamps. To further reduce the size and cost of the ballast power circuit, single-switch electronic ballasts have also been proposed [7]-[9] by integrating the well-known class E resonant inverter [10] with the PFC circuit. By operating the PFC stage, either a boost or a buck-boost converter, in discontinuous conduction mode (DCM), a very high power factor with desirable harmonics is achieved at the input. However, the main disadvantage in the class E resonant inverter is the high peak voltage and current associated with the switch. The voltage across the switch is times the input DC voltage of the inverter [9]. Hence, a special kind of MOSFET or a heat sink may be required to cool down the temperature in the ballast power circuit.

This paper proposes a new type of single-stage single switch electronic ballast topology using a SEPIC power factor corrector that is integrated with a single switch current fed inverter. The proposed circuit is compact and minimizes the circuit components in the ballast power circuit. As the switch in the proposed design is not connected in parallel with the resonant circuit, the resonant current does not flow through the switch, resulting in a lower current stress across the switch and lower switch conduction loss. The advantages of using SEPIC PFC in the proposed circuit topology will be reviewed and discussed in this paper. The operating principles and the design of the proposed circuit will be given in details in this paper. The feasibility and performance of the proposed circuit will be verified through simulation and an experimental prototype on a 26W CFL.

978-1-4244-1668-4/08/$25.00 ©2008 IEEE

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(a)

(b)Fig. 1 (a): Typical electronic ballast in CFL without PFC; (b):

Electronic ballast with PFC

II. ANALYSIS OF PROPOSED SINGLE SWITCH BALLAST

A. Descriptions of Proposed CircuitThe proposed single switch electronic ballast, as shown

in Fig. 2, is derived from the cascade combination of a SEPIC converter and a single switch current fed inverter. The SEPIC converter is chosen for PFC in the proposed design because: (1) it does not require a large size high-voltage DC link capacitor as in the boost PFC case; (2) unlike the DCM operating boost converter, the SEPIC converter DC-link capacitor does not need to suffer high voltage stress in order to achieve a high power factor [11]; (3) the output DC link voltage polarity is not inverted as in the buck-boost converter case, which allows simpler circuit configuration and input EMI filter designs [12]. When the SEPIC converter operates in DCM with a fixed switching frequency, the peak of the DCM inductor current also follows the rectified sinusoidal envelope and a close-to unity power factor is achieved at the input. As a result, SEPIC converter features all the advantages seen in boost and buck-boost converter. The only drawback is that an extra inductor and a capacitor are required.

Let the input line voltage is: vs(t)= Vpsin(2 fLt) with Vp= peak line voltage and fL = line frequency, the average current (is,avg(t)) drawn from the line is given in (1), where Leq= (L1L2)/(L1+L2) [12], Ts = switching period and d = duty ratio. It is observed from (1) that is,avg(t) is pure sinusoidal and is in phase with vs(t). Hence, a very high power factor is achieved at the input. The input average power equation is derived from (1) as given in (2). Fig. 3 shows the operating stages of the proposed circuit with the key waveforms shown in Fig. 4. Fig. 5 illustrates the operating waveforms at the PFC side to achieve high power factor in DCM. The operating principles of the proposed circuit are described as follows:

[interval 1]: M1 is on, iL rises linearly, iin begins to increase slowly due to the presence of Lin so that close to zero-current switching is provided at the turn-on of the MOSFET. The total current flowing through the switch is ids.

[interval 2]: M1 is off, iL decreases linearly. Current iinflows through Coss and decreases until it drops to zero.

[interval 3]: iL continues to decrease linearly until it drops to zero, then iL enters the discontinuous conduction period.

[interval 4]: all the diodes are off and the resonant circuit continues to deliver the required energy to the output.

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B. Analysis of Resonant InverterThe corner frequency (fr) and the quality factor equation

of the C-L-L resonant inverter are determined by (3) and (4) respectively. As the voltage generated across Cr is a close-to sinusoidal waveform, proper lamp current balancing is ensured at the output of the inverter circuit. If a high enough quality factor (Q) is chosen in the resonant circuit, then close-to-sinusoidal waveforms can be achieved at the output and fundamental approximation can be used in the linear analysis of the resonant circuit. During lamp ignition, the lamp resistance (Rlamp) is infinite and the resonant circuit becomes a parallel L-C circuit. The output voltage of the lamp during this phase is given in (5). By solving (5), the corresponding ignition frequency can be obtained as given in (6), where LT = Lr+Lp and Iin is the amplitude of iin.

After the lamp is ignited, the gas within the lamp becomes ionized and the lamp resistance decreases to a few hundreds of ohms. The resonant circuit now becomes a C-L-L resonant tank with a finite value of lamp resistance. The output lamp current is then calculated using the current gain relationship as shown in (7), where iin,1 is the fundamental component of iin, k = Lp/Lr and s is the angular switching frequency.

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21 (3)

lamp

rr

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Fig. 2: Proposed single switch high power factor electronic ballast

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Fig. 3: Operating principles of proposed circuit

Fig. 4: Input waveforms at the PFC side

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ids

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Fig. 5: Key waveforms of proposed circuit

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III. COMPONENT STRESS ANALYSIS

It is a well known fact that the active components in single stage or single switch converters may have to suffer high voltage or current stress when compared to the conventional two stages converters to achieve the same amount of power level. In the proposed circuit, it is important to investigate the voltage and current stress across the switch. As mentioned in section II, when the MOSFET conducts, the current components compose of iL, iC1 and iin. Hence, the maximum current stress occurs at the end of the conduction time of the switch, which is given in (8), where iL,pk is the peak current of inductor L1,iC1,pk is the peak current of inductor L2 and iin,pk is the peak of the inverter input current. Since the voltage across C1is equal to the rectified line voltage, iC1,pk and iL,pk can be combined and the corresponding equivalent inductance is represented by Leq. In (8), vcr(t) represents the voltage across capacitor Cr, which is the sum of the voltage across inductor Lr and the lamp voltage vo(t); Vdc is the DC link voltage across C2 and Vrect is the rectified line voltage. The voltage gain relationship between Vdc and Vrect is given in (9). Assume that a close-to-sinusoidal waveform is achieved at the output, i.e. vo(t) = Vocos( st), vcr(t) will also be a close-to-sinusoidal waveform with a phase angle

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of . The final expression in (8) is expressed in terms of vo, Vdc and Vpk, which are all known quantities so that the maximum current stress can be calculated. The peak current flowing through D1, Din and Db are also given in (10), (11) and (12) accordingly.

The rms voltage stress across the MOSFET when the MOSFET is off is given in (13). It is obtained by using KVL in the proposed circuit, where vL,in(t) is the voltage across inductor Lin. Since the current flowing through Linis almost equals to zero when the MOSFET is off, vL,in(t)is almost equal to zero as well during the switch off period. Using vct(t) derived earlier in (8) and substitutes it in (13) gives a good approximation of the rms voltage across the switch.

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IV. DESIGN EXAMPLE

To validate the feasibility of the proposed circuit, a dulux T/E 4-pins 26W CFL from Sylvania with Iout =0.32Arms is chosen as the testing load for the designed prototype with a line voltage of 110Vrms 60Hz. The switching frequency is 70 kHz and the quality factor is 2. The circuit parameters are then calculated by the following steps:

(1): Rlamp is first calculated using Iout and Pout as shown in (14). Then the values of Lr, Cr and Lp are obtained using (3), (4) and (5) respectively.

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Lp is selected to be higher than Lr so that sufficient high voltage can be guaranteed at the output during lamp ignition. In this example, Lp is selected to be 1.8mH.

(2): Calculations of L1, L2 ,C2

The SEPIC inductors (L1 and L2) are calculated by (2) as follow, with Vpk = 155V; d = 0.4; Ts = 1/70kHz; and = 90%:

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2647014.01559.0

4

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Since L1 is chosen to be equal to L2, L1 and L2 can be determined from Leq and are obtained to be 1.2mH. The output capacitor C2 can be obtained by first calculating the mean input resistance of the inverter circuit. This can be obtained by equating the input power of the SEPIC circuit and the output power of the SEPIC circuit as given in (15) assuming = 90%. From (15), Ri is calculated to be 2110 . Vdc is then calculated from (9) with d = 0.4 and Vpk = 155V. C2 is can then be calculated using (16) by allowing a 2% ripple in Vdc.

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(3): Selection of MOSFET and diodes The selection of the MOSFET is determined by both (8)

and (13). From (8), the approximated maximum current stress is calculated with Vpk = 155V, d = 0.4, Ts = 1/70kHz, Lin = 1.1mH.

AAmH

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kHzVids 95.13.0

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The rms switch voltage is obtained to be 460V using (13). To meet these two requirements, the MOSFET SPA06N60C3 is chosen for this design. For the diodes, ultra-fast recovery diodes are required for diodes Db, Dinand D1. As illustrated in (10)-(12), the maximum current flowing through Db and Din are equal to the peak of the DCM inductor current; whereas the maximum current going through D1 is equal to the peak of iin. Hence,MUR1560 are selected for all these diodes.

V. SIMULATION AND EXPERIMENTAL RESULTS

The proposed circuit is then verified with the design example simulated in SIMETRIX 5.0. Fig. 6(a) shows the simulated line current and a power factor of 0.995 is achieved. Fig. 6(b) shows the simulated output current and PFC inductor current: iout and iL; Fig. 6(c) shows the low frequency component of the simulated DCM input inductor current. Fig. 7 shows the electrical diagram of the experimental prototype. Fig. 8 shows all the experimental waveforms.

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(a)

(b)

(c)

Fig. 6 (a) Simulated input line current (is); (b) Simulated current waveforms (iout, iL); (c) Simulated DCM inductor current

Fig. 7: Electrical diagram of the design example

The lamp current and voltage is shown in Fig. 8(a) with a crest factor of 1.48 is measured. The measured current waveforms iout and iL are displayed in Fig. 8(b). The measured line current is shown in Fig. 8(c) with a power factor of 0.995 and a THD of less than 10% are achieved according to the harmonic spectrum of is shown in Fig. 8(d). Fig. 8(e) shows the switch current (ids) and switch voltage (vds) waveforms. The peak current flowing through the switch is about 1.98A. All the measured waveforms are observed to have good agreements with the

theoretical waveforms and simulation results. The overall efficiency is measured to be 91.8% at 110Vrms.

(iout: 0.25A/div; vout: 100V/div; time: 5ms/div)

(a)

(iout: 0.25A/div; iL: 0.5A/div; time: 5 s/div)

(b)

(is: 0.3A/div; vs: 50V/div; time: 5ms/div)

(c)

(is: 0.1A/div; frequency: 180Hz/div) (d)

(ids: 0.5A/div; vds: 150V/div; time: 5 s/div) (e)

Fig. 8 (a) Measured lamp current and voltage; (b) Measured lamp current and DCM inductor current ; (c) Measured line current; (d):

Harmonics of is; (e) Measured switch current and voltage

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VI. CONCLUSIONS

A compact, high power factor and high efficient single switch electronic ballast topology using an integrated SEPIC PFC converter has been presented in this paper. Features of the circuit and its operating principles have been discussed in this paper. This circuit saves a switch compared to the conventional design in CFL without PFC and saves at least two switches compared to the conventional high power factor electronic ballast design. Although it requires a few inductors in the circuit, the size and volume of these magnetic components have been justified in the experimental prototype. A detailed design example has been given in this paper to verify all the theoretical analysis. Experimental results finally confirmed that a very high power factor of 0.995 is achieved at the input on a commercial 26W CFL.

REFERENCES

[1] National Resources Canada, “Commercial and Institutional Retrofits - Technical Information - Fluorescent Lamp And Ballast Options” 2002.

[2] International standard IEC 1000-3-2 Class C. 1ed, March 1995. [3] T.-F. Wu and T.-H. Yu.; “A unified approach to developing single

stage power converters,” IEEE Trans. on Aerospace and Electronic Systems, vol. 34, no. 1, 1998, pp. 211-223

[4] A.J. Calleja, J.M. Alonso, J. Ribas, E. Lopez, J. Cardesin, J. Garcia and M. Rico-Secades, “Electronic ballast based on single-stage high-power-factor topologies: a comparative study,” in Proceedings of the 2002 IEEE Industrial Electronics Society Conf., pp.1196 – 1201.

[5] Alonso, J.M., Calleja, A.J.; Ribas, J., Corominas, E.L., Rico-Secades, M., “Analysis and design of a novel single-stage high-power-factor electronic ballast based on integrated buck half-

bridge resonant inverter,” IEEE Trans. on Power Electronics, vol. 19, no. 2, March 2004, pp. 550 – 559.

[6] Chiu, H.-J., Lin, L.-W., Wang, C.-M., “Single-stage dimmable electronic ballast with high power factor and low EMI,” inProceedings of the 2005 Electric Power Applications Conf., pp. 89 – 95.

[7] DeMorais, A.S., Farias, V.J.; deFreitas. L.C., Coelho, E.A.A., Vieira, J.B., Jr., “A high power factor ballast using a single switch with both power stages integrated,” IEEE Trans. on Power Electronics, vol. 21, no. 2, March 2006, pp. 524 – 531.

[8] Weihong Qiu; Moussaoui, Z.; Wenkai Wu; Batarseh, I., “Single-switch zero-voltage-switching high power factor electronic ballast,” in Proceedings of the IEEE 2002 Power Electronics Specialists Conf. pp. 773 – 778.

[9] Ponce, R. Vazquez and J. Arau, “High power factor electronic ballast for compact fluorescent lamps based in a class E amplifier with LCC resonant tank,” in Proceedings of the 1999 IEEE Applied Power Electronics Conf., pp. 486-492.

[10] Cheng, H.L.; Moo, C.S.; Yen, H.C.; Lin, T.F.; Huang, S.H.; “Single-switch high-power-factor electronic ballast for compact fluorescent lamps,” in Proceedings of the 2001 IEEE International Conference on Power Electronics and Drive Systems, pp. 764 – 769.

[11] Liu, K.-H.; Lin, Y.-L.; “Current waveform distortion in power factor correction circuits employing discontinuous-mode boost converters,” in Proceedings of the 1989 IEEE Power Electronics Specialists Conference. pp. 825 – 829.

[12] Simonetti, D.S.L.; Sebastian, J.; Uceda, J.; “The discontinuous conduction mode Sepic and Cuk power factor preregulators: analysis and design,” IEEE Trans on Industrial Electronics, vol 44, no. 5, Oct. 1997, pp. 630 – 637.