Development of Silicon Solar Cells for Six-Junction Tandem Stack Cells

Ngwe Soe Zin, Andrew Blakers and Vernie Everett

The Australian National University, Canberra ACT 0200, Australia

http://solar.anu.edu.au/

Email: soe.zin@anu.edu.au

ABSTRACT — This paper presents the development of small

(2.5x8.0mm2) silicon solar cells, to be used in a six-junction

tandem device. PC1D, numerical modeling and quasi steady

state photoconductance (QSSPC) measurement were used to

predict the targeted efficiency of silicon solar cells. Early batch

of cells had problems of shunting, series resistance and high

carrier recombination. Various techniques – junction isolation,

pin-hole analysis, diffusion drive-in, light-induced plating,

lifetime degradation studies and implied-Voc - were used to

improve the performance of the solar cells.

1. INTRODUCTION

The very high efficiency solar cell (VHESC) program

sponsored by DARPA adopts the six-junction independently-

wired tandem cell approach. The final objective is to achieve a

combined efficiency of >50% under 20suns illumination [1, 2].

Concentrated sunlight with power of around 2W/cm2 is incident

on the top of the package. Light of energy <1.42eV will be

transferred to the Si cell. The light incident on the Si cell will be

in the form of a 1.9mm diameter spot which will wander in a

track of approximately 2mm in width and 6.5mm in length.

Silicon is one of the cells in the tandem stacks and absorbs

photon energy in the range 1.42 – 1.1eV. Most of the light of

energy <1.1eV must pass through the Si cell to an underlying

low bandgap solar cell, and so texturing cannot be used.

The external dimensions of the silicon solar cell are 2.5mm

in width and 8mm in length as shown in figure 2.1. Cells were

fabricated using 500µm thick <100> p-type float-zone 1Ωcm

wafers. The cells have an n-type emitter region on both front

and back of cell with the dimension of 6.5 x 2.5mm2. Metal

contacts are made to both upper and lower surfaces of the cell.

The n-contact to the external world is on sunward side and the

P-contact is on the back of cell. Metal contacts are designed

with a spacing of 1.9mm in the lateral direction and a length of

5.5 mm as shown in the figure 1. Multiple cells are processed

simultaneously on each wafer until the metallization step is

completed, at which time they are diced out of the wafer to form

individual solar cells.

2. FABRICATION OF CELLS

Fabrication of efficient cells is challenging: the small size

of each cell complicates handling and exaggerates the effect of

electrical shunts; the area of each of the six surfaces of the cell

is significant and contributes to surface recombination (rather

than two or even one face being dominant as in conventional

cells); series resistance losses are significant due to the need to

keep contacts outside the optical path; the cell area is four times

larger than the illuminated spot (due to the need to

accommodate the light spot moving along its track) which

quadruples bulk and surface recombination; and the need to

transmit light to underlying cells requires that texturing be

eschewed in favour of thick cells, which reduces external &

internal quantum efficiency and increases bulk recombination.

Modelling predicts that untextured 500µm thick silicon

solar cells as described above can reasonably achieve a short-

circuit current (Isc) of 4.9mA and open-circuit voltage (Voc) of

680mV under full spectrum one sun illumination [4].

Fig 1: Silicon solar cell structure

During cell fabrication, wafers were processed in a series

of high temperature diffusion, oxidation and annealing steps.

Effective carrier lifetime was measured using QSSPC technique

after each high temperature process [5]. The effective carrier

lifetime after the final high temperature process was measured

to be around 560µs. Using the implied-Voc technique, the final

open-circuit voltage is predicted to be around 640mV [6].

Completed cells were diced out from the wafer to form

individual cells.

MetalsSiO2 + ARC

Metal build-up at

the pinhole from

plating

n++ n++

p+p+

n+P Bulk

#1

#4 #3

#2

Pinholes

Fig 2: Possible shunting paths in the solar cells

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3. DEVELOPMENT OF SOLAR CELLS

3.1 Shunting Improvements

Early batches of cells fabricated was found to have serious

shunting problems.. Even small shunts have serious

consequences for very small cells such as these.

Possible shunting routes for silicon solar cells were

identified, as shown in the figure 2:

1. Pinholes

2. Insufficient barrier oxide thickness to resist boron

diffusion

3. Tunneling between adjacent phosphorous and boron

diffusions.

4. Insufficient removal of the prior phosphorus diffusion

before the boron diffusion

A pinhole (scenario #1) can easily lead to direct shunting

between the phosphorous emitter and base contact after

metallization. Typical pinholes on the solar cells after

metallization are shown in Fig. 3. These pinholes are associated

with the particular quality of the LPCVD SiNx layer deposited

using our equipment, and are not regarded as generic [7]. To

find out if these pinholes can cause shunting problems, a method

to isolate the shunted regions from the active cell region was

used [8, 9]. A group of cells were fabricated using the same

processing sequence as shunted cells, but without boron

diffusion to eliminate possible shunt paths introduced by boron

diffusion. Junction isolation was performed on completed cells:

laser machining was used to scribe a trench on each side of the

solar cell, isolating the two p- and n-contacts totally. A deep

trench was produced by laser scribing and the cells subsequently

remeasured.

Fig 3: Pinholes on the cell after metallization

The cells previously shunted prior to the deep laser scribe had

recovered from the shunt completely, as shown in figure 4.

Insufficient oxide thickness to resist the heavy boron

diffusion (scenario #2) could lead to direct junction shunting

between the heavy phosphorous and heavy boron diffusions.

Following on from the heavy phosphorous diffusion, a thick

oxide was grown to prevent the subsequent boron diffusion

entering into phosphorous region. This oxide had to withstand

several process steps. Careful control of oxide thickness to

100nm, and minimisation of subsequent etching steps, allowed

the elimination of this shunting path.

If the post-boron-diffusion drive-in is insufficient, then

tunnelling between the boron and the adjacent phosphorus

diffused emitter (scenario #3) can create a shunt [10, 11]. Two

groups of cells were fabricated using similar process sequences

except for a post-boron-diffusion drive-in step. Cells without a

drive-in step were severely shunted compared with those with a

drive-in step as shown in figure 5. Hence insufficient or lack of

post-diffusion drive-in could contribute to the shunt resistance

issues in solar cells.

Fig 5: I-V curves for cells with or without diffusion drive-in

The boron diffusion follows the phosphorus emitter

diffusion. Insufficient etching of the p+ contact windows to

remove the underlying phosphorus prior to boron diffusion

could cause problems (scenario #4). Wet chemical etching to

thoroughly remove the emitter phosphorous diffusion resulted in

cells that were free from shunt.

3.2 Metallization Improvements

Metallization of contacts by light-induced plating (LIP) and

direct electrolyte plating were chosen for the n++

and p+ contacts

respectively. LIP (figure 6), frequently employed in high

performance solar cells, exploits the photovoltaic effect of a

solar cell by utilizing the electrolyte plating solution without the

need to contact the front side metal grid [12, 13, 14].

Fig 4: Shunted cell before (pink) and after (blue)

junction isolation Fig 6: Principle of Light Induced Plating

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Since light-induced plating technique is only suitable for plating

the front contact (n++), a direct-contact electroplating method

was chosen to plate back contact (p+). The benefit of the above

plating set up (fig 7) is that it provides an option of employing

both light-induced plating and electrolyte plating simultaneously

for silicon solar cells contacts. Series resistance in cells

fabricated by employing these two plating techniques are

relatively free of series resistance related to metal conductivity,

as shown in figure 7.

Fig 7: IV Curve for cells after metallisation improvements

3.3 Optimization of Cells Processing

As shown in table 1, after elimination of problems associated

with series and shunt resistance, cells had low open-circuit

voltage and short circuit current as compared to targeted results

caused by high surface and bulk carrier recombination due to

processing problems.

Table 1: IV data for cell tested under 1sun illumination

Cell# Intensity Voc(mV) Isc(mA) FF(%)

1 1 sun 552 3.2 78

2 1 sun 550 3.2 79

3 1 sun 549 3.2 78

The QSSPC measurement technique [5] was used to

characterize the effective lifetime at various stages of processing.

In standard processing of silicon solar cells, dielectric layers -

silicon dioxide (SiO2) or silicon nitride (SiNx) can be used as an

etch mask and a diffusion barrier. In our prior processing steps,

SiNx was used as a mask to stand off diffusion and resist etching.

Dry etching was used for selective emitter formation in replace

of photolithography, since the rugged topography of the cells

precluded application of resist. To characterize the difference

between samples using SiNx or SiO2 as a diffusion or etch mask,

an experiment was carried out by using P-type float zone, (100),

120Ωcm, 450µm thick wafers as shown in table 2. Deposition of

nitride and oxide on two different groups of wafer mimic the

step of creating a diffusion mask in the fabrication of solar cells.

QSSPC measurements show that samples using nitride as a

diffusion mask have much lower lifetime (<300µs) than samples

using oxide as a diffusion mask, as shown in figure 8.

Table 2. Characterization steps for recombination

1st Group of Wafer 2nd Group of Wafer

1 Deposit Nitride Grow Oxide

2 Measure Lifetime Measure Lifetime

3 Strip Nitride in HF Strip Oxide in HF

4 N+ diffusion N+ diffusion

5 Grow Oxide Grow Oxide

0

500

1000

1500

0 2 4 6 8 10 12

Life

tim

e (

µs)

Number of measurement

Lifetime Difference for Samples using Nitride/Oxide as

a Diffusion Mask

Nitride as a diffusion mask Oxide as a diffusion mask

Fig 8: Lifetime for samples using oxide/nitride as a mask

It has seen that depositing nitride directly on the silicon to be

used as a diffusion mask results in low lifetime and open-circuit

voltage, possibly due to defect generation [15]. The

incorporation of a thin oxide beneath the nitride eliminated this

problem.

Dry etching used for the selective emitter formation could have

an adverse effect on carrier lifetime. P-type float zone, (100),

120Ωcm, 450µm thick wafers were used for to characterize this.

Samples were oxidized and then processed with dry etching.

Subsequently, a passivation oxide was grown onto the samples.

Finally lifetime was measured compared with the lifetime of

former samples using oxide and nitride as diffusion barriers. As

shown in fig 9, samples etched by RIE had significantly lower

lifetime compared to any other samples. This degradation could

be due to damage induced by RIE ions bombardment to the

sample’s substrate during etching [16, 17].

0

500

1000

1500

0 2 4 6 8 10 12 14 16

Life

tim

e (

µs)

Number of measurement

Lifetime Comparison for Samples

nitride as a diffusion mask oxide as a diffusion mask smaples etched by RIE

Fig 9: Lifetime comparison for samples using SiO2/SiNx as a

mask and samples processed by RIE

-4.00E-03

-2.00E-03

0.00E+00

2.00E-03

4.00E-03

6.00E-03

8.00E-03

1.00E-02

1.20E-02

1.40E-02

-6.00E-01 -4.00E-01 -2.00E-01 0.00E+00 2.00E-01 4.00E-01 6.00E-01 8.00E-01

Isc(

mA

)

Voc(mV)

#31-A10-S3portion1-Cell2

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4. RESULTS

After addressing problems of shunt and series resistance, and

incorporating improved methods of using SiN and RIE, a new

batch of cells were fabricated with optimized processing steps.

Completed cells were diced out from the wafer to form

individual cells. Cells were tested by a current-voltage flash

tester [3] under one sun illumination intensity without having

the light being filtered by high band gap materials (GaAs). Cells

tested were recorded with sharply increased open-circuit voltage

and short-circuit current values (table 3) compared to the earlier

batch of cells as shown in table 1.

Table 3: Performance of cells under one sun illumination

Cell ID Voc (mV) Isc (mA) FF

A22-A1-C1 604 4.7 77%

A22-A1-C2 605 4.8 75%

A22-A1-C3 604 4.7 75%

A22-A3-C1 600 5.0 75%

A22-A3-C2 598 5.0 76%

A22-A3-C4 598 5.0 72%

A22-A5-C3 598 4.8 77%

A22-A5-C4 599 4.8 77%

A22-A5-C5 602 4.9 77%

5. CONCLUSION

Identification of shunting routes has allowed their elimination.

Incorporating light-induced plating for n++ metal contacts and

electrolyte plating for p++ metal contacts has eliminated series

resistance from the metal contacts. Characterising excessive

carrier recombination associated with certain processing steps

has allowed the cells to achieve sharply increased open-circuit

voltage and short-circuit current. Cells fabricated after these

improvements for carrier recombination, metallization and

shunting have achieved considerably higher conversion

efficiency, although there is still substantial room for further

improvement in open-circuit voltage. Cells will be next tested

for conversion efficiency under 20 suns concentration with

filtering from a high band gap material solar cell (GaAs) and a

mask having a pinhole of 1.9mm diameter.

6. ACKNOWLEDGEMENTS

The authors gratefully acknowledge the support of the

Australian Research Council and DARPA.

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