WIRE-TEXTURED SILICON SOLAR CELLS

Kejia Wang1, Oki Gunawan1, Naim Moumen1, George Tulevski1, Hisham Mohamed2, Babak Fallah3, Emanuel Tutuc3, and Supratik Guha1

1IBM T.J. Watson Research Center, Yorktown Heights, NY, 10598

2Egypt-IBM Nanotechnology Research Center Labs 3Department of Electrical and Computer Engineering, University of Texas Austin, TX

ABSTRACT

Wire array or nanowire based silicon solar cells based upon radial p-n junctions have been investigated over the past few years for enhanced light trapping, as well as for being able to offer radial junctions that are in close proximity to photogenerated carriers. To date, however, silicon wire array cells have not been able to demonstrate efficiencies higher than their planar controls. We have studied of wire textured solar cells using two approaches. The first experiment focuses on single crystal Si substrate. We use thin (2.3 µm) p- (~5x1015 /cm3) epitaxial Si/p+(~5x1019 /cm3) Si(100) substrates to fabricate wire arrays using a simple, top down process employing a self assembled mask of close packed polystyrene micro-spheres. The effective absorber depth is confined to the thin p- layer since the photocurrent generation in the p+ layer is negligible due to low minority carrier lifetimes. The thin layer accentuates the effect of the wire structures. Through a detailed study of wire diameter and conformality, we demonstrate wire array devices that outperform the planar controls in terms of efficiency and photocurrent. The second experiment focuses on multicrystalline Si. We show that the self assembled monolayer mask process can be adapted for wire texturing multicrystalline Si solar cells successfully in a low cost, scalable process using chemical functionalization as a result of which a simple dispensing technique can be used without the need for spinning or squeegee based approaches. We demonstrate cells with 20% higher short circuit current than the planar control, and show that the wire textured samples have a higher “pseudo”-efficiency when the series resistance effects are excluded. Finally, through an extensive examination of the electrical performance of the cells using both thin single crystal, as well as multi-crystalline bulk Si absorber layers, we have identified the key issues of light trapping, internal quantum efficiencies and series resistance as a function of wire diameter.

INTRODUCTION The main impediment to the widespread utilization of solar cells is their cost. For silicon technology that dominates the market today, almost half of the cost is associated with the silicon material that needs to satisfy certain minimum

thickness (typically > 100 µm) and a high material quality that yields high minority carrier lifetime. A way to address this problem is to engineer device geometries to enhance the light absorption and utilize poorer quality materials such as metallurgical grade, polycrystalline, or multi-crystalline silicon, such that smaller volumes of cheaper silicon can be used. One proposed solution is to use radial p-n junction geometry in cylindrical nano/micro wire structures [1], such that the photogenerated carriers remain in close proximity to a junction (i.e. within a diffusion length), where they can be collected before they can recombine. In addition these dense array of wires also serve as a natural light trapping layer that increases light absorption [2,3]. The promise of such an approach has generated many studies in the literature of nano or mico wire array silicon solar cells [2,4-8].

Figure 1: (a) Fabrication steps for the wire-array solar cells, using a thin (2.3 µµµµm) single crystal Si substrate. A. (b) Scanning electron micrographs (SEMs) of wire-array cells after etching, with starting microsphere diameters of 0.5, 1 and 2 µµµµm.

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DEVICE FABRICATION

We have developed a simple, inexpensive and large area-scalable of wire-array (or wire-texture) fabrication using microsphere lithography technique. This fabrication process is illustrated in Fig. 1(a). The single crystal (SC) or multicrystal (MC) silicon substrates were coated with a suspension of polystyrene microspheres [9,10] and were either spin coated (for the SC-Si ) or dispensed (for the MC-Si ) onto the silicon surface. The MC silicon surfaces were chemically functionalized with an amino-silane, while the micro-spheres were carboxyl functionalized, in order to use a simple dispensing technique for the micro-sphere suspension, which left a single monolayer of the self-assembled spheres on the surface. The single crystal substrates were spun-on. Both produced similar results, however, the MC technique can be scalable to larger areas. Wire structures were then defined using a reactive ion etching (RIE) process using either SF6 or HBr chemistries. The emitter layer was created using POCl3 diffusion at 800-860 °C for 50 min with a peak doping level of 6×1020/cm3 and a junction depth of ~ 380 nm. We then etch ~ 3 µm mesa to define the cell area of 10×10 mm. For the front contact we deposit Ti/Pd/Ag (50/50/120 nm) using a standard busbar-grid structure and a blanket Ti/Au (10/80 nm) as the back contact. The first part of study is a wire-diameter dependence of the device characteristics in single crystal Si wire-array solar cell. The substrate is 2.3 µm boron-doped p- (~5×1015 /cm3) epitaxial Si/p+(~5×1019 /cm3) Si(100) substrates, so that the effective absorber depth for photocurrent generation was limited to the top ~ 2.3 µm epitaxial p- Si layer (the photocurrent generated in the p+ substrate will be negligible due to a ~2 ns minority carrier lifetime). This was done in order to isolate and study the effect of the wires. We fabricated wire-array solar cells with starting micro-sphere diameters of 0.5, 1 and 2 µm, as shown in Fig 1(b). The wires form a honeycomb lattice structure dictated by the self assembled micro-sphere template with wire spacing set by the microsphere diameters. For simplicity we will refer these cells as 0.5, 1 and 2 µm wire-array cell. The resulting wire diameters at mid-height are 0.44, 0.85 and 1.65 µm, respectively, with 1.1 µm height for all samples [Fig. 1(b)]. For comparison, we also fabricated planar (control) samples that went through the same process as the wire-array cells, except that they do not have any wire-array structures.

The second part of the study is wire-texturized solar cells on MC-Si substrate. We use a lightly doped (~ 5×1016 cm-

3) p-type multi-crystalline Si wafer. The substrates were first etched with NHA (HF:HNO3:CH3COOH =2:10:5) solution to remove the surface saw damage of approximately 10 - 15 µm Si, since MC-Si wafers are typically received in as-sawn condition. We use 1 µm microsphere diameter as the wire template that yield wire diameters of ~0.8 µm [Fig. 4(a)].

Figure 2: Characteristics of the wire array single crystal silicon solar cells on 2.3 µµµµm p-/p+ Si(100) substrate: (a) light J-V characteristics, The red dotted curve represents the pseudo J-V curve of the 2 µµµµm-wire-array cell. (b) reflectivity spectra, and (c) internal quantum efficiency spectra. The highest efficiency and short circuit current are observed for the 2 µµµµm-wire-array cell.

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Figure 3: Device performance of the single crystal wire-array solar cell: (a) Short circuit current and open circuit voltage; (b) series resistance and (c) efficiency as a function of wire diameter. Series resistance is measured as a different between the light J-V curve and Jsc-Voc curve [11]. The pseudo efficiency is measured from Jsc-Voc curved measured using variable light intensity [12].

RESULTS The characterization results for the single crystal wire-array solar cell study are presented in Figures 2 and 3. From Fig. 2(a) we observe that the 2 µm wire-array cell demonstrates the highest efficiency and short circuit

current among all cells. The efficiency and short circuit data as a function of wire diameter show non-monotonic profile. This can be explained by several competing effects that are present in the wire–array solar cells. First we observe a favorable reduction in the reflectivity [Fig. 2(b)] which comes as a result of better light trapping effect with a denser and smaller wire structures on the surface. This effect primarily yield higher short circuit current. Second we observe an increase in the device series resistance [Fig. 3(b)]. This unfavorable effect happens because of the presence of the wires that perforate the emitter and contact layers (busbar or fingers) that effectively reduce their sheet resistance. This effect primarily lowers the fill factor of the cells. Nevertheless we can exclude this series resistance effect by measuring the pseudo efficiency values from Jsc-Voc data. The Jsc-Voc is measured using variable light intensity controlled by neutral density filters. The pseudo efficiency data indicates that the smallest (0.5 µm) wire array cell could also outperform the control cell in the absence of series resistance.

Figure 4: (a) SEM images of wire-texture after RIE. (b) Reflectivity of MC-Si, wire-textured MC-Si and a reference KOH-textured single crystal Si.

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The third effect is the apparent drop in the internal quantum efficiency [Fig. 2(c)] with smaller wire diameters. This effect can be associated with the reduction of the effective absorber volume. Note that in this experiment the emitter layer thickness remains fixed (~0.4 µm) as all the samples are subjected to the same POCl3 emitter layer formation step. Thus, smaller wire diameters will result in smaller photovoltaically active p- (absorber region) volume. Another detrimental factor that may contribute is the increase in the effective surface area with smaller wire diameters that will increase surface recombination and lower the quantum efficiency at short wavelengths. All these competing effects have to be considered in the process optimization to realize performance-enhancing wire-array solar cells.

Figure 5: Light J-V characteristics of the wire-textured multicrystalline silicon solar cell. Inset: Device schematic.

Table 1. Device parameters for the wire textured multi-crystalline silicon solar cells Figures 4 and 5 show the characterization results from the wire-textured solar cells on multi-crystalline silicon substrates. The wire texture is shown in the SEM micrographs in Figure 4(a). Figure 4(b) shows the

reflectivity data comparing three samples: MC-Si, wire-textured MC-Si and a KOH-textured SC-Si(100). This data shows that the wire-textured MC-Si sample demonstrates reflectivity values that are comparable to KOH-etched SC-Si control samples. Note that in the past, there have been no practical texturing method in MC-Si substrates capable of yielding reflectivity comparable to a KOH-etched Si(100) surface. Thus the wire-texturing technique demonstrated here shows a promising potential in improving the MC-Si solar cell process technology. Figure 5 shows the light J-V comparisons of the wire-textured MC-Si devices with the planar control sample. While the short circuit current of the wire sample is higher by ~20%, the fill factor and the open circuit voltage are lower. This coincidentally leads to the same power conversion efficiency as the control sample. Similar to the previous study on wire-array single-crystal Si, we observe a competing effect between the favorable increment in the shorts circuit current and the increase in series resistance that reduces the fill factor. The larger surface area of the wires also increases the surface recombination and lowers the open circuit voltage. Nevertheless if we can minimize this series resistance increase in the MC-Si wire-texturized cells, the pseudo efficiency values indicate a higher efficiency compared to that of the control sample by 16% (Table 1).

CONCLUSION

In summary, we demonstrated a simple inexpensive method for top-down fabrication of wire-texturized silicon solar cells using nano/microsphere lithography on single and multi crystalline silicon substrates. We performed systematic study of device characteristics of wire-array solar cell with various diameters on single crystal solar cell and identified three main competing effects as the wire size is reduced. First, the favorable reduction in reflectivity due to increase in light trapping effect, second unfavorable increase in series resistance that lower fill factor and third unfavorable reduction in internal quantum efficiency due to reduction of photovoltaically active absorber volume. We also demonstrated a wire array cell (with diameter 1.65 µm) that outperforms the control sample and the promising potential of wire-texturing technique for multi-crystalline Si solar cell technology.

ACKNOWLEDGEMENT We thank William Graham and IBM Microelectronics Research Laboratory for technical support in the RIE process, This work was conducted under, and partially funded by the 2008 joint development agreement between IBM Research and the Government of the Arab Republic of Egypt through the Egypt Nanotechnology Center (EGNC) - http://www.egnc-ibm.gov.eg/. The work at the University of Texas was funded in part by NSF grant DMR 0846573.

Control MC-wire

Eff. (%) 7.5 7.5 Pseudo Eff (%) 8.7 10.1 Fill factor 66 55 Voc (mV) 552 526 Jsc (mA/cm2) 20.8 25 Rs (ohm) 2.6 8.9

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