The Pseudo-Random Code Generator Design Based on FPGA

Lan Luan College of Computer Science and Information

Guizhou University Guiyang 550025, China

e-mail:chongzi_ll@163.com

Abstract—Pseudo-Random Sequence has the good property of frequency domain, based on the m sequence of pseudo-random code generated has been introduced. The 7-order pseudo-random sequence design of a FPGA program and the corresponding simulation results was given. The feasibility of design was validated.

Keywords-pseudo-random; code communication; EDA; FPGA

I. INTRODUCTION

In modern engineering practice, pseudo-random sequence is widely used in information security, digital communications, cryptography, automatic control and other areas [1]. Pseudo-random signal [2] has not only the good correlation as the random signals, but also has the regularity which another random signal does not have. Therefore, pseudo-random signal is easy to be identified and isolated from the interference signal, and they can be created and repeated conveniently. Its correlation function is close to that of white noise, and it has the advantage of the random noise, while avoid its shortcoming. Pseudo-randomness of the pseudo-random sequence finds expression in certain features in practice: It can be determined in advance, repeatable, easy to achieve coherent receiver and matching receiver, so it has a good anti-interference ability.

In spread spectrum communication system, the expansion of signal spectrum can be achieved through the spreading code, and theoretically speaking, the most ideal way to expand the signal spectrum is to use a pure random sequence. But in order to de-spread, the receiver should have a copy which in step with the spreading code of the sender. And since a purely random sequence is so difficult to reproduce, pseudo-random sequence is much more widely used as spreading codes in practical project.

II. THE RELATED TECHNOLOGIES

FPGA (Field Programmable Gate Array) [3], a product developed on the basis of the programmable devices such as PAL, GAL, CPLD, and so on, comes out as a semi-custom circuit in the field of Application-Specific Integrated Circuit (ASIC). It overcomes the shortages of custom circuits, as well as the shortcoming of limit number of gate circuits of the original programmable devices.

The current technical mainstream for the modern IC design verification is to test by way of quick burning the circuit design completed with hardware description language (Verilog or VHDL) to the FPGA through simple composition and layout. Those programmable elements can

be used to realize some basic logic gate circuits (such as AND, OR, XOR, NOT) or some even more complicated composed functions, such as decoder or math formula. In most FPGA, those programmable elements also consist of memory elements, such as Flip-flop, or other even more completed memory blocks.

FPGA adopts the concept of LCA (Logic Cell Array) and it is composed of three parts, namely CLB (Configurable Logic Block), IOB (Input Output Block) and Interconnect, as shown in Figure 1:

Figure 1. The structure of FPGA

The fundamental features of FPGA are: • Designing ASIC circuits with FPGA, the user can

obtain applicable chips without putting into production. • FPGA can be used as the pilot test sample for other full-

custom or semi-custom ASIC circuits. • There are lots of Flip-flops and I/O pins within FPGA. • FPGA is one of the elements with the shortest design

cycle, the lowest development expense and the minimum risk in ASIC circuits.

• FPGA, with low consumption, adopts high speed CHMOS technology and is compatible with CMOS and TTL electrical level.

We can say that FPGA chip is one of the optimal choices for small amount of systems to enhance systematic integration level and reliability.

The operation status of FPGA is set by the program in the RAM within the chip; therefore, the RAM in the chip should be programmed in operation. The user can adopt different programming methods in accordance with different configuration modes.

2010 International Conference on System Science, Engineering Design and Manufacturing Informatization

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DOI 10.1109/ICSEM.2010.171

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2010 International Conference on System Science, Engineering Design and Manufacturing Informatization

978-0-7695-4223-2/10 $26.00 © 2010 IEEE

DOI 10.1109/ICSEM.2010.171

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2010 International Conference on System Science, Engineering Design and Manufacturing Informatization

978-0-7695-4223-2/10 $26.00 © 2010 IEEE

DOI 10.1109/ICSEM.2010.171

292

2010 International Conference on System Science, Engineering Design and Manufacturing Informatization

978-0-7695-4223-2/10 $26.00 © 2010 IEEE

DOI 10.1109/ICSEM.2010.171

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978-0-7695-4223-2/10 $26.00 © 2010 IEEE

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When powered on, the FPGA chip will read the data in EPROM into the RAM in the chip. After configuration, the FPGA will enter the operation status. When powered off, the FGPA will return to original state, and the internal logical relationship will disappear, thus, the FPGA can be used repeatedly. The programming of FPGA needs no dedicated FPGA programmer and the general programmers like EPROM and PROM can be used. When it is required to alter the functions of FPGA, it is only required to change one piece of EPROM. So, the same piece of FPGA can generate different circuit functions with different programming data. Therefore, the usage of FPGA is very flexible.

The system designer can, as required, connect the logic blocks within FPGA via programmable connections, which is like to put a circuit breadboard into a chip. The logic blocks and connections of the delivered finished FPGA can be altered by the designer; therefore FPGA can accomplish the required logical functions.

Altera Quartus II, as a programmable design environment, is gradually welcomed by digital system designers due to its strong design ability and easy-to-use interfaces.

Quartus II design provides improved timing closure and Logic-Lock design flow based on blocks and is the only software of programmable logic device (PLD) boasting the features of timing closure and the design flow based on blocks. The Quartus II software improves the performance, enhances the functionality and solves the potential design delay, and it is the first to provide the unified workflow developed by FPGA and mask-programmed devices in the industry fields.

The Quartus II programmable logical software of Altera is the development platform of the fourth generation, which supports the design requirements in one working group environment, including supporting the cooperative design based on Internet. The Quartus platform is compatible with the developing tools of the EDA suppliers of Cadence, Exemplar-Logic, Mentor Graphics, Synopsys, etc. It improves the design function of Logic-Lock module, adds the Fast-Fit compile options, promotes the performance of web editing, and enhances the debugging ability.

The merits of such complicated digital logical system are: • The logical functions of the circuit are easy to

understand. • It is convenient for the computer to make analysis on

the logic. • The logic design and the realization of specific

circuits are operated in two separated stages. • The logic design is irrelevant with the actual

technology.• The resource accumulation of logic design can be

repeatedly used. • It is possible to design very complicated logic circuit

by many persons in a better and quicker way (the logic system with tens of thousands of gates).

The software design flow is illustrated in Figure 2 below:

Figure 2. The design process

III. RELATED THEORY

As a sequence, on the one hand, it can be predetermined, and be repeated production and reproducted; on the other hand, it also has random characteristics as some random sequences (ie, statistical property), we call it pseudo-random sequence. Therefore it can be said pseudo-random sequence is a determined sequence with some sort of random characteristics. Their sequences are generated and determined by the shift register, but they have some random features as random sequence. Because both of them are of random properties, we can not judge which one is the true random sequence or a pseudo-random sequence from the characteristics of the exist sequence, and can only reply on the method of how the sequence to be produced.

Pseudo-random sequence series have good randomness and the correlation function which is close to it of white noise, and it can be determined in advance and has the repeatability. These features make the pseudo-random sequence has been widely used, especially in the CDMA system, the spreading code has became a key issue in CDMA technology.

For the spread-spectrum pseudo-random code sequences, it should have the three characteristics as follows:

Balance: The number of statistical averages of the two kinds of elements (1,0) appearing in the sequence are the same.

Run-length features: In the sequence the elements number of run-length n is twice as much as the run-length (n + 1).

Related features: sequence has autocorrelation function similar to that of the white noise.

Binary m sequences (the longest linear shift register sequence) is a pseudo-random sequence, which has a good self-correlation function. It is a narrow pseudo-noise sequence and easy to produce and copy, so it has been widely applied in the spread-spectrum technology.

M sequence is the maximum length sequence of the linear feedback shift register, which can be identified in advance and repeatedly generate pseudo-random sequence. Shift register is composed of N tandem connected registers, a shift clock generator and the feedback logic circuit which is composed by the mode 2 summator. Each register is called a stage of the shift register, each of which can only in status of

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0 or 1. As shift clock comes, the state of each stage comes down to the next level, and then changes into a new state.

The output sequence in final stage of the shift register with a feedback logic circuit meets the feedback logic functions:

(1) )(

1n �� ��

�iniaCa

n

i

Here: stands for the operation of mode 2 addition, Ci =1 or 0 (i = 1, 2, �, n), it depends on whether i-mode participate in the operation of mode 2 addition. And the polynomial which is corresponding to the feedback logic function is called the characteristic polynomial of this feedback shift register, the expression is as follows:

(2) ��

�n

i

iixCxf

1)( )1,1( 0 �� nCC

When the characteristic polynomial is the primitive polynomial, the sequence generator will become m-sequence generator with the longest period. And the relationship between its period T and the order of n is as follows:

12 �� nT . The primitive polynomial can be found in tables. Knowing the primitive polynomial of m-sequence, we can determine the feedback logic function which generates this sequence. Generating m-sequence should also have a corresponding initial value of the shift register, that is, a primitive polynomial and the corresponding initial value of shift register determine a m-sequence. By changing the initial value (all 0 except for) of shift register can get different m-sequence.

In this system, we select the 127th m-sequence as the design of Pseudo-code generator. In practical application, we need to set the initial phase of m-sequence and primitive polynomial of the produced m-sequence. Therefore, in the design of m-sequence, tap coefficients at each level should be designed to be steerable, and the initial state of shift register can be loaded by a group of registers. Usually we storage the tap coefficients and the initial phase respectively by two sets of registers, and they were defined as the tap coefficient registers and the phase registers.

IV. FPGA DESIGN

In this structure, there are two types of data registers (tap coefficient register and phase registers) and the corresponding controlling signal, and all the registers are of 7-bit width [4]. When the enable signal of the phase registers is valid, the initial phase will be loaded into the shift register; while the write signal of the phase register is valid, the external input phase data will be stored. For tap coefficient register, we can make a different setting of tap coefficients by writing the signals, so as to set a different primitive polynomial.

In order to achieve spread-spectrum modulation, the common practice is to make a mode 2 plus for high-speed pseudo-code sequence and low-speed symbol sequences (the data waiting to be sent), and the transmitter work is in the symbol synchronization modulation mode. In other words, pseudo-code sequence is aligned with symbol-level in each

bit, and there is a complete pseudo-code period within each symbol. In this system, the data rate of the pseudo-code is 4.064Mbps, the rate of the symbolic sequence is 32Kbps, and through the spread-spectrum modulation, the spread-spectrum code sequence is changed into 4.064Mbps.

Figure 3. The implemented structure: RTL of Pseudo-code generator

V. SIMULATION VERIFICATION

Figure 4 is the result obtained from the simulation by using the model, in which clk_32k_all is the data clock, origin_data is a pre-symbolic spread-spectrum data, mout is the 127th m sequence to generate a polynomial--

7 6( ) 1g x x x� � � , post_data is the data after spread-spectrum. We can find it completely meets the design requirement .

Figure 4. Simulation map of Pseudo-code generator

VI. CONCLUSIONS

This thesis proposes the design based on pseudo-random code generator based on PFGA, and makes use of ideology of m sequence to achieve the generation and spread-spectrum of 7-band pseudo-random code. The experimental results are satisfactory, which indicates that the scheme is feasible and will be more easily used in practical application.

REFERENCES

[1] X. X. Niu, and Y. X. Yang, “Technology and application of software radio”, Beijing University of Posts and Telecommunications Press, Beijing, 2005.

[2] M. Naor and O. Reingold, “Number-theoretic constructions of efficient pseudo-random functions”, Journal of the ACM, pp.1-40, 2004.

[3] I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” in Proc. ACM/SIGDA 14th Int. Symp. FPGA, pp. 21–30, 2006.

[4] S. J. Wilton, N. Kafafi, et al, “Design considerations for soft embedded programmable logic cores,” IEEE J. Solid-State Circuits, Vol. 40, No. 2, pp. 485–497, Feb. 2005.

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