Fully-Integrated, Large-Time-Constant, Low-Pass, Gm-C Filter Based on Current Conveyors

Mohammad Hossein Maghami1, and Amir M. Sodagar1,2 1Integrated Circuits and Systems Lab., ECE Department, K.N. Toosi University of Technology, Tehran, Iran

2Ecole Polytechnique de Montreal, Montreal, Quebec, Canada E-mails: mhmaghami@ieee.org, amsodagar@eetd.kntu.ac.ir

Abstract— This paper describes a low-power fully integrated CMOS low-pass filter with extremely low cut-off frequency range for use in implantable biomedical applications. The filter takes advantage of system-level properties of applying indirect negative feedback on an OTA to realize a low-cut-off frequency. It also features active capacitance multiplication using a second-generation current conveyor. Both of these techniques help reduce the silicon area of the proposed low-pass filter. Based on the proposed idea, a 1st-order low-pass Gm-C filter was designed in a 0.5-µm standard CMOS process, occupying a core area of 0.0048mm2. Cut-off frequency of the filter is tunable from 0.75Hz to 9.4Hz. Operated with ±1.5V supply voltages, power consumption of the filter ranges from 50nW to 740nW.

I. INTRODUCTION Low power dissipation and small chip area are among the

key requirements in circuit design in many advanced application areas, such as embedded sensor interfaces and implantable biomedical devices [1]. One of the key building blocks for analog signal processing in such systems is integrated filters. Design of fully integrated analog filters becomes challenging when they are expected to provide low-frequency, low-voltage, and low-power operation at the same time [2]-[3]. In general, low-frequency filters are realized in both discrete and continuous time. Discrete-time low-frequency filters are designed using switched-capacitor (SC) methods [4]. SC techniques suffer from clock feedthrough, leading to rather small dynamic ranges. Furthermore, large capacitor ratios are required in SC implementations for very large time constants [4], [5], which usually results in not so small chip areas. Gm-C filters, on the other hand, exhibit convincing potential to fulfill the low power consumption and small chip area requirements [6], [7].

In general, high cut-off frequency of a 1st-order low-pass Gm-C filter (LPF) is set by the Gm/C ratio. To achieve very large time constants in the order of up to seconds (i.e., high cut-off frequencies down to as low as tenths of Hertz) different design techniques have been reported. Employing extremely low-Gm OTAs [7], current division [2], current cancellation [8], indirect feedback [9], and impedance scaling [10], [11] are among the design techniques reported in the literature for this purpose.

This paper introduces a fully-integrated Gm-C leaky integrator, functionally equivalent to a 1st-order LPF. The proposed circuit takes advantage of a proper combination of system-level properties of indirect negative feedback and impedance scaling in order to realize a very large time constant.

Figure 1. Closed-loop Gm-C leaky integrator

Figure 2. a) Block representation of the proposed idea, b) The two-stage

two-output OTA block diagram proposed in [9]

II. THE PROPOSED LOW-PASS FILTER Figure 1 shows a simple 1st-order Gm-C LPF, comprised

of an OTA in a unity-gain negative feedback loop and a capacitor connected at the output. As a result of applying voltage-series negative feedback, the equivalent resistance seen by the capacitor is the output resistance of the closed-loop amplifier, RO,CL, which is usually much smaller than the open-loop output resistance, RO,OL. Hence, to realize an LPF with a low cut-off frequency a very large capacitance will be needed, which cannot be easily implemented on chip.

Figure 2(a) illustrates the idea proposed in this paper to achieve a very large time constant in the order of around one second. The proposed integrator comprises a two-output OTA (TO-OTA) with the indirect feedback technique proposed in [9] followed by an active unity-gain capacitance multiplier. The first block is used to provide extremely large output resistance and the second stage multiplies the integrating C by a certain magnification factor, explained later in this section.

978-1-4577-1846-5/11/$26.00 ©2011 IEEE 281

1( )C Sαβ

xrαβ ||z yr r

Figure 3. a) Active capacitance multipication, b) Simplified model for the

equivalent input impedance for the circuit shown in part (a)

Figure 4. The two-stage TO-OTA introduced in [9]

As shown in Fig. 2(b), the OTA is designed with two identical output stages, A3 and A2. One of the outputs, Out1, is used to make a negative feedback loop around the OTA, and the other, Out2, is used as the main output. This way, the circuit benefits from system-level properties of applying negative feedback (e.g., insensitivity to variations in the internal parameters of the open-loop circuit) without having to have drastic reduction in the output resistance.

Figure 3(a) shows the capacitance multiplier circuit adopted from [10]. The circuit is based on a negative-gain second-generation current conveyor (CCII-) [12]. As is common, the CCII- used in this design comprises three input-output nodes: X input low impedance), Y input high impedance) and Z output high impedance). Electrical behavior of the CCII is described as:

0 0 0 0 0

0 0

Y Y

X X

Z Z

I VV II V

αβ

⎡ ⎤ ⎡ ⎤⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥=⎢ ⎥ ⎢ ⎥⎢ ⎥⎢ ⎥ ⎢ ⎥⎢ ⎥⎣ ⎦⎣ ⎦ ⎣ ⎦

(1)

where α is the tracking error factor (≈1), and β is the current gain between nodes X and Z (which is negative for a CCII-).

Taking into account the finite output resistance at X, Y and Z nodes, rx, ry and rz, respectively, equivalent input impedance of active capacitance multiplier of Fig. 3(a) is derived as:

1( ) || ||Y xEQ z y

IN S

V rZ r rI s Cαβ αβ

= = + (2)

in which, parasitic capacitances at nodes Y and Z have been neglected. Figure 3(b) gives the simplified model of equivalent input impedance seen from Y node. According to Eq. (2), the output-input signal transfer function of the proposed filter shown in Fig. 2 (a) will be:

(1 )

( ( ))1

CCS x

Out CC Ox xIn S CC O CC

CC O

r sC rV r R

r rV s C r R r

r R

αβαβ αβ

++=

+ ++

+

(3)

where RO is the output resistance of the OTA seen from Out2,

TABLE I. DIMENSIONS OF TRANSISTORS FOR THE TO-OTA AND CCII- CIRCUITS SHOWN IN FIGURES 4 AND 5

Transistor W/L (µm)/(µm) Transistor W/L (µm)/(µm) CCII- TO-OTA

M1,2 3.5/1.05 Mo1,2 3.5/1.05 M3,4 1.75//1.05 Mo3,4 1.75/1.05 M5r,6r 1.925/1.4 Mo5,6 2.8/1.05 M7r,8r 1.75/1.4 Mo7,8 1.75/1.4 M5,6 8.75/1.4 Mo6r 2.8/1.05 M7,8 5.075/1.4 Mo8r 1.75/1.4 M9,10 1.75/0.875 Mo9,10 1.75/0.875

and rCC is the parallel equivalent resistance of ry and rz modeling the finite input resistance of the current conveyor. Since RO and rCC are set to be larger than the finite input resistance at X node, and also because of the typically large enough αβ factor, Eq. (3) can be simplified to:

(1 )

1

CCS x

Out CC O

S O CCInCC O

r sC rV r R

s C R rVr R

αβ

++=

++

(4)

where xCC

rrαβ

and xO

rRαβ

are set to be smaller than O CCR r .

The transfer function in Eq. (4) introduces a pole located at 1

||S O CCC R rαβ− and a zero at 1

S xC r− . As the value of rx is

designed to be orders of magnitude smaller than ||O CCR r , the effect of the zero in the transfer function can be neglected and the Eq. (4) can be approximated as:

1 ( || )

CC

Out CC O

In S CC O

rV r RV s C r Rαβ

+≅

+ (5)

DC gain of the filter is determined by rCC and RO values and

the cut-off frequency of the filter is 1( || )S CC OC r Rαβ

.

III. CIRCUIT DESIGN A. The TO-OTA

Figure 4 shows the circuit schematic of the TO-OTA used in this work, adopted from [9]. According to Fig. 2 (b), output resistance of the circuit in a negative feedback configuration is:

6 8||O Oo OoR r r= (6) To achieve a very high output resistance for the circuit in the order of Giga Ohms, careful channel length sizing and bias current setting for the output transistors, Mo6 and Mo8, is of crucial importance. Channel sizing for the transistors used in the TO-OTA as well as those for the CCII- circuit, introduced later, are presented in Table I. Bias current for the TO-OTA, Ibias, can be set within the 2nA-50nA range in order to set the output resistance, RO, anywhere from 1.7GΩ to 46GΩ.

B. CCII- Circuit schematic of the CCII- designed for this work is

shown in Fig. 5. Design of this circuit is inspired from the TO- OTA of Fig. 4. Transistors Mo6 and Mo8 in the TO-OTA are replaced by M5 – M8 to obtain a current gain greater that unity.

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Figure 5. Current conveyor used in the capacitance multipier circuit

Figure 6. Transfer charestristic curve between nodes X and Y

It can be shown that in this circuit, β can be written as a function of circuit parameters as:

7 5

6 8

m m

m r m r

g gg g

β +=+

(7)

Hence, as a straightforward design choice to achieve β > 1, channel aspect ratios (W/L) for M5 and M7 need to be larger than those for M6r and M8r in Fig. 5.

To force the voltage at X be close enough to that of Y, as stated in Eq. (8), i.e.:

X YV Vα= (8) where α ≈ 1, internal negative feedback is used. The feedback mechanism returns the voltage at the drains of M6r and M8r denoted as node A in Fig. 5 to the input node X. This internal feedback also reduces the input resistance seen at node X, rx. The proposed CCII- circuit is designed for low-voltage operation by stacking no more than three transistors between the supply rails -VSS and VDD. Having the sources of all the NMOS transistors in the circuit tied to -VSS means that, designed in an N-well CMOS process, the circuit does not suffer from the body effect. This way, threshold voltages of all transistors are at minimum, making the circuit appropriate for low-voltage operation.

A. The Integrator Connection the OTA with indirect feedback and the

capacitance multiplier circuit together, an integrator is designed for a high cut-off frequency tunable in the range of below 1Hz to around 10Hz. The value of rCC is set to be around 33GΩ. Tunable by the bias current, Ibias, ranging from 2 to 50nA, equivalent resistance at the output of the integrator

Figure 7. Currents at input node X and output node Z in the time domain in the case of a 0.6-V(p-p), 100-Hz sin. input voltage applied to input node Y.

Figure 8. Frequency response of the proposed LPF.

ranges from 1.6GΩ to 19.2GΩ. Hence, to achieve the high cut-off frequency in the aforementioned range, a total capacitance of 10pF will be required. Employing the CCII-based capacitance multiplier shown in Fig. 3 (a) with a magnification factor of α.β = 7.6, an actual 1.35-pF capacitor was used. This is while, for instance, the traditional Gm-C configuration of Fig. 1(a) demands for a capacitance in the range of 8-80nF, or the idea presented in [9] requires a 10-pF capacitor to provide almost the same frequency response.

IV. SIMULATION RESULTS The 1st-order Gm-C LPF proposed in this paper was

designed in a 0.5-µm standard CMOS process. Figures 6 and 7 show the behavior of the current conveyor circuit operating with ±1.5V supply voltages according to which, α and β are determined, respectively. Slope of the static characteristic curve presented in Fig. 6 represents the α parameter, which is 1.00 over a wide input dynamic range (from -1.5V to 1.05V). According to the time-domain operation of the circuit, shown in Fig. 7, current gain of the proposed CCII-, β, is 7.6 as was already set in the design of the circuit.

Figure 8 shows the frequency response of the proposed LPF circuit for different external bias currents ranging from 2nA to 50nA, according to which, DC gain of the filter varies from -0.4dB to -7.4dB. DC gain variations are caused by RO changes, which is itself a function of Ibias.

In order to observe the operation of the proposed integrator in the time domain, a square-wave input with peak-to-peak amplitude of 700mV and frequency of 100Hz is applied to the circuit (Ibias= 30nA). The result is a triangular output waveform plotted in Fig. 9. Figure 10 shows the physical layout of the proposed LPF. Silicon area occupied by the core

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Figure 9. Response of the integrator circuit to a square wave input

Figure 10. The LPF layout

TABLE II. PERFORMANCE SUMMARY FOR THE PROPOSED LPF

Ibias (nA) Power Cons. (nW) DC Gain (dB) Cut-off Freq. (Hz)2 50 -7.4 0.75 5 92 -3.7 1.3

10 163 -2 2 20 307 -1.1 3.8 50 740 -0.4 9.4

circuit including the 1.35-pF integrating capacitor is 0.0048mm2 (which is still smaller than that of a 10-pF capacitor alone in this process).

Performance summary of the proposed LPF is reported in Table II. Table III compares the performance of the integrator proposed in this paper with some of the integrators reported for almost the same frequency range.

V. CONCLUSIONS A new continuous-time Gm-C LPF with a very low cut-off

frequency range is reported. To realize the proposed idea on a small chip area, two techniques are employed:

TABLE III. COMPARISON WITH OTHER LPF DESIGNS

Ref. Filter Order

Cut-off Freq. (Hz)

Int. C per Pole

(pF)

Power Cons. (µW)

CMOS Fab.

Process

SiliconArea

(mm2) [6] 6 2.4 5 10 0.8 µm 1 [7] 1 0.1-5 70 0.23-1.6 0.8 µm 0.1 [8] 1 0.06-1 47.5 0.075-7.5 0.8 µm 0.06 [9] 1 20 5 N/A 0.5 µm N/A [10] 1 1 100 N/A 0.5 µm N/A [11] 5 2.4-10k 80.44 28 0.35 µm N/A [13] 2 1.5-15 52.5 165-1650 0.35 µm 0.336 [14] 2 1.4-15 11.2 25.1 90 nm N/A [15] 1 2m-90 40 0.005-0.1 0.35 µm 0.07 This

Work 1 0.75-9.4 1.35 0.05-

0.740 0.5 µm 0.0048

- Large output resistance for the circuit is achieved by applying indirect negative feedback, and

- Large equivalent capacitance is implemented using a CCII-based capacitance multiplier circuit.

Fully integrated implementation, small chip area, low power dissipation, and circuit configuration with no body effect for all the transistors are among the more important features of the proposed integrator.

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