Design of a PJM Mode Tag

Youn Jaehyuk Department of Wireless Communications Engineering

Kwangwoon University Seoul, Korea

hyuk329@kw.ac.kr

Yang Hoongee Department of Electronics Convergence Engineering

Kwangwoon University Seoul, Korea

hgyang@kw.ac.kr

Abstract—This paper presents a receiver structure for a PJM mode tag and its implementation results. To acquire the simplicity of a tag receiver, especially a synchronizer, some additional blocks other than correlators, such as initial time selector (ITS) and violation bit detector (VBD), are required. Performance is examined by simulation and its hardware is verified through a synthesized register transfer level (RTL) implementation.

Index Terms—RFID, PJM mode, Bit synchronization, Violation bit

I. INTRODUCTION Phase jitter modulation (PJM) mode is one of the

international standards for a RFID operating in high frequency (HF) Band. As it uses multiple channels, unlike a amplitude shift keying (ASK) mode, it can provides a high speed reading [1]. On the other hand, since information is embedded in phase, the PJM tag should discriminate two signals whose phases differ at most 12 degree, while achieving synchronization. What is worse, the hardware simplicity of the tag should be assured, such as limitation in the number of correlators and analog-to-digital converter (ADC) sampling rate, etc.

In this paper, we present a receiver structure for a PJM tag that can be implemented with limited hardware complexity and show the results of its register transfer level (RTL) implementation. In Sec. II, we present functional blocks constituting a receiver and verify their operations by Modelsim simulation. Finally, conclusions are followed.

II. IMPLEMENTATIONS Main function of a tag receiver is to bit-synchronize and

demodulate a command signal which comes after the continuous wave (CW) period. Figure 1 shows a block diagram of the proposed receiver.

A. Initial Time Selector For the incoming CW, the initial time selector (ITS) makes

sampling at a rate such that one period of 13.56 MHz carrier is the integer multiple of ITS sampling period. ITS plays a role of choosing one sampling point at which the voltage of CW is closer to zero than the voltages at any other points [2]. Once it chooses the optimum sampling point, it samples the incoming signal once per period of a carrier and transmits the sampled sequence into a correlator 1.

B. Correlator 1 In ISO 18000-3 mode 3, all commands transmitted between

a reader and a tag are preceded by modified frequency modulation (MFM) flag shown in Fig. 2. Figure 3 (a) is the block of the correlator 1, shown on Quartus RTL Viewer and Fig. 3 (b) is the output of the correlator 1 obtained by the timing simulation. The correlator 1 performs the correlation with a template which is the sampled version of synchronizing string within the MFM flag. When the correlator 1 begins receiving the samples of a command preceded by the MFM flag, a sequence of peaks appears at the output of the correlator 1, as shown in Fig. 3 (b). A peak detector cascaded with the correlator 1 functions to detect a peak. As long as the peak detector finds any peak such as #2 or #3 in Fig. 3(b), it triggers a demodulator.

(a) (b) Fig. 3. (a) Correlator 1 block, (b) Output of correlator 1

Fig. 2. MFM flag

Fig. 1. Block diagram of tag receiver

978-1-4673-4728-0/12/$31.00 ©2012 IEEE APCC 2012992

C. Demodulator Under noise-free condition, a demodulator receives a

sequence of patterns that correspond to the discrete version of the MFM-encoded waveforms [3]. For example, a demodulator receives 64 consecutive samples of equal values for data bit “0”. For data bit “1”, due to the MFM encoding, it receives 32 consecutive samples of equal positive constant followed by 32 negative constant, or vice versa. Thus, we can design an optimum receiver for this input sequences as shown in Fig. 4 where discrete templates for correlations are indicated. The decision block outputs an estimated symbol d

) and an

estimated state S)

simultaneously by applying the following decision rule, which can easily be deduced from the MFM encoding waveform in [2]:

if 1 2 0X X+ > & 1 2 0X X- > , d)

=1, 2S S=)

if 1 2 0X X+ > & 1 2 0X X- < , d)

=0, 1S S=)

if 1 2 0X X+ < & 1 2 0X X- > , d)

=0, 4S S=)

if 1 2 0X X+ < & 1 2 0X X- > , d)

=1, 3S S=)

where 1X and 2X are the outputs of upper and lower correlator branches, respectively.

For the input d)

, the finite state machine which implements the MFM signaling state diagram, deduces a proper state for d

),

called FS . A violation bit detector (VBD) compares S)

with

FS to acknowledge the occurrence of a violation bit. Suppose a command signal with MFM flag shown in Fig. 5 is received at tag receiver. As soon as the peak detector finds a peak and triggers the demodulator, it outputs d

) and S

). Up to 14th bit

of a MFM flag, FS equals to S)

as long as d)

and S)

are correctly estimated. For 15th bit of “0”, the FS will be 1S

while the estimated state S)

is 4S . The VBD informs the demodulator of the occurrence of state discrepancy and a demodulator can expect a payload to start in one bit duration corresponding to trailing zero bit (see Fig. 5).

Figure 6 shows the result of the timing simulation for a command with payload data “01000011” when signal-to-noise ratio (SNR) is -4dB. It shows that #3 peak was detected and the start of payload was correctly found and demodulated bit sequence coins with original bit sequence.

Figure 7 is the synthesized overall receiver block. To generate a reader command, we also implemented a reader on the FPGA board. The generated PJM signal was introduced into the receiver through “ADC_input”.

III. CONCLUSIONS This paper presented a receiver structure and its hardware

implementation for the PJM mode tag. Initial synchronization was achieved through a correlator, along with a peak detector. As soon as a peak was detected, it triggered a demodulator. The demodulator, which turned out to be a matched filter, was also used to correctly estimate payload start. The entire receiver block was implemented on FPGA board.

ACKNOWLEDGMENT This research was supported by the MKE, Korea, under the

ITRC support program supervised by the NIPA (NIPA-2012-H0301-12-1001) and by Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education, Science and Technology (2011-0027107).

REFERENCES [1] Y. Nakagawa, M. Muraguchi, H. Kawamura, K. Ohashi, K.

Sakaguchi, K. Araki, “Novel multi-stage transmultiplexing digital down converter for implementation of RFID (ISO 18000-3 mode 2) reader/writer,” IEEE Int. Conf. on Vehicular Technology, April 2007.

[2] J. H. Youn, H. G. Yang, “Sampling based demodulation of RFID-PJM mode,” KICS, vol. 35, pp. 117–124, January 2010.

[3] Information technology ― RFID for item management ― Part 3: Parameters for air interface communications at 13.56MHz, ISO/IEC WD 18000-3 REV2, 2008.

Fig. 7. Synthesized receiver block

Fig. 6. Timing simulation waveform

Fig. 5. Command precede by MFM flag

Fig. 4. Demodulator block

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