ieee uhf receiver f

7/22/2019 Ieee Uhf Receiver f

1/14

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 2, FEBRUARY 2012 197

UHF Receiver Front-End: Implementation andAnalog Baseband Design Considerations

Raghavendra Kulkarni, Student Member, IEEE, Jusung Kim, Student Member, IEEE, Hyung-Joon Jeon,Jianhong Xiao, and Jose Silva-Martinez, Fellow, IEEE

AbstractAn integrated ultrahigh-frequency (UHF) receiver ispresented. A systematic analysis to quantify the interdependenceof baseband filter and analog-to-digital converter (ADC) dynamicrange in broadband receivers is presented. This analysis showsthat: 1) low-order Butterworth filters are favorable when unde-sired power is dominated by far out blockers and 2) high-orderinverse Chebyshev filters can reduce the resolution of a subse-quent ADC by up to two additional bits in the presence of adjacentanalog narrowband blockers. Based on the analysis, a cascaded,programmable, hybrid active-RC and switched-capacitor (SC)baseband filter is proposed. An all-digital nonoverlap clock tuningsystem to minimize the variation of available settling time window

in SC circuits is also proposed. The receiver integrates the pro-posed filter with an RF variable gain amplifier (RFVGA) and apassive mixer. This receiver achieves a measured noise figure of7.9 dB, an IIP3 of 8 dBm at maximum gain and 2 dBm at 9-dBRF attenuation. The chip consumes 120 mW (RFVGA, mixer andI-channel baseband) from 1.8-V analog/2.5-V digital dual supplyand occupies 2.14 mm

in IBM 0.18- m RF CMOS technology.

Index TermsActive balun, analog baseband, broadband re-ceiver front-end, continuous-time filters, RF CMOS, switchedcapacitor filters, ultrahigh-frequency (UHF) receiver.

I. INTRODUCTION

DEMAND for data, audio, and video on mobile devices

continues to rise with the increasing popularity ofmultimedia enabled handsets. A low-cost, high-performance

broadband receiver is critical for such handsets. Several stan-dards suitable for broadband consumer wireless applicationshave emerged (e.g., DVB-H standard for ultrahigh-frequency(UHF) spectrum (470862 MHz) [1], [2]). While some of the

earliest UHF receiver solutions were implemented in BiCMOSprocesses [3][5], the trend is to integrate these receivers inCMOS [6][9]. To this end, we present a CMOS UHF broad-band receiver with an analysis of design considerations for itsanalog baseband.

The key contribution of this paper is an analysis of inter-

dependence between the baseband filter and analog-to-digitalconverter (ADC) dynamic range (DR) requirement for a broad-

band receiver. High-DR ADCs (for a given bandwidth) demand

Manuscript received May 07, 2010; revised August 18, 2010; acceptedNovember 01, 2010. Date of publication December 30, 2010; date of currentversion January 18, 2012. This work was supported in part by the BroadcomFoundation.

R. Kulkarni, J. Kim, H.-J. Jeon, and J. Silva-Martinez are with the Analogand Mixed Signal Center, Department of Electrical and Computer Engi-neering, Texas A&M university, College Station, TX 77843 USA (e-mail:[email protected]; [email protected]; [email protected];

[email protected]).J. Xiao is with the Broadcom Corporation, Irvine, CA 92617 USA (e-mail:

[email protected]).

Digital Object Identifier 10.1109/TVLSI.2010.2096438

a steep 24 increase in power consumption per every addi-tional bit in resolution [10], [11]. This significant increase in

ADC power consumption justifies a systematic evaluation of theeffect of filtering on ADC DR. This work quantifies impact ofadjacent channels (digital or analog modulation) on filter-ADC

DR interdependence for Butterworth and inverse Chebyshev fil-ters. Analysis reveals that: 1) low-order Butterworth filters arequite efficient when the undesired power is dominated by far outblockers and 2) high-order Inverse Chebyshev filters can offerup to 12 dB additional reduction in ADC DR ( in power

consumption) compared with Butterworth filters in the presenceof analog modulated narrowband adjacent blockers. Based onthis analysis, a hybrid analog baseband low-pass filter parti-tioned into a combination of continuous- and discrete-time fil-

ters is proposed. The analog baseband output can be tapped fromeither the continuous- or the discrete-time section depending onthe filtering requirement in the receiver system. An all-digital

nonoverlap time tuning scheme to minimize the uncertainty inthe time available for settling is also proposed.

A direct-conversion receiver architecture as shown in Fig. 1 isadopted for analysis and implementation. The key system spec-

ifications (sensitivity level and signal-to-noise ratio (SNR) fordifferent modulation schemes) pertinent to UHF receivers arealso included in Fig. 1 [3]. The receiver has a single-ended RFinput and uses a broadband RF variable gain amplifier (RFVGA)to provide gain-independent matching [12], [13]. The single-to-

differential signal conversion is accomplished on-chip by two(I&Q) linear transconductors which in turn drive passive cur-rent-mode mixers.

The paper is organized as follows. Interdependence betweenbaseband filter and ADC DR is analyzed in Section II. Cir-cuit analysis and implementation are provided in Section IIIand experimental results in Section IV. Section V presents the

conclusions.

II. INTERDEPENDENCE OF BASEBAND FILTER

ANDADC REQUIREMENTS

Analog baseband performs two tasks: 1) filter undesired ad-jacent blocker power and 2) deliver constant power to the ADCwith sufficient signal-to-noise-and-distortion ratio (SNDR). For

a given input signal and blocker profile, choice of the basebandfilter (order and approximation) determines the required ADCDR.

ADC DR should exhibit the following characteristics.1) The ADC DR should be greater than the minimum DR

set by the SNR requirement of the modulation

scheme plus a design margin to minimize the SNR loss due

1063-8210/$26.00 2010 IEEE


2/14

198 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 2, FEBRUARY 2012

Fig. 1. Direct-conversion broadband UHF receiver architecture.

to quantization noise. For this work, is 44.8 dB setby 24.8-dB SNR plus a 20-dB margin [14][16].

2) It should accommodate the peak-to-average ratio (PAR) of

the received signal.3) It should include the desired signal power variation that is

not covered by automatic gain control (AGC).4) The ADC DR should accommodate the residual undesired

power at the ADC input after the channel select filter.

5) It should meet the outband linearity performance require-ment based on the residual blocker power.

In addition, the minimum sampling frequency of the ADC

should be chosen to keep the undesired aliased signal powerbelow the desired signal power by at least .

The effect of Butterworth filter order on sampling frequencyand resolution of the ADC has been analyzed in [17]. In this

paper, we focus on item 4) above and quantify the componentof the ADC DR required to accommodate the residual undesiredpower for Butterworth and Inverse Chebyshev filters with orders

ranging from 3 to 8.1 These two filters are chosen so that we cancompare the impact of an all-pole approximation (Butterworth)and an approximation with poles and stopband zeros (Inverse

Chebyshev). The residual power evaluation is performed forboth digital and analog adjacent channels as undesired blockers

in the UHF spectrum can employ either modulation scheme. Inanalog channels, the bulk of the signal energy is concentratednear the carrier, resulting in strong peaks. In contrast, the energyin a multicarrier modulated digital channel is spread smoothly

across the channel [18]. Understanding the impact of this differ-ence is important as analog modulation techniques continue tobe used along with digital broadcast [19]. The following anal-

ysis will show that the higher order inverse Chebyshev filtersperform better at reducing the undesired power in the presenceof analog adjacent channels.

1

A first-order pole is added to an 0

th inverse Chebyshev filter forcomparison to th-order Butterworth filter. This addition improves the high-fre-quency attenuation for even-order inverse Chebyshev filters.

A. Residual Undesired Power From Digital Adjacent Channels

To evaluate the residual undesired power for digital channels,the baseband input spectrum is modeled as shown in Fig. 2.

From Fig. 2, we observe the following. The input power spectral density (PSD) is defined

for a broadband frequency range . Subcarriers inthe input spectrum are separated by , resulting in

total subcarriers.

The desired channel resides in a single-sided bandwidthof with subcarriers in and a guardband with zero power carriers. Each undesired channelhas a two-sided bandwidth of with subcarriers in

. The input subcarrier power in the desired channel is set

to . The power of subcarriers in the first adjacent

channel (referredas the channel)is set dBhigherthan . For the remaining undesired channels

, the power of subcarriers is dBhigher than thedesired channel ( denotes ).

Total integrated input power is

(1)

This input spectrum is filtered using a transfer function .Hence, the integrated output power within a frequency range

is

(2)

Using (2), integrated power in the desired channel ,the residual integrated power due to the channel

, and the residual integrated power due to all theundesired channels are evaluated as indicated in


3/14

KULKARNI et al.: UHF RECEIVER FRONT-END: IMPLEMENTATION AND ANALOG BASEBAND DESIGN CONSIDERATIONS 199

Fig. 2. Baseband input spectrum with digital adjacent channels.

Fig. 3. Output power density and definitions of integrated power in the desired channel, residual adjacent channel, and residual power in all undesiredchannels.

Fig. 4. Residual dynamic requirement for digital adjacent channels with (a) Butterworth filter and (b) inverse Chebyshev filter.

Fig. 3. To quantify the component of the ADC DR requiredto accommodate the channel residual power and total

residual power, we evaluate

(3)

(4)

We find and for But-terworth and inverse Chebyshev filters as the first adjacent

channel power changes relative to the desired power (indi-cated by dB). Corner frequency is set to 4 MHz for both

TABLE IPARAMETERSUSED FOR THEANALYSIS

the filters. Subcarrier powers , , and are suitablyadjusted to maintain fixed input power 6 dBm with

dB 45 dB. Values of the other parameters are indicatedin Table I. Fig. 4 shows and

for filters of order 3 to 8 as dB is varied from 10 to40 dB in 10-dB step size. As expected, Fig. 4 indicates that

the residual DR requirement for the ADCreduces with increasing filter order.


4/14


Fig. 5. Analog adjacent channels with single analog carrier per channel.

The two important observations from Fig. 4 are given here.1) If the undesired input power is dominated by

channels dB 10 dB , then the first adjacent channelpower is easily filtered by both Butterworth and inverseChebyshev filters. In this case, lower order Butterworth fil-

ters (35) are quite effective compared with inverse Cheby-shev filters.

2) If the undesired input power is dominated by thechannel dB 40 dB , then

. In this case, both Butterworth and in-

verse Chebyshev filters have comparablerequirement from the ADC.

B. Residual Undesired Power From Analog Adjacent Channels

Compared with digital channels, analog channels use twonarrowband carriers (one for video and one for audio) located

within the channel bandwidth. The video carrier is 13 dB higherthan the audio carrier and is located closer to the passband edge[2]. Hence, a single worst-case carrier at from the edge

of the channel is modeled as shown in Fig. 5. For fair compar-ison, the input power of the single carrier is set equal to the in-tegrated power from the undesired digital channel. As indicatedin Fig. 5, the power of the analog carrier in the adjacent

channel and remaining channels is

(5)

(6)

Similar to the previous analysis, dB measures the differ-ence in the desired and undesired first adjacent channel input

power. As the requirement for worst case

high dBvalues is dominated by , the dif-ference in the performance of the two filters is highlighted with

. For 1.25 MHz,for Butterworth and inverse Chebyshev filters are evaluated,

and the results are shown in Fig. 6. The key observations aregiven here.

1) For lower filter orders (3 to 5), both Butterworth and

inverse Chebyshev filters provide similar attenuationfor the adjacent analog channel leading to comparable

requirement from the ADC .2) For higher order inverse Chebyshev filters (7 and 8), the

is 12 dB lower than that for Butterworthfilters. This improvement results from the sharp transition

band and nulls in the transfer function due to stopbandaxis zeros in the inverse Chebyshev approximation.

Fig. 6. Residual dynamic range for the analog adjacent channel.

Fig. 7. Estimated ADC power consumption (for 4-MHz bandwidth) based on

the survey data in [11].

In general: 1) low-order Butterworth filters are more efficient atreducing the undesired blocker power when it is dominated by

far out blockers for both digital and analog modula-tion; 2) Butterworth and inverse Chebyshev filters provide com-parable performance when the residual power is dominated by

the channelwithdigital modulation; and 3)higherorderinverse Chebyshev filters (orders 7 to 8) are more favorable thanButterworth filters when the residual power is dominated by the

channel with analog modulation.

The drop in the required ADC DR due to filtering translates

to reduction in ADC power consumption. ADC power con-sumption has a strong structural dependency [20]. Accordingto [10], the power efficiency of the ADC for a given SNDR canbe predicted using power per conversion bandwidth

metric. Published ADC data indicate that increasesapproximately at per additional bit but may approachper additional bit for noise limited high-DR ADCs [10], [11].

Based on the survey in [11], we estimate the power consump-tion of a 4-MHz signal bandwidth ADC as shown in Fig. 7.This estimation shows that drop in ADC power consumptiondue to filtering depends on the targeted SNDR and filtering can

result in significant ADC power saving for high SNDR ranges.Low-order Butterworth filters fare better than low-order inverse

Chebyshev filters if the undesired power is dominated by far outblockers. However, in the presence of strong blocker,


5/14


Fig. 8. Analog baseband architecture.

TABLE IIDESIREDBLOCKLEVELSPECIFICATIONS

TABLE IIIPOLE-ZEROPLACEMENT FOR EIGHTH-ORDER INVERSECHEBYSHEVAPPROXIMATION (3/4-MHz BANDWIDTHSETTING)

high-order inverse Chebyshev filters have either similar (digital

blocker) or better (analog blocker) performance than Butter-worth approximation of the same order. As quantified by the

previous analysis, inverse Chebyshev filters offer up to 12 dBadditional ADC DR reduction in the presence of strong analogadjacent blockers. Hence, to tolerate the presence of strong

adjacent channels (both analog and digital), inverseChebyshev approximation is chosen for implementation in thiswork.

III. CIRCUITIMPLEMENTATION

System simulations are performed using cascaded NF andIIP3 equations to maximize the receiver dynamic range and ar-

rive at block-level specifications [13], [21]. Table II shows thetargeted circuit block specifications. A gain range of 30 dB in the

RFVGA ensures that the mixer and baseband stages do not sat-urate. The RF take over point (i.e., when the RFVGA switchesfrom gain to attenuation) is set to 20 dBm at the input of themixer. In the baseband, variable gain must be distributed be-tween baseband VGA and filter to guarantee sufficient SNDR.

A. Analog Baseband Filter

Based on the analysis in the previous section, an inverseChebyshev approximation is chosen for the 4-MHz bandwidthfilter to provide 29 dB attenuation at 5.25 MHz for the imple-mentation. This results in an eighth-order approximation with

pole-zero locations as indicated in Table III.Excellent linearity performance of active RCfilters makes

them suitable for broadband receivers [3][9]. However, the ac-curacy of pole-zero ratios limits roll-off sharpness, and process

variations limit the absolute accuracy in active RCfilters un-less an automatic tuning scheme is employed. The complexity

of the filter tuning scheme to mitigate this variation dependson the desired precision. In contrast, switched-capacitor (SC)filters can implement precise transfer functions without tuning

but require anti-alias filtering. A solution that implements an SCladder filter with embedded anti-aliasing has been reported pre-viously [22]. The required frequency and gain programmabilityof the baseband filter in this work precludes the use of such hy-brid ladder architecture.

1) Cascaded Hybrid Baseband Architecture: The hybrid ac-tiveRCand SC filter with built-in anti-aliasing shown in Fig. 8is suitable for realizing cascaded transfer functions. The de-sired Inverse Chebyshev approximation is realized as a cascaded

function of four biquad stages . Each biquad transferfunction is given by

(7)

where is the dc gain, is the location of the complexpole-pair with quality factor , and is the location of the

axis zero pair. The required anti-aliasing transfer function is

realized using a part of the inverse Chebyshev approximation.Thus, the overall filter transfer function is

(8)

where , , and are realized with SC filters

while is approximated from by ignoring thehighest zero pair from the inverse Chebyshev approximation(29 MHz in Table III) to provide anti-aliasing. The cascaded SC

biquads implement precise stopband high- zeros to provideaccurate transition-band positioning and the output can beeasily coupled to a Nyquist-rate ADC due to the sampled natureof the output.

2) Active RC Implementation: Single-opamp multifeedback

(MFB) filter structure shown in Fig. 9 is used to implement. This structure has the advantage of low sensitivity (to

and variations). The transfer function of the filter is givenby

(9)

where

(10)


6/14


Fig. 9. ActiveRCMFB filter and programmable gain amplifier (single-ended structure shown).

with , , resistor ratio , anda capacitor ratio . For a given , and

are interdependent and thus cannot be set independently. Theoutput spot noise spectral density for the filter is

(11)

where is the input-referred noise density of the amplifier.The first term represents the noise contribution from and ,the second term represents the noise contribution from

, and the third term represents the noise contribution fromthe amplifier. Parameters and are

(12)

For a fully differential filter, the total capacitance is

. For a given , depending onthe choice of (and hence as set by ), the integrated noiseis plotted in Fig. 10. The optimum range of resistor ratio forreducing the noise for a given capacitance budget is 0.20.4.

Hence, we choose (resulting in ) and sizethe capacitors accordingly to meet the noise figure requirement.

Programmable capacitors and (see Fig. 9) are adjustedusing digital control bits to implement 3 and 4 MHz bandwidth

Fig. 10. Variation of integrated noise for a given total capacitance budget withvarying resistor ratio.

settings in the filter. Although not implemented in this design,the resolution of the capacitor bank can be increased to provide

the tuning to cover process variations.The filter linearity requirement IIP3 33 dBm sets the

minimum loop gain in the filter passband to suppress distortionadequately. The minimum loop gain and, hence, the gainband-

width (GBW) of the amplifier is obtained using simulations;thus, we designed a two-stage Miller amplifier with 160-MHzGBW. The amplifier consumes 2.15 mA from a 1.8-V supply.

The input resistor is split into two separate resistors withadditional capacitance (not shown in Fig. 9) resulting in third-order filter to further enhance the anti-aliasing and rejection offar-out blockers.

A continuous time PGA with a gain range of ( 6 to 18 dB)follows the MFB filter. The PGA resistors are sized to min-

imize the input-referred noise of the PGA 18 nV inthe maximum gain setting. The switches and resistor arrays are


7/14


TABLE IVGBWAND FEEDBACK FACTOR FOR SC B IQUAD OTASACROSSCONFIGURATIONS

Fig. 11. SC biquad implementation (single-ended structure shown).

ratioed proportionately to keep the gain of the PGA indepen-

dent of switch size to the first order. The PGA provides a lowclosed-loop output impedance to drive the subsequent SC filter.

3) SC Implementation: Three cascaded SC biquads imple-

ment the transfer functions , , and . Each bi-quad is a two-integrator loop implemented using operationaltransconductor amplifiers (OTAs) as shown in Fig. 11. The pre-ceding PGA allows us to relax the input-referred noise densityof the SC section 285 nV . For a sampling frequency of

80 MHz 12.5 ns , 1 ns is budgeted for slewrate effects, 1 ns for switch resistance delay, and 0.9 ns for thenonoverlapping time, yielding a on the order of3.35 ns [23]. The desired open-loop GBW Hz of each

OTA for 0.5% settling is

(13)

where is the feedback factor of the th OTA for a given filterconfiguration. Programmable capacitor arrays ( , andin Fig. 11) are used in the biquads to achieve accurate gain (0or 6 dB) and frequency programming (3 or 4 MHz). Compu-

tation of the required capacitor ratios and OTA GBW accountfor dynamic range node scaling and noise estimation. Feed-back factor and GBW for each OTA across programmable set-

tings are indicated in Table IV. In this prototype, the OTAsare designed for the worst case (4 MHz, 6 dB setting). Thenoise constraint determines the unit capacitor size,which in turn sets the power consumption of each OTA for a

desired . We select 113 fF (minimum value im-posed by the process), which results in a cascaded input re-

ferred noise density 100 nV for the maximum gain set-ting. Fully differential, folded cascode transconductors (PMOS

input) with switched SC common-mode feedback are used for

the OTAs. Including the biasing circuits, the three biquads con-sume 6.3, 7.7, and 6.7 mA from a 1.8-V supply. The input-re-

ferred noise density requirement for second and third biquadscan be reduced allowing to relax the minimum and thetotal capacitance used in the biquads. Such a power optimizationwill allow to reduce the power consumption of later stages of

filter. In this work, the process imposed constraint of minimum

113 fF prevented such optimization. The switches areimplemented with 2.5-V nMOS devices to provide headroom

for the signal swing. Hence, the digital clocking circuits to drivethe switches are implemented using a 2.5-V digital supply.

The active RC section provides 24-dB variable gain and

a third-order filter response with an attenuation of 4 dB at5.25 MHz. With the additional SC filter (sixth order), thisattenuation increases to 29 dB (42 dB) at 5.25 MHz (5.75 MHz)with an additional 18-dB variable gain. This improved atten-uation and variable gain consumes 37.3 mW (limited by the

high of the technology in this design). The variable gaincontrol in the RF and the baseband section were manuallycontrolled using digital control bits. The passband group delay

resulting from filter response adds to the total wireless channeldelay which is time-variant and has to be compensated bythe adaptive channel equalizer in the digital demodulator.Frequency-dependent gain and phase mismatch between I/Q

branches causes subcarrier-dependent errors within the band-width, but can be reduced at the system-level using digitalcompensation techniques [24].

4) All-Digital Nonoverlap Delay Tuning: Fig. 12 illustrates

a conventional two-phase nonoverlapping clock generator.Digital delays for two-phase nonoverlapping clock generationschemes suffer significantly from process variations (up to

based on simulation results), that results in settling

time window variations. As shown in Fig. 12, the valid timeavailable for linear settling is

(14)

where is reference clock period, is theNORgate delay, andis the delay to generate the nonoverlapping time. The clock

phases ( and ) must be nonoverlapping to guarantee thatcharge is not inadvertently lost. The design value ofcannot be arbitrarily small, lest the uncontrolled clock routingskews cause the phase to overlap. In slow process corners, delay

is maximum, so available settling time is minimum. In addi-tion, switch time constants also increase in the slow process

corner, demanding an over design of the OTA to accommodatethe smallest available settling time.


8/14


Fig. 12. Conventional two-phase nonoverlapping clock generation.

Fig. 13. All-digital nonoverlap time tuning system.

Typical SC circuits requiring multiphase clocks employ com-plex PLLs (or DLLs) to generate precision clocks to minimizethe variation in available settling time [25]. Timing skew and

duty cycle adjustment circuits for SC circuits have also beenproposed [26], [27]. Alternatively, this work proposes a low-complexity all-digital delay tuning scheme to reduce the uncer-tainty of available settling time. As shown in Fig. 13, a replicadelay element configured as a ring oscillator drives a counter,

which counts the number of ring oscillator transitions per ref-erence clock. The total number of delay cells in replica delayloop can be adjusted using digital control bits to the multiplexerto adjust the counter output. Ring delay can be tuned by compar-

ison of the count value to a desired value and toggling betweenup/down decisions can be avoided using hysteresis in the com-parison (not implemented in this prototype). The multiplexer

control bits thus obtained set the delay in Fig. 12. In this pro-totype, the multiplexer select bits are controlled manually. Thisscheme reuses the reference clock which is already availableto generate the nonoverlap clock phases. For an 80-MHz clock

12.5 ns , the low complexity tuning scheme reduces thevariation of available settling from 17% to less than 4% (900

ps to less than 200 ps out of nominal 5.25 ns) across processcorners.

B. RFVGA

The RF front-end consists of an RF variable gain amplifier

followed by single-to-differential transconductor and currentmode quadrature mixers. A single ended RF input is used

to reduce the system cost by obviating the external balun(see Fig. 14). The variable gain helps to maximize the outputSNDR. Adopted from [12], the RFVGA implements a modified

shunt feedback scheme to achieve wideband input matchingindependent of gain without a shunt peaking inductor. The

VGA consists of five identical stages connected with acapacitive divider configuration. This cascaded arrangementfacilitates a 6 dB coarse gain setting in the RFVGA. Fine gainsteps with smooth gain adjustment are implemented with a cur-

rent-steering scheme (not shown in the figure) using a processindependent control block [12]. Operating with a 1.8-V supply,

the RFVGA provides a gain range of 14 dB to 16 dB witha targeted NF of 3 dB at maximum gain and IIP3 performanceof 20 dBm at 14-dB RF attenuation.

C. Current-Mode Passive Mixer

A single-ended RF input in the receiver requires an on-chipsingle-to-differential balun in the signal processing chain to

minimize common-mode noise and even-order distortion. Onepossible approach to on-chip single-to-differential conversionis to utilize a combination of common-gate and common-sourcestages [28][30]. An on-chip transformer load could be usedto obtain a single-ended-to-differential LNA architecture [31],

[32]. In this work, single-ended to fully differential conversionis achieved with a single as indicated in Fig. 15. Withinthe desired bandwidth (470862 MHz), the single-to-differen-tial converter produces a gain and phase mismatch of 0.4 dB

and 14 , respectively. The transconductor uses resistivelysource-degenerated complementary nMOS and pMOS dif-ferential pairs to achieve high linearity and power efficiency

through current reuse [33]. The cross modulation betweenvery-high frequency (VHF) and UHF bands can generatein-band second-order intermodulation distortion (IM2) prod-ucts [30]. But the receiver in this work is targeted for the UHF

band only, hence the second-order intermodulation in the RFfront-end give rise only to out-of-band intermodulation tones.

The transconductor and the mixer switches are ac coupledmainly to eliminate the out-of-band IM2 distortion but also to


9/14


Fig. 14. RFVGA with gain-independent shunt feedback input matching [12].

Fig. 15. Single-to-differential converting transconductor driving the mixer switches.

suppress flicker noise, reduce dc offset, and provide biasingflexibility. The passive mixer shown in Fig. 16 is terminated atthe virtual ground of a transimpedance amplifier (TIA) stage[32], [34], [35] and exhibits higher linearity than a Gilbert-typemixer without the headroom constraints. The transconductor,

passive switch, and TIA cascaded together have an IIP3 of12.2 dBm with sinusoidal LO in simulation. The on-chip LOsignal is provided by a frequency divider consisting of twocurrent-mode logic (CML) latches, and such a signal is a

nonideal pulse with finite rise- and fall-times. For a typicalratio of 0.30.4, the IIP3 performance

is better than sinusoidal LO signal (IIP3 is 13.4 dBm for

). The TIA provides a broadbandlow impedance current path for the down con-verted signal using a wide GBW (460 MHz), fully differential,two-stage Miller-compensated amplifier. The mixer switches

are replica biased at the onset of inversion to minimize clockfeed through and even-order harmonic distortion. An on-chip

frequency divider generates the required quadrature LO sig-nals. A dc-offset cancellation loop is included around the TIA

stage (see Fig. 16), which has a high-pass corner frequencyof 2.4 kHz. Operating with a 1.8-V supply, the mixer andTIA provide a gain of 18 dB with a targeted NF and IIP3performance of 12 dB and 13 dBm, respectively.

IV. EXPERIMENTALRESULTS

The receiver was fabricated in IBM 0.18- m RF CMOS tech-nology. Fig. 17 shows the chip micrograph. Only one baseband

channel was realized (out of I and Q) in the prototype due toarea constraints; however, analog performance verification onlyrequires testing of one channel. The system occupies 2.14 mm

of active area and was characterized in a QFN80 package.Fig. 18 illustrates the measurement setup. Baseband outputs

tapped at intermediate points in the signal chain are bufferedwith on-chip open drain buffers, terminated on the board.

To accommodate output swing in the baseband outputs, theoutput buffers are source degenerated. The differential signal

outputs are buffered separately using highly linear commercialamplifiers.


10/14


Fig. 16. Current-mode passive mixer terminated at TIA input with dc-offset cancellation.

Fig. 17. Chip micrograph of the UHF receiver.

A. Baseband

The measured baseband transfer functions are shown inFig. 19. Fig. 19(a) shows the frequency (3 and 4 MHz) and

gain programmability ( 6 dB to 18 dB with 6 dB per step)of the continuous time section. Fig. 19(b) shows frequencyprogrammability of the composite hybrid filter (3- and 4-MHz

options) along with the additional gain programmability of theSC section (0 to 18 dB range with 0 or 6 dB per biquad). Forthe 4-MHz setting, the measured frequency response indicates astopband attenuation of 29 dB for frequencies 5.25 MHz,

while the continuous time filter provides 2.8 dB attenuationat the same frequency.

To measure the , input power spread over twochannels (generated using two signal generators and a power

combiner) is injected into the filter. A digital channel is gener-ated using 64-QAM modulation using Root-Nyquist (RNYQ)pulse shape with appropriately scaled symbol rate to generatea flat PSD through out the channel, while an analog channel is

generated using a single carrier. The output power levels be-tween the desired and the undesired channels is suitably ad-justed to vary the dBvalues to obtain a wide range of mea-

surements. Filtered PSD is measured at both the continuous- anddiscrete-time outputs. Fig. 20 shows the measured input and fil-tered outputs with digitally modulated desired and ad-jacent channel with dB 30 dB. The PSD shows atten-

uation below 1 MHz due to the frequency limitation from thepower combiner. Table V indicates the computed

from measurements for near digital and analog blocker (channel) and far-out digital blocker ( channel) for varying


11/14


Fig. 18. System characterization setup.

Fig. 19. Measured baseband transfer function. (a) Continuous-time section. (b) Continuous- and discrete-time sections together.

Fig. 20. Measured filtered output PSD with combined input of two 64-QAMdigital modulated channels (desired and adjacent) with dB dB.

dB values. The filtered PSD at the hybrid filter output forthe channel is below the output noise floor for dB

Fig. 21. Measured performance (after postprocessing for referenceimpedance).

values of 10 and 20 dB. The proposed hybrid filter reduces theby 17.5dB 2.0 bits for digital


12/14


TABLE VMEASURED WITH AND BLOCKERSWITHVARYING dB

Fig. 22. Measured linearity performance. (a) Two-tone measurement results for the system. (b) System IIP3 performance.

TABLE VIEXPERIMENTAL RESULTSWITHCOMPARISON TOPREVIOUSWORK

channel and 24.9 dB 3.9 bits for analog channel.Improvement in is better in the presence of analog adjacent channel for the hybrid filter as predicted by theanalysis in Section II.

B. System Performance

The desired input impedance of the RFVGA is (videostandard). The measured response from the network ana-

lyzer (referenced to ) is postprocessed to obtain matchingperformance with respect to (see Fig. 21). The plot in-dicates the performance for two cases of shunt feedbackmatching and resistive matching in the frequency range from

400 to 900 MHz. We measured a NF of 7.9 dB at maximumgain using the Y-factor method with an NC346B noise source.

We observed an additional NF penalty of 2.5 dB with respectto the simulation result, which can be attributed to: 1) insertion


13/14


loss of interconnections between the noise source and LNA; 2)

the noise contribution of the gain control block in the RFVGA;and 3)RCrouting parasitics between the RFVGA and the mixer.

To obtain the system linearity performance, two out-of-channel RF tones located at (516 MHz) and (531MHz) are injected at the LNA input, and the in-band distortion

tone located at 1 MHz after down conversion was measured.We varied the and tone input power in steps of 1 dB to obtain the system IIP3. The plot in Fig. 22(a) showsan IIP3 of 8 and 2 dBm for the highest gain and 9-dB RF

attenuation cases, respectively. Also, the third-order harmonicsaturation is measured at 23 dBm for the highest gain settingbut is not detected for 9-dB RF attenuation showing better

linearity performance.Table VI summarizes the experimental results and compares

this receiver to published UHF receivers. This work was fabri-

cated using IBM 0.18- m RF CMOS technology without using

any special RF components other than metalinsulatormetalcapacitors. The power consumption and the area metrics indi-

cated for this work do not include the frequency synthesizer, andquadrature generator. The RF front-end and baseband blocksconsume 58 and 52 mW from a 1.8-V supply, respectively. The

digital clock tree to drive the SC filter switches consumes 10mW from a 2.5-V digital supply. Compared with the previouslypublished UHF receiver solutions, this work implemented in

CMOS process offers competitive performance.

V. CONCLUSION

Analysis of tradeoffs between baseband filter (order and

approximation) and the required ADC DR requirements fora broadband receiver are presented with the implementation

of a UHF receiver. Analysis reveals that for digital modulatedchannels, the majority of the undesired residual power afterfiltering resides in the first adjacent channel. In the presence ofnarrow band analog carriers in the adjacent channel, high-orderinverse Chebyshev approximations are favorable for baseband

filter implementations. The proposed hybrid baseband imple-mentation achieves sharp roll-off with precise stopband zeroeswithout requiring precision filter tuning schemes. The presented

receiver integrates an RFVGA, an on-chip single-to-differentialtransconductor (balun) with current-mode passive mixer, anda hybrid analog baseband with an all-digital tuning schemefor nonoverlap clock generation and achieves performancecommensurate with the state of the art.

ACKNOWLEDGMENT

The authors would like to thank the MOSIS educational re-search program and IBM Corporation for fabricating this de-

sign. The authors would also like to thank E. Pankratz, F. Fer-nandez, and M. Onabajo for reviewing the manuscript and R.Srikantiah and Prof. S. Hoyos for discussions.

REFERENCES

[1] Digital Video Broadcasting(DVB); TransmissionSystem for HandheldTerminals (DVB-H) 2001.

[2] Mobile and Portable DVB-T Radio Access Interface Specification,ver. 1.0, Eur. Inf. & Commun. Technol. Industry Assoc. (EICTA),2004.

[3] P. Antoine, P. Bauser, H. Beaulaton, M. Buchholz, D. Carey, T. Cas-sagnes, T. K. Chan, S. Colomines, F. Hurley, D. T. Jobling,N. Kearney,A. C. Murphy, J. Rock, D. Salle, and T. Cao-Thong, A direct-conver-sion receiver for DVB-H,IEEE J. Solid-State C ircuits, vol. 40, no. 12,pp. 25362546, Dec. 2005.

[4] M. Womac, A. Deiss, T. Davis, R. Spencer, B. Abesingha, and P.Hisayasu, Dual-band single-ended-input direct-conversion DVB-Hreceiver, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.Papers, Feb. 2006, pp. 610611.

[5] K. Iizuka, H. Kawamura, T. Fujiwara, K. Kagoshima, S. Kawama, H.Kijima, M. Koutani,S. Toyoyama, andK. Sakuno, A 184 mWfullyin-tegrated DVB-H tuner with a linearized variable gain LNA and quadra-ture mixers using cross-coupled transconductor, IEEE J. Solid-StateCircuits, vol. 42, no. 4, pp. 862871, Apr. 2007.

[6] I. Vassiliou, K. Vavelidis, S. Bouras, S. Kavadias, Y. Kokolakis,G. Kamoulakos, A. Kyranas, C. Kapnistis, and N. Haralabidis, A m CMOS dual-band direct conversion receiver, in IEEE Int.Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp.606607.

[7] Y. J. Kim, J. W. Kim, V. N. Parkhomenko, D. Baek, J. H. Lee, E.Y. Sung, L. Nam, and B. H. Park, A multi band multi-mode CMOSdirect conversion DVB-H tuner, inIEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 608609.

[8] I. Vassiliou, K. Vavelidis, N. Haralabidis, A. Kyranas, Y. Kokolakis,S. Bouras, G. Kamoulakos, C. Kapnistis, S. Kavadias, N. Kanakaris,

E. Metaxakis, C. Kokozidis, and H. Peyravi, A 65 nm CMOS multi-standard,multiband TV tuner for mobile and multimedia applications,IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 15221533, Jul. 2008.

[9] M.-C. Kuo, S.-W. Kao, C.-H. Chen, T.-S. Hung, Y.-S. Shih, T.-Y.Yang, and C.-N. Kuo, A 1.2 V 114 mW dual-band direct-conversionDVB-H tuner in m CMOS, IEEE J. Solid-State Circuits, vol.44, no. 3, pp. 740750, Mar. 2009.

[10] B. Murmann, Limits on ADC power dissipation, in Analog CircuitDesign, M. Steyaert, A. H. M. Roermund, and J. H. v. Huijsing, Eds.Berlin, Germany: Springer, 2006.

[11] B. Murmann,ADC Performance Survey 19972010, [Online].Avail-able: http://www.stanford.edu/~murmann/adcsurvey.html

[12] J. Xiao, I. Mehr, and J. Silva-Martinez, A high dynamic range CMOSvariable gainamplifier for mobile DTV tuner,IEEE J. Solid-State Cir-cuits, vol. 42, no. 2, pp. 292301, Feb. 2007.

[13] J. Xiao, CMOS RF front-end design for terrestrial and mobile dig-ital television systems, Ph.D. dissertation, Dept. Eectr. Comput. Eng.,

Texas A&M Univ., College Station, TX, 2007.[14] B. Vejlgaard, P. Mopensen, and J. B. Knudsen, Performance analysis

for UMTS downlink receiver with practical aspects, in Proc. IEEEVeh. Technol. Conf., 1999, pp. 9981002.

[15] B. Razavi, CMOS RF receiver design for wireless LAN applications,inProc. IEEE Radio and Wireless Conf. , 1999, pp. 275280.

[16] V. Giannini, J. Craninckx, and A. Baschirotto, Baseban d An alog C ir-cuits for Software Defined Radio. Berlin, Germany: Springer, 2008.

[17] J. Jussila and K. Halonen, Minimization of power dissipationof analog channel-select filter and Nyquist-rate A/D converter inUTRA/FDD, inProc. ISCAS, 2004, pp. IV-9403.

[18] J. Norsworthy, Broadband tuners for modern systems, RF DesignAug. 2001 [Online]. Available: http://rfdesign.com/issue_20010801

[19] S. Sheng, Mobile television receivers: A free-to-air overview,IEEECommun. Mag., vol. 47, no. 9, pp. 142149, Sep. 2009.

[20] B. Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian, Analog-to-dig-ital converters,IEEE Signal Process. Mag., vol. 22, no. 6, pp. 6977,

Nov. 2005.[21] B. Razavi, Basic concepts in RF design, in RF Microelectronics.

Upper Saddle River, NJ: Prentice-Hall, 1998.[22] S. Azuma, S. Kawama, K. Iizuka, M. Miyamoto, and D. Senderowicz,

Embedded anti-aliasing in switched-capacitor ladder filters with vari-able gain and offset compensation, IEEE J. Solid-State Circuits, vol.37, no. , pp. 349356, Mar. 2002.

[23] J. Adut, J. Silva-Martinez, and M. Rocha-Perez, A 10.7-MHz sixth-order SC ladder filter in m CMOS technology, IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 53, no. 8, pp. 16251635, Aug. 2006.

[24] F. Horlin and A. Bourdoux, Digital Compensation for Analog Front-Ends: A New Approach to Wireless Transceiver Design. New York:Wiley, 2008.

[25] G. Manganaro, S.-U. Kwak, andA. R. Bugeja, A dual 10-b 200-MSPSpipelined D/A converter with DLL-based clock synthesizer, IEEE J.Solid-State Circuits, vol. 39, no. 11, pp. 18291838, Nov. 2004.

[26] G. Manganaro, Feed-forward approach for timing skew in interleavedand double-sampled circuits, Electron. Lett., vol. 37, no. 9, pp.552554, Apr. 2001.


14/14


[27] S. Karthikeyan, Clock duty cycle adjuster circuit for switched capac-itor circuits,Electron. Lett., vol. 38, no.18, pp.10081009, Aug. 2002.

[28] B. Gilbert, The MICROMIXER: A highly linear variant of the Gilbertmixer using a bisymmetric Class-AB input stage,IEEE J. Solid-StateCircuits, vol. 32, no. 9, pp. 14121423, Sep. 1997.

[29] S. C. Blaakmeer, E. Klumperink, D. M. W. Leenaerts, and B. Nauta,The blixer, a wideband balun-LNA-I/Q-mixer topology, IEEE J.Solid-State Circuits, vol. 43, no. 12, pp. 27062715, Dec. 2008.

[30] D. Mastantuono and D. Manstretta, A low-noise active balun withIM2 cancellation for multiband portable DVB-H receivers, in IEEE

Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009,pp. 216217.

[31] S. Lee, J. Bergervoet, K. S. Harish, D. Leenaerts, R. Roovers, R. v.d. Beek, and G. v. d. Weide, A broadband receive chain in 65 nmCMOS, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.Papers, Feb. 2007, pp. 418612.

[32] Y. Feng, G. Takemura, S. Kawaguchi, and P. Kinget, Design of a highperformance 2-GHz direct-conversion front-end with a single-endedRF input in m CMOS, IEEE J. Solid-State Circuits, vol. 44,no. 5, pp. 13801390, May 2009.

[33] E. Sacchi, I. Bietti, S. Erba, L. Tee, P. Vilmercati, and R. Castello, A15 mW, 70 kHz 1/f corner direct conversion CMOS receiver, in Proc.CICC 2003, Sep. 2003, pp. 459462.

[34] N. Poobuapheun, W.-H. Chen, Z. Boos, and A. M. Niknejad, A1.5-V 0.72.5-GHz CMOS quadrature demodulator for multiband

direct-conversion receivers,IEEE J. Solid-State Circuits, vol. 42, no.8, pp. 16691677, Aug. 2007.[35] A. Mirzaei, H. Darabi, J. C. Leete, X. Chen, K. Juan, and A. Yazdi,

Analysis and optimization of current-driven passive mixers in narrow-band direct-conversion receivers,IEEE J. Solid-State Circuits, vol. 44,no. 10, pp. 26782688, Oct. 2009.

Raghavendra Kulkarni (S10) received the B.E. de-gree in elecronics and communication from the Uni-versity of Mysore, Mysore, India, in 1997, and theM.Tech. degree in VLSI design, tools and technologyfrom the Indian institute of Technology, Delhi, India,in 2001.He is currentlyworkingtowardthe Ph.D. de-gree at Texas A&M University, College Station.

From 1997 to 1999, he was a Software Engineer

with Compaq, Bangalore, India, and as a Design En-gineer with Cypress Semiconductor, Bangalore. Heinterned at Intel, Santa Clara, CA, in 2001 as part of

his graduate work. From 2001 to 2004, he was a Design Engineer with LSILogic, Milpitas, CA, designingSDR/DDR memory interface circuits and LVDSI/Os. As a Design Engineer Intern with Texas Instruments, Dallas, TX, in 2005,he designed high-speed analog circuits for USB 2.0. His current research in-terests include analog baseband design, mixed-signal design, and high-speedinterface design.

Jusung Kim(S10) received the B. S. degree (withhighest honors) in electrical engineering from YonseiUniversity, Seoul, Korea, in 2006. He is currentlyworking toward the Ph.D. degree at Texas A&M

University, College Station.In the summer of 2008, he was a Design Intern

withTexasInstrumentsInc., Dallas, TX, wherehe de-signed the RF front-end for multistandard analog anddigital TV silicon tuners. In the spring and summerof 2011, he will be with Qualcomm Inc., working oncellular RF IC. His research interests include trans-

ceiver system and circuit design at RF and millimeter-wave frequencies.

Hyung-Joon Jeon received the B.S.E.E. degreefrom Seoul National University, Seoul, Korea, in2003, and the M.S.E.E. degree from Texas A&MUniversity, College Station, in 2009, where he iscurrently working toward the Ph.D degree.

During the summer of 2008, as a Design Intern,he was with Broadcom Corporation, Irvine, CA,working on LC VCO and high-speed frequency

dividers for RF tuners. His current research interestsinclude phase-locked loops, clock-and-data recovery,and high-speed data communication circuits.

Jianhong Xiao was born in China in 1979. Hereceived the B.Sc. degree in computer science andtechnology from Peking University, Peking, China,in 2001, and the Ph.D. degree from Texas A&MUniversity, College Station, in 2007.

He was a Design Engineer Intern with AnalogDevices in the summer and fall of 2004 and thesummer of 2005. He joined Broadcom Corporation,Irvine, CA, in 2007, where he is currently the SeniorStaff Scientist for the Broadband RF DevelopmentGroup. His main research interests cover analog and

RF front-end design for various broadband communication systems includingcable, satellite, and MoCA.

Jose Silva-Martinez (SM98F10) was born inTecamachalco, Puebla, Mxico. He received theM.Sc. degree from the Instituto Nacional de As-trofsica Optica y Electrnica, Puebla, Mxico, in1981, and the Ph.D. degree from the KatholiekeUnivesiteit Leuven, Leuven, Belgium, in 1992.

From 1981 to 1983, he was with the ElectricalEngineering Department, Instituto Nacional deAstrofsica Optica y Electrnica (INAOE), Puebla,Mxico, wherehe was involved withswitched-capac-itor circuit design. In 1983, he joined the Department

of Electrical Engineering, Universidad Autnoma de Puebla, where he re-mained until 1993; he pioneered the graduate program on Opto-Electronics in1992. In 1993, he rejoined the Electronics Department, INAOE, and, from May1995 to December 1998, was the Head of the Electronics Department; he was acofounder of the Ph.D. program in electronics in 1993. He is currently with theDepartment of Electrical and Computer Engineering, Texas A&M University,College Station, where he is a Professor. He has authored or coauthored over88 and 140 journal and conference papers, respectively, one book, and ninebook chapters. His current field of research is in the design and fabrication ofintegrated circuits for communication and biomedical applications.

Dr. Silva-Martinez has served as IEEE Circuits and Systems SocietyVice President Region-9 (19971998) and as Associate Editor for the IEEETRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS from 1997to 1998 and from 2002 to 2003, Associate Editor of the IEEE TRANSACTIONSON CIRCUITS AND SYSTEMSI: REGULAR PAPERS from 2004 to 2005 and2007 to 2009, and currently serves on the board of editors of six other major

journals. He was the recipient of the 2005 Outstanding Professor Award by theECE Department, Texas A&M University, the RF-IC 2005 Best Student PaperAward, and the 1990 European Solid-State Circuits Conference Best PaperAward.

ieee uhf receiver f

Documents