The 38th International Electronics

Manufacturing Technology

IEMT2018

4th - 6th September 2018· Plaza Ramada · Melaka, Malaysia

https://ieee-epsmalaysia.org/iemt/

Overview of IEMT 2018

Organizing Companies & Institutions :

The International Electronics Manufacturing Technology (IEMT) Conference is the premier IEEE event devoted to the manufacture of electronic, opto-electronic and MEMS/sensors devices and systems. IEMT is an established International conference of long standing organized by the Electronics Packaging Society (EPS) Society of IEEE. The 38th International Electronics Manufacturing Technology (IEMT) Conference 2018 is organised by the IEEE EPS Malaysia Chapter with co-sponsorship from IEEE Santa Clara Valley Chapter.

The objective is to create an international forum for the exchange, dissemination and discussion of state-of-the-art technologies and recent developments in electronic materials, packaging and assembly. Following the great success in the previous IEMT conferences which were well-attended by more than 10 major countries, the upcoming conference will be held in Malacca, Malaysia. So come and meet world-renowned authorities from the Asia-Pacific region, USA and Europe. Papers are invited from industry participants as well as researchers from the academia and government research organizations.https://ieee-epsmalaysia.org/iemt/

Program Overview

SHORT COURSES: 4th September, 2018, TUESDAY08:00-8:30 Registra�on at Secretariat [Main Foyer Level 7]

[Venue: Bunga Teratai] [Venue: Bunga Orkid 1&2] [Venue: Bunga Orkid 3&4] [Venue: Bunga Mela�]

08:30-12:00Failure Analysis of

Engineering Materials for IoT

PDC - Packaging for MEMS and Sensors

By Horst Theuss, Infineon AG

Electro-migra�on –The Hurdle For Miniaturiza�on

and High Power DevicesBy Ning-Chen Lee, Indium

WB Advancement: Smart Equipment for Smart ManufacturingBy Nelson Wong, KNS

12:00-13:30 --- Lunch ---

13:30-17:00 By Kuan Yew Cheong, USM

Breakthrough in Semiconductor Packaging Problem Solving

through Quality Func�on and Sta�s�cal Methodologies

By LF Chan, LF Training

Chip to Package Interac�ons: Trends, Developments and

Integra�on Challenges By Srinivasa Reddy, Infineon

Cu Wire Bonding for Automo�ve Grade

Semiconductor Product Packaging

By Mark Luke Farrugia,NXP

EXHIBITION – 5th-6th September, 2018, WEDNESDAY and THURSDAY

07:30-17:00 Tabletop Display [Main Foyer Level 7]

CONFERENCE SESSION: 5th September, 2018, WEDNESDAY07:30-17:00 Registra�on at Secretariat [Main Foyer Level 7]

08:30-09:00

Welcome Speech [Bunga Raya Grand Ballroom]Yik-Yee Tan, IEMT 2018 General Chair

Shaw Fong Wong, IEEE EPS Malaysia Chapter ChairWilliam Chen, Past IEEE EPS Chair, HQ

09:00-09:30 Keynote Address I “The AI Driven Manufacturing Transforma�on is Imminent” [Bunga Raya Grand Ballroom]By Qin Deng, IBM Electronics Industry

09:30-10:00 Keynote Address II “Automo�ve Industry Transforma�on: EV/HEV Impact on Power Modules, Design Changes and Packaging Innovations”By Claire Troadec, Yole Dévelopement

10:00-10:30 --- Refreshment Break + Exhibi�on + Poster Session I ---

10:30-12:10 Session A1 [Bunga Teratai]Advanced Packaging I

Session B1 [Bunga Orkid 1&2]Molding Technology

Session C1 [Bunga Orkid 3&4]Materials I

Session D1 [Bunga Mela�]Special Track- CREST

12:10-14:00 --- Lunch ---

14:00-15:00IEMT Panel Session- Ask the Experts [Bunga Raya Grand Ballroom]

“New Era of SMART Automo�ve Electronics- A Perspec�ve of Packaging Technology Challenges & Opportuni�es”Panelists: Alexander Mueller (Infineon), Laurent Herard (STMicro), Claire Troadec (Yole); Moderator: Choong Kooi Chee (Intel)

15:00-15:30 Keynote Address III “Heterogeneous Integra�on through SiP from Design to Manufacturing” [Bunga Raya Grand Ballroom]By William Chen, ASE

15:30-16:00 --- Refreshment Break + Exhibi�on + Poster Session I ---

16:00-17:40 Session A2 [Bunga Teratai]Advanced Packaging II

Session B2 [Bunga Orkid 1&2]Special Track- iNEMI

Session C2 [Bunga Orkid 3&4]Materials II

Session D2 [Bunga Mela�]Thermo-mechanical

19:00-22:00

Conference Gala Night Dinner [Bunga Raya Grand Ballroom]Highlights: Opening Address by Chee Hong Lee, Infineon Malaysia

SMART Talk- “Packaging for the Smart World” by Shi-Wei Ricky Lee, HKUST+ Cultural shows & more……

CONFERENCE SESSION: 6th September, 2018, THURSDAY

07:30-12:00 Registra�on at Secretariat [Main Foyer Level 7]

08:30-09:00Keynote Address IV “Opportuni�es and Challenges for Semiconductor and Optoelectronic Packages in the Emerging Markets of 4th

Industrial Revolu�on (4IR)” [Bunga Raya Grand Ballroom]By NorAzmi Alias, CREST

09:00-09:30 Keynote Address V “Enabling Heterogeneous Packaging: A Perspec�ve on Challenges & Opportuni�es“By Gaurang Choksi, Intel Corporation

09:30-10:00 Keynote Address VI “Growth of China’s Semiconductor Advanced Packaging – A Win-Win in a World-Wide Context”By Qian Wang, Institute of Microelectronics, Tsinghua University

10:00-10:30 --- Refreshment Break + Exhibi�on + Poster Session II ---

10:30-12:10 Session A3 [Bunga Teratai]WireBond Technology I

Session B3 [Bunga Orkid 1&2]Soldering Technology I

Session C3 [Bunga Orkid 3&4]Process Technology I

Session D3 [Bunga Mela�]FA & Reliability I

12:10-14:00 --- Lunch ---

14:00-15:40 Session A4 [Bunga Teratai]WireBond Technology II

Session B4 [Bunga Orkid 1&2]Soldering Technology II

Session C4 [Bunga Orkid 3&4]Process Technology II

Session D4 [Bunga Mela�]FA & Reliability II

15:40-16:10 --- Refreshment Break + Exhibi�on + Poster Session II ---

16:10-16:40 Keynote Address VII “Packaging for Automo�ve – Challenges and Solu�ons“[Bunga Raya Grand Ballroom]By Alexander Mueller, Infineon Technologies

16:40-17:10 Closing Ceremony & Awards Presenta�on [Bunga Raya Grand Ballroom](Award, Sponsor Recogni�on and Lucky Draw Presenta�on)

38th International Electronics Manufacturing Technology (IEMT) Conference 2018Program Overview T

I EM

2018

MELAKACONFERENCEMALAYSIA

OUR SPEAKERS

Short CoursesCheong Kuan YewScience University (USM), Malaysia

Failure Analysis of Engineering Materials for Application in Internet of ThingsThis training provides the understanding of fundamental concepts of surface, interface, thin-film and solid-states as background to effectively provide precise prediction on the root-cause of failure. A Generalization Approach is introduced to simplify and link these factors to explain typical failures such as corrosion, delamination, surface contamination, etc. Characterization methods are also introduced together with strategies on how to overcome these failures.

Ning-Cheng LEEIndium Corporation, USA

Electromigration – The Hurdle For Miniaturization and High Power DevicesThis course covers all critical aspects of electromigration of solder joints, including failure mechanism, effect of solder alloy composition, solder joint metallurgy and configuration, pad design, pad composition, current density, temperature, and current polarity. Electromigration behavior within redistribution layer is also reviewed and discussed. Recommendation will be provided on how to achieve long life under high current-stressed conditions for solder joints and redistribution layer through optimized designs.

Theuss HorstInfineon Technologies AG, Germany

PDC – Packaging for MEMS and SensorsThis course provides an overview on assembly & interconnect technologies for MEMS and sensors. Case studies cover pressure, magnetics, gyro sensors and silicon microphones – addressing both consumer and automotive applications. How can standard packaging platforms be extended to MEMS/sensors? will be addressed. . The course will further discuss toolbox elements necessary for heterogeneous integration of MEMS/sensors (SoC, SiP) and the importance of testing & process adaptation to specific needs of MEMS/sensors.

Srinivasa YeduruInfineon Technologies Kulim, Malaysia

Chip to Package Interactions: Trends, Developments and Integration ChallengesThis course starts with general trends in semiconductor devices followed by an overview of various device technologies, their application backgrounds and potential failures and reliability challenges. Chip to package interactions will be explained by highlighting critical interfaces, material combinations and failures that arise due to various interfacial interactions. Special case studies will be discussed addressing different failure mechanisms in device technology to package combinations.

Mark Luke FarrugiaNXP Semiconductors, The Netherlands

Cu Wire Bonding for Automotive Grade Semiconductor Products PackagingThis course covers the fundamentals of metal joining and failure mechanisms that make Cu wire-bonding a challenge in the semiconductor packaging industry, as well as best practices and breakthroughs that mitigate these challenges and enable Cu wire bonded products to meet Automotive grade quality requirements and expectations.

Nelson WongKulicke & Soffa Private Limited, Malaysia

WB Advancement: Smart Equipment for Smart ManufacturingThis course covers a wide range of knowledge in advanced wire-bonding equipment and smart manufacturing to support Industry 4.0. The knowledge learnt through this course can be immediately applied to your work, study and business processes. The course discusses the evolution of wire-bonding, current wire-bonding capabilities and WB development to cater to smart manufacturing.

LF ChanLF Training, Malaysia

Breakthrough in Semiconductor Packaging Problem Solving Through Quality Function and Statistical MethodologiesThis course covers a wide range of the advance quality planning & statistical tools for semiconductor packaging problem solving. You will understand the 4 phase quality function & discover the benefits of various statistical tools at each phase. The knowledge learnt through this course can be immediately applied to your work, study and business processes.

OUR SPEAKERS

Invited Paper

Azman JalarUniversiti Kebangsaan Malaysia

The intermetallic compound (IMC) layer at metallurgical joint has received much attention due to its influence on the joining quality and reliability of electronics packaging. This work reviews the suitability of adopting quantitative metallography and stereometry in describing the IMC layer in metallurgical interconnection. The value of ‘thickness’, ‘area’ and ’volume’ of IMC layer will be discussed based on their appropriateness to represent quantitative values. Statistical analysis using the ‘average thickness’ will also be discussed along with other statistical values such as ‘median’ and ‘mod’.

Stereometry and quantitative metallography on intermetallic compounds layer of metallurgicalinterconnection in semiconductor packaging

Mohd Nasir TaminUniversiti Teknologi Malaysia

This paper addresses a damage mechanics-based approach in describing the progressive failure of a typical through-silicon via(TSV) assembly. The Armstrong-Frederic-Chaboche model is examined to describe the stress-strain hysteresis and cyclic hardening of the Cu layer. The accumulated plastic strain is monitored and used to define the onset of damage initiation. Finite element (FE) simulation of a unit cell model with a single TSV is employed to quantify the mechanics of the failure processes.

Damage Mechanics-based Approach to Quantify the Failure Processes in Through-Silicon Vias

Kyung W. PaikKAIST

Conductive adhesive films, such as ACFs (Anisotropic Conductive Films) and NCFs (Non Conductive Films), is one of the promising fine pitch and flexible packaging and interconnection technologies. New nano-fiber ACFs and APL (Anchoring Polymer Layer) ACFs have been successfully invented by KAIST for various fine-pitch applications. In this paper, the ACFs, NCFs and EMFs adhesive materials will be introduced for various advanced electronic packaging applications such as display, wearable, 3D-TSV, and PLP products.

Recent Advances of the Conductive Adhesive Films Materials for Advanced Electronics PackagingApplications

Ghazali OmarUniversiti Teknikal Malaysia Melaka

CNT-filled Polymer Composites as Stretchable Conductive Ink (SCI) have received an increasing demand due to their excellent flexibility and expendability while maintaining high-level conductivity. This paper investigates the anisotropic performance of the carbon nanotube (CNT) reinforced in stretchable conductive ink (SCI) under different environment and mechanical factors. The results of this research are beneficial for the industry as an essential baseline that was analyzed based on actual field applications both on their functionality and reliability.

CNT-filled Polymer Composites for Enhanced Electrical Performance in Electronic Componentsfor Surface Mount Technology

Kuan Yew CheongUNIVERSITI SAINS MALAYSIA

processed into a thin film for the use of next generation “brain-like” or neuromorphic computer. To achieve this, an important building block that interfaces connectors for linking, transmitting, processing, and storing data with ultra-low energy must be developed. Technologically, the synapse can be replicated by a metal-insulator-metal thin-film structure, where the insulator works as an artificial synapse. This paper compares the possible natural organic materials suitable for the insulating thin film.

Nature Organic Thin Film as a Renewable Material for Artificial Synapse in NeuromorphicComputing for Application in Internet-of-Things

Hsiang-Chen HsuSt. John’s University

A real time temperature measurement technique using embedded sensors on heterogeneous IC packaging material during ultrafast laser scribing has been developed. The heterogeneous material used is epoxy molding compound (EMC) and specially-designed ultrathin print circuit board (PCB), commonly used in package-on-package design (PoP). Thermal couples were designed and embedded inside the heterogeneous material to record in-situ temperature distributions during ultrafast laser scribing. A series of comprehensive experiments on laser scribing this jam-packed area has been conducted to validate the developed technique.

Thermal Design and Real Time Temperature Measurement on Heterogeneous Packaging duringUltrafast Laser Machining

Shi-Wei Ricky LeeHong Kong University of Science and Technology

This paper proposes an alternative approach for implementing MB and RDL by additive manufacturing (AM) at the chip level. The conductive ink is printed on the chip or a fraction of the wafer to form RDL. MB is formed by polymer-jetting and subsequent layering of surface metallization. Since the AM approach does not require photolithography, it will reduce the fabrication cost, shorten the processing time, and increase the design flexibility, essential for effective rapid prototyping.

Micro-bumping and Re-distribution by Additive Manufacturing for Chip Level Packaging

OUR SPEAKERS

Invited Paper

Rick NicholsAtotech

Quad Flat No-lead (QFN) packages are standardized IC packages with in-built heat sinks used in the surface mount technology. Contacts and heat sinks are usually electrolytically tin-plated as the mounting areas. However, after singulation copper alloy flanks are exposed which are not possible to be wetted by the solder during the reflow attachment cycle. This paper promulgates the incorporation of an immersion tin process to enable a 3-D connection/fillet possible even for a QFN package, enhancing bond quality, and enabling possible automatic optical inspection.

Improving Reliability by Forming a 3D Connection for Quad Flat No-lead ICs Using Immersion Tin

Laurent HerardSTMicroelectronics

Recent improvements in packaging materials and equipment lead to high package level reliability of the last interconnection technologies and compatibility with quality requirements for automotive, including higher temperature storage conditions. The primary challenge remains on the demanding board level reliability with severe thermal-cycling and vibration conditions. This paper gives an overview of the challenges driven by automotive mission profile for the adoption of some advanced packaging innovation, such as WLCSP, flip chip, and QFN in terms of packaging design and material.

Packaging – a key enabler towards robust miniaturization for smart driving

Mike SeddonON Semiconductor

The drive for smaller, thinner, more efficient, higher power, more complex, and of course, lower cost packages requires new innovative assembly solutions. As additional functionality is added to the final product, and as its form factor is reduced to for mobility and compatibility, the semiconductor package and its assembly process has become even more critical in the integration and overall success of the device. This paper discusses some of the key building blocks which are critical to the success of an advanced package, including advanced wafer ultra-thinning techniques, plasma for increased reliability and other applications, and alternative low cost materials.

Understanding Key Components for Today’s Advanced Packages

Hui Teng WangInfineon Technologies Asia Pacific, Singapore

Constant load scratch test is introduced to determine the maximum allowable load on thin plating layer before copper exposure occurs. The critical load (Lc), corresponding to copper exposure, is determined, together with the coefficient of friction (CoF): the ratio of normal load over scratch friction force. The plating layer hardness, surface morphology, surface roughness, and plating layer thickness are characterized. In general, both Lc and CoF are able to characterize various pre-plated leadframes (PPF) technologies.

Study of Critical Load Force towards Thin Plating on Pre-Plated Leadframe

Sung YiMechanical and Materials Engineering Department, Portland State University, Portland, OR, USA

Ultrasonic curing technique is an alternative to the conventional thermal curing of adhesives. It is applicable for bonding epoxy adhesives or ACFs. The advantages of the ultrasonic polymer bonding technology are low cost, simplicity, and fast assembly time at low temperature. However, it is not well-understood how ultrasonic epoxy curing works. In this study, a chemo-thermo-viscoelastic model has been developed to predict the change in viscoelastic properties of epoxy adhesives or ACFs by the parameters such as time, temperature, and degree of cure. Then, the curing mechanism of epoxy adhesives or ACFs by ultrasonic loading is studied and presented.

Chemo-thermo-viscoelasticity of Thermosetting Polymers for Ultrasonic Curing

OUR SPEAKERS Invited Paper

Haley FuiNEMI (International Electronics Manufacturing Initiative)

A flower of sulfur (FoS) test chamber has been developed by the iNEMI taskforce on creep corrosion on printed circuit boards (PCBs). Besides testing for creep corrosion, the FoS chamber has the potential of replacing the mixed-flowing gas (MFG) chamber as a general-purpose corrosion chamber for testing a whole range of electronic components and assemblies. This paper will describe the chamber design and recommended test procedure for creep corrosion and its use as a low-cost, convenient and easily maintainable chamber for a whole range of testing of electronic hardware.

Flowers Of Sulfur Test For Creep Corrosion And More

Jianghai GuCisco Systems, Inc.

The demand for large form factor Flip Chip Ball Grid Array (FCBGA) package has been increasing to meet the growing needs of high bandwidth network traffic but it is well-known that FCBGA packages are sensitive to external mechanical shock. In this paper, three-dimensional Finite Element (FE) models have been developed to study the impact of different heatsink attachment methodologies for minimizing mechanical shock. The models developed with this methodology enable board designers, thermal engineers, manufacturing and packaging teams to optimize the package, board and heatsink design and build a mechanically reliable product.

System Level Mechanical Shock Reliability of BGA Packages: Experimental and Numerical Analysis

Ning-Cheng LeeIndium Corporation

For SiP or SMT assembly process, solder paste has been the choice of primary soldering material. In the meantime, miniaturization has been the trend of electronic industry. While the size of components, pads, stencil thickness, aperture, pitch, and solder powder has been shrinking continuously so far, it is about time to ask whether the solder paste technology is able to support this trend forever. This paper studies the performance of different types of solder paste and limitations towards fine pitch applications.

Assessment of Solder Paste Technology Limitation at Miniaturization for SIP and SMT Application

Kuah Teng Hock, EricASM Technology Singapore

Sintered Silver (Ag) as a lead-free die attach material to replace high-Pb solder has many technical advantages such as high melting point, high thermal conductivity, high electrical conductivity, and high reliability. The global ban on internal-combustion engines (fossil fuel vehicles) will accelerate the electrification process of automobiles. This paper discusses technical solutions to overcome challenges to deliver repeatable and reliable pressure sintering process in high-volume, cost-effective way and how these solutions can be translated for making high volume manufacturing possible.

Challenges of Silver Sintering and Some of Its Possible Solutions

Linda M. BalTechSearch International, Inc

ADAS features are created by using a variety of radar, camera, LIDAR, V2X inputs along with sensor fusion. What types of packages are being used for each sensor or processor? How do we qualify these packages for the operating environment? How is compute integration affecting these packages? Examples of the various sensor packages and packaging trends are presented. This presentation also discusses some of the opportunities in automotive packaging and the challenges in meeting automotive specifications.

ADAS Packaging Challenges Before the Dawn of Autonomous Driving

OUR SPEAKERS

Keynote

Qin DengIBM Electronics Industry

Artificial intelligence, smart manufacturing and digital technologies are radically changing the competitive landscape across industries. As end users generate higher demands for personalized products, manufacturing is becoming more complex and fragmented. The challenge that organizations faces is how to adapt manufacturing systems, traditionally designed for high volume, to accommodate mass customization. The Keynote introduces IBM's latest development of AI in manufacturing, share real cases of how AI helped manufacturers to transform operations, and present an outlook of the impact of AI on manufacturing.

The AI Driven Manufacturing Transformation is Imminent

Alexander MuellerInfineon Technologies

High performance automotive power packages have to fulfill thermal and performance requirements and quality targets, as well as to meet cost targets. There will be no single package solution fulfilling all needs. This Keynote introduces the plurality of requirements and package applications in automotive power electronics. System integration solutions will be introduced and discussed with respect to architecture, Co-Design requirements, materials and process requirements. The ever-increasing reliability requirements of automotive applications will be another topic in the light of autonomous driving and electro mobility.

Packaging for Automotive – Challenges and Solutions

Claire TroadecYole Developpement

The Automotive Industry is seeing a strong transformation period with 2 major trends: automation and electrification. With its market adoption, EV/HEV will represent a large part of the overall power electronics industry. Automotive industry is known to drive standards and push new technology to the market. In this Keynote, we present how automotive electrification is changing the power module supply chain and increasing opportunities for new technologies to be adopted. We explain why Power module manufacturing is an area of tough competition and illustrate some of the main technical progress we expect in packaging for automotive.

Automotive Industry Transformation: EV/HEV impact on Power Modules, Design Changes andPackaging innovations!

William Chen (Bill)ASE

At this intersection of explosive expansion of electronic products into global society, and plateauing of CMOS scaling economic advantage, continued progress requires a different phase of electronics innovations. This Keynote will address Heterogeneous Integration through SiP - the key technology direction going forward - to initiate this new era of technological and scientific advances, with system integration together with components & device integration converging in collaboration and competition across the electronics industry. We shall conclude with a brief overview of Heterogeneous Integration Roadmap with a 15 years vision into the future.

Heterogeneous Integration through SiP from Design to Manufacturing

OUR SPEAKERS

Keynote

Gaurang ChoksiIntel Corporation

This Keynote provides an overview of typical current and future electronic packaging technologies and demands across different market segments. Challenges for facilitating effective analysis and characterization to enable efficient design, materials selection and associated assembly and test manufacturing processes will be reviewed and mapped to an assessment of the current state-of-the-art and areas of opportunities. The role of inter-disciplinary solutions and the need for new competencies will be discussed. The need for improved solutions, including multi-physics and multi-scale approaches, will be reviewed. Trends in technologies, advanced analysis / simulation tools and metrologies and their applications to electronic packaging will be comprehended.

Enabling Heterogeneous Packaging: A Perspective on Challenges & Opportunities

Qian WangInstitute of Microelectronics, Tsinghua University

China’s electronic packaging and testing industry has become an integral part of the global industrial chain with a rapid growth rate of above 10% CAGR. To expand its product structure and production capacity, Chinese OSATs have strengthened their world-wide cooperation and human talent strategy; merger and technology innovation becomes the theme. China OSATs have also developed several technologies and products with independent intellectual properties, such as, FO-ECP (Fanout-Embedded Chip Packaging) and FO-eWLB (Fanout-Embedded Wafer Level BGA) of JCET and eSiFO of HuaTian Technology, to meet the market demand.

Growth of China’s Semiconductor Advanced Packaging – A Win-Win in a World-Wide Context

NorAzmi AliasCollaborative Research in Engineering Science & Technology (CREST) Center

The continuous miniaturization of electronic devices into a wearable, thinner and light form factor yet demanding higher computing power and communication speed demands for new packaging schemes, substrate design and materials to ensure two most crucial aspects of energy and thermal are managed within the performance and lifetime of these devices. These market trends, products evolution and technology challenges will be shared to invite views and potential collaboration discussion among the participants.

Opportunities and Challenges for Semiconductor and Optoelectronic Packages in the EmergingMarkets of 4th Industrial Revolution (4IR)

Institute of Electrical and Electronics Engineers

38th International Electronics ManufacturingTechnology Conference (IEMT 2018)

Ramada Plaza, Malacca, Malaysia 4h – 6th September, 2018 IEEE Component, Packaging andManufacturing Technology Society

CONFERENCE REGISTRATION FORM

A. Participant’s Information (use additional sheet if needed).

Name Designation Preferred Name on Badge IEEE Membership No.

1. ------------------------------------ ----------------------------- ---------------------------------- ------------------------------2. ------------------------------------ ----------------------------- ---------------------------------- ------------------------------

B. Contact Information

Organization: Dept: Tel: Fax:Mailing Address:

City/State: Zip: Country: Email:

R E G I S T R A T I O N F E E D E T A I L SPART I: CONFERENCE REGISTRATION (Please tick ( √ ) on the appropriate box/boxes accordingly).

8CONFERENCE ON 5ST & 6th SEPTEMBER 201 (2 FULL DAYS). CATEGORIES CONFERENCE FEE SHORT COURSE FEE CONFERENCE + SHORT COURSE

[ ] SPEAKERS [ ] RM650 [ ] RM600 [ ] RM1200

[ ] IEEE MEMBER [ ] RM750 [ ] RM600 [ ] RM1250

[ ] NON IEEE MEMBER [ ] RM850 [ ] RM700 [ ] RM1500

[ ] FULL TIME STUDENTS [ ] RM600 [ ] RM500 [ ] RM1000

[ ] Vegetarian

TOTAL AMOUNT

• Conference registration fee on 5th and 6th September 2018 include daily luncheons, 2 coffee breaks, program book and softcopy of proceedings.• Short Course registration fee on 4th September 2018 include one luncheon, 2 coffee breaks and a set of course notes.

PART II: SHORT COURSE REGISTRATION (Please tick ( √ ) on the respective box accordingly)SHORT COURSE ON 4th SEPTEMBER 2018 (1 FULL DAY)

MORNING SHORT COURSE (8:15 – 12:15 PM) AFTERNOON SHORT COURSE (1:30 – 5:30 PM)

[ ] Short Course I (Full Day)Topic : Failure Analysis of Engineering Materials for Application in IoT

Instructor : Prof Cheong Kuan Yew (USM) [ ] Short Course II A (Half Day)Topic : PDC - Packaging for MEMS and Sensors

Instructor : Horst Theuss (Infineon AG)

[ ] Short Course II B (Half day)Topic : Breakthrough in semiconductor packaging problem solving through quality function and statistical methodologiesInstructor : LF Chan (LF Training)

[ ] Short Course III (Half Day)Topic : Electro-migration – The Hurdle For Miniaturization and High Power DevicesInstructor : Lee Ning Cheng (Indium)

[ ] Short Course III (Half Day)Topic : Chip to Package Interactions: Trends, Developments and Integration ChallengesInstructor : Srinivasa Reddy (Infineon)

[ ] Short Course IV-A (Half Day)Topic : WB Advancement: Smart Equipment for Smart ManufacturingInstructor : Nelson Wong (KNS)

[ ] Short Course IV-B (Half Day)Topic : Cu Wire Bonding for Automotive Grade Semiconductor Products Packaging Instructor : Mark Luke Farrugia(NXP)

PAYMENT DETAILS (IN MALAYSIAN RINGGIT)Registration is limited so please register early. To register, fill out registration form, and send along with the proof of IBG/online transaction or credit card payment. All payments for the registration are to be made payable in Ringgit Malaysia to:Acc. Name : IEEE CPMT Malaysia Acc. No. : 5051-2120-5375 Bank : Maybank BerhadPreferred payment methods are:[ ] Credit Card Payment Amount Paid:…………………[ ] IBG/Online Payment Amount Paid:…………………

e-mail your registration form to:IEMT-EMAP 2018 Secretariat, (Attention: Paramesvari Vaithilingam)Infineon Technologies (M) Sdn Bhd, Batu Berendam Free Trade Zone, 75350 Melaka, Malaysia Tel : +606 235 7668Email : Paramesvari.V@infineon.com Conference website : https://ieee-epsmalaysia.org/iemt/

To Fax / Email this Room Reservation Form to:Reservation Department, Ramada Plaza MelakaTel No: +6-06-289 9989 / +6-06-289 9808 Fax No: +6-06-2835351Email: reservations@ramadaplazamelaka.com

(PROMO CODE - 46918) ROOM RESERVATION FORM

IEMT 2018 CONFERENCE - 4 - 6 SEPTEMBER 2018Please fax or email this reservation form to the hotel as stated below:-

Name :

Address :

Email address :

Hand phone no :Name of person sharing room :

Check in date : Check out date :

Room Types inclusive of breakfast Price No. of Rooms

Premier room Single - breakfast for one (1) RM225.00++ (RM261.00 nett)

Premier room Twin - breakfast for two (2) RM250.00++ (RM290.00 nett)

Executive Deluxe King bed - breakfast for two (2) RM300.00++ (RM348.00 nett)Junior Suite Room Queen bed - breakfast for two (2) RM350.00++ (RM406.00 nett)

* Extra person sharing room with one breakfast @RM100 ++ (RM116.00 nett)* Additional breakfast @ RM35.00 nett per person

Terms & Conditions:• The booking must be made before 15 August 2018, after which it will be subject to availability. • Rates are quoted in Malaysia Ringgit (MYR) • All prices quoted are subject to 10% Service Charge, 6% Govt. Sales & Services Tax(SST) -(Taxes may be

subject to any regulatory change as and whom imposed) & a RM2.00 Melaka Heritage Tax.

Effective from 1 September 2017, 12:01am (Regulation 4 – Tourism Tax Regulation 2017) by Royal Malaysian Customs Department, all non-residents/non Malaysians will be subjected to the Tourism Tax of MYR10.00 per room per night.

• Check-in time is from 1500hrs and Check-out till 1200hrs.• A credit card number is required to guarantee the booking. • Full Payment to be settled upon check-out.• Hotel reserves the right to cancel or modify reservations where it appears that a customer has engaged in

fraudulent or inappropriate activity or under other circumstances where it appears that reservations containor resulted from a mistake or error. This rate is not valid with other promotional offer, packages, or discount.

• Any cancellation less than 7 days or in the event of no-show, one night stay per room will be imposed on thecredit card given. Any cancellation less than 2 days, a full duration of stay will be charged.

AUTHORIZATION OF PAYMENT

I hereby authorize Ramada Plaza Melaka to charge RM______________ to my credit card details as follows:Credit card type (please tick):

Visa Master Amex JCB Diners

(For Amex, please provide the ID no........................................... and / 4 digit in front of card .. ............... )Credit Card Name :Credit Card No :Expiry Date : Signature :