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Integrierte Hard- und Softwaresysteme
IHS 3: Test of Digital Systems
R.Ubar, A. Jutman, H-D. Wuttke, T. Vietzke
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Overview
1. Introduction2. Theory: Boolean differential algebra3. Theory: Decision diagrams4. Fault modelling
5. Test generation6. Fault simulation7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Applets for Learning RT- Level Test
Functional Test mode:The test vectors are operands results can be observed at the
output, no extra test parts
Deterministic Test mode:Gate level test for each FU
separatly, generate test vectors, local test panel,
cumulative FC calculation
BIST mode:Functional-, Logical- Circular Built In Self Test via extra test
part: Test Pattern Generator and Signature analyzer
Because of interaction the learning process becomes more efficient
The game-like character raises the students' curiosity
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Functional Test
• The test vectors areoperands results can be observed at the output,
• no extra test parts
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Deterministic Test
• Adder (F2)– Schematic level– Like Gate level test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Deterministic Test
• Insert test vectors manually and simulate the fault coverage (FC)
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Built-In Self-Test
• Motivations for BIST:– Need for a cost-efficient testing– Doubts about the stuck-at fault model– Increasing difficulties with TPG (Test Pattern Generation)– Growing volume of test pattern data– Cost of ATE (Automatic Test Equipment)– Test application time– Gap between tester and UUT (Unit Under Test) speeds
• Drawbacks of BIST:– Additional pins and silicon area needed– Decreased reliability due to increased silicon area– Performance impact due to additional circuitry– Additional design time and cost
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Linear Feedback Shift Register (LFSR)
Pseudorandom Test generation by LFSR:
1 x x2
x3
x4
x2 x 1x4
x3
Polynomial: P(x) = 1 + x3 + x4
Standard LFSR
Modular LFSR
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Problems with BIST
Time
Faul
t Cov
erag
e
Problem: low fault coverageThe main motivations of using random patterns
are:- low generation cost- high initial efeciency
0 2n-1
Possible patterns from LFSR: Pseudorandom
test:
Hard to test faults
0 2n-1Dream solution: find LFSR so that:
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Built In Self Test (BIST)
• Functional– No additional part
• Logical– Additional TPG
• Test Pattern Generator
• Circular– Additional TPG/SA
• Test Pattern Generator• Signature AnalyzerBuilt-in logic block observation (BILBO)
CSTP: Circular BIST, Circular self-test Path
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Test-per-Clock BIST Architectures
BILBO - Built- In Logic Block Observer:
CSTP - Circular Self-Test Path:
LFSR - Test Pattern Generator
Combinational circuit
LFSR - Signature analyzer
LFSR - Test Pattern Generator
& Signature analyser
Combinational circuit
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
13
Overview
1. Introduction2. Theory: Boolean differential algebra3. Theory: Decision diagrams4. Fault modelling5. Test generation
6. Fault simulation7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
14
Fault simulationGoals:• Evaluation (grading) of a test T (fault coverage)• Guiding the test generation process• Constructing fault tables (dictionaries)• Fault diagnosis
Generate initial T
Evaluate T
Sufficientfault coverage?
Update T Done
YesNo
Select target fault
Generate test for target
Fault simulate
Discard detected faults
Done
No morefaults
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Deductive Fault Simulation Algorithm
&
&1
1
12
345 a
c
b11
000
0
01
1 y
Fault list calculation:
La = L4 L5
Lb = L1 L2
Lc = L3 La
Ly = Lb - Lc-----------------------------------------------------------Ly = (L1 L2) - (L3 (L4 L5))
Gate-level fault list propagation
La – faults causing erroneous signalon the node a
Ly – faults causing erroneous signalon the output node y
Library of formulas for gates
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Overview
1. Introduction2. Theory: Boolean differential algebra3. Theory: Decision diagrams4. Fault modelling5. Test generation6. Fault simulation
7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
17
Combinational Fault diagnosis
F1 F2 F3 F4 F5 F6 F7
T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 1 1 0 1 0 1 0T4 0 1 0 0 1 0 0T5 0 0 1 0 1 1 0T6 0 0 1 0 0 1 1
Fault F5 locatedFaults F1 and F4 are not distinguishable
Fault localization by fault tables
E1 E2 E3
0 0 10 1 00 1 01 0 11 0 10 0 0
No match, diagnosis not possible
E1,E2,E3: ExperimentsEntry (i,j) = 1(0) if Fi is detectable (not detectable) by Tj
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Combinational Fault Diagnosis
• Fault dictionaries contain the sama data as the fault tables with the differencethat the data is reorganised
• The column bit vectors can be represented by ordered decimal codes or by somekind of compressed signature
Fault localization by fault dictionaries
No Bit vectors Decimal numbers Faults1 000001 01 F72 000110 06 F53 001011 11 F64 011000 24 F1, F45 100011 35 F36 101100 44 F2
Test results:E1 = 06, E1 = 24, E1 = 38
No match
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Learning Logic Level Diagnosis
x3
x2
x1
I3
I1
I0 &
&
I4 1
I5 1
I6 &
I2 &
&
1
1
0
0
1
01
0
1
OUT
I 6a
I 6b
I 4a
I 4b
I 1 a
I 1 b OK
F
OK
F
OK
OK
Error
Signal probing Bad student’s experiment
Fault is located with 6 probes
0
Strategy: test all inputs of the circuits =>
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Learning Logic Level Diagnosis
x3
x2
x1
I3
I1
I0 &
&
I4 1
I5 1
I6 &
I2 &
&
1
1
0
0
1
01
0
1
OUT
I 6a
I 4b
I 1 b
F
F
OK
Error
Signal probingAverage student’s experiment
Fault is located with 3 probesStrategy: test all lines of the path =>
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Binary Decision Diagrams and Testing
1
Pathactivation
FaultStuck-at-0
Fault activation
Correct signal
Error
1 0
7654321 )( xxxxxxxy
x1x2
x3 = 1x4x5x6x7
y
0
0
0 F (X)
x1
x2
y
x3
x4 x5
x6 x7
0
11
0x1
x2
y
x3
x4 x5
x6 x7
0
1
15427613
xxxxxxxy
1
0
0
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Sequential Fault Diagnosis
Sequential fault diagnosis by Edge-Pin Testing
T1 F1,F4,F5,F6,F7P
T2P
F1,F4
F2, F3 T3P
F3
F
F
F2
F
F5,F6,F7 T3P
F5,F7
F
F6
T4P
F7
F
F5
F1,F2F3,F4F5,F6F7
F1 F2 F3 F4 F5 F6 F7
T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 1 1 0 1 0 1 0T4 0 1 0 0 1 0 0T5 0 0 1 0 1 1 0T6 0 0 1 0 0 1 1
Two faults F1,F4 remain indistinguishable Not all test patterns used in the fault table are needed
Different faults need for identifying test sequences with different lengthsThe shortest test contains two patterns, the longest four patterns
Diagnostic tree:
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Sequential Fault Diagnosis
Guided-probe testing at the gate level
x8
No faultsP
F
x6
P
F
x4
x5,2
P
F
OR- x8 is faulty
x2
P
F
x3,1 PF
NOR- x5 is faulty
x3
P
F
Line x3,1 is faulty
Line x3 is faultyLine x2 is faulty
Line x2is faultyF
P
x3,2
P AND- x6 is faultyF x3
P
F
Line x3,2 is faulty
Line x3 is faulty
x2
x3
x4
x3,1x3,2
x5,1x5,2
x5
x6
x7
x8
11
1
Searh tree:
Faulty circuit
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault Collapsing
Further reduction of the complexityFault Collapsing:Two faults are considered equivalent if the faulty functions produced by the two faults are equal. Alternatively, the two faults are equivalent if they can be detected by the same tests.(a/0=z/0) b/0=z/0
a/0 and b/0can be dropped
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault Collapsing
Further reduction of the complexityFault Collapsing:A fault f is considered to dominate another fault gwhen every test for g is also a test for f.
z/1 dominatesthe fault a/1
Fault z/1 can bedropped
Test vektors{01,10,11}
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault collapsing
Equivalence realtionshipsAND-Gate OR- Gate NOT-Gate
Dominance realtionships
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault collapsing
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault collapsing
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault Collapsing
Which faults can be dropped?
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault Collapsing
Which faults can be dropped?
Faults: {s/0, s/1, s3/0, s3/1, a/0, a/1, b/0, b/1, s1/0, s1/1, s2/0, s2/1, c/0, c/1, d/0, d/1, z/0, z/1}Local collapsing: {s/0, s/1, s3/0, s3/1, a/1, b/1, s2/1, c/0, d/0, z/1}The faults s/0, b/1, z/1 dominate s3/1, faults s/1, a/1 dominate s2/1. The fault s3/0 is equivalent to c/0. The global collapsed fault list for the circuit is thus {s2/1, s3/1, c/0, d/0}. Hence, by using global fault collapsing number of faults from 18 to 4. This is in effect a 77.78% reduction from the original fault list.
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fragen