impact of the itrs metrology roadmap

Impact of the ITRS MetrologyImpact of the ITRS MetrologyRoadmapRoadmap

Where am Igoing and

how will I getthere ?

Alain Diebold

AGENDAAGENDA• ITRS Overview

• Metrology Roadmap Overview

• Lithography Metrology

• Front End Processes Metrology

• Interconnect Metrology

• Integrated Metrology

• Materials & Contamination Characterization

• The Future

Metrology

Interconnect

Packaging

Lithography Front End Processes

Process Integration, Devices. & Structures

ITRS Focused RoadmapsITRS Focused Roadmaps

ITRS Cross-cut RoadmapsITRS Cross-cut Roadmaps

Metrology

ES&H

Modeling &Simulation

Defect Reduction Technology

Three ITRS views of the futureThree ITRS views of the future

IC Node and Capability Timing

Logic and DRAM, wireless, SOC

New Process Tool Timing

sub field

stitched fields

stitchingdeflectors

step scan

mask stage

waferstage

scan

step

interferometers

lens

Litho λλλλ, cluster, wafer size

New Materials, Structures, & Process Timing

SECS-IICIM Framework

Compatible

Add-OnSensors

EquipmentControlSystem

ProcessChamber

Add-On Sensors

S1 S2

SensorActuators

connection

connection

FactoryCIM

FDC & MBPCalgorithm execution

Real-Time

MIMO

Embedded

Gate Gate

Drain

Source

High/Low k, USJ, beyond CMOS

ITRS High Level IC TimingITRS High Level IC TimingChip Frequency: Logic - 1999 ITRSChip Frequency: Logic - 1999 ITRS

Chip Frequency

1

10

100

1,000

10,000

100,000

1980 1990 2000 2010 2020

MH

z

U.S. MPU: high perf.

U.S. MPU: cost perf.

Toshiba

ITRS 1999: on-chip local clock (high perf.)

ITRS 1999: on-chip, across chipclock (high perf.)

ITRS 1999: on-chip, across chipclock (cost perf.)

1998 Update: on-chip localclock, (high perf.)

1998 Update: on-chip, across chipclock (high perf.)

1998 Update: on-chip, across chipclock (cost perf.)

b1chf00a1.xls 7/2/99

1999-2011No Change1998 Update-> 1999 ITRS

Potential 10Ghz Limit ?Identified by Design TWG1998 Update-> 1999 ITRS

Historical

Data /

Trends

Source: S'TECH CAG

Historical Cost-Perf Trend: ~ 2x / 2.5 Years

Recent Hi-Perf Historical Trend: ~ 2x / 2 Years

ITRS Hi-Perf Proposed Trend: ~ 2x / 4 Years

ITRS Cost-Perf Trend: ~ 2x / 6 Years

ITRS Roadmap Node TimingITRS Roadmap Node Timing(from Litho TWG Summary

95 97 99 01 04 07 10

1994

1997

1998

Min

imu

m F

eatu

re S

ize

(nm

)

500

350

250

180

130

100

70

50

35

25

IRCAgreement as of

Sept 24,1999

MPU Gate

DRAM Half Pitch

95 97 99 01 04 07 10

13

13








• The Future

Metrology

OFF-Line

In-SituIn - Line

No Single Business Model for New Metrology?No Single Business Model for New Metrology?

New Materials, Structures, & Process Timing


Compatible

Add-OnSensors


ProcessChamber

Add-On Sensors

S1 S2

SensorActuators

connection

connection

FactoryCIM


Real-Time

MIMO

Embedded

Gate Gate

Drain

Source

High/Low k, beyond CMOS, USJ

New Process Tool Timing

sub fie

ld

stitched fields

stitchingdeflectors

step scan

mask stage

waferstage

scan

step

interferometers

lens

Litho λλλλ, cluster, wafer size

IC Node and Capability Timing

Logic and DRAM, wireless, SOC

Driver New Metrology

Optical & Electrical Metrology for High k, USJ, and low k

157 nm EllipsometrySensors & Clustered Metrology

High Frequency testing of low k

Microscopy is a critical needMicroscopy is a critical needMetrology

Masks

Dense Lines 130nm

130nm Contacts

Semi Dense = 75nm

New devices

SEMSEMDepth of Focus IssueDepth of Focus Issue

Today DoF ~ 0.4 micron2 nm/0.005 rads = 400 nm

Tomorrow DoF ~ 0.02 micron1 nm/0.050 rads = 20 nm

SPM SPM Probe Tip IssueProbe Tip Issue

Dai, et al.,Nature 384, 147 (1996

High Aspect Ratiossub 100 nm trench and via widths

DoFDoF = (resolution) / = (resolution) / (convergence angle) (convergence angle)

David Joy, Univ. of TN

Nanotip fieldemitter

Structure

Coherent illumination

unscattered

scattered

illumination footprint

•At low energies and glancing angles, the reflectivity = 50%

detector

detector

Electron Holography :Electron Holography :a Long Term Potential Solutiona Long Term Potential Solution

Interface ControlInterface Control

Low k / barrieretch stop / low k

Barrier Layer / Cu

14 Å 17 Å 20 Å 29 ÅC-V

HRTEM 14.2 ± 1.7 Å 17.1 ± 2.0 Å 18.6 ± 1.7 Å 26.2 ± 2.2 Å

The Metrology Precision RoadblockThe Metrology Precision RoadblockYear of First Product

ShipmentTechnology Generation

1999180 nm 2000 2001 2002

130 nm 2003 2004 2003100 nm Driver

DRAM 1/2 Pitch 180 165 150 130 120 110 100 D½Logic Isolated Lines 140 120 100 85 80 70 65 M Gate

Microscopy and LithographyMicroscopy resolution(nm) for P/T=0.1 1.4 1.2 1.0 0.85 0.8 0.7 0.65 MPU

Wafer Gate CDControl* 13 12 10 8.5 8 7 6.3 MPU

Wafer CD ToolPrecision* P/T=.2Isolated Lines**

2.6 2.4 2.0 1.8 1.6 1.4 1.3 MPU

Mask Area MetrologyTool Precision P/T=.2 4.8 4.2 3.4 2.8 2.6 2.4 2.2 MPU

Front End P roce sse sLogic Dielectric ThickPrecision 1σσσσ (nm) B 0.0025 0.0024 0.0021 0.0017 0.0016 0.0013 0.0012

MPUGate

2D Dopant ProfileSpatial Resolution (nm) 3 3 3 2 2 2 1.5

MPUGate

In te rconne ctBarrier layerThick (nm)process range (± 3σ σ σ σ )Precision 1σσσσ (nm)

2320%0.08

1920%0.06

1620%0.05

1320%0.04

1120%

0.035

720%0.02

320%0.01

MPU



• Lithography Metrology& New Structures from PIDS





• The Future

Lithography MetrologyLithography Metrology

concave aspheric mirrors

waferconvex

aspheric mirrors

clear aperture

mask

laser

Xe gas jetplasma

EUV radiation

sub fie

ld

stitched fields

stitchingdeflectors

step scan

mask stage

waferstage

scan

step

interferometers

lens

SCALPEL

EUV

193 nm and 157 nmOptical Extension

Research Required Development Underway Qualification/Pre-Production

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the technology solution.

First Year of IC Production 2002 20051999 2011 2014 2008

248nm

248nm + PSM193nm

193nm + PSM157nmEPLXRLIPL

NarrowOptions

157nm + PSMEPLEUVIPLXRLEBDW

NarrowOptions

EUVEPLIPLEBDW

NarrowOptions

EUVIPLEPLEBDWInnovative Technology

NarrowOptions

Note: Production level exposure tools should be available one year before first IC shipment.

Tec

hnol

ogy

Opt

ions

at T

echn

olog

y N

odes

(D

RA

M H

alf P

itch,

nm

)

180

130

100

70

50

35

DRAM Half Pitch(Dense Lines)

Lithography MetrologyLithography Metrology

Wafer Measurements• CD

• overlay• defects

Mask Measurements• CD

• inspection

Low k Impacts• CD

• overlay• defects

New Litho Tools=

New Masks

• Phase Shift & Optical Proximity Correction

• EUV and Electron Projection

Gate Gate

Drain

SourceVerticalVertical

TransistorTransistor

CD is a FilmCD is a FilmThicknessThickness

Rafi Kleiman

250 nm isolated linesNominal Feature:225nm Isolated

-2

Exp (mJ×cm )®Focus (mm) ¯

8.775 9.450 10.125 10.800 11.475 12.150 12.825 13.500 14.175

-0.1

Feature Size 244 232 248 251 250 266 210 211+0.1

Feature Size 298 301 280 272 270 267 263 249 240+0.3

Feature Size 296 291 276 285 270 243 235 226 236+0.5

Feature Size 289 281 269 264 256 238 233 221 236+0.7

Feature Size 293 276 251 226 195 194

Focus / Exposure MatrixFocus / Exposure MatrixA routine setup metrology requirementA routine setup metrology requirement

Lithography MetrologyLithography MetrologyImprove CD-SEMImprove CD-SEM thru thru 100 100 nm nm nodenode

top downCD-SEM

NEED: Determine CD from Fundamental Model

2D / 3D Information

Intensity Profiles From SNP / SEMIntensity Profiles From SNP / SEM

SEMSNP

Thanks to Joe GriffithThanks to Joe Griffith

Microscopy Issues:Microscopy Issues:CD and Detection requireCD and Detection requirenew microscopynew microscopy

• SEM with resolution required for sub 100 nm has poor Depth of Focus

• 3D Information Required

• Improved throughput required

Today : Depth of focus > 1 micron

SEM

With Future Resolution: Depth of focus << 1 micron

Scatterometry Scatterometry : A Potential Solution: A Potential Solution

Inputlaser beam

Scattered light

Detector

Θ Θ

Resist

ARC

Poly

Parameters

Variables :CD = 270 ± 60nm

Resist thickness = 725 ± 25nmPoly thickness = 2500 ± 350nm

ARC thickness = 80 ± 10nmSidewall angle = 86 ± 2º

Fixed :Pitch

Resist, Poly and ARC optical properties

Signature GeneratorSoftware

ΑΑΑΑll parametercombinations

2-ΘΘΘΘ scatterometer: CDS-2Vary Vary λλλλλλλλ

Fixed angleFixed angle

Advantage of Advantage of scatterometryscatterometryis throughput and sensitivityis throughput and sensitivity

Wavelength variationWavelength variationscatterometryscatterometry can be can be

done on andone on an Ellipsometer Ellipsometer

1717

Offset from CD-SEM by Angle

-20

-10

0

10

20

30

40

50

60

84 85 86 87 88 89 90 91 92

Sidewall Angle

CD

Off

set

(S

cat

tero

met

er -

SE

M) Dense Line Offset

Isolated Line Offset

Is this evidence for loss of Depth of Focus ?

CC Baum and S Farrer




• Front End Processes Metrology& New Structures from PIDS




• The Future

Key FEP CMOS Scaling ChallengesKey FEP CMOS Scaling Challenges

Hi-K Dielectric

Gate Electrodes

USJ Process

Engineered Contacts

70nm“Beyond CMOS Era?”

250

180

130

100

“CMOSScaling”

2005

1999

S/D Leakage-Short ChannelS/D Leakage-Short Channel

Boron PenetrationBoron Penetration

Poly Depletion LayerPoly Depletion Layer

Highly Doped UltraHighly Doped Ultra Shallow Xj scaling Shallow Xj scaling

Contact ResistanceContact Resistance

Gate Leakage - TunnelingGate Leakage - Tunneling

Hi-Poly ResistanceHi-Poly Resistance

50

35

25

18

2011

2017

Absorbs in visible

zro2-tauclor Optical Constants

Photon Energy (eV)2.0 3.0 4.0 5.0 6.0 7.0

Rea

l(Die

lect

ric C

onst

ant)

, ε 1

Imag(D

ielectric Constant),

ε2

4.0

5.0

6.0

7.0

8.0

9.0

10.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

ε1ε2

ZrO2

Impact of New FEP MaterialsImpact of New FEP Materials

100 nm

70 nm

130 nmOxynitrideN control

correlate correlate electrical metrology (C-V & I-V)

with optical metrology

Should Future In-Line Ellipsometers include IR or VUV

Issue:Control of Oxynitride, Silicon dioxide/Silicon nitride stacks

and high k with oxynitride interfacial layers

Impact of Ultra-Shallow JunctionsImpact of Ultra-Shallow Junctions

Year

0

5

10

15

20

25E

OT

(A

)

0

10

20

30

40

50

60

70

Xj (

nm

)

EOT (A) 22 17 12 10 8 6 5

Xj (nm) 66 48 40 34 28 25 24

1999 2002 2005 2008 2011 2014 2017

Regime for Si/SiO2 nitride extensions

TransitionRegion

Regime for high-kand metal gates

Regime for Transition Regime for Implant/RTA,LTA Region Elevated S/D

Node (D1/2) 180 130 100 70 50 35 25

GL (nm) 140 86- 90 65 45 30-32 20-22 18

Junction Depth MeasurementJunction Depth Measurementin the FABin the FAB

Objective lens

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RedGeneration laserIR Probe laser

Beamsplitter

Visionsystem

Detector

Detail inwafer

Junction

BeamExcess carriers

Carrier Illumination

Example of new technology from a Startup : Boxer-Cross

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

290 300 310 320 330 340 350Boxer Cross Junction Depth (A)

Dri

ve C

urr

ent

(arb

. Un

its)

Correlation to drive current(0.18 µµµµm NMOS)

AMD and Boxer-Cross

Transistor Evolution ?Transistor Evolution ?

DeviceStructure

Size

PlanarCMOS

Non-Planar CMOS

New SwitchStructure

0 - 7 years. 7 - 12 years 12 + Years.

TIME

Sub 50nm ?

Transistor and Capacitor MetrologyTransistor and Capacitor MetrologyNew Transistor Designs New Transistor Designs vs vs MetrologyMetrology

Vertical,Vertical, dual channel dual channel Transistor Transistor sub 100nm sub 100nm

CD done by filmCD done by film thickness thickness

Doping in LDD byDoping in LDD by diffusion diffusion

Rafi Kleiman Rafi Kleiman (Lucent) (Lucent)

Gate Gate

Drain

Source

200 nm

Transistor and Capacitor MetrologyTransistor and Capacitor MetrologyVertical Transistor : Gate Dielectric is vertical

Front End Process MetrologyFront End Process MetrologyIn-Situ Needs In-Situ Needs vs vs Integrated Metrology TrendIntegrated Metrology Trend

CooldownChamber

Loadlocks

RTP-RTO wet/dry-RTN-RTA

Nitride (Thin/Thick) Poly (Doped/Undoped)

FutureHigh K

FuturePreclean

ΑΑΑΑ

ΒΒΒΒ

C D

E

F

Clusteredgate dielectric

& electrode

e.g., e.g., Metal MetalGate forces in-Gate forces in-situ metrologysitu metrologyfor dielectricfor dielectric








• The Future

Interconnect Challenges due to ClockInterconnect Challenges due to ClockFrequency:Frequency:

How long will Copper / low k work?How long will Copper / low k work?

0.1

1

10

100

Rel

ativ

e D

elay

Gate Delay

Local

Global withR t(Scaled Die Edge)

Global w/oR t(Scaled Die Edge)

250180 130 100 70 50

(Fan out 4)

(Scaled)

35

Technology Node (nm)Low k / barrier

etch stop / low k

Low Low κκκκκκκκ Timing Timing

70nm

250

180

130

100

2005

1999

50

35

25

18

2011

2017

κ= 2

.7–3

.5κ=

1.6–2

.2

κ= 1

.5

κ= <

1.5

κ= <

1.5

Porous Insulators

Impact on MetrologyImpact on Metrology

Low κκκκ Porosity

Gradient in % Porosity

Thickness MeasurementNew Optical Modelsfor each low κκκκ stack

CMP ControlR&D for each new

low κκκκ stack

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1

2

3

4

0

50

100

150

200

250

-25 0 25 50 75 100

Time (ns)

Sig

nal

(m

V)

12

3

1 / Acoustic Frequency

Cu 270 MHzCu 270 MHz

ZY

X

Wafer Positioning Stage

Sample

Detector

Aperture

Lens

Probe Laser

Excitation Laser

Neutral Density (ND) Filters

Phase Masks (PM)

Lens

Lens

20x 90 mm Spot Size

~1-2 seconds/point (measurement + data analysis + stage motion)

Excitation LaserDiode-Pumped, Pulsed, Frequency-Doubled Nd:YAG microchip laser. 600 ps Pulse

AlGaAs Diode Laser

Metal Film Thickness and CMP ControlMetal Film Thickness and CMP Control3 methods3 methods

•• ISTS ISTS

••PicosecondPicosecond UltrasonicsUltrasonics

•• X-ray Reflectivity X-ray Reflectivity

•• Near Future : Near Future : Patterned Wafer Capability Patterned Wafer Capability through better modeling through better modeling

Depth of Focus Requirements for Depth of Focus Requirements for LithoLithoCMP Metrology tool should measure what litho tool “sees”

TILT CONTINUOUSLY DURING SCAN

Scanning SteppersScanning Steppers

Site FrontsideScanning*

site reference

Range = SFSRDeviation = SFSD

SEMI STD

SITE LEAST SQUARESREFERENCE PLANE

TILT ONCE PER SITE

Full Field SteppersFull Field SteppersSEMI STD

Site Frontsideleast-sQuaredsite reference

Range = SFQRDeviation = SFQD

AGENDAAGENDA

• ITRS Overview







• The Future

SENSOR based Integrated MetrologySENSOR based Integrated MetrologyComments on :Comments on :Advanced Process Control - Advanced EquipmentAdvanced Process Control - Advanced EquipmentControlControl


Compatible

Add-OnSensors


ProcessChamber

Add-On Sensors

S1 S2

SensorActuators

connection

connection

FactoryCIM


Real-Time

MIMO

Embedded

AEC/APC GOAL : AEC/APC GOAL :

model based predictive controlmodel based predictive control

based on process and metrologybased on process and metrology

models using in-situ and in-linemodels using in-situ and in-line

measurementsmeasurements

Momentum Shift ? Momentum Shift ?

Now suppliers advocate Now suppliers advocate

Integrated Metrology Integrated Metrology

AGENDAAGENDA

• ITRS Overview







• The Future

Inte

nsi

ty

1400 1600 1800 2000 22000

500

1000

1500

2000

Microcalorimeter

Energy (eV)

W M γγγγW M ζζζζ

1,2

Si Kββββ

W Mββββ

W M αααα 1 2

WSi2 on SiO2

Si Kα α α α 1 21 21 21 2

EDS spectrometer

Martinis, Woolmanet al. NIST

New New MicrocalorimeterMicrocalorimeter X-ray detector X-ray detectorIndustry needs accelerated commercializationIndustry needs accelerated commercialization

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050100150200

-20

-10

0

10

20

30Bulk-like Oxide

Sub-Oxide

Total O Signal

Oxygen Signal (Arb. Units)

Dis

tan

ce (

Å)

Interfacial Oxide

Electron Energy Loss & HA-ADF STEMElectron Energy Loss & HA-ADF STEMInterfacial State changes in O and Interfacial State changes in O and SiSi K edge K edge

Dave Muller - Lucent in G. Temp et al, IEDM 98, p615

High Angle - Annular Dark Field STEMHigh Angle - Annular Dark Field STEM

GaAs

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EELS Spectrometer

Annular Detector

1.4Å

As Ga

1.3Å Scanning

Probe

Objective Lens

��

I ∝∝∝∝ Z 2

Z=31 Z=33

Electron Beam

Thin Foil Sample

Image Plane

diffracted beammisses annular detector

Enlarged view of Lattice Planes“on axis” to

electron beam

scatter from atoms or atomic columns

HA-ADF & EELS

2D 2D Dopant Dopant ProfilingProfilingRequires Improved Spatial ResolutionRequires Improved Spatial Resolution

180 nm

source drain

gate

NanopotentiometryNanopotentiometryTEM Electron Holography

IMEC - W.IMEC - W. Vandervorst Vandervorst

SSRMSSRMSCMSCM

R. Kleiman - Lucent

Rau and Ourmazd et al., IHP

GI-XRR at NIST - R. GI-XRR at NIST - R. DeslattesDeslattes, et al, et al








• The Future

Metrology Funding TypesMetrology Funding Types

Innovation Driven• Entrepreneurial • High Market Risk• Longer Dev. Time• Can precede requirement

• “Classic funding”

• Self Risk Mitigation

Application Driven• Equipment Supplier “Customer” Driven • Medium Market Risk• Shorter Dev. Time• Specific Process requirement• Joint funding with Process tool supplier• Co-Risk Mitigation

Market Driven• ex post facto IC “Customer” Driven • Low Market Risk• Market Window• Specific Process requirement• Possible Joint funding with IC Manufacturer• Self Risk Mitigation

~10% ~30% ~ 60%

ZY

X

Wafer Positioning Stage

Sample

Detector

Aperture

Lens

Probe Laser

Excitation Laser

Neutral Density (ND) Filters

Phase Masks (PM)

Lens

Lens

20x 90 mm Spot Size

~1-2 seconds/point (measurement + data analysis + stage motion)

Excitation LaserDiode-Pumped, Pulsed, Frequency-Doubled Nd:YAG microchip laser. 600 ps Pulse

AlGaAs Diode Laser

Barrier/Metal Thickness ISTS

&Picosecond acoustics 157 nm ellipsometry

Si

Light source(Xe, D2, lasers)

polarizeranalyzer

Detector, electronics, computer(PMT, diodes)

monochromator

Ep

s

Polarizationbefore sample

p

s

E(t)

Polarizationafter sample

p

s

p

s

Will Market Risks allow for innovation?Will Market Risks allow for innovation?

Metrology RoadmapMetrology Roadmap

Metrology Timing Metrology Timing vsvsInfrastructure CapabilitiesInfrastructure Capabilities

Process Tool Supplier Development

Pilot Line FAB Startup & Volume Manufacture

Volume Sales of Metrology Tools

Need for Process Tool

Qualification/Preproduction

Development Underway

Typical Potential Solutions Time Line for Process Tool

Research Required

Need for Metrology Tool

Gap in long term R&D Gap in long term R&D Spending + Development Spending + Development Funding ModelFunding Model

Dave Perloff - VeecoDave Perloff - Veeco

2000 Metrology Roadmap2000 Metrology Roadmap

IN-SITU IN-LINE OFF-LINE / AT-LINE

EuropeEurope Alec Reader (Philips)Alec Reader (Philips)WilfriedWilfried VandervorstVandervorst (IMEC) (IMEC)

JapanJapan Fumio Mizuno (Hitachi)Fumio Mizuno (Hitachi)

Taiwan Taiwan Henry Ma (EPISIL)Henry Ma (EPISIL)George Yen (George Yen (ProMOSProMOS))

USUS BobBob Scace Scace (NIST) (NIST)Alain Alain DieboldDiebold (SEMATECH) (SEMATECH)

Acknowledgements

• Will Chism, Jesse Canterbury, Lizz Judge

• Curt Richter and countless others at NIST

• US Metrology TWG

• Metrology and Analytical Lab Managers Councils

• ISMT Litho images - Dan Holladay

• Images of Litho tools - John Canning and Chris VanPeski - International SeMaTech

• FEP overhead - Mike Jackson, Howard Huff, EdStrickland, Rinn Cleavelin

Junction Depth MeasurementJunction Depth Measurementin the FABin the FAB

Objective lens

��

��

��

RedGeneration laserIR Probe laser

Beamsplitter

Visionsystem

Detector

Detail inwafer

Junction

BeamExcess carriers

Carrier Illumination

Example of new technology from a Startup : Boxer-Cross

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

290 300 310 320 330 340 350Boxer Cross Junction Depth (A)

Dri

ve C

urr

ent

(arb

. Un

its)

Correlation to drive current(0.18 µµµµm NMOS)

AMD and Boxer-Cross

impact of the itrs metrology roadmap

Documents