Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 3, Number 9 (2013), pp. 1121-1134 © Research India Publications http://www.ripublication.com/aeee.htm

Improved NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes

E. Ramakrishna Naik* and L.S. Devaraj** *M.Tech(VLSI), Dept. of ECE, Intellectual Institute Of Technology, Anantapur.

Assistant professor Dept. of ECE, Intellectual Institute Of Technolog, Anantapur. E-mail: *ramakrishnanaik4067@gmail.com, **ramakrishna4067@gmail.com

Abstract

Multi-level cell (MLC) NAND flash memories are popular storage media because of their power efficiency and large storage density. Conventional reliable MLC NAND flash memories based on BCH codes or Reed-Solomon (RS) codes have a large number of undetectable and miscorrected errors. Moreover, standard decoders for BCH and RS codes cannot be easily modified to correct errors beyond their error correcting capability t = [d-1/2] , where d is the Hamming distance of the code. In this paper, we propose two general constructions of nonlinear multi-error correcting codes based on concatenations or generalized from Vasil’ev codes. The proposed constructions can generate nonlinear bit-error correcting or digit-error correcting codes with very few or even no errors undetected or miscorrected for all codewords. Moreover, codes generated by the generalized Vasil’ev construction can correct some errors with multiplicities larger than t without any extra overhead in area, latency, and power consumption compared to schemes where only errors with multiplicity up to t are corrected. The design of reliable MLC NAND flash architectures can be based on the proposed nonlinear multi-error correcting codes. The reliability, area overhead and the penalty in latency and power consumption of the architectures based on the proposed codes are compared to architectures based on BCH codes and RS codes. The results show that using the proposed nonlinear error correcting codes for the protection of MLC NAND flash memories can reduce the number of errors undetected or miscorrected for all codewords to be almost 0 at the cost of less than 20% increase in

E. Ramakrishna Naik & L.S. Devaraj

1122

power and area compared to architectures based on BCH codes and RS codes. Index Terms: Multi-error correcting codes, nonlinear codes, re-liable memory.

1. Introduction The semiconductor industry has witnessed an explosive growth of the NAND flash memory market in the past several decades. Due to its high data transfer rate, low power consumption, large storage density and long mechanical durability, the NAND flash memories are widely used as storage media for devices such as portable media players, digital cameras, cell phones, and low-end netbooks.

The increase of the storage density and the reduction of the cost per bit of flash memories were traditionally achieved by the aggressive scaling of the memory cell transistor until the multi-level cell (MLC) technology was developed and implemented in 1997. MLC technology is based on the ability to precisely control the amount of charge stored into the floating gate of the memory cell for he purpose of setting the threshold voltage to a number of different levels corresponding to different logic values, which enables the storage of multiple bits per cell.

However, the increased number of programming threshold voltage levels has a negative impact on the reliability of the device due to the reduced operational margin. The raw bit error rate of the MLC NAND flash memory is around 10 and is at least two orders of magnitude worse than that of the single level cell (SLC) NAND flash memory . Moreover, the same reliability concerns as for SLC NAND flash memories, e.g., program/read disturb, data retention, programming/erasing endurance, and soft errors [may become more significant for MLC NAND flash memories.

Hence a powerful error correcting code (ECC) that is able to correct at least 4-bit errors is required for the MLC NAND flash memories to achieve an acceptable application bit error rate, which is no larger than 10 .

Several works have investigated the use of linear block codes to improve the reliability of MLC NAND flash memories. In, the authors presented a high-throughput and low-power ECC

NAND flash memory chip incorporating a 250 MHz BCH error correcting

architecture was shown. The author of demon-strated that the use of strong BCH codes (e.g., 12,15,67,102) can effectively increase the number of bits/cell thus further in-creasing the storage capacity of MLC NAND flash memories. In , an adaptive-rate ECC architecture based on BCH codes was proposed. The design had four operation modes with dif-ferent error correcting capabilities. An ECC architecture based on

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E. Ramakrishna Naik & L.S. Devaraj

1126

clock cycle, 10 information bits are inputted to the encoder. The most significant bit of the message is input via a separate port. The first information bit for the BCH

code is derived by XORing with the first bit of at the first clock cycle (when as shown in the figure). The bottom half of the architecture is a parallel LFSR

used to generate the redundant bits for BCH codes. is a 10 70 binary matrix . During each clock cycle, the 10 most significant bits in the shift register are XORed with the new input and then multiplied by . The output of the multiplier is XORed with the shifted data from the shift register to generate the input to the register. The top half of the architecture is for the computation of nonlinear redundant bits. During the even-numbered clock cycles, the 10-bit input is buffered. During the odd-numbered clock cycles, the buffered data is multiplied by the new input in and then added to the output registers. A 10-bit mask is XORed with the data in the output register to generate the nonlinear redundant bits. For the (8281,8201,11) 5-error-correcting code, 820 clock cy-cles are required to complete the encoding of the message.

The encoder for the (8280,8200,11) nonlinear 5-bit error correcting code based on Theorem 1 is similar to the one shown

Fig. 2: Architecture of the encoder for the (8281,8201,11) nonlinear 5-error-

correcting code.in Fig. 2. The same structure (top half) is used to compute the 10-bit nonlinear redundant bits. The main difference be-tween the two encoders is as follows. First, the encoder for the (8280,8200,11) code does not require a separate port for . All information bits are input via in 820 clock cycles, assuming a parallelism level of 10. Second, the encoding of the (8280,8200,11) code needs one more clock cycle to complete compared to the (8281,8201,11) code. At the 821th clock cycle, the input to (Fig. 2) is switched to the already-generated nonlinear check bits using a 10-bit 2:1 multiplexer.The former, however, requires that all operations are performed in

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Improved NAND Flash Memories Storage Reliablity Using Nonlinear Multi 1131

the multipliers in other blocks for the purpose of reducing the hardware overhead. Since the square operation is simple in , the inverter adds minimal area overhead and has a latency similar to the Galois filed multiplier in our design.

C. Area, Latency, and Power Consumption The area, latency, and the power consumption for architec-tures based on the six alternatives presented in Section V are shown in Table III. The designs are modelled in Verilog and synthesized in RTL Design Compiler using 45-nm NANGATE library [34]. In practice the logic circuits used in NAND flash memory could be different from those used in standard digital designs. The estimation presented here is only for the purpose of investigating the increase in area, power and latency of archi-tectures based on the proposed nonlinear multi-error correcting codes compared to architectures based on the widely used BCH codes and RS codes.

During the synthesis we fixed the clock rate for the encoder and the decoder and compared the area and the power consump-tion for architectures based on different codes. The encoders work at 1 GHz. The decoders work at a lower frequency— 400 MHz—due to the long critical path in Berlekamp-Massey block [12]. The six alternatives require the similar latency in terms of the number of clock cycles for encoding and decoding. Due to the computation of the error magnitude and the pipeline for the inverter in the Galois field, digit-error correcting codes (RS, etc.) need eight more clock cycles to complete the decoding compared to bit-error correcting codes (BCH, etc.).

The encoders for the digit-error correcting codes require 40% 50% more area overhead and power than the encoders for bit-error correcting codes (see Figs. 6 and 7) due to the fact that all operations are in . The decoders for digit-error correcting codes, however, require 20% 30% less overhead in area and power because of a much simpler serial architecture.

Compared to BCH codes and RS codes, the proposed non-linear multi-error correcting codes need about 10% 20% more area and power in total for the encoder and the decoder and have the similar latency in terms of the number of clock cycles required to complete the encoding and decoding. The(8281,8201,11) nonlinear 5-bit error correcting codes based on Theorem 3 (columns 6 and 7 in Table III), for example, requires 17.5% more area and consumes 10.0% more power in total for the encoder and the decoder compared to the (8262,8192,11) BCH code.

We note that the encoder and the decoder are only a very small portion in the MLC NAND flash memory chip, where the major portion is the memory cell array. Thereby the increase in area overhead for the encoder and the decoder is not significant for the reliable memory design.

5. Implementation and Results The proposed NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes. The code is completely synthesized using Xilinx XST and

E. Ramakrishna Naik & L.S. Devaraj

1132

implemented on device family Spatran 3E, device XC3S500E, package FG 320 with speed grade -4.

6. Conclusion In this paper, the constructions of two nonlinear multi-error correcting codes are proposed. Their error correcting algorithms are presented. The proposed codes have much less undetectable and miscorrected errors than the conventional BCH codes and RS codes.

The designs of reliable MLC NAND flash memories based on the proposed nonlinear multi-error correcting codes are pre-sented. We compare the area, the latency and the power con-sumption of the reliable MLC NAND flash architectures using the proposed nonlinear multi-error correcting codes to architectures based on BCH codes and RS codes. The encoder and the decoder for all the alternatives are modeled in Verilog and synthesized in RTL Design Compiler. The results show that architectures based on nonlinear multi-error correcting codes can have close to zero undetectable and miscorrected errors while consuming less than 20% more area and power consumption than architec-tures based on the BCH codes and the RS codes.

References

[1] G. Atwood, A. Fazio, D. Mills, and B. Reaves, “Intel Strata memory technology overview,” Intel Technol. J., vol. 1, 1997 [Online]. Avail-able: http://www.intel.com/technology/itj/archive/1997.htm

[2] J. Cooke, “The inconvenient truths about NAND flash memory,” pre-sented at the Micron MEMCON Presentation, Santa Clara, CA, 2007.

[3] R. Dan and R. Singer, “Implementing MLC NAND flash for cost-effective, high capacity memory,” M-Syst. White paper, 2003 [Online]. Available: http://support.gateway.com/s/Manuals/Desk-

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[4] tops/5502664/Implementing_MLC_NAND_Flashwhite%20paper.pdf [5] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash

memory,” Proc. IEEE, vol. 91, no. 4, pp. 489–502, Apr. 2003. [6] G. Cellere, S. Gerardin, M. Bagatin, A. Paccagnella, A. Visconti, Bonanomi,

S. Beltrami, R. Harboe-Sorensen, A. Virtanen, and [7] Roche, “Can atmospheric neutrons induce soft errors in NAND floating gate

memories?,” IEEE Electron Device Lett., vol. 30, no. 2, pp. 178–180, Feb. 2009.

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