improving timing accuracy for tlm-lt models …€¦ · advanced temporal decoupling (atd) ......

Advanced Temporal Decoupling (ATD) European SystemC Users’ Group Workshop

2013/03/22 Grenoble

Simon Hufnagel, Hendrik Post, Nico Bannow Christoph Grimm

Robert Bosch GmbH Technical University Kaiserslautern

Corporate Sector

Research and Advance Engineering

CR/AEH2-Hf | 2013/03/22 | AE2-1094 | © Robert Bosch GmbH 2013. Alle Rechte vorbehalten, auch bzgl. jeder Verfügung, Verwertung,

Reproduktion, Bearbeitung, Weitergabe sowie für den Fall von Schutzrechtsanmeldungen.

Improving Timing Accuracy for TLM-LT

Models

1



Content

Context

Transaction Level Modeling

Advanced Temporal Decoupling (ATD)

Case Study “Night Vision“

Conclusion

2

Seamless Modeling

Refinement, Evaluation,

Test

CR/AEH2 | 2013/03/22 | AE2-1094 | © Robert Bosch GmbH 2013. Alle Rechte vorbehalten, auch bzgl. jeder Verfügung, Verwertung,


Context

Compilation

Results

Optimization

Refinement

Simulation

Analysis

C-Code

Translation

Algorithm

Idea

Modeling

Final System

Environment

Digital Analog

Functional

Environment

Digital AnalogDigital Analog

Functional

Implementation

ATD Modeling Method

3

Advanced Temporal Decoupling



Context

Central Question

„How to efficiently create accurate and performing virtual prototypes?”

Transparent TLM*) Advanced Temporal Decoupling (ATD)

*) see 26th ESCUG Workshop Dresden 2012:

“Using IP-XACT to ease system development with SystemC TLM

The Transparent TLM (TTLM) Approach”

Simon Hufnagel, Bosch, DE,

Christoph Grimm, Vienna University of Technology, AT

4



Context

Abstraction Level Overview

Functional Level no hardware aspects (architecture, timing)

communication based on shared variables and function calls

Transaction Level basic hardware structure

transaction based communication

timing accuracy from untimed to cycle accurate

Register Transfer Level synthesizable hardware specification

signal based communication

clock cycle accurate timing

function

1

function

2

function

3

Master

1

Master

2

Slave 1 Slave 2

Bus

comb.

logic

comb.

logic

clk

D D Q Q

risin

g a

bstr

action

5



Content

Context




Conclusion

6




Transaction Level Modeling Variants

TLM-CA

Functional

Model

TLM-PVT

untimed approximately

timed

cycle

accurate

application

packet

bus packet

bus word

Timing Accuracy

Data Granularity

figure according to: “Transaction Level Modeling – An Abstraction Beyond RTL”, L. Maillet-Contoz and F. Ghenassia, Springer, 2005

TLM-PV: programmer’s view

TLM-PVT: programmer’s view with timing

TLM-CA: cycle-accurate

TLM-PV

TLM-PVT

7

RTL

timing granularity varies with the number of function calls per transaction




Transaction Level Modeling Techniques*)

*) according to: Accellera Systems Initiative. “IEEE 1666-2011 Standard SystemC 2.3.” IEEE Std 1666TM-2011.

Target Initiator

multiple function calls

request

response

001 ttt

0t

223 ttt

wait 0t

wait 2t

wait 1t

wait 3t

112 ttt

334 ttt

approximately timed

simulated time

Target Initiator

initiate

finish

single function call

001 ttt

0t

wait 0t

wait 1t112 ttt

loosely timed

simulated time

8

global simulation time is extended by local simulation time offset

communication time consumption is aggregated




Temporal Decoupling*)

*) according to: Accellera Systems Initiative. “IEEE 1666-2011 Standard SystemC 2.3.” IEEE Std 1666TM-2011.

Target Initiator 0t

wait 1t

simulated time

local offset 101 ttt

0

initiate 0t 0t

finish 1t 1t

9

Interfered bus accesses by multiple masters 3 word low priority transfer from Master 1 to Slave 1 starting @ 100ns

3 word high priority transfer from Master 2 to Slave 2 starting @ 200ns




Simple TLM Example

Thread 1 Thread 2 Master 1 Master 2

simulated time

Thread 1 Thread 2

100ns

200ns

300ns

Slave 1 Slave 2

400ns

0ns

Bus

interruption of low

priority transfer

continuation of low

priority transfer

= Shared Resource Access (SRA)

low prio

high prio

= 50ns

expected timing behavior:

word 1/3

word 2/3

word 3/3

word 1/3

word 2/3

word 3/3

= Shared Resource

10

low prio

word 1/3

Low priority word trans-

fer looses arbitration … word 1/3

high prio

300ns word 2/3

word 3/3

400ns

… and continues after

high priority transfer word 3/3

successive single word transfers Masters send one single word TLM transaction per clock cycle

Bus arbitrates masters within each clock cycle




TLM – Cycle Accurate Implementation

Thread 1 Thread 2

Master 1 Master 2

Thread 1 Thread 2

Slave 1 Slave 2

simulated time

0ns

Bus

Exhaustive timing accuracy

Low simulation performance due to tiny simulation step width

= 50ns

100ns

200ns

word 2/3

11

One burst transfer per master Masters initiate one application packet transfer at designated start times

Typically, transactions are executed immediately within master’s context




TLM-PVT – Non Cycle Accurate Implementation

Thread 1 Thread 2

Master 1 Master 2

simulated time

Thread 1 Thread 2 100ns

200ns

300ns Slave 1 Slave 2

400ns

0ns

Bus Resource contention

disregarded

High simulation speed due to lowered simulation time granularity

Reduced simulation accuracy due to disregarded resource contention

low prio

high prio = 50ns

3 words

3 words

12

Further simulation speed improvement due to reduced context switch count

In order execution is not assured automatically & timing errors are accumulated

Masters run ahead in simulation time Masters initiate multiple 3 word burst transfers at designated start times without

suspending




Temporal decoupled Implementation

Thread 1 Thread 2

Master 1 Master 2

simulated time

Thread 1 Thread 2 200ns

400ns

600ns Slave 1 Slave 2

800ns

0ns

Bus

Timing error

accumulation

= 50ns

low prio

3 words

low prio

3 words

high prio

3 words

high prio

3 words

13

Global Quantum / Quantum Keeper1)

used to narrow local offset compared to global simulation time

large quantum high simulation speed, but low timing accuracy

disregards functional dependencies synchronization is fully obliged to the designer

can not guarantee absence of timing errors even for low quantum values

Trace driven simulation acceleration

trace extraction from high level system representation2)

trace extraction from lower level cycle accurate simulation3)



Related Work

Handling Speed vs. Accuracy Trade-Off

1) Accellera Systems Initiative. “IEEE 1666-2011 Standard SystemC 2.3.” IEEE Std 1666TM-2011.

2) Gladigau, Jens, Christian Haubelt, and Jürgen Teich. “Model-based Virtual Prototype Acceleration.” IEEE Trans. Computer-Aided

Design Integr. Circuits Syst. (2012).

3) Plyaskin, R., A. Masrur, M. Geier, S. Chakraborty, and A. Herkersdorf. “High-level Timing Analysis of Concurrent Applications on

MPSoC Platforms Using Memory-aware Trace-driven Simulations.” In VLSI System on Chip Conference (VLSI-SoC), 2010.

simulation speed

timing accuracy

size of global quantum

14

Statistical approaches1),2)

resource contention effects are approximated using statistical methods or finer grained

previous simulations

cycle accuracy can not be achieved

Postponed timing correction in case of resource conflicts:

Quantum Giver3), TLM+ Resource Model4), Result Oriented Modeling5)

resource contention is detected and simulation time of the corresponding thread is

updated accordingly

transactions are executed with non-preemptable semantic (either at the designated start

time or end time of the transaction)



Related Work

Improving Timing Accuracy

15

1) Bobrek, Alex, JoAnn M. Paul, and Donald E. Thomas. “Shared Resource Access Attributes for High-level Contention Models.” In

Proceedings of the 44th Annual Design Automation Conference, 720–725. DAC ’07. New York, NY, USA: ACM, 2007.

2) Atitallah, Rabie Ben, Smail Niar, Samy Meftali, and Jean-Luc Dekeyser. “An MPSoC Performance Estimation Framework Using

Transaction Level Modeling.” In An MPSoC Performance Estimation Framework Using Transaction Level Modeling, 2007.

3) Stattelmann, S., O. Bringmann, and W. Rosenstiel. “Fast and Accurate Resource Conflict Simulation for Performance Analysis of

Multi-core Systems.” In Design, Automation Test in Europe Conference Exhibition (DATE), 2011, 1–6, 2011.

4) Ecker, Wolfgang, Volkan Esen, Robert Schwencker, Thomas Steininger, and Michael Velten. “TLM+ Modeling of Embedded HW/SW

Systems.” In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, 75–80, 2010.

5) Schirner, G., and R. Dömer. “Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM.” Computer-Aided Design of

Integrated Circuits and Systems, IEEE Transactions On 26, no. 9 (September 2007): 1688 –1699.



Related Work

Transaction Level Modeling Trade-Offs


TLM-CA

Functional

Model

TLM-PVT


timed

cycle

accurate

application

packet

bus packet

bus word

Timing Accuracy

Data Granularity

TLM-PV

TLM-PVT

?! Fixed Data Granularity and

cooperative multitasking

limits Timing Accuracy

16

RTL

Allows variable data granularity to achieve cycle accuracy

Based on Temporal Decoupling for high simulation speed

Resources contain Temporal Decoupled Semaphores (TDSem)

managing resource accesses




Solution: Advanced Temporal Decoupling

Master 1 Master 2

Thread 1 Thread 2

Slave 1 Slave 2

Bus = 50ns

Temporal Decoupled

Semaphores (TDSem)

use look-a-head to determine potential future preemptions

17



Content

Context




Conclusion

18



Advanced Temporal Decoupling – Concept

Shared Resource Access (SRA) creation phase execute runable simulation threads in temporal decoupled manner

threads register SRAs at corresponding TDSems without processing them

suspend threads at predefined synchronization points

ATD simulation course: two alternating phases

Thread 1 Thread 2 global simulation time

remains constant

synchronization points

(wait for resume event)

registered and unprocessed SRAs

19




Synchronization Points

Temporal decoupling has to stop if data dependencies would be violated

remark: Synchronization Points are integrated into TTLM library components

instructions not necessarily comprising data dependency write access to external resource considering error type conversion*)

write access to local volatile variable

occurrence of interrupts

*) see “Abstract Modeling of Communication Errors in Cyber-Physical Systems using uPN” ,

S. Hufnagel, N. Bannow, C. Grimm, J. Ou, MBMV 2012 for details on error type conversion

Synchronization Point remarks

Read access from external resource

Read access from local volatile variable

Access to simulation time In case there are pending resource accesses

Notification of and wait for user events In case there are pending resource accesses

20




1. check if there are pending SRAs within “sc_time_to_pending_activity()”

2. select next SRA

3. calculate time budget

Shared Resource Access execution phase

Thread 1 Thread 2

sc_time_to_pending_activity()

next SRA

time budget

1. 2.

3.

21




4. (partially) execute next SRA considering time budget

5. delay related and/or conflicting SRAs and synchronization points

Shared Resource Access execution phase (cont’d)

Thread 1 Thread 2

next SRA

Thread 1 Thread 2

4.

2 words

Thread 1 Thread 2

5.

2 words

22




6. repeat steps 1 to 5 until there are no pending SRAs within

“sc_time_to_pending_activity()”

7. advance global simulation time and continue with next SRA creation phase

Shared Resource Access execution phase (cont’d)

7.

…

Thread 1 Thread 2 Thread 1 Thread 2

6.

2 words 2 words

3 words 3 words

Thread 1 Thread 2

2 words

1 word

3 words

23

incorporation of user defined scheduler delay of conflicting low priority SRA




Speedup ≥ 2,5x (larger transaction size larger speedup)

Simulation accuracy equals cycle accurate model

Simple TLM example performance evaluation

332k

835k940k

0k100k200k300k400k500k600k700k800k900k

1000k

TLM-CA ATD sync after each application

packet

ATD sync after 10 application

packets

Transactions / s

24




synchronous and asynchronous resource accesses

preemptable and non-preemptable resource accesses

Features

Resource Thread Resource Thread

sync async

Resource Thread 1 Thread 2

preemptable low priority resource access is

interrupted by high priority access

non-preemptable low priority resource access

defers execution of high priority access

Resource Thread 1 Thread 2

low prio high prio

low prio

high prio

25




supported resource properties: interacting resources

multiport resources

dynamic access priorities

user specified scheduler for simultaneous resource accesses

generation of profiling information resource utilization ratio

minimum interaction matrix

…

Features (cont’d)

Res. 1 Thread Res. 2

26

…



Advanced Temporal Decoupling – Implementation

Facts each SRA has exactly one source (thread / superior SRA)

each thread / SRA might have an arbitrary amount of pending SRAs

SRA registration might happen out-of-order (temporal decoupling)

each SRA is associated to exactly one resource

actual SRA execution might differ from model semantics

related SRAs influence each other

Implementation: SRA Tree for inter-SRA-dependencies

SRA Matrix for resource conflict detection

SRA Management

27




One SRA Tree per thread

Arbitrary amount of pending SRAs per thread / parent SRA

SRA Tree for inter-SRA dependencies

completed

SRAspending SRAs

active SRA

async SRA sync SRA

iTh thread = root

level = 1

level = 2

simulated time

level = 0

ns

i

t

Th SRA 1ns

i

t

Th SRA 2ns

i

t

Th SRA

1s

nst

iTh

t

SRASRA 1

1

s

nst

iTh

t

SRASRA

2

1

s

nst

iTh

t

SRASRA

28




SRA Matrix for resource contention detection

dynamic Threads...

ji TDSemTh SRA

SRAiTh

0Th 1Th 2Th iTh

0TDSem

1TDSem

jTDSem

Th

TDSem

jTDSemSRA

29




ATD provides dynamic Data Granularity


TLM-CA

TLM-PVT


timed

cycle

accurate

application

packet

bus packet

bus word

Timing Accuracy

Data Granularity

TLM-PV ATD

30

Functional

Model

TLM-PVT

RTL




31

ATD Usage

Initiators remain unchanged (exception: synchronization points)

integrate TDSem into resources …

… having multiple target ports

… allowing asynchronous accesses

TDSem not needed for cascaded single port resources allowing

synchronous accesses only

pass transaction to TDSem within TLM (n)b_transport call

implement SRAExecution_if which gets called to process the

transaction



Content

Context




Conclusion

32




Night Vision

33

automotive driver assistance application

improves obstacle visibility at night

based on advanced video processing algorithms




complete representation of Night Vision video computation system

(HW architecture, video algorithms, …)

cycle accurate implementation

runs original Night Vision video algorithms

based on SystemC with “Module-Adapter“ extension*)

*) see “Modeling and Optimization of a Multiprocessor Control Unit using SystemC” , PhD thesis N. Bannow, 2009

34

Model properties of existing virtual prototype




Model structure and dataflow

Source: „Modeling and Optimization of a Multiprocessor Control Unit using SystemC“, PhD thesis N. Bannow, 2009

1. frame transfer from

camera

2. DMA based transfer

to uC buffer

3. frame processing by

NV algorithms

4. DMA based transfer

back to FPGA buffer

5. output on display

35

simulation runtime improvement: ~5x

delta cycle count reduction: ~20x

simulation accuracy equals cycle accurate model

further improvements possible, if abstracted software model is used



Case Study “Night Vision”

Night Vision evaluation results

35716086

1925626

0

5000000

10000000

15000000

20000000

25000000

30000000

35000000

40000000

CA NV model ATD based NV model

# of delta cycles / frame11,02 s

2,42 s

0,00 s

2,00 s

4,00 s

6,00 s

8,00 s

10,00 s

12,00 s

CA NV model ATD based NV model

simulation runtime / frame

36



Content

Context




Conclusion

37

Advanced Temporal Decoupling …

… enables cycle accuracy in context of temporal decoupling automatic execution order preserving management of resource contention effects

time budget calculation for dynamic data granularity

simple TLM-LT like user API

… improves simulation performance of TLM-CA models speed up ~5x in industrial simulation model

TLM-CA simulation accuracy is retained

… can be used in conjunction with TTLM methodology model structure: TTLM library + TTLM generator

simulation performance + accuracy: Advanced Temporal Decoupling

synchronization points integrated into TTLM library elements



Summary

38

CR/AEH2-Hf | 2013/03/22 | © Robert Bosch GmbH 2012. Alle Rechte vorbehalten, auch bzgl. jeder Verfügung, Verwertung, Reproduktion,

Bearbeitung, Weitergabe sowie für den Fall von Schutzrechtsanmeldungen.

Thanks for your attention!

Questions ??

39

improving timing accuracy for tlm-lt models …€¦ · advanced temporal decoupling (atd) ......

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