inductor on chips

7/27/2019 Inductor on Chips

http://slidepdf.com/reader/full/inductor-on-chips 1/139

ON-CHIP SPIRAL INDUCTORS FOR

SILICON-BASED RADIO-FREQUENCY

INTEGRATED CIRCUITS

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF

ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Chik Patrick Yue

July 1998



ii

© Copyright by Chik Patrick Yue 1998

All Rights Reserved



iii



iv

Abstract

Recently, there has been tremendous interest in silicon-based integrated circuits for

radio-frequency (RF) applications. This trend can be attributed to the enormous potential

of the wireless communication market, the low-level integration of current transceiver

implementations, and the rapid advancements in silicon processing technologies. RF

designs require a large number of passive components realized today mostly in discrete

form. To attain a high level of integration, circuit blocks and passive elements need to be

fabricated on the same substrate using a single technology. Silicon technology has pro-

gressed to offer device performance suitable for analog operations at GHz frequencies and

consequently has become the cost-effective choice for RF front-end circuits. Nevertheless,

silicon-based RF designs face some unique challenges that must be resolved before the

monolithic transceiver can be realized. In particular, the quality factor (Q) of on-chip

inductors and noise coupling through the substrate are among the most pressing issues to

overcome. Since typical spiral inductors span a few hundred microns on each side, sub-

strate noise coupling associated with these elements can be significant.

Although numerous results of on-chip inductors have been reported, the basic under-

standing of performance limitations and the procedures for optimizing the quality factor

are lacking. Most published inductor models rely on numerical techniques which are not



v

intuitive enough to provide the insight needed in a design process. This dissertation pre-

sents a physical model that addresses the phenomena and parasitics important to the

behavior of on-chip inductors. This scalable model has been confirmed with measured and

published data of inductors having different geometric and process parameters. Based on

this compact model, an efficient design methodology for inductors on silicon is discussed.

With the insight gained from the physical model, this dissertation presents a patterned

ground shield inserted between an on-chip spiral inductor and the substrate to suppress sil-

icon parasitic effects. The patterned ground shield can be realized in standard silicon

technologies without additional processing steps. The impacts of shield resistance and pat-

tern on inductance, parasitic resistances and capacitances, and quality factor are studied

extensively. Experimental results show that a polysilicon patterned ground shield achieves

the most improvement. The addition of the shield can increase the inductor quality factor

and reduce the substrate coupling between two adjacent inductors. We also show that the

quality factor of a LC tank can be nearly doubled with a shielded inductor. The amount of

improvement can be further increased by the optimization techniques based on the physi-

cal inductor model.



vi

Table of Contents

Abstract.............................................................................................................................. ivList of Tables .......................................................................................................................xList of Figures ................................................................................................................... xii

Chapter 1 Introduction 1

1.1 Worldwide Wireless Communication Market.......................................................1

1.2 System on a Chip ..................................................................................................3

1.3 The Role of Inductors in RF Designs ...................................................................4

1.4 The Advantages of Integration..............................................................................6

1.5 Dissertation Organization .....................................................................................9

Chapter 2 On-Chip Inductors 11

2.1 Active Inductors..................................................................................................11

2.2 Bond Wire Inductors...........................................................................................14

2.3 Spiral Inductors...................................................................................................17

Chapter 3 Modeling and Characterization 25

3.1 Inductance and Parasitics of a Spiral Inductor....................................................26

3.1.1 Series Inductance ....................................................................................273.1.1.1 Self Inductance.........................................................................283.1.1.2 Mutual Inductance ...................................................................30



vii

3.1.1.3 Spiral Inductance .....................................................................31

3.1.2 Series Resistance.....................................................................................363.1.2.1 Proximity Effect on Resistance................................................38

3.1.2.2 Skin Effect on Resistance ........................................................40

3.1.3 Feed-through Capacitance ......................................................................44

3.1.4 Substrate Parasitics .................................................................................46

3.2 A Physical Model................................................................................................48

3.3 Testing and Parameter Extraction .......................................................................48

3.4 Measured and Modeled Results ..........................................................................54

3.4.1 Individual Elements in the Physical Model ............................................54

3.4.2 Two-Port S Parameters............................................................................56

3.5 Impact of Technology on Inductor Performance ................................................57

3.6 Design Methodology...........................................................................................66

3.7 Summary.............................................................................................................68

Chapter 4 Patterned Ground Shields 69

4.1 Design Considerations ........................................................................................70

4.1.1 Definitions of Quality Factor ..................................................................70

4.1.2 Understanding of Substrate Effects.........................................................72

4.1.3 Drawback of Solid Ground Shields ........................................................75

4.1.4 Design of Patterned Ground Shields.......................................................78

4.2 Experimental .......................................................................................................80

4.2.1 Experiment Design..................................................................................80

4.2.2 Effects on Inductance and Parasitics.......................................................82

4.2.3 Improvement in Inductor Q.....................................................................89

4.2.4 Improvement in Q of a LC-Tank.............................................................91

4.2.5 Suppression of Substrate Noise Coupling...............................................92

4.3 Summary.............................................................................................................93

Chapter 5 Effects of Epitaxial and Lightly Doped Substrates 95

5.1 Theory and Simulation........................................................................................96

5.2 Experimental Results ........................................................................................101

5.2.1 Bond Pads .............................................................................................101

5.2.2 Spiral Inductors.....................................................................................104

5.3 Summary...........................................................................................................111



viii

Chapter 6 Conclusions 113

6.1 Summary...........................................................................................................113

6.2 Future Work ......................................................................................................1146.2.1 Improvement in Q .................................................................................114

6.2.2 On-Chip Transformers and Baluns .......................................................115

6.2.3 On-Chip Tunable Bandpass Filters.......................................................115

Bibliography 117



ix



x

List of Tables

Table 1.1: RF front-end component count..................................................................7

Table 3.1: Properties of spiral inductance. For all cases, the inner dimension is fixedat 100 µm, line width at 12 µm, line spacing at 2 µm, and metal thicknessat 1 µm.....................................................................................................34

Table 4.1: Comparison of measured inductor parameters for the NGS (11 Ω-cm) andpolysilicon PGS cases at 2 GHz..............................................................88

Table 5.1: Summary of 100 × 100 µm2 bond pads...................................................99

Table 5.2: Summary of spiral inductors..................................................................103



xi



xii

List of Figures

Figure 1.1: Worldwide cellular population (a) in 1996, and (b) the forecast for2000. (Data source: the Cellular Telecommunications IndustryAssociation.) ..........................................................................................2

Figure 1.2: Typical impedance matching networks. (a) L-match. (b) π-match........4

Figure 1.3: Comparison of frequency response of a simple amplifier with andwithout tuned load..................................................................................5

Figure 1.4: The printed circuit board inside a digital cellular phone for theEuropean DCS-1800 and the component count for the RF front-endcircuit. (Bosch 1997.).............................................................................7

Figure 2.1: Gyrator-based active inductors in (a) single-ended and (b) floatingconfigurations.......................................................................................12

Figure 2.2: A gyrator-based inductor for illustrating the noise properties of activeinductors. The resistor and MOSFET constitute the gyrator. ..............14

Figure 2.3: Die photo of the VCO presented by J. Craninckx et al., which used fourbond wires to implement two inductors...............................................15

Figure 2.4: Limitation of IC interconnects for implementation of 3D coils: (a)vertical coils are limited by the number of available metal layers (b)horizontal coils achieve little mutual coupling due to short via length inthe vertical direction. ...........................................................................18

Figure 2.5: Cross section of multi-level interconnects in a typical IC. ..................19

Figure 2.6: Layout of a 3-turn square spiral inductor. ............................................20

Figure 2.7: Cross-sectional view of the spiral and the center-tap underpass. ........21



xiii

Figure 2.8: Scanning electron micrographs of a 7-turn square spiral inductor. .....22

Figure 3.1: Cut-away view of a conventional spiral inductor on silicon substratewith the inductance and RC parasitics highlighted..............................24

Figure 3.2: The dependency of self inductance on the wire cross-section dimensionfor different wire lengths......................................................................26

Figure 3.3: The dependency of self inductance on the wire length for differentcross-section dimensions. ....................................................................27

Figure 3.4: Two parallel wires with the same dimensions for studying mutualcoupling................................................................................................29

Figure 3.5: The mutual inductance and coupling coefficient between two wires as afunction of line-to-line spacing............................................................30

Figure 3.6: The mutual inductance and coupling coefficient between two wires as a

function of line pitch............................................................................31Figure 3.7: Positive and negative mutual couplings in a 4-turn spiral inductor. ....32

Figure 3.8: Proximity effect on series resistance for (a) side-by-side and (b) stackedwires.....................................................................................................36

Figure 3.9: Eddy current effect in the conductors of a (a) coaxial and (b) microstriptransmission line. .................................................................................39

Figure 3.10: Effective thickness (t eff ) of a conductor with finite thickness (t) underskin effect.............................................................................................40

Figure 3.11: Effective thickness of (a) aluminum and (b) copper as a function of frequency..............................................................................................41

Figure 3.12: A three-turn inductor: (a) layout and relevant elements (b) distributedmodel and (c) lumped model. ..............................................................43

Figure 3.13: (a) Real and (b) imaginary parts of the input impedance of the inductormodel circuits in Figure 3.12 for studying the importance of crosstalk and overlap capacitance to the overall feed-through capacitance........45

Figure 3.14: (a) Lumped physical model of a spiral inductor on silicon. (b)Equivalent model with combined impedance of C ox, C Si, and C Sisubstituted by R p and C p. .....................................................................47

Figure 3.15: S parameters measurement set-up and a sample test structure consisted

of an open and a device under test (DUT). ..........................................48Figure 3.16: Equivalent circuit of the measurement set-up......................................49

Figure 3.17: Parameter extraction procedure for the lumped elements in the inductormodel shown in Figure 3.14(b)............................................................51

Figure 3.18: Measured and modeled values of (a) Ls and Rs, (b) C p and R p for twoinductors with different spiral metal materials: one with copper and theother with aluminum............................................................................53



xiv

Figure 3.19: Measured and modeled values of S 11 and S 21 plotted on a Smith chart. .55

Figure 3.20: Measured and modeled values of (a) real and (b) imaginary parts of S 11and S 22..................................................................................................56

Figure 3.21: Measured and modeled values of (a) real and (b) imaginary parts of S 12and S 21..................................................................................................57

Figure 3.22: Measured and modeled values of (a) Q and (b) degradation factors fortwo inductors with 1-µm spirals in copper and aluminum. .................59

Figure 3.23: Effect of metal scheme on Q................................................................60

Figure 3.24: Effect of oxide thickness on Q.............................................................61

Figure 3.25: Effect of substrate resistivity on Q.......................................................62

Figure 3.26: Effect of layout area on Q....................................................................62

Figure 3.27: Verification of the physical model using published data. ....................63

Figure 3.28: Contour plots of Q as a function of inductance and outer dimension of square spiral inductors at (a) 0.6 GHz, (b) 1.0 GHz, (c) 1.6 GHz, and(d) 3.0 GHz. .........................................................................................65

Figure 4.1: Lumped physical model of a spiral inductor on silicon.......................71

Figure 4.2: Equivalent model with the combined impedance of C ox, C Si, and RSi inFigure 4.1 substituted by R p and C p.....................................................72

Figure 4.3: (a) Perspective view of a spiral inductor on solid ground shield and theresulting electromagnetic field lines. The fields are substantially

attenuated by the shield. (b) Perspective view of a solid ground shieldshowing the induced loop current and its associated magnetic fieldlines......................................................................................................75

Figure 4.4: Circuit model for illustrating the effects of negative mutual couplingbetween a spiral inductor and a solid ground shield............................76

Figure 4.5: Close-up photo of the patterned ground shield. ...................................77

Figure 4.6: Die photos of ground-signal-ground (GSG) test structure and theinductors: (a) spiral inductor with no ground shield (NGS), (b) solidground shield (SGS) shown without and with spiral, (c) patternedground shield shown without and with spiral. .....................................79

Figure 4.7: Two-port test structure for measuring crosstalk via substrate betweentwo adjacent inductors (shown with un-shielded inductors)................80

Figure 4.8: Effect of aluminum ground shields on: (a) spiral inductance ( Ls), (b)series resistance ( Rs). ...........................................................................82

Figure 4.9: Effect of aluminum ground shields on: (a) parasitic capacitance (C p),and (b) parasitic resistance ( R p). ..........................................................83

Figure 4.10: Effect of polysilicon ground shields on: (a) spiral inductance ( Ls), (b)



xv

series resistance ( Rs). ...........................................................................85

Figure 4.11: Effect of polysilicon ground shields on: (a) parasitic capacitance (C p),and (b) parasitic resistance ( R

p

). ..........................................................86

Figure 4.12: Effect of (a) aluminum and (b) polysilicon ground shields on Q. .......87

Figure 4.13: Effect of polysilicon patterned ground shield on Q of a 2-GHz LC tank.89

Figure 4.14: Effect of polysilicon patterned ground shield on substrate couplingbetween two adjacent inductors. ..........................................................90

Figure 5.1: (a) A parallel-plate capacitor with SiO2 and Si as dielectric slabs. (b) Aequivalent circuit model for the SiO2-Si system..................................95

Figure 5.2: Simulation results of (a) C p and (b) R p for a MOS structure with 16-µmwide metal on 1 µm thick oxide and 500 µm thick silicon..................98

Figure 5.3: Frequency response of (a) C pad and (b) Rpad for metal pads on varioussubstrates (see Table 5.1). ..................................................................101

Figure 5.4: Frequency response of Q for the metal pads......................................102

Figure 5.5: Measured results of (a) series inductance and (b) series resistance forthe inductors listed in Table 5.2. ........................................................104

Figure 5.6: Frequency response of Q for the inductors. .......................................105

Figure 5.7: Comparison of substrate parasitic capacitance for inductors on epi andlightly doped substrate. ......................................................................106

Figure 5.8: ω Ls /Rs for Epi5nH and Ld8nH. .........................................................106

Figure 5.9: Substrate loss and self-resonance factors for Epi5nH and Ld8nH. ...107Figure 5.10: Frequency response of Q for Epi5nH with and without PGS. Diffusion

and polysilicon PGS are considered. .................................................108

Figure 5.11: Resonator Q of Epi5nH with and without PGS. Diffusion andpolysilicon PGS are considered. ........................................................109

Figure 5.12: Substrate parasitic capacitance of Epi5nH with and without PGS.Diffusion and polysilicon PGS are considered. .................................110



1

Chapter

1 Introduction

The interest in on-chip inductors has surged with recent growing demand for silicon-based

radio-frequency (RF) integrated circuits. This chapter presents the impetus behind the

integration of inductors from both economic and technological viewpoints. First of all, a

survey of the current status and future trends of the worldwide wireless communication

market is reported. The impacts on the IC industry are addressed. The critical role of

inductors in RF circuits and systems is illustrated by examples. The advantages of on-chip

inductors towards “system on a chip” for RF designs is elucidated. The last section out-

lines the organization of this dissertation.

1.1 Worldwide Wireless Communication Market

The cellular telephone industry has enjoyed phenomenal growth since its inception in

1983. According to the Cellular Telecommunications Industry Association (CTIA), in

1996 there were 87 million cellular subscribers worldwide: 38 million in North America,

25 million in Europe, 19 million in Asia Pacific, and 5 million in the rest of the world (See

Figure 1.1). In 1997, the cellular populations in North America and Europe have already

grown to 48 and 50 million, respectively. In Asia Pacific, Japan alone has now more than

31 million subscribers, reported recently by Japan’s Ministry of Posts and Telecommuni-

cations (MPT). Among the most well established markets, Japan has the highest

population penetration at 24% followed by North America and Europe at 18% and 13%,

respectively. Nevertheless, the percentage of population using wireless communication is

still less than 5% worldwide. CTIA forecasts that by year 2000 the global cellular sub-

scribers will increase to 300 million: 125 million in North America, 75 million in Europe,



2 Chapter 1: Introduction

80 million in Asia Pacific, and 20 million in the rest of the world. This translates to an

astonishing annual growth rate of nearly 40% in the next several years.

One of the driving forces behind this aggressive growth is the allocation of new radio

spectra for wireless communication. The Broadband Personal Communications Services

(PCS) which operates from 1850 to 1910 MHz (downlink) and from 1930 to 1990 MHz

(uplink) is currently the fastest growing cellular service in North America. In April 1997,

the Federal Communications Commission (FCC) licensed the band between 2305 to

2320 MHz and 2345 to 2360 MHz for Wireless Communication Services (WCS) which

are expected to be in service in three years. The FCC auctioned another 25-MHz band

from 4660 to 4685 MHz in May 1998 for General Wireless Communication Services

(GWCS). In Europe, the Global System for Mobile Communications (GSM) is the

entrenched standard with the original version working at 890 to 915 MHz (downlink) and

at 935 to 960 MHz (uplink). The newer version known as the Digital Communication Sys-

Figure 1.1: Worldwide cellular population (a) in 1996, and (b) the forecast for 2000.(Data source: the Cellular Telecommunications Industry Association.)

(b)(a)

Europe25 Million29%

North America38 Million43%

Asia Pacific19 Million22%

Other 5 Million6%

Europe75 Million25%

North America125 Million41%

Asia Pacific80 Million27%

Other 20 Million7%

Year 1996 87 Million Subscribers

Year 2000 300 Million Subscribers



1.2. System on a Chip 3

tem (DCS-1800) uses the spectrum between 1710 to 1785 MHz (downlink) and 1805 to

1880 MHz (uplink). The Universal Mobile Telecommunication System (UMTS), the suc-

cessor to the second-generation GSM, will be in service as early as 2001 at frequencies

between 1885 to 2025 MHz and 2110 to 2200 MHz.

Another reason for the surge of wireless communication is the constant reduction in

service fees due to market competition. To enhance network capacity, new cellular stan-

dards emphasize the utilization of digital radio access technologies, such as code-division

multiple access (CDMA) and time-division multiple access (TDMA). Using digital trans-

mission, more users can be accommodated into the available bandwidth without degrading

the voice quality. Consequently, cellular services become more affordable. This is espe-

cially important for developing countries such as China and India where populations are

large and wired telephony infrastructure is lacking. Since wireless communication is the

only option which avoids constructing more costly copper-based networks, low-cost ser-

vice will expedite the adoption and spread of cellular telephony.

1.2 System on a Chip

The wireless trend continues to have a large impact on the IC industry. The U.S. sales of

analog and mixed-signal IC’s into the cellular-handset market soared from $654 million in

1993 to over $3.2 billion in 1996 according to Dataquest Inc., San Jose, CA. In addition to

cellular and cordless phones, novel portable electronics continue to emerge ranging from

handsets for wireless e-mail and Internet access to navigation systems based on the Global

Positioning System. The success of these consumer products depends heavily on the cost,

battery lifetime, functionality and weight. To meet these requirements, the chip manufac-

turers are pursuing the system-on-a-chip approach aiming to integrate a RF transceiver

and baseband digital signal processing on a single piece of silicon. Among the various

technical challenges, the integration of passive components, especially inductors, has

received a great deal of attention due to their vital roles in RF front-end systems [1][2].




1.3 The Role of Inductors in RF Designs

The operating frequency of most cellular services ranges from 0.8 to 2.5 GHz. At suchhigh frequencies, impedance matching networks are required between the circuit blocks in

a RF system to ensure maximum power transfer. The primary function of these matching

networks is to match the output impedance of a circuit block to the input impedance of the

following block. Maximum power transfer is attained when the reactive parts of the

impedances are a conjugate pair and the resistive parts are equal. Inductors are an integral

part of impedance transformation circuits, such as the L-match and π-match networks

shown in Figure 1.2. Design guidelines for such networks are described extensively in [3].

Inductors are often employed in the design of tuned amplifiers, mixers, and oscillators.

Low-noise amplifiers and power amplifiers with tuned loads are widely adopted to amplify

the desired signals and to filter the out-of-band signals simultaneously. The main advan-

tages of using tuned amplifiers over broadband designs include relative ease of obtaining a

specified gain at radio frequencies, high immunity to low-frequency noise, and low power

consumption. In general, the difficulty of obtaining a certain gain-bandwidth product is

approximately independent of the center frequency [3]. For instance, a constant gain of 10

up to 1 GHz implies a gain-bandwidth product of 10 GHz −− a task difficult to accom-

plish. On the other hand, if the desired signal has a bandwidth of 25 MHz (typical in

Figure 1.2: Typical impedance matching networks. (a) L-match. (b) π-match.

(a) (b)

L L

C C 1 C 2



1.3. The Role of Inductors in RF Designs 5

cellular standards), then a 1-GHz tuned amplifier with a gain-bandwidth product of only

250 MHz will be sufficient. To illustrate this idea, consider the effect of the inductor ( L) on

the frequency response of the amplifier gain as shown in Figure 1.3. Without L, the circuit

reduces to a simple common source amplifier having a gain of gm R and a −3-dB band-

width of 1/ RC . The corresponding gain-bandwidth product is gm / C . With L, the circuit can

be modeled as an ideal transconductor driving a parallel RLC tank. At low frequencies, the

inductor acts as a short and the amplifier gain is small; whereas at high frequencies, the

Figure 1.3: Comparison of frequency response of a simple amplifier with and withouttuned load.

C

R

gm

V out

V in

Gain

Frequency f center

BWBW

Without L With L

= ( RC ) -1

= ( LC ) -1/2

L

= ( RC ) -1




capacitor behaves as a short and causes the gain to roll off. At the tank resonance fre-

quency, namely ( LC )−0.5, the load is simply R and the gain is gm R for the effects of the

inductor and the capacitor cancel each other. Since the bandwidth of the tank is 1/ RC , the

gain-bandwidth product remains as gm / C . This example demonstrates the essential func-

tion of inductors at radio frequencies for tuning capacitances. More detailed treatment of

tuned amplifiers can be found in [3].

In addition to tuned amplifier loads [4][5], inductors are also used as emitter or source

degeneration for improving linearity and matching [5]−[10] and as series and parallel LC

resonators for RF filters [11]−[14] and oscillators [15][16].

1.4 The Advantages of Integration

Current transceivers typically consist of parts manufactured in several technologies: bipo-

lar or BiCMOS for the low-noise amplifier, mixer, and voltage-controlled oscillator; GaAs

or bipolar for the power amplifier; and CMOS for the baseband signal processing [1][2].

The large number of required passive components are realized today mostly on the PCB

using thick-film techniques or in discrete form (See Figure 1.4). To increase the level of

integration, circuit blocks and passive elements need to be fabricated on the same substrate

using a single technology. Silicon technology has progressed to offer device performance

suitable for analog operations at a few gigahertz [17]−[21] and consequently emerges as

the cost-effective choice for RF front-end circuits.

Cost. In the front-end radio of a cellular phone, the majority of the components on the

PCB are discrete passive elements. Although the component cost of discrete RLC ele-

ments constitutes a small fraction (about 10%) of the board cost, the associated assembly

cost is substantial. In fact, the overall cost due to passive components often exceeds one

third of the board cost. Consequently, integrating the passives on chip can reduce both

component and assembly costs. More importantly, with the intermediate LC matching net-

works integrated, individual circuit blocks are more readily manufactured on the same



1.4. The Advantages of Integration 7

Figure 1.4: The printed circuit board inside a digital cellular phone for the EuropeanDCS-1800 and the component count for the RF front-end circuit. (Bosch1997.)

Table 1.1: RF front-end componentcount.

Inductor 11

Capacitor >100

Resistor >50

IC 5

Transistor 12

Crystal 1

Filter 2




silicon substrate. As a result, the cost of IC packaging and testing will drop drastically

because fewer IC’s are needed to implement a system.

Power. Power savings is another important benefit. When signals travel between com-

ponents on the PCB, additional power is dissipated in driving large parasitic inductances

and capacitances due to bond pads, bond wires, IC packages, PCB traces, and discrete

packages.

Size. Discrete passives occupy for most of the PCB area in today’s systems. Increasing

demand for miniature portable system has resulted in large reductions in the footprints of

surface mount RLC elements. The state-of-the-art discrete resistors and capacitors are

available in a 0402 package. The smallest surface mount inductors are limited to a 0603

package due to the volume required for wire winding [22]. However, because of the over-

head area required for solder attachments and vias, the PCB area savings offered by these

advanced packages is not significantly. Further miniaturization of component size will

result in diminishing improvements in form factor. Integrating RLC elements on chip is a

more effective solution.

Reliability. Monolithic implementation will also improve system reliability by reduc-

ing transitions and interfaces arising from component soldering.

Matching. Most wireless communication circuits operate between 0.8 to 2.5 GHz. At

such high frequencies, typical inductances required range from 1 to 25 nH. The small

inductance values are difficult to match with discrete implementation. For surface mount

inductors, tolerance for component values is usually between 2% to 25% and is worse for

smaller inductances (below 10 nH) due to package parasitics [22]−[24]. Monolithic imple-

mentation of the required inductance values is quite feasible. On-chip inductors offer

superior matching and repeatability because of the tight control in IC processing.

Design Flexibility. The integration of passive components allows more flexibility in

impedance matching designs by keeping signals on chip and thus avoiding the need for

matching to the off-chip 50-Ω environment.



1.5. Dissertation Organization 9

Testing. Integration of more components will simplify and reduce IC testing and as a

result lower cost.

The advantages of integrating passive elements on chip are clear. In silicon technolo-

gies, resistors and capacitors are readily available since they have been used extensively in

analog IC’s which typically operate up to a few hundred megahertz. In contrast, on-chip

inductors are rarely employed in those IC’s. This is mainly because the required induc-

tances are too large to be realized on chip in a reasonable area and with adequate

performance. The advent of RF IC’s demands inductors to be included in the IC family.

1.5 Dissertation Organization

This dissertation is devoted to the fabrication, modeling, characterization, and design of

on-chip spiral inductors using conventional silicon IC technologies. Chapter 2 presents the

reasons for the limited usefulness of gyrator-based and bond-wire on-chip inductors. The

fabrication of spiral inductors using standard IC interconnect technologies is reviewed.

The impacts of micro-machining techniques and advanced metallization materials are pre-

sented. The focus of Chapter 3 is on modeling, testing, and characterization of inductors

with various process and layout parameters. A design methodology for optimal inductor

layout is also described. Based on the physical insights gained, Chapter 4 presents the

design of a patterned ground shield inserted between an inductor and the substrate to

improve the overall performance. Chapter 5 discusses the effect of lightly doped and epi-

taxial substrates on inductors and demonstrates the effectiveness of a patterned ground

shield for both substrates. Lastly, conclusions and future work are summarized in

Chapter 6.



11

Chapter

2 On-Chip Inductors

This chapter evaluates several common approaches for integrating inductors on chip. Inte-

grated inductors can be categorized into active and passive implementations. Regardless of

the circuit scheme, active inductors virtually all share the same drawbacks of excess noise,

extra power dissipation, and limited dynamic range owing to the required active circuit-

ries. Passive inductors can be realized using the available conductors on a chip which

include regular interconnects and bond wires. The predictability and reproducibility of

bond wire inductors are fairly poor and thus have limited their widespread adoption. Spiral

inductors are the most feasible and widely used choice because of their compatibility with

IC processing.

2.1 Active Inductors

Inductances can be emulated through the reciprocation of capacitances. A gyrator is a cir-

cuit that performs impedance reciprocation by creating an phase inversion to the original

impedance. Since IC technologies offer good quality capacitors, inductances can be

obtained by utilizing on-chip gyrators and capacitors [25]−[27]. Figure 2.1 shows the gen-

eral form of gyrator-based inductors in single-ended and floating configurations. It can be

shown that the emulated inductance in both configurations is

(2.1) Lef f

C

gm1g

m2

--------------------=



12 Chapter 2: On-Chip Inductors

Figure 2.1: Gyrator-based active inductors in (a) single-ended and (b) floatingconfigurations.

-gm1

gm2

C

i1

iin

i2

vin

–

+vc

–

+

-gm1

gm2

C

i1

iin

i2vin

–

+

vc

–

+

gm1

-gm2

i3

iin

i4

(a)

(b)

Lef f

C

gm1

gm2

--------------------=

Lef f

C

gm1g

m2

--------------------=



2.1. Active Inductors 13

where the gm terms represent the transconductance of the gain blocks and C is the capaci-

tance of a passive capacitor.

The major drawback of active inductors is their excess noise. To understand the noise

properties of active inductors, consider the simple gyrator-capacitor circuit shown in

Figure 2.2 [3]. In this example, the idealized gyrator is comprised of a parasitic-free MOS-

FET and a resistor. Under the assumptions that 1/ RC is much lower than the inductor’s

operating frequency and that the quality factor, Q, of the inductor is much greater than

unity at all frequencies of interest, one can derive the effective inductance and Q as

(2.2)

and

(2.3)

where f is the frequency in Hz. (Q is a measure of the inductor’s efficiency for storing

magnetic energy. A detailed treatment for the definition of Q is given in Chapter 4.) The

effective current noise density due to the thermal noise of R is

(2.4)

which indicates that the thermal noise of the resistor (4kT / R) is amplified by a factor of

(Qeff 2+1). This effect is due to a voltage drop across the capacitor caused by the resistor

noise current. This noise voltage is then amplified by the MOSFET transconductance.

While a high Qeff is desirable for most circuit applications, it also leads to an unacceptably

high noise level. This trade-off fundamentally limits the application of active inductors in

RF designs.

Besides the thermal noise of the resistor, additional noise sources due to the MOSFET

also contribute to the overall noise of the active inductor. The usefulness of active induc-

Lef f

RC

gm

--------=

Qef f

gm

2π fC -------------=

I R

2 4kT

R---------- Q

ef f

21+( )⋅=




tors is further hampered by the power dissipation and the dynamic range limitations of the

active circuitries.

2.2 Bond Wire Inductors

Bond wires are used to make electrical connections between a chip and the IC package.Conventional bond wires are made of gold with a diameter of about 1 mil (25 µm) and a

typical length of 2−5 mm. It is known that in high-speed digital circuits when large tran-

sient current is drawn from the supply in a short time, the inductance of bond wires may

cause detrimental power supply fluctuations as described by

. (2.5)

Using bond wires as inductors in RF circuits was first proposed by J. Craninckx et al.in the design of a voltage-controlled oscillator [28][29] whose die photo is shown in

Figure 2.3. F our wires were bonded across the chip to implement two inductors.

The dc inductance of a wire with circular cross section can be estimated using

C

R

gm

inR

2 4kT

R----------∆ f =

Figure 2.2: A gyrator-based inductor for illustrating the noise properties of activeinductors. The resistor and MOSFET constitute the gyrator.

V supply

∆ Lt d

d I

transcient =



2.2. Bond Wire Inductors 15

(2.6)

where Lself is the inductance in nH, l is the wire length in cm, and r is the radius in cm

[30]. According to (2.6), the inductance of a typical bond wire is about 1 nH/mm. It

should be pointed out (2.6) assumes that the wire is straight and hence does not account

for any curvature of the bond wire.

At high frequencies, the skin effect causes attenuation of the magnetic field in the

wire. However, this has little effect on the overall inductance since most of the magnetic

field is external to the wire.

On the other hand, the non-uniform current density in the wire due to the skin effect

must be accounted for when computing the high-frequency resistance. The skin depth of a

conductor is

(2.7)

where ρ, µ, and f represent the resistivity in Ω-m, permeability in H/m, and frequency in

Hz, respectively [31]. For gold (ρ = 2.4 µΩ-cm), the skin depth at 1 GHz is 2.5 µm which

Figure 2.3: Die photo of the VCO presented by J. Craninckx et al., which used fourbond wires to implement two inductors.

Lself 2l

2l

r -----ln 0.75–

=

δ ρπµ f ----------=




is only one tenth of the bond wire diameter. Since the ac current flows near the bond wire

surface, the effective cross-section area is roughly equal to the circumference of the bond

wire times the depth of penetration (δ). Thus, the ac resistance of a bond wire can be

approximated by

. (2.8)

For gold bond wires, the ac resistance is 122 mΩ /mm at 1 GHz and increases to

172 mΩ /mm at 2 GHz.

The Q of bond wire inductors can be estimated by substituting (2.6) and (2.8) into

. (2.9)

Assuming an inductance of 1 nH/mm, (2.9) yields a Q of approximately 50 at 1 GHz

which increases to 70 at 2 GHz.

Although bond wire inductors offer high Q, they have many disadvantages. As can be

seen in Figure 2.3, the achievable inductance is limited by the chip dimensions. For exam-

ple, to obtain 10 nH on a 4-mm-by-4-mm chip, several bond wires connected in series are

required.

The routing of bond wire inductors is cumbersome. Since the bond wire has to stretch

over a long distance, the two ports of the inductor are remotely spaced across the chip. To

overcome the routing difficulty, each inductor requires a pair of bond wires connected at

one end of the chip. However, the mutual coupling between the two wires must be consid-

ered in the designs. The mutual inductance, M , in nH between two bond wires with the

same length, l, and separation, d , both in cm can be computed using [30]

. (2.10)

For instance, two 5-mm bond wires with 1-mm separation have a mutual inductance of

1.5 nH, which is about 30% mutual coupling. The mutual inductance is positive if the cur-

Rac

ρl

2πr δ------------

l

2r -----

ρµ f

π----------= =

Q2π f L

self

Rac

----------------------=

M 2ll

d --- 1

l2

d 2

------++

ln 1d

2

l2

------+–d

l---+=



2.3. Spiral Inductors 17

rents in the wires flow in the same direction and negative otherwise. The mutual

inductance decreases slowly as d increases as can be inferred from the logarithmic depen-

dency. Since multiple inductors are needed on the same chip, the large mutual coupling

can cause unwanted interactions and lead to deleterious effects on the circuits.

Another issue is related to the pads where the wires are bonded. The bond pads are

typically 100-µm-by-100-µm, and therefore introduce considerable parasitic capacitance

and resistance due to the underlying oxide layer and silicon substrate. This is especially

problematic when several bond wires are connected in series to implement a single

inductor.

The controllability and consistency of bond wire inductance also pose problems. Due

to the positioning uncertainties of the bonding process, a conservative estimation of the

inductance tolerance is about ±6% [29]. Variation in wire size, length, spacing, and curva-

ture are responsible for the high tolerance.

2.3 Spiral Inductors

Discrete inductors are usually solenoid coils because of the large mutual coupling betweenturns and the ease of inserting high-permeability (µ) material inside the coil to increase the

inductance and Q. In conventional silicon IC technologies, however, three-dimensional

coils are hard to realize. The difficulty stems from the limited number of metal layers and

the short via lengths in the vertical direction as shown in Figure 2.4. For vertical coils, the

close proximity of the turns in different layers induces significant eddy currents in each

other and increases the overall ohmic loss (see Section 3.1.2). Furthermore, the inter-layer

metal-to-metal overlap capacitance is large and lowers the maximum usable frequency

substantially. The importance of the overlap capacitance is explained in Section 3.1.3. Due

to the short via length, the net positive mutual inductance for horizontal coils is almost

zero. Also, the resistance of via stacks is typically quite large and thus raises the resistive




loss to intolerable level. For both vertical and horizontal coils, the substrate loss becomes

more severe as the separation to the lossy silicon substrate is reduced.

Planar inductors are more compatible with the IC interconnect scheme. Today, IC’s

typically have 3−5 levels of interconnects (see Figure 2.5). The top layer metal is usually

Figure 2.4: Limitation of IC interconnects for implementation of 3D coils: (a) verticalcoils are limited by the number of available metal layers (b) horizontal coilsachieve little mutual coupling due to short via length in the verticaldirection.

Metal

Metal

Metal

Via

Via

Via Via Via ViaMetal

Metal

(a)

(b)




the thickest at 1−2.5 µm while the lower layers are typically 0.7−1.0 µm thick. The sepa-

ration between the top layer metal and the silicon substrate is determined by the overall

dielectric thickness which is typically 4−7 µm.

Several planar inductor structures are possible including loop, meander, and spiral

[32]. Spirals are preferred because of their large positive mutual inductance. One can pic-

ture a planar spiral as a special form of solenoid with turns of descending diameter on the

same plane. The layout of a 3-turn square inductor is shown in Figure 2.6. The current

flow directions are indicated on the layout. Note that the interconnect segments with the

same current direction are close to each other while those with opposite currents are sepa-

rated far apart. This arrangement ensures the net mutual inductance is positive and

therefore enhances the overall inductance.

Figure 2.5: Cross section of multi-level interconnects in a typical IC.




It has been reported that the series resistance of circular and octagonal spirals is

approximately 10% less than that of a square spiral with the same inductance [33]. Never-

theless, square spiral remains the common choice in IC designs because non-Manhantton

geometries are not supported by many layout tools. If necessary, the diagonal segments of

an octagonal line can be drawn as Manhattan stair-step jogs. However, it may require a

fine step size to assure smooth edges.

Figure 2.6: Layout of a 3-turn square spiral inductor.

id

od

s

w

od

id

N = 3

AA’




For square spirals, the layout parameters are the number of turns ( N ), line width (w),

line spacing (s), and outer dimension (od ). One can also specify the layout using the inner

dimension (id ) instead of the outer dimension. For an inductance of 1−20 nH, the typical N

is 2−10 turns. Higher inductance values require more turns to achieve more mutual cou-

pling. The line width usually ranges from 5−30 µm. In general, large inductance values are

realized with narrower line widths to avoid excessive parasitic capacitance. Smaller induc-

tance values can tolerate more parasitic capacitance and therefore usually employ wider

lines. The line spacing is generally kept to the minimum allowed by the technology, usu-

ally 1−5 µm, to reduce the spiral series resistance. The outer dimension varies from

100−500 µm depending on the inductance and the available chip area.

The cross section of the 3-turn inductor along AA’ is shown in Figure 2.7. The spiral is

patterned in the top layer to take advantage of the low series resistance and to stay away

from the lossy silicon substrate. The contact to the center of the spiral is realized with an

underpass in a lower level interconnect. The entire inductor structure is separated from the

silicon substrate by oxide. Figure 2.8 shows the scanning electron micrographs of a square

spiral inductor with N = 7, w = 13 µm, s = 7 µm, and od = 300 µm.




Figure 2.7: Cross-sectional view of the spiral and the center-tap underpass.

AA’

t

t ox

Silicon

Oxide

t oxM1-M2




Figure 2.8: Scanning electron micrographs of a 7-turn square spiral inductor.



25

Chapter

3 Modeling and

Characterization

The lack of an accurate equivalent circuit model for on-chip inductors presents one of the

most difficult problems for RF designers. In conventional IC technologies, inductors are

not considered standard components like transistors, resistors, or capacitors whose models

are included in the technology library. However, this situation is changing as the demand

for RF IC’s continues to grow [34]−[40]. Various approaches for inductor modeling have

been reported [41]−[47]. Most of these models, however, are not scalable with layout

dimensions and process parameters. The modeling difficulties stem from the complexity

of the physical phenomena such as the skin effect and substrate loss. This chapter presents

an analytical model which accounts for these physical effects. Each element of the model

must be consistent with the physical phenomena occurring in the part of the inductor

structure it represents. The behavior of spiral inductors with different structural parame-

ters can therefore be predicted over a broad range of frequencies. Furthermore, the model

is sufficiently compact for circuit simulation and layout optimization.

In this chapter, an analysis of a spiral inductor is carried out by treating separately the

spiral inductance and other parasitics [48]. To confirm the validity of the analytical model,

test structures for various inductors are fabricated and measured. Test structure design and

the techniques for extracting the parasitics are described. The impact of layout and process

parameters on the inductor quality factor, Q, are studied and compared to the model pre-

diction. Lastly, Q contour plots are presented as a design tool for optimization of inductor

layout.



26 Chapter 3: Modeling and Characterization

3.1 Inductance and Parasitics of a Spiral Inductor

The key to accurate physical modeling is the ability to identify the relevant parasitics andtheir effects. Since an inductor is intended for storing magnetic energy only, the inevitable

resistance ( R) and capacitance (C ) in a real inductor are counter-productive and thus are

considered parasitics. The parasitic resistances dissipate energy through ohmic loss while

the parasitic capacitances store electric energy. In general, the RC parasitics hamper the

quality of the inductor.

A cut-away view of a spiral inductor on silicon is depicted in Figure 3.1. to highlight

the parasitics existing in the structure. The inductance and resistance of the spiral and the

underpass is represented by the series inductance, Ls, and the series resistance, Rs, respec-

tively. The overlap between the spiral and the underpass allows direct capacitive coupling

Figure 3.1: Cut-away view of a conventional spiral inductor on silicon substrate withthe inductance and RC parasitics highlighted.

C s

Cox

CSi

RSi

Ls

R s



3.1. Inductance and Parasitics of a Spiral Inductor 27

between the two terminals of the inductor. This feed-through path is modeled by the series

capacitance, C s. The oxide capacitance between the spiral and the silicon substrate is mod-

eled by C ox. The capacitance and resistance of the silicon substrate are modeled by C Si

and RSi. The characteristics of each element are investigated extensively in the following

sections.

3.1.1 Series Inductance

Inductance is the ratio of magnetic flux to current whereas capacitance is the ratio of elec-

tric charge to voltage. These relationships can be expressed as

(3.1)

(3.2)

(3.3)

(3.4)

where L, Φ, I , C , Q, V , µ, ε, H , E, and d S are the inductance in henries (H), magnetic flux

in webers (Wb), current in amperes (A), capacitance in farads (F), electric charge in cou-

lombs (C), permeability in henries per meter (H/m), permittivity in farads per meter (F/m),

magnetic field density in amperes per meter (A/m), electric field density in volts per meter

(V/m), and area in meters squared (m2), respectively. Inductors store energy from the

applied voltage in their magnetic field through flux just like capacitors store energy from

the applied current in the electric field through charge.

The foundation for computing inductance of practical inductors is built on the con-

cepts of the self inductance of a wire and the mutual inductance between a pair of wires. A

comprehensive collection of formulas and tables for inductance calculation was summa-

rized by F.W. Grover in [30]. Using Grover’s formulas, the self and mutual inductance for

IC interconnect lines are characterized in the following sections.

LΦ I ----=

C Q

V ----=

Φ µ H Sd ⋅∫ =

Q ε E Sd ⋅∫ =




3.1.1.1 Self Inductance

The dc self inductance of a wire with a rectangular cross-section area is expressed as

follows:

(3.5)

where Lself is the inductance in nH, l is the wire length in cm, w is the width in cm, and t is

the thickness in cm. Using (3.5), the dependency of the self inductance on the cross-sec-

tion dimension and length are plotted in Figure 3.2. and Figure 3.3. The cross-section

dimension refers to the sum of width and thickness. As shown in Figure 3.1, the induc-

tance decreases slowly with larger cross-section dimensions. For instance, the inductance

of a 1-cm wire decreases by only a factor of two when the cross-section dimensions

increases by two orders of magnitude from 1 µm to 100 µm. Since the inductance is pri-

Lself 2l2l

w t +------------ln 0.5

w t +

3l------------+ +

=

Figure 3.2: The dependency of self inductance on the wire cross-section dimensionfor different wire lengths.

1 10 100 1000

w + t (µm)

0.00

0.01

0.10

1.00

10.00

100.00

L s e l f

( n H )

l = 1 cm

l = 1 mm

l = 100 µm

l = 10 µm




marily determined by the magnetic flux external to the wire, the variation in the wire

cross-section dimensions has little effect on the inductance. In general, the wires with

smaller cross-section area have a slightly larger inductance because they generate more

magnetic flux external to the wire. It should also be pointed out that (3.5) is not valid for

wires having cross-section dimension approximately twice their length. For example, as

indicated in Figure 3.2, with a cross-section dimension of 700 µm, the inductance of a

10-µm wire is larger than the 100-µm case. It is physically impossible for a shorter wire to

have larger inductance. Although wires with such geometries are hardly used in practice,

they point out the limitation of (3.5).

Figure 3.3 shows that the increase in inductance with length is slightly more than lin-

ear, which is due to the positive mutual coupling between parts of the wire. However, this

transformer effect is insignificant as suggested by the logarithmic dependency on (w+t ) in

(3.5). For (w+t ) equal to 10 µm, a 250-µm and 1000-µm wire yield inductance per milli-

Figure 3.3: The dependency of self inductance on the wire length for differentcross-section dimensions.

10 100 1000 10000

l (µm)

0.00

0.01

0.10

1.00

10.00

100.00

L s e l f

( n H )

w + t = 1 µm

w + t = 10 µm

w + t = 100 µm

w + t = 1 mm




meter at 0.88 nH and 1.16 nH, respectively. Typical wire segments of an on-chip spiral

inductor have widths of 5−30 µm and lengths of 100−400 µm which result in self induc-

tances of 0.7−1.1 nH/mm.

3.1.1.2 Mutual Inductance

The mutual inductance between two parallel wires can be calculated using the following

equations. In general,

(3.6)

where M is the inductance in nH, l is the wire length in cm, and Q is the mutual inductance

parameter, which can be calculated using

. (3.7)

In (3.7), GMD is the geometric mean distance between the wires, which is approximately

equal to the pitch of the wires. A more accurate expression for the GMD is given as

(3.8)

where w and d are the wire width and pitch in cm, respectively.

Two parallel wires with the same dimensions are shown in Figure 3.4. The self and

mutual inductance can be obtained using (3.5) through (3.8) and they are related as

(3.9)

where L1 and L2 are the self inductance of the two wires and are both equal to L. k is the

mutual coupling coefficient. Figure 3.5 shows the mutual inductance ( M ) and the corre-sponding coupling coefficient (k ) as a function of the line-to-line spacing, s. The self

inductance of the 1-µm, 10-µm, and 50-µm (w+t ) wires are 1.48 nH, 1.14 nH, and 0.84 nH

respectively. All three wires are 1 µm thick and 1 mm long. In general, the mutual induc-

tance is larger for narrower wires. For small s, the difference in M is more pronounced

M 2lQ=

Ql

GMD-------------- 1

l

GMD--------------

2++ln 1GMD

l--------------

2+GMD

l--------------+–=

GMDln d lnw

2

12d 2

------------–w

4

60d 4

------------–w

6

168d 6

---------------–w

8

360d 8

---------------–w

10

660d 10

-----------------– ....–=

M k L1 L2 kL= =




because the narrower wires have larger k and L. As s increases, k of the narrower wires

decreases more rapidly and eventually drops below those of the wider cases. Nevertheless,

the narrower wires have larger mutual inductances even with a larger spacing due to their

higher self inductances.

Figure 3.6 plots M and k with respect to the line pitch, d . Note that M does not vary

with the width when the pitch is fixed. This indicates that for on-chip inductors with the

same turn-to-turn pitch, variations in spiral width have little effect on the overall induc-

tance. This also implies that the variation of inductance due to process fluctuation is

extremely small.

3.1.1.3 Spiral Inductance

Based on Grover’s formulas, Greenhouse developed an algorithm for computing the

inductance of planar rectangular spirals [49]. The Greenhouse’s method states that the

overall inductance of a spiral can be computed by summing the self inductance of each

wire segment and the positive and negative mutual inductance between all possible wire

segment pairs. For instance, a four-turn rectangular spiral has sixteen segments and hence

sixteen self inductance terms (see Figure 3.4.). The mutual inductance between two wires

Figure 3.4: Two parallel wires with the same dimensions for studying mutualcoupling.

d

t

w

s

l




Figure 3.6: The mutual inductance and coupling coefficient between two wires as afunction of line pitch.

(a)

(b)

1 10 100 1000

d (µm)

0.1

1.0

M ( n H )

2.0

1 10 100 1000

d (µm)

0.1

1.0

k

w = 1 µm

w = 10 µmw = 50 µm

w = 1 µm

w = 10 µm

w = 50 µm

d




inductance terms, and thirty-two negative mutual inductance terms. In general, each rect-

angular spiral has

, (3.10)

, (3.11)

and

, (3.12)

where N is the number of turns.

To understand the characteristics of spiral inductance, L as a function of N is listed in

Table 3.1. N is varied from 1−10. For all cases, the inner dimension is fixed at 100 µm,

line width at 12 µm, line spacing at 2 µm, and metal thickness at 1 µm, which are typical

values in RF designs. The spiral L is computed with the Greenhouse algorithm which cal-

culates all the self and mutual inductances using (3.5)−(3.8) and then sums them together.

L is proportional to N m where m is approximately 2 because of the positive mutual induc-

tance. It should be pointed out that the power m is a function of N , line pitch and the ratio

of outer to inner dimension. In general, m increases with N but decreases with larger line

pitch. Spirals with a small outer-to-inner-dimension ratio have a higher power m. In a typ-ical spiral layout, the value of m lies between 1.7 and 2.5.

The third column of Table 3.1 contains the spiral length which is simply the sum of all

individual segments’ lengths. For comparison, the self inductance of a straight wire with

length equal to the spiral length is calculated using (3.5) and is listed in the last column.

The width and thickness of the straight wire are 12 µm and 1 µm, respectively, the same as

the spiral. Notice that for N less than 3, the wire L is actually higher than the spiral L. This

is mainly because the negative mutual inductance outweighs the positive one. To reduce

the negative mutual coupling, the inner dimension can be increased. Another reason is that

the self inductance increases with length more than linearly as indicated in (3.5). Although

the total length of the spiral segments is the same as the length of the straight wire, the spi-

ral actually has less self inductance than the straight wire. To illustrate this point, consider

a 1-mm long wire and four 0.25-mm long wires. According to (3.5), the 1-mm wire has an

number of self inductnace terms 4 N =

number of positive mutual inductnace terms 2 N N 1–( )=

number of negative mutual inductnace terms 2 N 2=




inductance of 0.97 nH whereas the 0.25 mm wires each has 0.17 nH. It follows that the

total inductance of the four shorter wires is 0.69 nH which is less than 0.97 nH. For larger

N ’s, the positive mutual inductance dominates and spirals achieve much larger inductances

per unit length compared to straight wires.

Although many empirical formulas exist in the literature for estimation of spiral induc-

tance [3][50][51], they are not able to accurately account for different geometries.

However, the Greenhouse method has been verified with various experimental results

[11][12][43]. For high accuracy, the series inductance in the physical inductor model is

obtained using the Greenhouse method. Even though the Greenhouse method appears to

be a tedious algorithm, it is actually fairly compact to implement in software.

3.1.2 Series Resistance

Resistance is a measure of the opposition offered by a conductor to the current flow under

an applied voltage. Since the total current is equal to the current density times the area (for

materials with uniform resistivity), the resistance can be expressed as

Table 3.1: Properties of spiral inductance. For all cases, the inner dimension isfixed at 100 µm, line width at 12 µm, line spacing at 2 µm, and metalthickness at 1 µm.

N Spiral L (nH) Spiral Length (µm) Wire L (nH)

1 0.27 448 0.42

2 0.94 1034 1.15

3 2.03 1720 2.09

4 3.60 2518 3.25

5 5.71 3428 4.64

6 8.41 4450 6.267 11.77 5584 8.10

8 15.84 6830 10.19

9 20.68 8188 12.51

10 26.36 9658 15.07




. (3.13)

The frequency dependence of R is due to the change in current density as frequency varies.

The current density in a wire is uniform at dc; however, as frequency increases, the current

density becomes non-uniform due to the formation of eddy currents. The eddy current

effect occurs when a conductor is subjected to time-varying magnetic fields and is gov-

erned by Faraday’s law [52][53]. Eddy currents manifest themselves as skin and proximity

effects. In accordance with Lenz’s law, eddy currents produce their own magnetic fields to

oppose the original field. In the case of the skin effect, the time-varying magnetic field due

to the current flow in a conductor induces eddy currents in the conductor itself. The prox-

imity effect takes place when a conductor is under the influence of a time-varying field

produced by a nearby conductor carrying a time-varying current. In this case, eddy cur-

rents are induced whether or not the first conductor carries current. This is essentially a

transformer action. If the first conductor does carry a time-varying current, then the

skin-effect eddy current and the proximity-effect eddy current superimpose to form the

total eddy current distribution. Regardless of the induction mechanism, eddy currents

reduce the net current flow in the conductor and hence increase the ac resistance. The dis-

tribution of eddy currents depends on the geometry of the conductor and its orientation

with respect to the impinging time-varying magnetic field. The most critical parameter

pertaining to eddy current effects is the skin depth which is defined as

(3.14)

where ρ, µ, and f represent the resistivity in Ω-m, permeability in H/m, and frequency in

Hz, respectively. The skin depth is also known as the “depth of penetration” since it

describes the degree of penetration by the electric current and magnetic flux into the sur-

face of a conductor at high frequencies. The severity of the eddy current effect is

determined by the ratio of skin depth to the conductor thickness. The eddy current effect is

negligible only if the depth of penetration is much greater than the conductor thickness. In

general, eddy currents increase with frequency and thus further reduce the skin depth.

R f ( ) V

I f ( )----------

V

J f ( ) Area⋅-----------------------------= =

δ ρπµ f ----------=




Since a spiral inductor is a multi-conductor structure, eddy currents can potentially be

caused by both proximity and skin effects. The following sections will investigate the rela-

tive importance of each effect.

3.1.2.1 Proximity Effect on Resistance

Due to the close proximity between the conductor segments in a spiral inductor, the cur-

rent in each segment can induce eddy currents in other segments and cause the resistance

to increase. It is difficult to analytically determine the significance of the mutual eddy cur-

rent and resistance caused by the proximity effect [52]. To investigate this problem, an

electromagnetic field solver based on the finite element method [54] is employed to study

the effect of magnetic mutual coupling on resistance. Three side-by-side wires, as shown

in Figure 3.8(a), are simulated. Each wire has a width and thickness of 20 µm and 1 µm,

respectively. The spacing between lines is 2 µm. During the simulation, an ideal ground

plane with infinite conductivity is placed 500 µm below the wires for carrying the return

current. At 1 GHz, the inductance and resistance matrix are

Figure 3.8: Proximity effect on series resistance for (a) side-by-side and (b) stackedwires.

(a)

(b)

1 2 3

321

Wire

Wire




µH/m (3.15)

and

Ω /m (3.16)

respectively. L11, L22, and L33 are the self inductance of each wire and the off-diagonal

terms represent the mutual inductances. The mutual coupling, k , between adjacent wires is

0.76 while k between wire 1 and wire 3 is 0.65. R11, R22, and R33 are the self resistances of

each wire and the off-diagonal terms represent the mutual resistances which signify

induced eddy currents. The overall resistance of each wire can be obtained by summing

the self and mutual resistances along a row or column of the resistance matrix. For

instance, the resistance of wire 2 is 2042 Ω /m whereas for wire 1 and wire 3, it is

1976 Ω /m. The mutual resistance is less than 1% for side-by-side wires because the

mutual coupling is relatively weak.

To investigate further the proximity effect on wire resistance, three stacked wires, as

shown in Figure 3.8(b), are simulated. The separation between wires is 1 µm. At 1 GHz,

the inductance and resistance matrix are

µH/m (3.17)

and

L11 L12 L13

L21 L22 L23

L31 L32 L33

1.24 0.95 0.81

0.95 1.23 0.95

0.81 0.95 1.24

=

R11 R12 R13

R21 R22 R23

R31 R32 R33

1961 15 0

15 2012 15

0 15 1961

=

L11 L12 L13

L21 L22 L23

L31 L32 L33

1.24 1.23 1.21

1.21 1.24 1.23

1.21 1.23 1.24

=




Ω /m (3.18)

respectively. In this case, the magnetic coupling is nearly prefect (k > 0.97) and as a result,

the mutually induced eddy current is more significant compared to the side-by-side config-

uration. In particular, the resistance of all three wires is approximately the same and is

equal to 3000 Ω /m which is 50% greater than the self resistance of each wire.

3.1.2.2 Skin Effect on Resistance

To learn about the skin effect in practical systems, consider the coaxial transmission line

shown in Figure 3.9(a). At high frequencies, the current flow is limited to the outer surface

of the inner conductor whereas the return current in the ring-shape conductor is confined

to the inner surface. This is attributed to the fact that eddy currents are more severe at the

center for the inner conductor and at the outer surface of the ring-shape outer conductor. In

these regions, as a result, the current density is significantly lower than the dc level. For

on-chip spiral inductors, the line segments can be treated as microstrip transmission lines

such as the one shown in Figure 3.9(b). In this case, the high frequency current recedes to

the bottom surface of the wire, which is above the ground plane [55][56]. The attenuation

of the current density ( J in A/m2) as a function of distance away from the bottom surface

is shown in Figure 3.10[57] and can be represented by

. (3.19)

The current ( I in A) is obtained by integrating J over the wire cross-sectional area. Since J

only varies in the x direction, I can be calculated as

R11 R12 R13

R21 R22 R23

R31 R32 R33

2008 498 489

498 2012 498

489 498 2004

=

J J 0 e- x / δ⋅=




(3.20)

where t is the thickness of the wire. An effective thickness can be expressed as

Figure 3.9: Eddy current effect in the conductors of a (a) coaxial and (b) microstriptransmission line.

(a)

(b)

E

H

H

E

H

E

Current

Conductor

x

0

t

(see Figure 3.10)

I J Ad ⋅∫ =

J 0 e⋅- x / δ

w xd ⋅ ⋅0

t

∫ =

J 0 w t ef f

⋅ ⋅=

J 0 w δ 1 e- t / δ

–( )⋅ ⋅ ⋅=




. (3.21)

The effective thickness for aluminum and copper as a function of frequency is plotted in

Figure 3.11. The dotted lines in each graph denotes the skin depth. At 1 GHz, the skin

depth of Al and Cu are 2.8 µm and 2.5 µm respectively. With t = 3 µm, t eff for Al and Cuare 1.8 µm and 1.7 µm respectively. Note that at dc t eff equals to t as δ approaches infinity.

On the other hand, at high frequencies, δ is much smaller than t and t eff approaches δ as the

exponential term in (3.21) vanishes.

Substituting (3.20) and (3.21) into (3.13), R can be expressed as

. (3.22)

Since

, (3.23)

(3.22) can be rewritten as

x (m)t 0

J 0

J (A/m2)

t eff

Figure 3.10: Effective thickness (t eff ) of a conductor with finite thickness (t ) underskin effect.

Same Area

t ef f δ 1 e- t / δ

–( )⋅=

RV

J 0 w δ 1 e- t / δ

–( )⋅ ⋅ ⋅-----------------------------------------------------=

V E l⋅=

ρ J 0 l⋅ ⋅=




Figure 3.11: Effective thickness of (a) aluminum and (b) copper as a function of frequency.

(a)

(b)

0.01 0.10 1 10

Frequency (GHz)

0.1

1.0

10.0

100.0

t e f f

( µ m )

δt = 10

µm

t = 3 µm

t = 2 µm

t = 1 µm

0.01 0.10 1 10

Frequency (GHz)

0.1

1.0

10.0

100.0

t e f f

( µ m )

Copper

Aluminum

δt = 10 µm

t = 3 µm

t = 2 µm

t = 1 µm




(3.24)

where ρ and l represent the resistivity and length of the wire. As δ decreases with fre-

quency, R increases. To compute the series resistance of a spiral inductor, (3.24) is used

with l equal to the total length of all segments.

3.1.3 Feed-through Capacitance

The feed-through capacitance (C s) models the parasitic capacitive coupling between input

and output ports of the inductor. This capacitance allows the signal to flow directly from

the input to output port without passing through the spiral inductor. Based on the induc-

tor’s physical structure, both the crosstalk between adjacent turns and the overlap between

the spiral and underpass contribute to C s. However, since the adjacent turns are almost

equipotential, the effect of the crosstalk capacitance is negligible. Furthermore, the

crosstalk capacitance can be reduced by increasing the spacing between the turns. The

overlap capacitance is more significant because of a larger potential difference between

the spiral and the underpass [58][59]. Therefore, in the inductor model, it is sufficient to

model C s as the sum of all overlap capacitances, which is equal to

(3.25)

where n is the number of overlap, w is the spiral line width, and t oxM1-M2 is the oxide thick-

ness between the spiral and the underpass.

To verify that the crosstalk capacitance is indeed unimportant to an inductor’s charac-

teristics, consider the three-turn inductor and its equivalent models as shown in

Figure 3.12. In the distributed model, the 3-turn inductor is divided into six half-turn sec-

tions. Each section is represented by an inductance and resistance. Furthermore, there are

four crosstalk capacitances (C ct1−C ct4) and three overlap capacitances (C ov1−C ov3). The

inductor layout is chosen such that the sum of crosstalk capacitance is equal to the sum of

overlap capacitance. In the lumped model, the total inductance and resistance of the induc-

Rρ l⋅

w δ 1 e- t / δ

–( )⋅ ⋅-------------------------------------------=

C s

n w2 εox

t oxM1-M2

----------------------⋅ ⋅=




Figure 3.12: A three-turn inductor: (a) layout and relevant elements (b) distributedmodel and (c) lumped model.

(a)

(b)

(c)

C ov1

C ov1

C ov3

C ov2

C ov3

C ov2

C ct1

C ct2

C ct4

C ct3

C ct1C ct2C ct4 C ct3

Port 1

Port 2

Port 1Port 2

C s = C ov1 + C ov2 + C ov3

Ls Rs




tor are used. However, the lumped feed-through capacitance includes only the overlap

part. Using a circuit simulation program such as SPICE, the real and imaginary parts of

the inductor impedance are obtained. Three different cases are simulated with the distrib-

uted model. In the first case, both the overlap and crosstalk capacitances are included. In

the second case, the crosstalk capacitances are omitted from the model. For the third case,

only the overlap capacitances are included. As shown in Figure 3.13, the distinction

between the inductor impedance using “overlap and crosstalk” and “overlap only” is

barely noticeable. On the other hand, gross difference is observed when comparing “over-

lap and crosstalk” to “crosstalk only”. This can be explained by the fact that the overlap

capacitances are effectively in parallel with one another and therefore they add together toaccount for most of the feed-through capacitance. In contrast, the crosstalk capacitances

appear in series with each other and consequently have little influence on the feed-through

capacitance. Figure 3.13 also shows that by using the lumped model with overlap capaci-

tance only, both the real and imaginary parts of the inductor impedance can be modeled

with insignificant discrepancies up to 5 GHz.

3.1.4 Substrate Parasitics

The characteristics of microstrip structures on semiconductor substrate, especially metal

on oxide on silicon, have been investigated extensively [60]−[63]. In general, a MOS

microstrip structure can be modeled by a three-element network comprised of C ox, RSi and

C Si (see Figure 3.1). C ox represents the oxide capacitance whereas RSi and C Si represent

the silicon substrate resistance and capacitance, respectively. The physical origin of RSi is

the silicon conductivity which is predominately determined by the majority carrier con-

centration. C Si models the high-frequency capacitive effects occurring in the

semiconductor. For spiral inductors on silicon, the lateral dimensions are typically a few

hundred micro-meters which is much larger than the oxide thickness and is comparable to

the silicon thickness. As a result, the substrate capacitance and resistance are approxi-

mately proportional to the area occupied by the inductor and can be estimated by




Figure 3.13: (a) Real and (b) imaginary parts of the input impedance of the inductormodel circuits in Figure 3.12 for studying the importance of crosstalk andoverlap capacitance to the overall feed-through capacitance.

(a)

(b)

0.1 1.0 10.0 100.0

Frequency (GHz)

0.0

2.0

4.0

6.0

8.0

10.0

R e [ Z

i n ] ( Ω )

Overlap and Crosstalk

Overlap only

Crosstalk only

Overlap only

Lumped model:

Distributed model:

0.1 1.0 10.0 100.0

Frequency (GHz)

0.001

0.01

0.1

1

10

I m [ Z

i n ] ( k Ω )

Overlap and Crosstalk

Overlap only

Crosstalk only

Overlap only

Lumped model:

Distributed model:




, (3.26)

(3.27)

and

(3.28)

where C sub and Gsub are capacitance and conductance per unit area for the silicon sub-

strates. εox and t ox are the dielectric constant and thickness of the oxide layer between the

inductor and the substrate. The area of the spiral is equal to the product of the spiral

length, l, and width, w. C sub and Gsub are functions of the substrate doping and are

extracted from measurement results. The effects of lightly doped and epitaxial substrates

on inductors will be studied extensively in Chapter 5.

3.2 A Physical Model

Combining the inductance and parasitics described in the previous sections, a physicalmodel for spiral inductors on silicon is formed in Figure 3.14(a). In Figure 3.14(b), Ls, Rs,

and C s remain unchanged as in Figure 3.14(a). The combined impedance of C ox, C Si, and

RSi is substituted by R p and C p. Therefore, R p and C p are frequency dependent. The reason

for this substitution is twofold: it facilitates the extraction of R p and C p from measured S

parameters and the analysis of their effects on Q.

3.3 Testing and Parameter ExtractionTo examine the validity of the proposed inductor model, square spiral inductors with dif-

ferent structural and process parameters were fabricated with standard silicon processing

technology. This section describes the techniques for testing and parameter extraction.

C ox1

2--- l w

εox

t ox

-------⋅ ⋅ ⋅=

C Si1

2--- l w C sub⋅ ⋅ ⋅=

RSi2

l w Gsub⋅ ⋅--------------------------=



3.3. Testing and Parameter Extraction 49

Figure 3.14: (a) Lumped physical model of a spiral inductor on silicon. (b) Equivalentmodel with combined impedance of C ox, C Si, and C Si substituted by Rp

and C p.

(b)

(a)

C s

Ls Rs

C ox C ox

C Si

RSi

C Si

RSi

C s

Ls

Rs

C p R pC p R p




On-wafer testing was performed with a HP8720B Network Analyzer and Cascade

Microtech coplanar ground-signal-ground (GSG) probes [64]. The measurement set-up is

shown in Figure 3.15. The set-up is calibrated using the Cascade Impedance Standard

Figure 3.15: S parameters measurement set-up and a sample test structure consisted of

an open and a device under test (DUT).

G

G

SG

G

S

OPEN

Device Under Test

ProbeStation




Substrate (ISS) [65]. The full two-port calibration procedure involves steps known as the

short-load-open-through (SLOT). To ensure that the parasitics up to the GSG probe tips

are indeed calibrated out and accounted for by the Network Analyzer’s built-in error mod-

els, several structures on the ISS with known values are measured and compared to the

specification. These standard test structures include a 0.5-nH inductor, a 0.25-pF capaci-

tor, various resistors, and a few attenuators. If the measured results are consistent with the

standard specification, then the set-up is qualified for testing. It should be emphasized that

the post-calibration measurements with standard structures are crucial for validating the

calibration. The shunt parasitics of the test structure were de-embedded using open cali-

bration structures fabricated next to the device under test (DUT) [66]−[68]. An equivalentcircuit for the two-port measurement set-up is shown in Figure 3.16. Since the on-chip

ground paths for the return currents appear in series with the DUT, the parasitic inductance

and resistance of these ground paths should be made insignificant compared to the DUT

impedance.

Figure 3.16: Equivalent circuit of the measurement set-up.

On-chip Ground

for Return Current

On-chip Groundfor Return Current

G

S

G

G

S

G

PowerSource

50 Ω 50 ΩDeviceUnderTest




During the inductor measurements, the substrate was grounded from the wafer

back-side through the testing chuck. Two-port S parameters were measured, instead of

one-port parameter, to allow extraction of the inductance and other parasitics without any

curve-fitting. The extraction procedure is summarized in Figure 3.17. From the de-embed-

ded S parameters, the complex propagation constant and characteristic impedance are

computed. Then, the lumped elements in the series and shunt branches of the inductor

model in Figure 3.14(b) are solved using the relationships shown in the bottom block of

Figure 3.17. To extract Ls, Rs, and C s from the real and imaginary parts of the measured

series impedance, some assumptions about Ls and C s need to be made. Ls and Rs are sub-

ject to skin effect, which governs the magnetic field intensity and current density in theconductor at high frequencies [52]. As frequency increases, the penetration of magnetic

field into the conductor is attenuated, which causes reduction in the magnetic flux internal

to the conductor. However, Ls does not decrease significantly with increasing frequency

because it is predominantly determined by the magnetic flux external to the conductor.

Thus, Ls can be approximated as constant with frequency. The skin effect on Rs is much

more pronounced because Rs is directly affected by the non-uniform current distribution in

the conductor. C s is considered independent of frequency since it represents the

metal-to-metal overlap capacitance between the spiral and the center-tap. At low frequen-

cies, the reactance is dominated by ω Ls because ω Ls is much greater than 1/ ωC s. C s is

extracted using the low-frequency Ls value and the resonant frequency of the series

branch. Then, with C s held constant, Ls and Rs are solved using the real and imaginary

parts of the series impedance at each measurement frequency. In the shunt branch, R p and

C p can be extracted readily from the real and imaginary parts of the shunt admittance,

respectively.




Figure 3.17: Parameter extraction procedure for the lumped elements in the inductormodel shown in Figure 3.14(b).

S11 S12

S21 S22

De-embedded

S parameters A B

C D

S to Transmission

Matrix Conversion

A B

C D

γ l cosh Z0 γ l sinh

Z0

1– γ l sinh γ l cosh

Solve for Propagation Constant (γ )

and Characteristic Impedance ( Z 0)

=

γ l Z0=

2Z0

γ l ---------= =

C p

R p

C s

C p

Rs Ls

R p




3.4 Measured and Modeled Results

3.4.1 Individual Elements in the Physical Model

The modeled and measured results for two spiral inductors fabricated on 10 Ω-cm silicon

substrate are shown in Figure 3.18. The inductors have the same layout and process

parameters: 7 turns, 13-µm width, 7-µm spacing, 300-µm outer dimension, and 4.5-µm

oxide. However, the spiral metal material is different for the two cases, one with copper

and the other with aluminum. Both metal films are 1 µm thick. The measured dc sheet

resistance of the copper and aluminum films is 20 mΩ /sq. and 30 mΩ /sq., respectively.

For Ls, the Greenhouse method predicts an inductance value of 8.1 nH which is consis-

tent with the measured data. Since the inductance is not a function of the metal material,

both the copper and aluminum inductors are expected to achieve the same inductance.

This is indeed observed in the experimental results shown in Figure 3.18(a). The slight

decrease in Ls with frequency indicates that the skin effect on inductance is small and the

assumption of constant Ls is in fact valid.

The copper inductor has lower Rs than the aluminum sample, which is in agreement

with the dc measurements. The skin effect on Rs is more pronounced because Rs is

inversely proportional to the effective cross-sectional area. An increase in Rs with fre-

quency is observed for both inductors. The modeled and measured values are in excellent

agreement for both cases. This proves that the effective thickness (t eff ) described in

Section 3.1.2.2 is adequate to account for the frequency and material dependence of Rs.

Using (3.25) with n = 6, w = 13 µm, and t oxM1-M2 = 1.3 µm, the modeled value of C s is

28 fF. From the measurements, the resonance frequency of the series branch in the induc-

tor model is found to be approximately 11 GHz. With a low frequency Ls of about 8.2 nH,

the extracted value of C s is 26 fF, which is very close to the modeled value.

The frequency behaviors of R p and C p are governed by C ox, C Si, and RSi. As shown in

Figure 3.18(b), the measured shunt parasitics of the inductors are independent of the spiral



3.4. Measured and Modeled Results 55

Figure 3.18: Measured and modeled values of (a) Ls and Rs, (b) C p and R p for twoinductors with different spiral metal materials: one with copper and theother with aluminum.

(a)

(b)

0.1 1 10Frequency (GHz)

0

5

10

15

20

25

R p

( k Ω )

0

50

100

150

200

250

C p

( f F )

Copper

Aluminum

Model


0

2

4

6

8

10

L s

( n H )

0

5

10

15

20

25

R s

( Ω )

Copper

Aluminum

Model




metal material. This further confirms that the proposed parameter extraction procedure

and the inductor model are consistent with the physical effects. Using (3.26)−(3.28), the

modeled values of C ox, C Si, and RSi are 230 fF, 45 fF, and 850 Ω, respectively.

At low frequencies, the electric field terminates at the oxide-silicon interface and C p is

primarily determined by C ox. Since almost all the electric energy is stored within the oxide

layer along the spiral, little conduction current flows in the silicon substrate and thus R p is

large [61]. As frequency increases, the electric field starts to penetrate into the silicon sub-

strate which reduces C p because of the series connection of oxide and silicon substrate

capacitances. The roll-off in R p signifies increasing electric energy storage and hence more

dissipation in the silicon substrate. At high frequencies, electric energy is stored mainly in

the silicon substrate causing C p and R p to approach C Si and RSi respectively; C ox is effec-

tively short-circuited. Based on this effect, C sub and Gsub in (3.27)−(3.28) can be obtained

by dividing the measured values of C p and R p at high frequencies by the spiral area.

3.4.2 Two-Port S Parameters

In the previous section, it is shown that the individual elements in the physical model is

consistent with the values extracted from measured S parameters. To confirm that the

physical model can indeed predict the overall inductor behavior, a comparison between

the measured and modeled two-port S parameters is carried out. Using SPICE, two-port S

parameters of the physical inductor model are generated. The model components are com-

puted using the algorithm and equations described. Then, the modeled results are

compared directly with the as-measured S parameters from the Network Analyzer. On the

Smith Chart shown in Figure 3.19, the modeled and measured S 11 and S 21 are graphed and

show excellent agreement. In Figure 3.20 and Figure 3.21, the measured real and imagi-nary parts of the two-port S parameters are compared with the modeled values.



3.5. Impact of Technology on Inductor Performance 57

3.5 Impact of Technology on Inductor Performance

To demonstrate the scalability of our model, spiral inductors with various structural

parameters including different metal material, metal thickness, oxide thickness, substratematerial, and layout geometry are fabricated and tested. The efficiency of an inductor is

measured by its quality factor, Q, which is limited by the parasitic resistance and capaci-

tance. In terms of the elements shown in Figure 3.14(b), the Q of a spiral inductor on

silicon substrate can be derived as (See Chapter 4 for the detailed derivation.)

Figure 3.19: Measured and modeled values of S 11 and S 21 plotted on a Smith chart.

S 21

S 11

Model




Figure 3.20: Measured and modeled values of (a) real and (b) imaginary parts of S 11

and S 22.

(a)

(b)

0.1 1 10

Frequency (GHz)

0.0

0.2

0.4

0.6

0.8

1.0

I m [ S 1

1 ] , I m [ S 2

2 ]

0.1 1 10

Frequency (GHz)

0.0

0.2

0.4

0.6

0.8

1.0

R e [ S 1

1 ] , R e [ S 2

2 ]

Re [S 11]

Re [S 22]

Model

Im [S 11]

Im [S 22]

Model




(3.29)

where ω L s /Rs accounts for the magnetic energy stored and the ohmic loss in the series

resistance. The second term in (3.29) is the substrate loss factor representing the energy

dissipated in the semiconducting silicon substrate. The last term is the self-resonance fac-

tor describing the reduction in Q due to the increase in the peak electric energy with

frequency and the vanishing of Q at the self-resonant frequency. Hence, the self-resonant

frequency can be solved by equating the last term in (3.29) to zero.

Figure 3.22(a) shows the measured and modeled Q of the copper and aluminum induc-

tors studied in the previous section. At low frequencies, Q is well described by ω Ls /Rs for

both inductors. The copper inductor has higher Q because it has lower series resistance.

As frequency increases, the quality factors start to deviate from ω Ls /Rs due to the substrate

effects. The rapid degradation of Q at high frequencies is a combined effect of the sub-

strate loss and the self-resonance. At high frequencies, the quality factors merge together

and reduce to zero at the self-resonant frequency. This indicates that the substrate effects

are independent of the metal layer as expected. The close agreement between the mea-

sured and modeled results indicates the physical model is capable of accounting for

variation in the metal material.

Figure 3.22(b) shows the relative importance of the substrate loss and the self-reso-

nance to the overall quality factor for the two inductors. At low frequencies, both the

substrate loss factor and the self-resonance factor are at unity. As frequency increases, the

substrate loss factor starts to drop from unity earlier than the self-resonance factor. In par-

ticular, the substrate loss alone causes 10−30% reduction from ω Ls /Rs at 1−2 GHz.

Physically, the substrate loss stems from the penetration of electric field into the silicon.

As the potential drop in the semiconductor increases with frequency, the energy dissipa-

tion in the substrate through RSi becomes more severe.

Qω Ls

Rs

---------- R p

R p ω Ls Rs ⁄ ( )2 1+[ ] Rs+-------------------------------------------------------------- 1

Rs2 C s C p+( )

Ls

-------------------------------– ω2 Ls

C s

C p+( )–⋅ ⋅=

ω Ls

Rs

---------- Substrate Loss Factor Self-resonance Factor ⋅ ⋅=




Figure 3.22: Measured and modeled values of (a) Q and (b) degradation factors fortwo inductors with 1-µm spirals in copper and aluminum.

(a)

(b)

0.0

0.2

0.4

0.6

0.8

1.0

S e l f - R e s o n a n c e F a c t o r


0.0

0.2

0.4

0.6

0.8

1.0

S u b s t r a t e L o s s F a c t o

r

Copper

Aluminum

Model


0

2

4

6

8

10

Q

Copper

AluminumModel

ω Ls / Rs




Besides replacing aluminum by copper, another approach to reduce the series resis-

tance is to use thicker metal for the spiral. Figure 3.23 illustrates the effect of different

metal thicknesses and schemes on Q. Four inductors with different metal thicknesses are

fabricated and measured. A significant improvement in Q is obtained by increasing the

aluminum thickness from 1 µm to 2 µm. However, the 3 µm data reveals that further

thickening the metal has diminishing improvements in Q. This is due to the more severe

skin effect suffered by the thicker spiral. Since the current flow is concentrated at the bot-

tom side of the spiral, metal thicker than the skin depth is ineffective for lowering the

series resistance. For instance, at 1 GHz, the effective thicknesses of 1-µm, 2-µm, and

3-µm aluminum are 0.84 µm, 1.43 µm, and 1.83 µm respectively. After including the sub-strate factors, the improvement in Q at 1 GHz is 57% and 81% as the metal thickness is

increased from 1 µm to 2 µm and 3 µm. This effect is well predicted by the physical

inductor model. Since the thinner metal suffers less severe skin effect, one may attempt to

obtain more effective thickness by building an inductor with three levels of 1 µm alumi-

Figure 3.23: Effect of metal scheme on Q.


0

2

4

6

8

Q

3 levels of 1

µm Al in parallel

2 µm Al

3 µm Al

1 µm Al

Model




num connecting in parallel. That is the three spirals are connected to each other only at the

ends and are isolated by oxide along the path. The measurement, however, shows that Q

obtained in this case is the same as the one level 3 µm inductor. At first, this observation is

counter-intuitive. As discussed in Section 3.1.2.1, because the three layers are close to

each other, there are strong mutual coupling between them. The proximity effect induces

additional eddy currents comparing to an isolated 1 µm layer. This explains that breaking

up the 3 µm into three levels of 1 µm results in essentially the same effective thickness.

Q can be improved by fabricating the inductor farther away the silicon substrate with

thicker oxide. Three inductors with the same layout but different oxide thicknesses are

fabricated and measured. Figure 3.24 shows that increasing oxide thickness improves Q

because the substrate effects are suppressed. But as frequency increases, C ox is effectively

short-circuited, substrate effects become dominant, and the Q’s merge together.

Figure 3.25 shows that lowering silicon substrate resistivity decreases RSi and

increases C Si, causing the Q roll-off to occur at a lower frequency and a reduction of the

Figure 3.24: Effect of oxide thickness on Q.


0

2

4

6

8

Q

6.0 µm oxide

2.5 µm oxide

4.5 µm oxide

Model




self-resonance frequency. The increase in C Si can be attributed to the fact that in a more

conductive substrate, the electric field is terminated closer to the silicon surface and there-

fore the effective substrate is thinner.

Figure 3.26 illustrates the effect of layout area on Q for inductors with the same induc-

tance but different layout parameters. Three 8-nH inductors are designed with outer

dimension equal to 550, 400, and 300 µm. The inductors fabricated using larger area can

accommodate wider line width; and as a result, achieve lower series resistance. However,

they also have more shunt substrate parasitics because they occupy larger area. At low fre-

quencies, the larger inductors offer higher Q’s because of lower series resistance. At high

frequencies, the substrate effects dominate and the smaller inductors actually achieve

higher Q’s. At about 1 GHz, the medium size inductor achieves the highest Q because the

resistive loss and the substrate effects are balanced.

Published results are used to further confirm the inductor model and the equation for

Q. Figure 3.27 shows a comparison of the measured Qpeak of the inductors presented by

Figure 3.25: Effect of substrate resistivity on Q.


0

2

4

6

8

Q

10 Ω-cm Si:

Gsub = 4.0×10-8

S/ µm2

6 Ω-cm Si:

C sub = 1.6×10-3 fF/ µm2

C sub = 6.0×10-3 fF/ µm2

Gsub = 1.6×10-7 S/ µm2

Model




Figure 3.26: Effect of layout area on Q.


0

2

4

6

8

Q

550 µm, 41 µm

300 µm, 13 µm

400 µm, 24 µm

Outer Dimension, Line Width

Model

Figure 3.27: Verification of the physical model using published data.

(b)

0 5 10 15 20Measured Qpeak presented by Ashby et al.

0

5

10

10

20

Q P r e d i c t e d b y o u r m o d e l 5 µm

9 µm

Line Width

14 µm

19 µm

24 µm




Ashby et al. [12] and the Q values predicted by our model. These 15 inductors were fabri-

cated using 4.5 µm of gold on silicon with high substrate resistivity of about 200 ohm-cm.

Excellent agreement is obtained.

3.6 Design Methodology

The trade-off between series resistance and substrate losses represents a practical scenario

that RF designers encounter when using on-chip inductors in their circuits. As an example,

consider that a 8 nH inductor is needed for an application at 1.6 GHz. Furthermore,

because of the chip size limit, the inductor can occupy an area no larger than 400 µm by

400 µm. A design tool capable of optimizing the inductor layout by considering these con-

straints and the technology profile can significantly expedite the design flow. In

Figure 3.28, Q contour plots are presented. These plots are generated using the physical

inductor model. The contour curves represent the values of Q which are plotted as a func-

tion of the inductance and the outer dimension of the square spiral. Each point on the

contour plot corresponds to a specific inductor layout design which is defined by the

parameter set N , w, s, od , where N is the number of turns, w is the metal width, s is the

metal spacing, and od is the outer dimension of the inductor. These contour plots can iden-

tify the optimal spiral layout for achieving a specific inductance with the highest Q

possible for a given technology at the frequency of interest.

At low frequencies, such as 600 MHz shown in Figure 3.28(a), larger areas result in

higher Q’s for all inductance values considered. This is because lower series resistances

can be achieved and they are the limiting loss mechanism at low frequencies. As the fre-

quency increases to 1 GHz, the substrate loss and self-resonance effects are starting to

become important for inductors occupying large areas. As a result, the Q contours at the

upper-right-hand corner begin to roll off. For the design example (maximum Q for a 8 nH

inductor at 1.6 GHz), the contour plot in Figure 3.28(c) shows that the highest Q achiev-

able for 8 nH is 5.5 using this technology. This is achieved with a spiral that has an outer

dimension of 300 µm. This is confirmed by the experimental data. Note that if the 8-nH



3.6. Design Methodology 67

Figure 3.28: Contour plots of Q as a function of inductance and outer dimension of square spiral inductors at (a) 0.6 GHz, (b) 1.0 GHz, (c) 1.6 GHz, and (d)3.0 GHz.

Measured Q

3.4

0 100 200 300 400

Outer Dimension (µm)

0

2

4

6

8

10

I n d u c t a n c e ( n H )

5

3

1

2

1

1

3

5

5

7

9

3

7

9

4

4

5

4

7

9

0.6 GHz 1.0 GHz

1.7

1.6 GHz 3.0 GHz

Measured Q

4.62.9

Measured Q

4.06.1

Measured Q

5.24.0

0 100 200 300 400

Outer Dimension (µm)

0 100 200 300 400Outer Dimension (µm) 0 100 200 300 400Outer Dimension (µm)

0

2

4

6

8

10

I n d u c t a n c e ( n H )

1

(c) (d)

(a) (b)




inductor were fabricated using the maximum area available (i.e. 400 µm by 400 µm), a

lower Q would result while precious chip area would be wasted. Figure 3.28(d) shows that

if the frequency of operation is increased to 3 GHz, the inductor with an outer dimension

of 300 µm will no longer be the optimal design because the substrate effects are now even

more severe. In fact, an inductor layout that has an outer dimension of 220 µm will offer

the highest Q of slightly above 5.

In addition to optimizing Q in a limited area, the inductor design methodology pre-

sented above can have different combinations of optimization targets and constraints. For

example, in a tuned amplifier with shunt-peaking load [3], it is desirable to maximize the

product of Q and inductance instead of Q. For inductors used as emitter or source degener-

ation [5], it is important to limit the parasitic capacitances. In general, the contour plots

can be tailored for specific design goals.

3.7 Summary

In this chapter, a physical model for planar spiral inductors on silicon is presented. The

characteristics of each component in the model have been investigated extensively. The

physical phenomena important to the prediction of Q are considered and analyzed. The

scalable inductor model shows excellent agreement with measured and published data.

The effects of various layout and process parameters on Q are explained using the inductor

model and confirmed with experimental data. Finally, Q contour plots are introduced to

assist RF designers to optimize inductor design under various constraints.



69

Chapter

4 Patterned Ground

Shields

It has been shown that the inductor quality factor (Q) degrades at high frequencies due to

energy dissipation in the semiconducting silicon substrate in Chapter 3. For RF circuits,

the importance of noise coupling via the substrate at gigahertz frequencies has been

reported [69][70]. As spiral inductors occupy substantial chip area, they can potentially be

the source and receptor of detrimental noise coupling. Furthermore, the physical phenom-

ena associated with the substrate effects are complicated to characterize and model.

Therefore, decoupling the inductor from the substrate can enhance the overall perfor-

mance: increase Q, improve isolation, and simplify modeling.

Some approaches have been proposed to address the substrate issues; however, theyare accompanied by drawbacks. Ashby et al. [12] suggested the use of high-resistivity

(150 to 200 Ω-cm) silicon substrate to mimic the low-loss semi-insulating GaAs substrate,

but this is an uncommon option for current silicon technologies. Chang et al. [71] demon-

strated that etching a pit in the silicon substrate under the inductors can remove the

substrate effects. However, the etch adds extra processing cost and is not readily available.

Moreover, it raises reliability concerns such as packaging yield and long-term mechanical

stability. For low-cost integration of inductors, the solution to substrate problems should

avoid increasing process complexity.

This chapter presents a patterned ground shield, which is compatible with standard sil-

icon technologies, to reduce the unwanted substrate effects. To provide some background,

Section 4.1.1 presents a discussion on the fundamental definitions of Q for inductors and

LC -tanks. Next, the physical model for spiral inductors on silicon is reviewed. The mag-



70 Chapter 4: Patterned Ground Shields

netic energy storage and loss mechanisms in an on-chip inductor are discussed. Based on

this insight, it is shown that energy loss can be reduced by shielding the electric field of the

inductor from the silicon substrate. Then, the drawbacks of a solid ground shield are ana-

lyzed. This leads to the design of a patterned ground shield. Design guidelines for

parameters such as shield pattern and resistance are given. In Section 4.2, experimental

results are reported to study the effects of shield resistance and pattern on inductance, par-

asitic resistances and capacitances, and inductor Q. Next, the improvement in Q of a

2-GHz LC tank using a shielded inductor is illustrated. A study of the noise coupling

between two adjacent inductors and the efficiency of the ground shield for isolation are

also presented.

4.1 Design Considerations

4.1.1 Definitions of Quality Factor

The efficiency of an inductor is measured by its quality factor, Q, which is defined as [72]

. (4.1)

Interestingly, (4.1) also defines the Q of a LC tank. The definition in (4.1) is fundamental

in the sense that it does not specify which element stores or dissipates the energy. The sub-

tle distinction between an inductor Q and a LC -tank Q lies in the intended form of energy

storage. For an inductor, only the energy stored in the magnetic field is of interest. Any

energy stored in the inductor’s electric field, because of some inevitable parasitic capaci-

tances in a real inductor, is counter-productive. Hence, Q is proportional to the net

magnetic energy stored, which is equal to the difference between the peak magnetic and

electric energies. An inductor is at self-resonance when the peak magnetic and electric

energies are equal. Therefore, Q vanishes to zero at the self-resonant frequency. Above the

self-resonant frequency, no net magnetic energy is available from an inductor to any exter-

nal circuit. In contrast, for a LC tank, the energy stored is the sum of the average magnetic

and electric energies. Since the energy stored in a (lossless) LC tank is constant and oscil-

Q 2π Energy Stored

Energy Loss in One Oscillation Cycle

------------------------------------------------------------------------------------------⋅=



4.1. Design Considerations 71

lates between magnetic and electric forms, it is also equal to the peak magnetic energy, or

the peak electric energy. The rate of the oscillation process is the tank’s resonant fre-

quency at which Q is defined. For a lossless LC tank, Q is infinite.

To illustrate the distinction between these two cases, consider a simple parallel RLC

circuit first as an inductor model, then as a LC -tank model. The expressions for the ener-

gies and the resonant frequency, ω0, are:

, (4.2)

, (4.3)

, (4.4)

, (4.5)

, (4.6)

and

, (4.7)

where V 0 denotes the peak voltage across the circuit terminals. In terms of an inductor

model, C is regarded as the parasitic capacitance of the inductor. According to the defini-

tion of inductor Q, it can be shown that

(4.8)

E Peak Magnetic

V 02

2ω2 L--------------=

E Peak Electric

V 02

C

2-----------=

E Loss in One Oscillation Cycle

2πω------

V 02

2 R-------⋅=

E Average Magnetic

V 02

4ω2 L--------------=

E Average Electric

V 0

2

C 4

-----------=

ω01

LC ------------=

Q Induct or 2π Peak Magnetic Energy Peak Electric Energy–

Energy Loss in One Oscillation Cycle----------------------------------------------------------------------------------------------------------------⋅=

R

ω L------- 1

ωω0

------ 2–⋅=




which equals to zero at ω = ω0, and is less than zero beyond ω0. It is worthwhile to men-

tion that the result in (4.8) can also be obtained using the ratio of the imaginary to the real

parts of the circuit impedance. The circuit impedance is inductive below ω0 and capacitive

above ω 0. In terms of a LC -tank model, C is regarded as the tank capacitance of the LC

oscillator. The Q can be expressed as

. (4.9)

The above result can also be derived using a more well-known relationship: the ratio of the

resonant frequency to the −3-dB bandwidth.

Both Q definitions discussed are of importance, and their applications are determined

by the intended function in a circuit. When evaluating the quality of an on-chip inductor asa single element, the definition in (4.8) is more appropriate. In Section 4.2, when LC tanks

are studied, the definition in (4.9) is used.

4.1.2 Understanding of Substrate Effects

The physical model developed in Chapter 3 is shown in Figure 4.1. An on-chip inductor is

physically a three-port element including the substrate. The one-port connection shown

avoids unnecessary complexity in the following analysis and at the same time preservesthe inductor characteristics. In the model, the series branch consists of Ls, Rs, and C s. Ls

represents the spiral inductance which can be computed using the Greenhouse method. Rs

is the metal series resistance whose behavior at RF is governed by the eddy current effect.

This resistance symbolizes the energy losses due to the skin effect in the spiral intercon-

QTank 2π Average Magnetic Energy Average Electric Energy+

Energy Loss in One Oscillation Cycle--------------------------------------------------------------------------------------------------------------------------------------⋅

ω ω0=

=

2π Peak Magnetic Energy

Energy Loss in One Oscillation Cycle------------------------------------------------------------------------------------------⋅

ω ω0=

R

ω0 L----------==

2π Peak Electric Energy Energy Loss in One Oscillation Cycle------------------------------------------------------------------------------------------⋅

ω ω0=

ω0 RC ==

R

L C ⁄ ---------------=




nect structure as well as the induced eddy current in any conductive media close to the

inductor. The series feed-forward capacitance, C s, accounts for the capacitance due to the

overlaps between the spiral and the center-tap underpass. The effect of the inter-turn fring-

ing capacitance is usually small because the adjacent turns are almost equipotential, and

therefore it is neglected in our model. The overlap capacitance is more significant because

of the relatively large potential difference between the spiral and the center-tap underpass.

The parasitics in the shunt branch are modeled by C ox, C Si, and RSi. C ox represents the

oxide capacitance between the spiral and the substrate. The silicon substrate capacitance

and resistance are modeled by C Si and RSi respectively. The ohmic loss in RSi signifies the

energy dissipation in the silicon substrate.

In Figure 4.2, the combined impedance of C ox, C Si, and RSi is substituted by R p and C p

which are therefore frequency dependent while Ls, Rs, and C s remain unchanged as in

Figure 4.1. The reason for this substitution is twofold: it facilitates the analysis of R p’s

effect on Q and the extraction of the shunt parasitics from measured S parameters. In

terms of the circuit elements in Figure 4.2, the energies can be expressed as:

Figure 4.1: Lumped physical model of a spiral inductor on silicon.

C ox

C Si RSi

C s

Rs

Ls




, (4.10)

, (4.11)

and

, (4.12)

where

, (4.13)

Figure 4.2: Equivalent model with the combined impedance of C ox, C Si, and RSi inFigure 4.1 substituted by R p and C p.

C s

Rs

Ls

C p R p

E Peak Magnetic

V 02 Ls

2 ω Ls( )2

Rs2

+[ ]⋅

-------------------------------------------=

E Peak Electric

V 02

C s C p+( )

2--------------------------------=

E Loss in One Oscillation Cycle

2πω------

V 02

2------

1

R p

------ R

s

ω Ls( )2 Rs2+

------------------------------+⋅ ⋅=

R p

1

ω2C ox

2 RSi

------------------------- Rsi C ox C Si+( )2

C ox

2---------------------------------------+=




, (4.14)

and V 0 denotes the peak voltage across the inductor terminals. The inductor Q can be

derived by substituting (4.10)−(4.12) into (4.8):

(4.15)

where ω L s /Rs accounts for the magnetic energy stored and the ohmic loss in the series

resistance. The second term in (4.15) is the substrate loss factor representing the energy

dissipated in the semiconducting silicon substrate. The last term is the self-resonance fac-

tor describing the reduction in Q due to the increase in the peak electric energy with

frequency and the vanishing of Q at the self-resonant frequency. Hence, the self-resonant

frequency can be solved by equating the last term in (4.15) to zero.

From (4.15), it can be seen that the substrate loss factor approaches unity as R p

approaches infinity. In other words, by increasing R p to infinity, we can reduce the sub-

strate loss. From (4.13), it can be shown that R p approaches infinity as RSi goes to zero or

infinity. This is an important observation because it implies that Q can be improved by

making the silicon substrate either a short or an open thereby eliminating energy dissipa-

tion. Using high-resistivity silicon, or etching away the silicon, is equivalent to making the

substrate an open circuit. In this paper, we explored the option of making the substrate a

short circuit to eliminate the loss. The approach is to insert a ground plane to block the

inductor electric field from entering the silicon.

4.1.3 Drawback of Solid Ground Shields

The effectiveness of solid ground shield for reducing silicon parasitics has been reported.

Rofougaran et al. used metal one as ground shields for metal-two bond-pads to improve

C p

C ox

1 ω2C

oxC

Si+( )C Si

RSi

2+

1 ω2C

ox

C Si

+( )2 R

Si

2+

---------------------------------------------------------------⋅=

Qω L

s

Rs

---------- R

p

R p ω Ls Rs ⁄ ( )2 1+[ ] Rs+-------------------------------------------------------------- 1

Rs2 C

sC

p+( )

Ls

-------------------------------– ω2 Ls

C s

C p+( )–⋅ ⋅=

ω Ls

Rs

---------- Substrate Loss Factor Self-resonance Factor ⋅ ⋅=




the input impedance matching of a low-noise-amplifier fabricated in CMOS process [73].

Tsukahara et al. used a similar technique with polysilicon layer as ground shields for

metal-insulator-metal capacitors in a bipolar process [74]. The polysilicon ground shields

eliminated the silicon parasitics associated with the bottom plate of the capacitors. At

1 GHz, 30-dB reduction in substrate cross-talk was reported.

A solid conductive ground shield (see Figure 4.3)can be inserted between the inductor

and the substrate to provide a short to ground. This is equivalent to placing a small resis-

tance in parallel with C Si and RSi of the circuit model in Figure 4.1. Physically, the electric

field of the inductor is terminated before reaching the silicon substrate. One of the serious

drawbacks with this approach is that the solid ground shield also disturbs the inductor’s

magnetic field. According to the Lenz’s Law, image current, also known as loop current,

will be induced in the solid ground shield by the magnetic field of the spiral inductor. The

image current in the solid ground shield will flow in a direction opposite to that of the cur-

rent in the spiral. The resulting negative mutual coupling between the currents reduces the

magnetic field, and thus the overall inductance.

Using an equivalent circuit model, one can treat the inductor with the ground shield as

a transformer. In Figure 4.4, the primary and secondary circuits represent the spiral andthe solid ground shield respectively. The induced current flowing in the secondary induc-

tor will impose a counter-electromotive-force on the primary inductor. This effect can be

accounted for by adding a reflected impedance, Zr , in series with the impedance of the pri-

mary circuit [75]. Zr can be expressed in terms of the mutual inductance, M , and the series

impedance of the secondary circuit as

. (4.16)

Therefore, the input impedance seen by the source is

. (4.17)

Zr ω M ( )2

R2 jω L2+

--------------------------=

Zin R1 jω L1 Zr + +=




Figure 4.3: (a) Perspective view of a spiral inductor on solid ground shield and theresulting electromagnetic field lines. The fields are substantiallyattenuated by the shield. (b) Perspective view of a solid ground shieldshowing the induced loop current and its associated magnetic field lines.

(a)

(b)




Note that the imaginary part of Zr is negative which signifies the reduction in the overall

inductance. Also of importance is the increase in the overall resistance due to the real part

of Zr , which denotes the additional energy loss associated with the ground shield conduc-

tor. From (4.16) and (4.17), one can easily show that the effect of Zr on Zin diminishes as

R2 approaches infinity. An infinite R2 can be achieved by inserting features in the ground

shield that oppose the flow of the image current.

4.1.4 Design of Patterned Ground Shields

To increase the resistance to the image current, the ground shield is patterned with slots

orthogonal to the spiral as illustrated in Figure 4.5 [76]. The slots act as an open circuit to

cut off the path of the induced loop current. The slots should be sufficiently narrow such

that the vertical electric field cannot leak through the patterned ground shield into the

underlying silicon substrate. With the slots etched away, the ground strips serve as the ter-

Figure 4.4: Circuit model for illustrating the effects of negative mutual couplingbetween a spiral inductor and a solid ground shield.

R1

L1

I 1

M

R2

L2

I 2

Zin




mination for the electric field. The ground strips are merged together around the four outer

edges of the spiral. The separation between the merged area and the edges is not critical.

However, it is crucial that the merged area does not form a closed ring around the spiral

since it can potentially support unwanted loop current. The merged area of the shieldshould be strapped with the top layer metal to provide a low-impedance path to ground.

The general rule is to prevent negative mutual coupling while minimizing the impedance

to ground.

Figure 4.5: Close-up photo of the patterned ground shield.

Slots between Strips

Induced Loop Current

Ground Strips




The shield resistance is another critical design parameter. The purpose of the patterned

ground shield is to provide a good short to ground for the electric field. Since the finite

shield resistance contributes to energy loss of the inductor, it must be kept minimal. Spe-

cifically, by keeping the shield resistance small compared to the reactance of the oxide

capacitance, the voltage drop that can develop across the shield resistance is very small.

As a result, the energy loss due to the shield resistance is insignificant compared to other

loses. A typical on-chip spiral inductor has parasitic oxide capacitance between 0.25 to

1 pF depending on the size and the oxide thickness. The corresponding reactance due to

the oxide capacitance at 1 to 2 GHz is on the order of 100 Ω, and hence shield resistance

of a few ohms is sufficiently small not to cause any noticeable loss.

As the magnetic field passes through the patterned ground shield, its intensity is weak-

ened due to the skin effect [52]. This directly causes a decrease in the inductance since the

magnetic flux is lessened in the space occupied by the ground shield layer. To avoid this

attenuation, the shield must be significantly thinner than the skin depth at the frequency of

interest. For example, the skin depth of aluminum at 2 GHz is approximately 2 µm which

is only three to four times the typical metal-one thickness. This implies that using a typical

metal one layer for the shield may result in reduction of the magnetic field intensity andhence the inductance. Polysilicon could be a better choice for the ground shield.

4.2 Experimental

4.2.1 Experiment Design

In Figure 4.6, the test structures are shown for the inductors studied in this work: (a) no

ground shield (NGS), (b) solid ground shield (SGS), and (c) patterned ground shield(PGS). Each spiral is fabricated using 2-µm thick aluminum with 12-mΩ /sq. sheet resis-

tance. A 1-µm thick underpass is used to contact the center of the spiral. The spiral and the

ground shield are separated by 5.2-µm of oxide. The ground shield is separated from the

silicon substrate by 0.4-µm of oxide. The inductors are fabricated on 10 to 20 Ω-cm bulk



4.2. Experimental 81

Figure 4.6: Die photos of ground-signal-ground (GSG) test structure and theinductors: (a) spiral inductor with no ground shield (NGS), (b) solidground shield (SGS) shown without and with spiral, (c) patterned groundshield shown without and with spiral.

(a)

(b)

(c)




silicon substrates. Each inductor has 7 turns, 15-µm line width, and 5-µm line space. The

outer dimension of the spirals is 300 µm. The spiral layout is optimized to achieve maxi-

mum Q for the un-shielded inductor at about 1.5 GHz. The same layout is used for the

shielded inductors to demonstrate the general advantage of inserting the PGS beneath an

inductor without deliberate optimization. This implies that further improvement for the

shielded inductor is attainable with the layout optimized to account for the parasitics of the

shield.

To investigate the effect of shield pattern, ground shields with different slot widths (1.5

and 2.5 µm) and pitches (5 and 20 µm) are fabricated. To study the effect of shield resis-

tance, 0.5-µm aluminum (64 mΩ / sq.) and 0.5-µm doped polysilicon (12 Ω /sq.) are used

to implement the shield. The polysilicon sheet resistance is chosen to be similar to that of

MOSFET gates or BJT emitters. In technologies with silicided gate or emitter, the sheet

resistance of the polysilicon layer can be as low as a few ohms per square which is more

suitable for our purpose. Nevertheless, the measured results will reveal that our doped pol-

ysilicon is conductive enough not to cause any observable loss.

Noise coupling between inductors is studied. Crosstalk was measured between two

adjacent un-shielded inductors on substrates with different resistivities. The test structureis shown in Figure 4.7. Each inductor has one end grounded, and the metal ground rings

surrounding the inductors are not connected. The efficiency of the ground shield for isola-

tion is evaluated using the same test structure with shields inserted underneath the

inductors.

4.2.2 Effects on Inductance and Parasitics

In Figure 4.8(a), measurement results for the effect of aluminum ground shields on Ls areplotted. Two inductors with NGS on 11 and 19-Ω-cm substrates are included for compari-

son. For the inductors without ground shields, the extracted Ls’s are about 8 nH: the slight

decrease with frequency justifies the assumption that Ls is almost frequency-invariant.

Furthermore, no noticeable difference in the Ls’s is observed for the two different sub-




strates confirming that the magnetic fields of the inductors do not interact strongly with the

substrates. The extracted C s’s are 18 fF: both inductors have the same C s since the layout

and process parameters are identical except the substrate resistivity. In the shielded induc-

tors, however, Ls can no longer be assumed as frequency-invariant due to the induced loop

current and attenuation of the magnetic flux in the shield layer. The extraction of Ls, con-

sequently, is more difficult. In contrast, it is reasonable to expect C s to remain the same,

with the introduction of the shield. Therefore, Ls of the shielded inductors are extracted

with C s equal to 18 fF. For the inductor with SGS, the extracted Ls decreases significantly

as frequency increases. This is caused by the negative mutual coupling between the spiral

and the SGS as explained in Section II-C. With the PGS, most of the inductance is recov-

ered, which confirms the effectiveness of the slot pattern for stopping the image current.

Close inspection reveals that the inductance for the PGS case is lower than the two NGS

cases and the difference increases with frequency. This suggests that aluminum is too con-

ductive to be optimal as the ground shield layer. In Figure 4.8(b), the extracted Rs of the

inductors with NGS increases with frequency due to the skin effect of the spiral conductor.

Figure 4.7: Two-port test structure for measuring crosstalk via substrate between twoadjacent inductors (shown with un-shielded inductors).




Figure 4.8: Effect of aluminum ground shields on: (a) spiral inductance ( Ls), (b) seriesresistance ( Rs).

0.1 1 10

Frequency (GHz)

0

2

4

6

8

10

L s

( n H )

0.1 1 10

Frequency (GHz)

0

5

10

15

20

25

R s

( Ω )

PGS

SGS

NGS (19 Ω-cm)NGS (11 Ω-cm)

(a)

(b)

PGS

SGS

NGS (19 Ω-cm)

NGS (11 Ω-cm)




Figure 4.9: Effect of aluminum ground shields on: (a) parasitic capacitance (C p), and(b) parasitic resistance ( R p).

0.1 1 10

Frequency (GHz)

0

50

100

150

200

250

300

C p

( f F )

0.1 1 10

Frequency (GHz)

0

5

10

15

20

R p

( k Ω )

(a)

(b)

PGS

SGS

NGS (19 Ω-cm)

NGS (11 Ω-cm)

PGS

SGS

NGS (19 Ω-cm)

NGS (11 Ω-cm)




Figure 4.10: Effect of polysilicon ground shields on: (a) spiral inductance ( Ls), (b)series resistance ( Rs).

0.1 1 10

Frequency (GHz)

0

2

4

6

8

10

L s

( n H )

0.1 1 10

Frequency (GHz)

0

5

10

15

20

25

R s

( Ω )

PGS

SGS


(a)

(b)

PGS

SGS

NGS (19 Ω-cm)

NGS (11 Ω-cm)




Figure 4.11: Effect of polysilicon ground shields on: (a) parasitic capacitance (C p),and (b) parasitic resistance ( R p).

0.1 1 10

Frequency (GHz)

0

50

100

150

200

250

300

C p

( f F )

0.1 1 10

Frequency (GHz)

0

5

10

15

20

R p

( k Ω )

PGS

SGS

NGS (19 Ω-cm)

NGS (11 Ω-cm)

PGS

SGS


(a)

(b)




4.2.3 Improvement in Inductor Q

Figure 4.12 show the effects of aluminum and polysilicon ground shields on Q. The induc-

tor with aluminum SGS has the lowest Q because of its lowest Ls and highest Rs. In

Figure 4.12(b), the polysilicon SGS yields a Q similar to those of the NGS cases indicat-

ing that it is resistive enough to prevent most of the image current from flowing. Finally,

the polysilicon PGS, which combines the appropriate sheet resistance and pattern, yields

the most improvement in Q, range from 10-33%, between 1 to 2 GHz. Note that the inclu-

sion of the ground shields increases C p, which causes a fast roll-off in Q above the peak-Q

frequency and a reduction in the self-resonant frequency. Comparison between the induc-

tor parameters for the NGS (11 Ω-cm) and polysilicon PGS cases is shown in Table 4.1.

The results at 2 GHz are compared to emphasize that the relative importance of the degra-

dation mechanisms above the peak-Q frequency. In particular, the un-shielded inductor

suffers greatly from substrate loss with nearly 50% reduction from ω L s /Rs. Although the

shielded inductor has a lower self-resonance factor, it is almost free of substrate loss. The

overall effect is a 33% improvement in Q at 2 GHz with the addition of polysilicon PGS.

Further optimization of the shielded inductor layout to decrease the self-resonance factor

and increase the Q is possible.

Table 4.1: Comparison of measured inductor parameters for the NGS (11 Ω-cm)and polysilicon PGS cases at 2 GHz.

NGS Polysilicon PGS

Ls (nH) 7.5 7.4

Rs (Ω) 8.2 8.5

C s (fF) 18.0 18.0

C p (fF) 108.1 268.2

R p (k Ω) 1.2 15.0




Figure 4.12: Effect of (a) aluminum and (b) polysilicon ground shields on Q.

(a)

(b)

0.1 1 10

Frequency (GHz)

0

2

4

6

8

Q

0.1 1 10

Frequency (GHz)

0

2

4

6

8

Q

PGS

SGS


PGS

SGSNGS (19 Ω-cm)

NGS (11 Ω-cm)




can be determined by ratio of the resonant frequency, at which the tank impedance is max-

imum, to the −3-dB bandwidth. Even though the parasitic capacitance of both inductors

are incorporated as part of the tank capacitance, the tank with the un-shielded inductor

suffers from a lossy R p. As a result, QTank is improved from 6.0 to 10.2 when a shield is

used under the inductor. It is important to note that maximum QTank exceeds the maximum

inductor Q for both cases (see Table 4.1). This can be attributed to the fact that the reduc-

tion of the inductors’ Q caused by their parasitic capacitances become irrelevant as the

capacitances are “absorbed” by the LC tanks as discussed in Section 4.1.1.

4.2.5 Suppression of Substrate Noise Coupling

Substrate noise coupling between two adjacent inductors is measured by the magnitude of

the transmission coefficient, |S 21|. During the measurements, the substrate is grounded to

study realistic scenario in RF IC’s. Figure 4.14 shows that for the un-shielded inductors,

Figure 4.14: Effect of polysilicon patterned ground shield on substrate couplingbetween two adjacent inductors.

0.1 1 10

Frequency (GHz)

-90

-80

-70

-60

-50

-40

| S 2 1

| ( d B )

PGS

NGS (19 Ω-cm)

NGS (11 Ω-cm)Probes up



4.3. Summary 93

the one on a more conductive substrate (11 Ω-cm) has stronger coupling due to the higher

substrate admittance. The peaks in |S 21| for the NGS cases correspond to the onset of sig-

nificant electric field penetration into the silicon substrate, and hence more coupling

through the substrate. In contrast, the inductors shielded by the polysilicon PGS’s show

significantly better isolation, up to 25 dB improvement, at gigahertz frequencies. It should

be noted that like any other isolation structure, such as a guard ring, the efficiency of the

PGS is highly dependent on the integrity of the ground connection. Designers often need

to make a trade-off between the desired isolation level and the chip area that is required for

a low-impedance ground.

4.3 Summary

On-chip spiral inductors with patterned ground shields are presented. The parasitic effects

of an inductor on silicon are analyzed with the aid of a physical model. A patterned

ground shield is devised to eliminate the silicon parasitics of the on-chip spiral inductor.

The effects of shield resistance and pattern are studied both theoretically and experimen-

tally. Measurement results confirmed that a patterned ground shield improves Q and

isolation of an on-chip inductor. Furthermore, with the addition of the ground shield, an

inductor’s characteristics are less dependent on substrate variation and hence are easier to

model. The implementation of the ground shield is compatible with standard silicon IC

technology. The experimental results presented in this chapter are exclusively based on

lightly-doped (10−20 Ω-cm) substrates. Given the increasing interest in CMOS RF IC’s,

the effectiveness of the patterned ground shields on heavily-doped (10−20 mΩ-cm) sub-

strates will be discussed in the next chapter.



95

Chapter

5 Effects of Epitaxial and

Lightly Doped

Substrates

Based on measured results, this chapter presents an extensive study of substrate effects on

RF passive components with an emphasis on spiral inductors. The results facilitate the

integration of passive components on epitaxial (epi) and lightly doped substrates for sili-

con-based RF IC’s. There is growing interest in CMOS RF IC’s because CMOS offers

low-cost production and the potential of integrating RF and base-band circuits. Epi sub-

strates are routinely employed in CMOS logic and ASIC processes while lightly doped

(1−30 Ω-cm) substrates are commonly used in bipolar or BiCMOS processes and CMOS

memory technologies. Epi substrates are comprised of a lightly doped (1−30 Ω-cm) epi-

taxial layer grown on a degenerately doped (10−20 mΩ-cm) bulk substrate. The heavily

doped silicon bulk provides immunity to latch and enhances defect gettering. Although

numerous results for inductors on silicon have been reported, most of them are limited to

lightly doped substrates. Furthermore, it is generally believed that the highly conductive

bulk of epi substrates cause more loss. The goal of this work is to investigate the substrate

effects and thus improve the performance of on-chip passive components.

This chapter begins with an interfacial charge model that describes the substrate para-

sitics. Then, measured results of bond pads and spiral inductors on different substrates are

presented. The study shows that substrate parasitic capacitance is significantly larger for

epi substrates. However, the results also reveal that epi substrates are actually less lossy

than lightly doped cases, which is counter-intuitive to the common perception. For spiral



96 Chapter 5: Effects of Epitaxial and Lightly Doped Substrates

inductors, substrate eddy current are proven to be negligible even in epi wafers. Inductors

on epi substrates with and without patterned ground shields are measured. Experimental

data show an increase of 15% in inductor Q at 1.5 GHz and an improvement of 400% in

resonator Q at 3.75 GHz with the introduction of the patterned ground shields. Further-

more, it is shown that patterned ground shields implemented using MOSFET gate

polysilicon or source/drain diffusion layers achieve similar improvement in Q.

5.1 Theory and Simulation

On-chip passive components are realized using interconnect layers which are insulated

from the semiconducting silicon by oxide. Therefore, the substrate parasitics can be repre-

sented by a generic SiO2-Si system such as the one shown in Figure 5.1(a). The

characteristics of a SiO2-Si system can be explained using a parallel-plate capacitor model

with both SiO2 and Si as dielectric slabs [60][77]. When an ac voltage is applied, a

time-varying electric field is established across the capacitor. Under the influence of the

electric field, the majority carriers in the silicon form a layer of surface charge at the

oxide-silicon interface. The relaxation time constant of this interfacial charge density, ρs,

can be determined by solving the following field equations:

, (5.1)

, (5.2)

and

, (5.3)

which yield

(5.4)

where

ρs

εSi E Si εox E ox–=

∂ρs

∂t ⁄ J Si σSi E Si= =

t ox E ox t Si E Si+ V =

ρs

εox

t ox

------- V et τre ⁄ –

1– ⋅ ⋅=



5.1. Theory and Simulation 97

. (5.5)

The value of τre governs whether or not the majority carriers can follow the time-varying

electric field instantaneously. If τre is small compared to the period of the time-varying

electric field, then the silicon acts as a potent supply of charge and therefore terminates the

electric field at the SiO2-Si interface.

The SiO2-Si system can also be modeled by the equivalent circuit shown in

Figure 5.1(b). The transient behavior of ρs can be obtained using the following circuit

equations:

Silicon (εSi, σSi)

interfacial charge (ρs)

t ox

t Si

E ox

E Si

+

−

V

Oxide (

εox)

(a)

(b)

+

−

V Si

V ox

+

−

Figure 5.1: (a) A parallel-plate capacitor with SiO2 and Si as dielectric slabs. (b) Aequivalent circuit model for the SiO2-Si system.

GSi

σSi

t Si

--------= C Si

εSi

t Si

-------=

C ox

εox

t ox

-------=

τre

εSi εox t Si t ox ⁄ ( )+

σSi

-------------------------------------------=




, (5.6)

, (5.7)

and

, (5.8)

which yield

(5.9)

where

. (5.10)

This is the same result as in (5.5) as expected.

For conventional IC’s, the silicon substrate thickness is about 500 µm whereas the

oxide thickness varies between 2−6 µm. As a result, τre is usually much greater than the

dielectric relaxation time constant of silicon (τSi = εSi / σSi) due to the large ratio of t Si to

t ox. It is worthwhile to mention that the transient behavior of ρs is the physical origin of the

slow-wave phenomena for microstrip structures on SiO2-Si [61]. The relaxation frequency,

f re, associated with ρs is defined as

. (5.11)

For instance, a lightly doped silicon wafer with resistivity of 10 Ω-cm, t Si = 500 µm, and

t ox = 4 µm, τre and f re are 450 ps and 350 MHz, respectively. This implies that the interfa-

cial charge can only track signals not exceeding a couple hundred mega-hertz. For passive

components, f re marks the frequency limit above which the substrate parasitics becomes

significant and must be considered in the equivalent model. For the heavily doped bulk of

an epi wafer with resistivity of 10 mΩ-cm and the same oxide and silicon thickness, τre

decreases to 450 fs and f re increases to 350 GHz. This indicates that the bulk parasitics can

ρs

C SiV Si C oxV ox–=

C ox

d

dt -----V ox⋅ GSiV Si C Si

d

dt -----V Si⋅+=

V ox V Si+ V =

ρs C ox V et τre ⁄ –

1– ⋅ ⋅=

τre

C Si C ox+

GSi

------------------------εSi εox t Si t ox ⁄ ( )+

σSi

-------------------------------------------= =

f re1

2πτ re

-------------=



5.1. Theory and Simulation 99

be neglected for signals up to a couple hundred gigahertz. However, the thin lightly doped

epi layer causes the substrate effects to appear at much lower frequencies.

To verify the interfacial charge theory, a MOS structure is simulated using the Max-

well software. The metal width is 16 µm. The oxide and silicon substrate thickness is

1 µm and 500 µm, respectively. Three substrate resistivity values are simulated: 20, 0.1,

and 0.01 Ω-cm. The simulation results for the equivalent substrate parallel capacitance

(C p) and resistance ( R p) are plotted in Figure 5.2. Below 100 MHz, C p is equal to the

oxide layer capacitance. For the lightly doped case (20 ohm-cm), C p start to decreases as

frequency is increased above 300 MHz. This indicates that the electric field begins to pen-

etrate into the silicon substrate as the interfacial charge can no longer track the

high-frequency electric field.

The above analysis is incomplete because it only describes the behavior of the sub-

strate in response to a time-varying electric field. But it provides no information about the

potential magnetic coupling between the metal feature and the underlying silicon sub-

strate. The magnetic coupling is important for on-chip inductors. On-chip magnetic

parasitic effects are difficult to model analytically because the substrate behave as a vol-

ume ground plane with a finite conductivity. In order for the substrate to noticeablyinterfere with the time-varying magnetic field, the substrate must have sufficient carriers to

oppose the time-varying magnetic field in accordance to the Lenz’s Law. Recently, results

based on FASTHENRY simulation showed that even for heavily doped substrate with

doping concentration of 1019 cm-3 (resistivity ≈ 6 mΩ-cm), inductive coupling with the

substrate is negligible up to 20 GHz [78]. And for a lightly doped substrate with 1017 cm-3

doping (resistivity ≈ 0.1 Ω-cm), the frequency limit extends to as high as 100 GHz. Fur-

thermore, our experimental results on the solid polysilicon ground shield, as described in

Chapter 4, supports these simulations. This suggests that the substrate eddy current is

probably insignificant even for epi substrates. To verify this, a set of spiral inductors on

glass, lightly doped, and epi substrates are fabricated and measured. The results will be

presented in the next section.




Figure 5.2: Simulation results of (a) C p and (b) R p for a MOS structure with 16-µmwide metal on 1 µm thick oxide and 500 µm thick silicon.

(a)

(b)

0.01 0.10 1.00 10.00

Frequency (GHz)

1e-01

1e+01

1e+03

1e+05

1e+07

R p

( Ω / m )

20 Ω-cm

0.1 Ω-cm

0.01 Ω-cm

0.01 0.10 1.00 10.00

Frequency (GHz)

10-11

10-10

10-9

C p

( F / m )

20 Ω-cm

0.1 Ω-cm

0.01 Ω-cm



5.2. Experimental Results 101

5.2 Experimental Results

5.2.1 Bond Pads

To investigate capacitive substrate effects, bond pads are fabricated on epi, lightly doped,

and quartz (εr = 3.9) wafers. Description of the substrate profile under the pads are listed

in Table 5.1. S 11 are measured using an HP8720B Network Analyzer and coplanar

ground-signal-ground probe. During measurements, the wafer backsides are grounded

through the testing chuck. S 11 are converted to Y 11 from which pad capacitance (C pad),

resistance ( Rpad), and quality factor (Qpad) are extracted using the following relationships:

, (5.12)

, (5.13)

and

(5.14)

where ω is the angular frequency.

Table 5.1: Summary of 100 × 100 µm2 bond pads.

Pad Capacitanceat 175 MHz

Substrate Profile

Epi4.1µm 114.3 fF 4.1 µm oxide on epi on p

+

SiLd4.5µm 100.0 fF 4.5 µm oxide on 10 Ω-cm Si

Ld5.5µm 79.9 fF 5.5 µm oxide on 10 Ω-cm Si

Ld6.5µm 67.2 fF 6.5 µm oxide on 10 Ω-cm Si

Qz2.1µm 5.0 fF 2.1 µm oxide on quartz

C pad

Im Y 11[ ]ω

--------------------=

Rpad1

Re Y 11[ ]--------------------=

Qpad

Im Y 11[ ]

Re Y 11[ ]--------------------=

ω R pC p=




The frequency behavior of C pad and Rpad is plotted in Figure 5.3. C pad and Rpad are in par-

al lel with each other . In the quartz case, C pad is approximately 6 fF and is

frequency-independent since the electric field penetrates through the entire substrate. In

contrast, the silicon samples show strong frequency dependence. At low frequencies, C pad

is equal to the oxide capacitance. As frequency increases, C pad decreases and finally

approaches the high-frequency limit of CSi. The relaxation frequency, f re, is seen to range

from 300 to 600 MHz depending on the oxide thickness, which are consistent with the

predictions based on the interfacial charge theory. Above 1 GHz, C pad of the epi sample

begins to decrease from the oxide capacitance as the electric field penetrates into the epi

layer. C pad of the epi sample is larger than the lightly doped cases because the epi layer isonly 7 µm thick and the electric field is terminated at the interface of the epi layer and

bulk. Figure 5.3(b) shows that Rpad decreases with frequency indicating that there is more

energy loss to the substrate as frequency increases. The quartz sample has much higher

Rpad than the silicon samples because it does not support the flow of conductor current to

flow.

The quality factor of the pad capacitance, Qpad, is a measure of energy loss in the sub-

strate, that is high Q represents low loss. The measured results are plotted in Figure 5.4.The insulating quartz substrate has significantly higher Qpad compared to the semiconduct-

ing silicon substrates. Comparing the lightly doped substrates which have 4.5, 5.5, and

6.5-µm oxide, it shows that Qpad is larger with thicker oxide since the lossy silicon is fur-

ther away from the pad. On the other hand, Qpad on the epi substrate is the highest among

all the silicon samples even though it has the thinnest oxide (4.1 µm). This indicates that

epi substrate is much less lossy compared to lightly doped substrates. While it seems

counter-intuitive, this observation is actually consistent with the interfacial charge theory.

The p+ bulk behaves as a ground for the electric field up to a couple hundred gigahertz and

therefore dissipates little energy. Therefore, the electric field can only penetrate into the

resistive epi layer. Since the epitaxial layer is thin with typical thickness of 3−10 µm, the

lossy volume is considerably smaller than the lightly doped bulk substrates.




Figure 5.3: Frequency response of (a) C pad and (b) Rpad for metal pads on varioussubstrates (see Table 5.1).

(a)

(b)

0.1 1 10

Frequency (GHz)

0

20

40

60

80

100

120

140

C p a d = ( I m [ Y 1 1

] ) / ω

( f F )

Epi4.1µm

Ld4.5µm

Ld5.5µm

Ld6.5µm

Qz2.1µm

0.1 1 10

Frequency (GHz)

0.1

1

10

100

1000

R p a d = 1 / ( R e [ Y 1 1

] ) ( k Ω

)

Epi4.1µm

Ld4.5µm

Ld5.5µm

Ld6.5µm

Qz2.1µm




5.2.2 Spiral Inductors

Spiral inductors are fabricated on epi, lightly doped, and quartz wafers to investigate

potential inductive coupling with substrates. The quartz sample serves as a control since

no substrate eddy current can be induced in the dielectric. The inductor Gp8nH is fabri-

cated with a 0.32-Ω /sq. aluminum solid ground plane (SGP) underneath the spiral to

deliberately create the image current. By comparing the inductors on epi substrate to the

ones on quartz and SGP, one can evaluate the significance of the substrate eddy current.

Moreover, the GP sheet resistance is adjusted to be similar to that of the p

+

bulk for the episubstrate. This allows a direct measure of the magnetic interference caused by the p+ vol-

ume ground. Detailed descriptions of the inductors are summarized in Table 5.2 including

measured spiral inductance at 175 MHz and resistance at dc. For comparison purposes, the

inductors are designed to have similar L / R ratio of about 1.6. Inductance, parasitic resis-

Figure 5.4: Frequency response of Q for the metal pads.

0.1 1 10

Frequency (GHz)

1

10

Q p a d

30

Epi4.1µm

Ld4.5µm

Ld5.5µm

Ld6.5µm

Qz2.1µm




tances and capacitances, and Q are extracted from measured two-port S parameters using

the techniques described in Chapter 3.

Table 5.2: Summary of spiral inductors.

The measured series inductance and resistance are shown in Figure 5.5. Both the inter-

connect resistance and substrate resistance resulting from induced image current

contribute to the series resistance as discussed in Section 4.1.3. The same spiral layout and

metal thickness are used for Ld8nH, Gp8nH, and Qz8nH to produce equal interconnect

resistance. As shown in Figure 5.5, Ld8nH and Qz8nH have the same series inductance

and resistance indicating that the substrate resistance due to inductive coupling is insignif-

icant for the 19-Ω-cm lightly doped substrate. In contrast, Gp8nH exhibits much lower

inductance and higher resistance owing to the image current flowing in the SGP. For the

inductors on epi substrates, Epi5nH and Epi10nH manifest the same kind of inductance

and resistance frequency behavior as Ld8nH and Qz8nH, proving that inductive coupling

with the epi substrate is indeed insignificant up to 10 GHz. Although the p+ bulk has sheet

resistance close to that of the SGP in Gp8nH, it does not allow noticeable image currents

to be induced. This can be attributed to the fact that the carriers in the p + bulk are distrib-

uted over a much larger volume and hence are effectively much farther away from the

spiral.

Inductor Inductance at175 MHz

Resistanceat dc

Substrate Profile

Epi5nH 5.3 nH 3.0 Ω 4.1 µm oxide on epi on p+ Si

Epi10nH 10.5 nH 7.0 Ω 4.1 µm oxide on epi on p+ Si

Ld8nH 8.1 nH 5.0 Ω 5.6 µm oxide on 19 Ω-cm Si

Gp8nH 7.9 nH 5.0 Ω 5.2 µm oxide on ground plane

Qz8nH 7.9 nH 5.0 Ω 2.1 µm oxide on quartz




Figure 5.5: Measured results of (a) series inductance and (b) series resistance for theinductors listed in Table 5.2.

(a)

(b)

0.1 1 10

Frequency (GHz)

0

2

4

6

8

10

12

S e r i e s I n d u c t a n c e ( n H )

0.1 1 10

Frequency (GHz)

1

10

100

S e r i e s R e s i s t a n c e ( Ω )

Qz8nH

Ld8nHGp8nH

Epi5nH

Epi10nH

Qz8nH

Ld8nH

Gp8nH

Epi5nH

Epi10nH




In Figure 5.6, measured inductor Q are plotted. Qz8nH has the highest Q because it

has the lowest substrate loss and the smallest capacitance. Gp8nH has the worst Q due to

the severe inductive coupling which resulted in decrease in inductance and increase in

resistance. Epi5nH and Epi10nH have much lower self-resonant frequency (srf ) compared

to Ld8nH. This is because the epi substrate has a much larger substrate capacitance (C p).

To confirm this, Figure 5.7 shows that for the lightly doped substrate, at 1−2 GHz, C p

decreases to 30−40% of its low-frequency value whereas for the epi substrate, C p only

reduces to 65% of its low-frequency value.To understand the degradation mechanism for inductors on epi substrate, substrate loss

and self-resonance need to be considered (see Chapter 4). Figure 5.8 shows that Epi5nH

and Ld8nH have the same ω Ls / Rs. In Figure 5.9, it shows that the substrate loss factor is

also the same but the self-resonance factor for Epi5nH is considerably smaller than that

Figure 5.6: Frequency response of Q for the inductors.

0.1 1 10

Frequency (GHz)

1

10

Q

30

Qz8nH

Ld8nH

Gp8nH

Epi5nH

Epi10nH




Figure 5.7: Comparison of substrate parasitic capacitance for inductors on epi andlightly doped substrate.

0.1 1 10

Frequency (GHz)

0

0.2

0.4

0.6

0.8

1.0

C p

/ C p

a t 1 7 5 M H z

Ld8nH (Cp = 219.2 fF at 175 MHz)

Epi5nH (Cp = 445.6 fF at 175 MHz)

Figure 5.8: ω Ls / Rs for Epi5nH and Ld8nH.

0.1 1 10

Frequency (GHz)

1

10

ω L s / R s

Ld8nH

Epi5nH




Figure 5.9: Substrate loss and self-resonance factors for Epi5nH and Ld8nH.

(a)

(b)

0.1 1 10

Frequency (GHz)

0

0.2

0.4

0.6

0.8

1.0

S u b s t r a t e L o s s F a c t o r

0.1 1 10

Frequency (GHz)

0

0.2

0.4

0.6

0.8

1.0

S e l f - r e s o n a n c e F a c t o

r

Ld8nH

Epi5nH

Ld8nH

Epi5nH




for Ld8nH. This is an important observation because it proves that inductors on epi sub-

strate have lower Q at high frequencies than on the lightly doped substrate not because of

substrate eddy current, but rather due to the larger epi parasitic capacitance. Although sub-

strate loss due to magnetic coupling is insignificant, loss in the epi layer caused by electric

field penetration is present. However, the electric loss can easily be eliminated by using

the patterned ground shield.

To confirm this, Epi5nH is fabricated with a patterned ground shield as described in

Chapter 4. It was shown that polysilicon PGS offers the most improvement. In this experi-

ment, PGS’s implemented using gate polysilicon and source/drain p+ diffusion layers are

fabricated in a standard 0.5-µm CMOS process. As shown in Figure 5.10, the inductor Q

is improved by about 15% with both polysilicon and p+ diffusion PGS. As suggested in

[34], another technique for evaluating the inductor quality is by measuring the inductor

impedance near srf and taking the ratio of srf to −3-dB bandwidth. This technique essen-

Figure 5.10: Frequency response of Q for Epi5nH with and without PGS. Diffusionand polysilicon PGS are considered.


0

2

4

6

8

Q

Epi5nH

Epi5nH (Diff. PGS)

Epi5nH (Poly. PGS)




entire bulk for lightly doped substrates but only in the epi layer for epi substrates. It is

shown that epi substrates have larger substrate capacitances then the lightly doped sub-

strates as the electric field penetration is confined to the thin epi layer. For spiral inductors,

substrate eddy currents are proven to be negligible even in epi substrates. It is shown that

the high-frequency roll-off of Q for inductors on epi substrates is caused by self-reso-

nance. Furthermore, the substrate loss is only due to electric coupling. As a result, the PGS

is equally effective on epi substrates and is able to improve inductor Q by 15% and the res-

onator Q by a factor of 4. Moreover, measured results also show that a p+ diffusion layer is

as effective as a polysilicon layer for implementing PGS. However, the effectiveness of the

p+ diffusion layer in reducing substrate coupling is yet to be evaluated.

Figure 5.12: Substrate parasitic capacitance of Epi5nH with and without PGS.Diffusion and polysilicon PGS are considered.

0.1 1.0 10.0

Frequency (GHz)

0

100

200

300

400

500

C p

( f F )

Epi5nH

Epi5nH (Diff. PGS)

Epi5nH (Poly. PGS)



113

Chapter

6 Conclusions

6.1 Summary

The wireless communication market has experienced tremendous growth in recent years.

It is projected to expand at an even faster pace during the next decade with new spectrum

allocated for increasing applications. Portable electronic appliances will become an inte-

gral part of the overall communication infrastructure in the 21st century. The low-power,

low-cost, and small-form-factor requirements for future radio-frequency (RF) systems

continue to motivate innovations at the levels of system, circuit, device, and fabrication.

One of the characteristics of RF systems is the relatively large ratio of passive components

to active devices. In particular, inductors are indispensable to achieve many RF circuit

functions and are especially important for low power operation. For low cost production, it

is advantageous to utilize the ever-improving high-volume silicon integrated circuit (IC)

technologies to implement as many circuit functions as possible. Therefore, it is desirable

to integrate inductors and other passive elements on chip for the next generation RF sys-

tems. In addition, reducing the number of off-chip passive components can significantly

reduce the printed circuit broad area, which leads to smaller form factor for the final

product.

In Chapter 2, different approaches for inductor integration are studied. It was shown

that active inductors are impractical due to the extra power consumption, inferior noise

properties, and limited dynamic range. Bond wire inductors offer high Q, but their induc-

tance are difficult to predict and control due to the wire curvature. Moreover, bond wire

inductors have large unwanted mutual coupling and poor matching properties. The attain-



114 Chapter 6: Conclusions

able inductance is limited by the chip size. Spiral inductors are the most practical and

common choice for RF IC’s.

The most challenging problem associated with on-chip inductor is modeling and char-

acterization. Chapter 3 presented a physical model which accounts for the important

parasitic effects in an on-chip inductor. Using this model, the impact of technology and

layout parameters on inductor performance are addressed. Contour plots of Q are pre-

sented as an effective design tool for optimizing inductor layout.

Patterned ground shields (PGS) are introduced in Chapter 4 to eliminate substrate loss

due to the electric field penetration into the silicon substrate at high frequencies. The fun-

damental definitions of inductor Q and resonator Q are elucidated. The design criteria for

PGS are explained in detail. The improvement in Q and substrate noise coupling are

presented.

Based on experimental and simulation results, Chapter 5 presented a study of the sub-

strate effects on RF passive components with an emphasis on spiral inductors. The results

show that lightly doped substrates are actually more lossy than epi substrates. This is

counter-intuitive to the general belief that higher substrate conductivity mean more loss

and lower Q. The analysis also demonstrates that epi substrates have significantly greater

substrate parasitic capacitance in comparison to lightly doped substrates. Substrate eddy

currents induced by an on-chip inductor is proven to be negligible even in epi substrates.

The effectiveness of patterned ground shields for inductors on epi substrate is established

with measured data.

6.2 Future Work

6.2.1 Improvement in Q

Today’s multi-level interconnect technology typically has three to four layers of 0.5−1 µm

thick metal and a total oxide thickness of about 4−5 µm. Therefore, inductor Q is often

limited to 10. Such performance level is adequate for many RF functions. However, for



6.2. Future Work 115

circuits such as narrow-band bandpass filters and low-phase-noise voltage-controlled

oscillators, inductor Q in the range of 50−100 is needed. One approach to attain high Q

values is to use thick metals and dielectrics on the orders of tens and hundreds of

micro-meters. These layers can be added on top of the finished standard wafers through

post-processing steps similar to those described in [38]. The key challenges include yield,

thermal budget, and processing cost. New materials and processing techniques maybe

required to fulfill these stringent requirements. Due to the large potential improvement,

active research are being conducted in this area [79].

6.2.2 On-Chip Transformers and Baluns

Transformers are often used in RF designs for impedance matching and other functions

[80][81]. Balanced-to-unbalanced’s, or “baluns” are useful for conversion between differ-

ential and single-ended signals [80][82]. In order for transformers and baluns to become

standard IC components, they must have accurate models. The physical inductor model

developed in this work can be expanded into transformer and balun models. Since the

physical phenomena such as skin effects, mutual coupling, substrate loss, and self-reso-

nance are common to inductors, transformers, and baluns, only a few modifications arerequired to convert the inductor model into a transformer or balun model. However, vali-

dation and optimization of the new models will demand more effort in terms of layout

design and parameter extraction technique. Moreover, on-chip inductive components will

continue to benefit from the usage of patterned ground shields.

6.2.3 On-Chip Tunable Bandpass Filters

High-Q tunable bandpass filters are useful building blocks in a RF front-end system [13].These filters have traditionally been realized off-chip using dielectric resonators and sur-

face-acoustic-wave devices. With high-Q inductor using advanced processing technology

or novel circuit techniques [83] and new devices such as the accumulation-mode MOS

varactors [84], on-chip tunable bandpass filters can potentially replace the bulky off-chip

parts in a highly integrated RF system.



116 Chapter 6: Conclusions



117

Bibliography

[1] P.R. Gray and R.G. Meyer, “Future directions in silicon ICs for RF personalcommunications,” in Proceedings of the IEEE 1995 Custom Integrated Circuits

Conference, pp. 83−90, May 1995.

[2] L.E. Larson, “Integrated circuit technology options for RFIC’s − present status andfuture directions,” IEEE Journal of Solid-State Circuits, vol. 33, no. 3,pp. 387−399, March 1998.

[3] T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, New York,New York: Cambridge University Press, 1998.

[4] N.M. Nguyen and R.G. Meyer, “A silicon bipolar monolithic RF bandpassamplifier,” IEEE Journal of Solid-State Circuits, vol. 27, no. 1, pp. 123−127,January 1992.

[5] D.K. Shaeffer and T.H. Lee, “A 1.5 V, 1.5 GHz CMOS low noise amplifier,” IEEE

Journal of Solid-State Circuits, vol. 32, no. 5, pp. 745−759, May 1997.

[6] Y. Imai, M. Tokumitsu, and A. Minakawa, “Design and performance of low-current GaAs MMIC’s for L-band front-end applications,” IEEE Transactions

on Microwave Theory and Techniques, vol. 39, no. 2, pp. 209−215, February 1991.

[7] R.G. Meyer and W.D. Mack, “A 1-GHz BiCMOS RF front-end IC,” IEEE Journal

of Solid-State Circuits, vol. 29, no. 3, pp. 350−355, March 1994.



118 Bibliography

[8] A.R. Shahani, D.K. Shaeffer and T.H. Lee, “A 1A 12-mW wide dynamic rangeCMOS frond-end for a portable GPS receiver,” IEEE Journal of Solid-State

Circuits, vol. 32, no. 12, pp. 2061−2070, December 1997.

[9] D.K. Shaeffer et al., “A 115 mW CMOS GPS Receiver,” in 1998 International

Solid-State Circuits Conference Digest of Technical Papers, pp. 122−123,February 1998.

[10] R.G. Meyer, W.D. Mack, and J.J.E.M. Hagreraats “A 2.5-GHz BiCMOStransceiver for wireless LAN’s,” IEEE Journal of Solid-State Circuits, vol. 32,no. 12, pp. 2097−2104, December 1997.

[11] N.M. Nguyen and R.G. Meyer, “Si IC-compatible inductors and LC passivefilters,” IEEE Journal of Solid-State Circuits, vol. 25, no. 4, pp. 1028−1030,

August 1990.

[12] K.B. Ashby, I.A. Koullias, W.C. Finley, J.J. Bastek, and S. Moinian, “High Q

inductors for wireless applications in a complementary silicon bipolar process,” IEEE Journal of Solid-State Circuits, vol. 31, no. 1, pp. 4−9, January 1996.

[13] S. Popolos, Y.P. Tsividis, J. Fenk, and Y. Papananos, “A Si 1.8 GHz RLC filter withtunable center frequency and quality factor,” IEEE Journal of Solid-State Circuits,vol. 31, no. 10, pp. 1517−1525, October 1996.

[14] J. Macedo, M.A. Copeland and P. Schvan, “A 1.9 GHz silicon receiver withon-chip image filtering,” in Proceedings of the IEEE 1997 Custom Integrated

Circuits Conference, pp. 181−184, May 1997.

[15] N.M. Nguyen and R.G. Meyer, “A 1.8-GHz monolithic LC voltage-controlledoscillator,” IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 444−450,March 1992.

[16] J. Craninckx and M.S.J. Steyaert, “A 1.8-GHz low-phase-noise CMOS VCO usingoptimized hollow spiral inductors,” IEEE Journal of Solid-State Circuits, vol. 32,no. 5, pp. 736−744, May 1997.

[17] T. Yamaguchi et al., “Process and device characterization for a 30-GHz f T

submicrometer double poly-Si bipolar technology using BF2-implanted base withrapid thermal process,” IEEE Transactions on Electron Devices, vol. 40, no. 8,pp. 1484−11495, August 1993.

[18] K. O et al., “A low cost and low power silicon npn bipolar process with NMOStransistors (ADRF) for RF and microwave applications,” IEEE Transactions on

Electron Devices, vol. 42, no. 10, pp. 1831−1840, March 1995.



Bibliography 119

[19] L. Su et al., “A high-performance 0.08 µm CMOS,” in 1996 Symposium on VLSI

Technology Technical Digest , pp. 12−13, June 1996.

[20] T.C. Holloway et al., “0.18 µm CMOS Technology for high-performance,low-power, and RF applications,” in 1997 Symposium on VLSI Technology

Technical Digest , pp. 12−13, June 1997.

[21] M. Saito et al., “0.15-µm RF CMOS technology compatible with logic CMOS forlow-voltage operation,” IEEE Transactions on Electron Devices, vol. 45, no. 3,pp. 737−742, March 1998.

[22] RF Inductors, Power Magnetics, Filters, Coilcraft Inc., 1997.(http://www.coilcraft.com)

[23] Chip Inductor , Delta Products Corporation, 1997.(http://www.deltaca.com)

[24] Accu-L SMD High-Q RF Inductor , AVX Corporation, 1997.(http://www.avxcorp.com)

[25] R. Sennani and R.N. Tiwari, “New canonic active RC realizations of grounded andfloating inductors,” Proceedings of The IEEE , vol. 66, no. 7, pp. 803−804, July1978.

[26] G.F. Zhang and J.L. Gautier, “Broad-band, lossless monolithic microwave activefloating inductor,” IEEE Microwave and guided Wave Letters, vol. 3, no. 4,

pp. 98−100, April 1993.

[27] Y.-H. Cho, S.-C. Hong, Y.-S. Kwon, “A novel active inductor and its application toinductance-controlled oscillator,” IEEE Transactions on Microwave Theory and

Techniques, vol. 45, no. 8, pp. 1208−1213, August 1997.

[28] M.S.J. Steyaert and J. Craninckx, “1.1 GHz oscillator using bondwire inductance,” Electronics Letters, vol. 30, no. 3, pp. 244−245, February 1994.

[29] J. Craninckx and M.S.J. Steyaert, “A 1.8-GHz CMOS low-phase-noisevoltage-controlled oscillator with prescaler,” IEEE Journal of Solid-State Circuits,

vol. 30, no. 12, pp. 1474−1482, December 1995.

[30] F.W. Grover, Inductance Calculations, Princeton, New Jersey: Van Nostrand,1946. Reprinted by New York, New York: Dover Publications, 1962.

[31] S. Ramo, J.R. Whinnery, T. Van Duzer, Fields and Waves in CommunicationElectronics, New York: John Wiley & Sons, 1994.



120 Bibliography

[32] K. Kawabe, H. Koyama, and K. Shirae, “Planar inductor,” IEEE Transactions on

Magnetics, vol. MAG-20, no. 5, pp. 1804−1806, September 1984.

[33] S. Chaki et al., “Experimental study on spiral inductors,” in 1995 IEEE MTT-S International Microwave Symposium Digest , pp. 753−756, June 1995.

[34] R.B. Merrill, T.W. Lee, H. You, R. Rasmussen, L.A. Moberly, “Optimization of high Q integrated inductors in mutli-level metal CMOS,” in 1995 International

Electron Devices Meeting Technical Digest , pp. 983−986, December 1995.

[35] J.N. Burghartz, M. Soyuer, and K.A. Jenkins, “Integrated RF and microwavecomponents in BiCMOS technology,” IEEE Transactions on Electron Devices,vol. 43, no. 9, pp. 1559−1570, September 1996.

[36] J.N. Burghartz, et al., “Integrated RF components in a SiGe bipolar technology,” IEEE Journal of Solid-State Circuits, vol. 32, no. 9, pp. 1440−1445, September1997.

[37] R. Groves, D.L. Harame, and D. Jadus, “Temperature dependence of Q andinductance in spiral inductors fabricated in a silicon-germanium/BiCMOStechnology,” IEEE Journal of Solid-State Circuits, vol. 32, no. 9, pp. 1455−1459,September 1997.

[38] B.-K. Kim et al., “Monolithic planar RF inductor and waveguide structures onsilicon with performance comparable to those in GaAs MMIC,” n 1995

International Electron Devices Meeting Technical Digest , pp. 717−720, December1995.

[39] A.C. Reyes et al., “Coplanar waveguides and microwave inductors on siliconsubstrates,” IEEE Transactions on Microwave Theory and Techniques, vol. 43,no. 9, pp. 2061−2021, September 1995.

[40] M. Park, C.S. Kim, J.M. Park, H.K. Yu, K.S. Nam, “High Q microwave inductorsin CMOS double-metal technology,” in 1997 International Electron Devices

Meeting Technical Digest , pp. 59−62, December 1997.

[41] J.R. Long and M.A. Copeland, “The modeling, characterization, and design of

monolithic inductors for silicon RF IC’s,” Journal of Solid-State Circuits, vol. 32,no. 3, pp. 357−369, March 1997.

[42] A.M. Niknejad and R.G. Meyer, “Analysis and optimization of monolithicinductors and transformers for RF ICs,” in Proceedings of the IEEE 1997 Custom

Integrated Circuits Conference, pp. 375−378, May 1997.



Bibliography 121

[43] J. Crols, P. Kinget, J. Craninckx, and M.S.J. Steyaert, “An analytical model of planar inductors on lowly doped silicon substrates for high frequency analogdesign up to 3 GHz,” in 1996 Symposium on VLSI Circuits Digest of Technical

Papers, pp. 28−29, June 1996.

[44] D. Lovelace, N. Camilleri, and G. Kannell, “Silicon MMIC inductor modeling forhigh volume, low cost applications,” Microwave Journal, pp. 60-71, August 1994.

[45] E. Pettenpaul et al., “CAD models of lumped elements on GaAs up to 18 GHz,” IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 2,pp. 294−304, February 1988.

[46] P.R. Shepherd, “Analysis of square-spiral inductors for use in MMIC’s,” IEEE

Transactions on Microwave Theory and Techniques, vol. MTT-34, no. 4,

pp. 467−472, April 1986.

[47] D. Cahana, “A new transmission line approach for designing spiral microstripinductors for microwave integrated circuits,” in 1983 IEEE MTT-S International

Microwave Symposium Digest , pp. 245−247, 1983.

[48] C.P. Yue, C. Ryu, J. Lau, T.H. Lee, and S.S. Wong, “A physical model for planarspiral inductors on silicon,” in 1996 International Electron Devices Meeting

Technical Digest , pp. 155−158, December 1996.

[49] H.M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE

Transactions on Parts, Hybrids, and Packing, vol. PHP-10, no. 2, pp. 101−109,June 1974.

[50] F.E. Terman, Radio Engineering Handbook , New York: McGraw-Hill, 1943.

[51] H.E. Bryan, “Printed inductors and capacitors,” Tele-Tech & Electronic Industries,pp. 68, December 1955.

[52] H.A. Wheeler, “Formulas for the skin effect,” Proceedings of I.R.E., vol. 30,pp. 412−424, September 1942.

[53] J.A. Tegopoulos, E.E. Kriezis, Eddy Currents in Linear Conducting Media, New

York, New York: Elsevier Science Pub. Co., 1985.

[54] Maxwell 2D Parameter Extractor User’s Reference, Ansoft Corporation, 1997.

[55] R.A. Pucel, D.J. Massé, and C.P. Hartwig, “Losses in microstrip,” IEEE

Transactions on Microwave Theory and Techniques, vol. 16, no. 6, pp. 342−350,June 1968.



122 Bibliography

[56] R. Faraji-Dana and Y.L. Chow, “The current distribution and ac resistance of amicrostrip structure,” IEEE Transactions on Microwave Theory and Techniques,vol. 38, no. 9, pp. 1268−1277, September 1990.

[57] Y. Eo and W.R. Eisenstadt, “High-speed VLSI interconnect modeling based onS -parameter measurements,” IEEE Transactions on Components, Hybrids, and

Manufacturing Technology, vol. 16, no. 5, pp. 555−562, August 1993.

[58] R.H. Jansen et al., “Theoretical and experimental broadband characterization of multiturn square spiral inductors in sandwich type GaAs MMIC,” in Proceedings

of 15th European Microwave Conference, pp. 946−951, 1985.

[59] L. Wiemer and R.H. Jansen, “Determination of coupling capacitance of underpasses, air bridges and crossings in MICs and MMICs,” Electronics Letters,

vol. 23, no. 7, pp. 344−346, March 1987.

[60] I.T. Ho and S.K. Mullick, “Analysis of transmission lines on integrated-circuitchips,” IEEE Journal of Solid-State Circuits, vol. SC-2, no. 4, pp. 201−208,December 1967.

[61] H. Hasegawa, M. Furukawa, and H. Yanai, “Properties of microstrip line onSi-SiO2 system,” IEEE Transactions on Microwave Theory and Techniques,vol. MTT-19, no. 11, pp. 869−881, November 1971.

[62] G.W. Hughes and R.M. White, “Microwave properties of nonlinear MIS andSchottky-barrier microstrip,” IEEE Transactions on Electron Devices, vol. ED-22,no. 10, pp. 945−955, October 1975.

[63] J.-S. Yuan, W.R. Eisenstadt, and J.J. Liou, “A novel lossy and dispersiveinterconnect model for integrated circuit simulation,” IEEE Transactions on

Components, Hybrids, and Manufacturing Technology, vol. 13, no. 2,pp. 275−280, June 1990.

[64] On-wafer measurements using the HP 8510 network analyzer and CascadeMicrotech wafer probes, Hewlett Packard Product Note 8510-6, 1986.

[65] Cascade Series 1000-2000 Manual, Cascade Microtech.

[66] P.J. van Wijnen, H.R. Claessen, and E.A. Wolsheimer, “A new straightforwardcalibration and correction procedure for ‘on wafer’ high frequency S-parametermeasurements (45 MHz−18 GHz),” in Proceedings of the IEEE 1987 Bipolar

Circuits and Technology Meeting, pp. 70−73, September 1987.

[67] Layout Rules for GHz-Probing, Cascade Microtech application note, 1988.



Bibliography 123

[68] H. Cho and D.E. Burk, “A three-step method for the de-embedding of high-frequency S-parameter measurements,” IEEE Transactions on Electron

Devices, vol. 38, no. 6, pp. 1371−1375, June 1991.

[69] M. Pfost, H.-M. Rein, and T. Holzwarth, “Modeling substrate effects in the designof high speed Si-bipolar IC’s,” IEEE Journal of Solid-State Circuits, vol. 31,no. 10, pp. 1493−1501, October 1996.

[70] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substrate crosstalk reduction using SOI technology,” IEEE Transactions on Electron Devices, vol. 44,no. 12, pp. 2252−2261, December 1997.

[71] J.Y.-C. Chang, A.A. Abidi, and M. Gaitan, “Large suspended inductors on siliconand their use in a 2-µm CMOS RF amplifier,” IEEE Electron Device Letters,

vol. 14, no. 5, pp. 246−248, May 1993.

[72] H.G. Booker, Energy in Electromagnetism, London, New York: Peter Peregrinuson behalf of the Institution of Electrical Engineers, 1982.

[73] A. Rofougaran, J.Y.-C. Chang, M. Rofougaran, A.A. Abidi, “A 1 GHz CMOS RFfront-end IC for a direct-conversion wireless receiver,” IEEE Journal of Solid-State

Circuits, vol. 31, no. 7, pp. 880−889, July 1996.

[74] T. Tsukahara and M. Ishikawa, “A 2 GHz 60 dB dynamic-range Silogarithmic/limiting amplifier with low-phase deviations.” International

Solid-State Circuits Conference Digest of Technical Papers, pp. 82−83, February1997.

[75] P.H. Young, Electronic Communication Techniques, Englewood Cliffs, NewJersey: Macmillan Publishing Company, 1994.

[76] C.P. Yue and S.S. Wong, “On-chip spiral inductors with patterned ground shieldsfor Si-based RF IC’s,” IEEE Journal of Solid-State Circuits, vol. 33, no. 5,pp.743−752, May 1998.

[77] R. Plonsey and R.E. Collin, Principles and Applications of Electromagnetic Fields,New York: McGraw-Hill, 1961, pp.177−183.

[78] Y. Massoud and J. White, “Simulation and modeling of the effect of substrateconductivity on coupling inductance,” in 1995 International Electron Devices

Meeting Technical Digest , pp. 491−494, December 1995.



124 Bibliography

[79] D.J. Young, V. Malba, J.-J. Ou, A.F. Bernhardt, and B.E. Boser, “Monolithichigh-performance three-dimensional coil inductors for wireless communicationapplications,” in 1997 International Electron Devices Meeting Technical Digest ,

pp. 67−70, December 1997.

[80] J.R. Long and M.A. Copeland, “A 1.9 GHz low-voltage silicon bipolar receiverfront-end for wireless personal communication systems,” IEEE Journal of

Solid-State Circuits, vol. 30, no. 12, pp. 1438−1448, December 1995.

[81] J.-J. Zhou and D.J. Allstot, “A fully integrated CMOS 900MHz LNA utilizingmonolithic transformers,” in 1998 International Solid-State Circuits Conference

Digest of Technical Papers, pp. 132−133, February 1998.

[82] R.H. Jansen, J.Jotzo, and M. Engels, “Improved compaction of multilayer

MMIC/MCM baluns using lumped element compensation,” in 1997 IEEE MTT-S International Microwave Symposium Digest , pp. 277−280, June 1997.

[83] D.R. Pehlke, A. Burstein, M.F. Chang, “Extremely high-Q tunable inductor forsilicon-based RF integrated circuit applications,” in 1997 International Electron

Devices Meeting Technical Digest , pp. 63−66, December 1997.

[84] T. Soorapanth, C.P. Yue, D.K. Shaeffer, T.H. Lee, and S.S. Wong, “Analysis andoptimization of accumulation-mode varactor for RF ICs,” in 1998 Symposium on

VLSI Circuits Digest of Technical Papers, June 1998.

inductor on chips

Documents