infiniband trade association

InfiniBandTM Architecture

Specification Volume 2

Release 1.1

Errata

Copyright © 2003 by InfiniBandSM Trade Association.All rights reserved.

August, 2003Draft

InfiniBandTM Architecture Release 1.1 August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA

InfiniBandSM Trade Association Proprietary and Confidential

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LEGAL DISCLAIMER "This IBTA document is provided "AS IS" and withoutany warranty of any kind, including, without limita-tion, any express or implied warranty of non-infringe-ment, merchantability or fitness for a particularpurpose.

In no event shall IBTA or any member of IBTA be liablefor any direct, indirect, special, exemplary, punitive,or consequential damages, including, without limita-tion, lost profits, even if advised of the possibility ofsuch damages."

Table 1 Revision History

Revision Release Date

1.1a 8/xx/2003 Errata to Release 1.1

InfiniBandTM Architecture Release 1.1 Chapter 1: Introduction Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA

InfiniBandSM Trade Association Page 1 Proprietary and Confidential

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CHAPTER 1: INTRODUCTION ERRATA

Page: 29 Line: 19 Section: 1.2 Ref: xxxx

Replace Original Text none

With New Text [26] IEEE Standard 181-2003

InfiniBandTM Architecture Release 1.1 Chapter 2: Glossary Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 2: GLOSSARY ERRATA

Page: 46 Line: 13 Section: 2 Ref: 3729

Replace Original Text None

With New Text Symbol Clock - the transmit time for 1 symbol. With 8b/10b encoding, a symbolis 10 bits long; thus, a symbol clok is 10*UI (eg. For 2.5Gb/s signaling, thesymbol clock time is 4ns).

InfiniBandTM Architecture Release 1.1 Chapter 3: Physical Overview Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 3: PHYSICAL OVERVIEW ERRATA

no errata

InfiniBandTM Architecture Release 1.1 Chapter 4: Port Signal Definition Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 4: PORT SIGNAL DEFINITION ERRATA

no errata

InfiniBandTM Architecture Release 1.1 Chapter 5: Link/Phy Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 5: LINK/PHY ERRATA

Page: 106 Line: 4 Section: 5.6.3 Ref: 3533

Replace Original Text In Figure 15: LinkErrorRecover

With New Text LinkPhyRecover


Replace Original Text In Figure 16: LinkErrorRecover

With New Text LinkPhyRecover

Page: 128 Line: 40-41 Section: 5 Ref: 3785

Replace Original Text The received TS1 status is valid only when the RxCMD is WaitTS1.

With New Text The received TS1 status is valid at any time TS1 is received.


Replace Original Text The received TS2 status is valid only when the RxCMD is WaitTS2.

With New Text The received TS2 status is valid at any time TS2 is received.

InfiniBandTM Architecture Release 1.1 Chapter 6: High Speed Electrical Signaling Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 6: HIGH SPEED ELECTRICAL SIGNALING ERRATA


Replace Original Text none

With New Text Additional information is available from the IEEE (I&M) subcommittee on Pulsemeasurement Techniques (SCOPT). Methods of performing pulse amplitudeand parametric measurements should be conducted in accordance to IEEE Std.181-2003, and this will be referenced explicitly throughout this chapter.

Page: 139 Line: 33 Section: 6.2.1 Ref: xxxx

Replace Original Text ie

With New Text i.e.


Replace Original Text Replace Table 16

With New Text Table 16 below. Changes are noted

Table 16 Driver Characteristics

Symbol Parameter Maximum Minimum Units Notes

VCM Common Mode Voltage

note 12

1.0 0.50 V (Vhigh+Vlow)/2

The common mode is unde-fined if DC blocking capaci-tors are used.

Vdiff Differential output (note 4) 1.6 1.0 V Peak-Peak differential volt-age. 100 ohm differentialload

Differential unsigned wave-form amplitude into 100 ohmdifferential load Note13,14,15

Vdisable Disabled Mode output (note5)

1.6 0 V The output in disabled or qui-escent state may be zerovolts differential.

Vstandby Standby Mode output

(note 5)

1.6 0 V

tDRF Driver Rise/Fall TransitionTime

100 ps at 20-80% at the packagepins into 100 ohm load

IACCM AC Common Mode current

(note 3, note 6)

(RMS Voltage)

5 uA Determined by EMI restric-tions and shielding effective-ness.

30 MHz to 6.25 GHz



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1. At the InfiniBand connector pins from 100 MHz to 1.875 GHz.2. A transmitter which implements pre emphasis shall meet the receiver mask with theminimum and maximum allowable interconnect configuration.3. The AC common mode voltage is limited in order to control radiated EMI. Some causes

VACCM AC Common Mode Voltage

(Note 3, Note 6, Note 7)

25 mV RMS

ZD Differential Output Imped-ance

(note 1)

125 75 Ω differential mode

Note 11.

ZSE Single Ended OutputImpedance

(note 1)

75 30 Ω Single ended, either output,current -15 to 15 ma, driveractive both pins driven.

Note 11

ZSEDC Single Ended OutputImpedance--Low Fre-quency

Note 10, Note 12

10,000 30 Ω Single ended, either output,current -15 to 15 ma, driveractive both pins driven.

Note 11

ZMSE Single Ended OutputImpedance Matching withina single lane (note 1)

10 per-cent.

The output impedance of theplus and minus outputs of thedifferential driver shall matchwithin 10%.

Note 11

IDShort Short Circuit Current 100 -100 mA To any voltage between 1.6and ground, power on or off.

SDBtB Skew 500 ps between any two physicallanes within a single transmit-ter.

JD1 Deterministic Jitter

(note 2,note 8)

.17 UI Without pre-emphasis

Port Type 1

JT1 Total Jitter

(note 8)

.35 UI At +/- 7σ

JD2 Deterministic Jitter

(note 8, 9)

0.09 UI Without pre-emphasis

Port Type 2

JT2 Total Jitter

(note 8, 9)

0.24 UI At +/- 7σPort Type 2

UID Unit Interval 400.04 400

399.96

ps Plus/Minus 100 ppm.

Plus/Minus 100 ppm mea-sured over a minimum of10E4 UI’s.

Table 16 Driver Characteristics

Symbol Parameter Maximum Minimum Units Notes



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of AC common mode are skew between the true and complement outputs of thedifferential driver, mismatched levels between the true and complement outputs of thedifferential driver, and power supply or ground noise such as that caused by switchingactivity being conducted through the driver.4. The output level is increased above the minimum required by the specified backplaneattenuation to allow for cable attenuation as well as provide headroom for noise. Also notethat this is a peak to peak voltage. The actual maximum differential amplitude is half thisvalue. Peak-Peak voltage=2(Vhigh-Vlow). Amplitude is measured for the first bit in a run ifa Backplane port, for all bits of a Cable Port.5. Chapter 5: Link/Phy Interface defines states in which the transmitter is quiescent. Inthese states driving node is inactive and there are no transitions on the link. Driver outputsshall be static in these states.6. Common mode current is measured on an IB cable assembly using a detectorbandwidth of 120 kHz below 1 GHz and 1MHz above 1 GHz. All physical lanes shall betransmitting the idle pseudo-random character sequence.7. Since cable shield effectiveness is in excess of 40 dB and common mode impedance isapproximately 50 ohms, driver common mode voltage of 25 mV is specified8. Jitter is measured as defined in IBTA CIWG Test Specification. At the currentspecification level the only patterns that the transmitter can be easily caused to emit areTS1, TS2, or pseudo random idle data. In the future, facilities for test and verification maybe architected and required.9. Port Type 2.10. DC to 100 MHz11. Driver impedences selected to adequately absorb reflections and other noise withoutrequiring the expense and complication of resistor calibration circuitry. ContemporaryProcessing can build resistors with 20 percent tolerance and 5 percent tracking. Trackingin the single ended impedance is necessary to minimize common mode to differentialconversion.12. In the absence of DC blocking capacitors. Undefined if DC blocking capacitorspresent.

13. Refer to IEEE Std.181-2003 for definitions and procedures around un-signedwaveform amplitude measurements. (amplitude unsigned.)14. Waveform amplitude measurements shall be conducted only on consecutive transitionbits, over a 2UI Epoch (IEEE Std. 181-2003) unit interval, to a minimum population of 10E4UI’s. This test should apply to any unsigned consecutive transition bit in the test pattern.15: Top and Base level calculations should be determined based on the histogram meantechnique as described in IEEE Std. 181--2003 (Determining State Levels from theHistogram).



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Replace Original Text Replace Table 17

With New Text Table 17 below. Changes are noted

Table 17 Receiver Input Characteristics

Symbol Parameter Maximum Minimum Units Conditions or Remarks

JDR Deterministic Jitter atReceiver

.47 UI Port Type 1

JTR Total Jitter at Receiver .65 UI at 10-12 BER

JDRPD Deterministic Jitter atReceiver

.41 UI Port Type 2

JTRPD Total Jitter at Receiver

1X Pluggable Device

.71 UI at 10-12 BER

Port Type 2

ZRTerm Termination 62.5 40 Ω To Vtt (differential impedanceis double) See Figure 24.

Vtt Termination Voltage

Note 3, Note 6

1.0 0.5 V See Figure 24

ZMRTerm Termination Matching withinphysical lane

5% -5% The plus and minus rails ofthe signal are each termi-nated to Vtt and must bematched to avoid commonmode to differential conver-sion. note 4.

Measured at IB connectorpins.

ZVtt Vtt Impedance 30 0 Ω note 4.

ZVtt Vtt Impedance

Note 6

10,000 0 Ω Note 5

Use of large values canreduce excess power causedby Vcm conflicts betweendriver and receiver.

LDR Differential Return Loss 10 dB note 4.

LCMR Common Mode ReturnLoss

6 dB note 4



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1. Signals meeting the InfiniBand input eye specification shall be received with amaximum bit error rate of 1*10-12

2. Signals having p-p an un-signed differential amplitude less than VRSD shall be ignored.Signals having p-p an un-signed differential amplitude greater than VRSD and less thanVRSense may be ignored.3. Unless DC blocking capacitors are present between the termination and the InfiniBandmodule pins.4. Over a frequency range of 100 MHz to 1.875 GHz.5. Frequency from DC to 100 MHz6. In the absence of DC blocking capacitors. Undefined if DC blocking capacitors present.7. Refer to IEEE Std.181-2003 (Amplitude, Waveform, Unsigned) for definitions andmeasurement procedures.8. Waveform amplitude measurement’s shall be conducted only on consecutive transitionbits, over a 2UI Epoch (IEEE Std. 181-2003), over a minimum population of 10E3 UI’s.This test should apply to any unsigned consecutive transition bit in the testpattern.

9: Top and Base level calculation should be determined based on the histogram mean

VRSense Input Sensitivity

(peak-peak)

175 mV Minimum differential inputamplitude p-p note 1.

Minimum differentialunsigned waveform ampli-tude. note 1,7,8

See Figure 24 on page 150

VRSD Signal Threshold

(peak-peak)

85 mV note 2.

note 2,7,8

See Figure 24 on page 150

Vrmax Maximum Input Voltage

(peak-peak)

1.6 V Maximum differential voltagepeak-peakunsigned wave-form amplitude

note 7,8,9

VRCM Common Mode Voltage

Note 6

1.25 0.25 V (Vhigh+Vlow)/2 Note 3.

IROff Off Current 50 -50 mA Max. current into a pin withpower off.

VRHP Hot Plug Voltage

(Voltage applied with poweroff or on)

1.6 -0.5 V Applied without damage toany IB connector signal pin.

tREye Eye Opening Width 140 ps See Figure 24.

note 9

SRBtB Total Skew 24 ns Across receive physical laneson a port. (seeSection 5.6.7.4, “RxCMD =EnDeSkew,” on page 127Item 2)

Table 17 Receiver Input Characteristics

Symbol Parameter Maximum Minimum Units Conditions or Remarks



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technique as described in IEEE Std. 181--2003 (Determining State Levels from the His-togram).


Replace Original Text C6-1: The beacon detection shall meet the following requirements: Thebeaconing detector shall detect a minimum amplitude of 175 mV p-p asa valid signal present. Signals less than 85 mV p-p shall be consideredabsent. Signals with transitions only at less than 10 MHz shall be consid-ered absent. The beaconing sequence is transmitted at the in band sig-naling rate of 2.5 Gbits/second with an active period of 2 ms and aquiescent period of 100 ms (See Section 5.6.4.2, “Polling States,” onpage 110).

With New Text C6-2: The beacon detection shall meet the following requirements: Thebeaconing detector shall detect a minimum un-signed waveform ampli-tude of 175 mV as a valid signal present. Un-signed waveform amplitudesless than 85 mV shall be considered absent. Signals with transitions onlyat less than 10 MHz shall be considered absent. The beaconing sequenceis transmitted at the in band signaling rate of 2.5 Gbits/second with an ac-tive period of 2 ms and a quiescent period of 100 ms (See Section 5.6.4.2,“Polling States,” on page 110).


Replace Original Text Both the driver and the interconnect are responsible for producing the specifiedeye at the receiver pins.

With New Text Both the driver and the interconnect are responsible for producing the specifiedsignal at the receiver pins.

Page: 153 Line: 20 Section: 6.6.2.2 Ref: xxxx

Replace Original Text The maximum loss from the IC package to the board connector is...

With New Text The maximum loss from the IC package to the backplane connector is...


Replace Original Text Correction or de-embedding may need to be performed to derive actualmeasured data, taking into account the configuration of the test setup.

With New Text Correction or de-embedding must be performed to derive actual measured data,taking into account the configuration of the test setup.


Replace Original Text Board/Backplane specification points

With New Text Board/Backplane test points


Replace Original Text Board/Cable specification points

With New Text Board/Cable test points



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Replace Original Text Table 19

With New Text Replace Table 19 with the following version:

Note: All measurements for only LUT active1. Refer to IEEE Std.181-2003 (Amplitude, Waveform, Unsigned) for definitions andprocedures around un-signed waveform amplitude measurements.2. Waveform amplitude measurements shall be conducted only on consecutive transitionbits, over a 2UI Epoch (IEEE Std. 181-2003) unit interval, over a minimum population of10E4 UI’s.

Table 18 Signal Test Points

TestPoint

Description

Amplitude

(volts p-p)

Un-SignedWaveformAmplitude

(volts)Note 1,2

EyeOpeningW

idth

TP1 Transmitted signal at board side ofbackplane connector

.8 250 ps

TP2 Transmitted signal at backplane side ofbackplane connector

.75 240 ps

TP3 Received signal at board side of con-nector

.316 150 ps

TP4 Received signal at backplane side ofconnector

.335 160 ps

TP5 Transmitted signal at board side ofcable connector

.89 250 ps

TP6 Transmitted signal at cable side of cableconnector

.82 240 ps

TP7 Received signal at board side of cableconnector

.282 150 ps

TP8 Received signal at cable side of cableconnector

.30 160 ps

TP9 Transmitted signal at board side ofpluggable interface socket

.89 296 ps

TP10 Received signal at board side of plugga-ble interface socket

.282 126 ps



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Replace Original Text C6-2.1.1: Backplane Connections shall comply with the amplitude andeye opening at TP2 and TP3. TP1 and TP4 are for reference.

With New Text C6-2.1.2: Backplane Connections shall comply with the amplitude andeye opening at TP1 and TP3. TP2 and TP4 are for reference.


Replace Original Text C6-2.1.3: Cable Connection shall comply with the amplitude and eyeopening at TP6 and TP7. TP5 and TP8 are for reference.

With New Text C6-16.1.2: Cable Connection shall comply with the amplitude and eyeopening at TP5 and TP7. TP6 and TP8 are for reference.


Replace Original Text board connector

With New Text backplane connector


Replace Original Text board connector

With New Text backplane connector


Replace Original Text The entirety of Section 6.10

With New Text See below.

6.1 RECOMMENDED TEST AND CHARACTERIZATION FACILITIES

Test, characterization, debug, and compliance verification of an IB portmay require additional states, modes, or accessible signals that are notrequired for functional operation. In this level of the specification, somerecommended facilities for such testing are defined. In future levels of thespecification, the incorporation of such facilities may become mandatoryto facilitate standardization of Compliance Testing.

In the sense used here, "arbitrary" means externally defined by the re-quirements of the testing being performed.

6.1.1 CONFIGURATION

Configuring the IB port to a useful default state should be possible withoutthe presence of a connection to another port or any other training se-quence. Activation of any of the provided test modes should require min-imal interaction with the device under test.



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6.1.2 TEST TRANSMIT MODE

The port should be able to transmit an arbitrary symbol stream from itslanes independent of the connection status. Passing through configura-tion or training states should not be required. Control of which lanes areactive should be provided.

6.1.3 TEST PACKET TRANSMIT MODE

The port should be able to transmit an arbitrary stream of IB packets andidle data at defined widths independent of connection status. Passingthrough configuration or training states should not be required.

6.1.4 TRANSMIT CLOCK

A clock output at the symbol rate or an integer multiple of the symbol rateshould be available at IC pins. A differential signal is suggested.

6.1.5 TEST DATA IN PORT

A means of inputting an arbitrary symbol pattern to be transmitted shouldbe provided. Means for storing such pattern and repetitively transmitting iteither as raw data or IB Packets should be provided. Maximum lengthshould be the MTU supported by the chip

6.1.6 TEST DATA OUT PORT

A means for observing the raw deserialized data should be provided

6.1.7 PARALLEL WRAP

A means for connecting the received data to the transmitter such that thesame data that is received is retransmitted. No skip ordered sets or othersymbols may be added to or subtracted from the input data stream.Common reference clocks may be required.

6.1.8 ERROR TRIGGER

A signal which is activated upon a selectable error condition should beprovided. Examples of these error conditions are

• Disparity Error

• Coding violation

• CRC error (packet mode)

• Bad Packet (various reasons)

• Unexpected Control Character

6.1.9 ERROR CAPTURE

A means for capturing data immediately preceding surrounding a bit erroris desirable. A means for transferring it out to an external device for anal-ysis should be provided.

InfiniBandTM Architecture Release 1.1 Chapter 7: Copper Cable Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 7: COPPER CABLE ERRATA


Replace Original Text Signal Ground shall not be connected to Chassis Ground in the connector.

With New Text Signal Ground shall not be connected to Chassis Ground in the connector. SeeSection 9.5.4.







Page: 171 Line: 26 Section: 7.7.5.4 Ref: 3440

Replace Original Text "... key with width of 1 mm, which is centered horizontally in the connector body."

With New Text "... key with width of 1 mm, which is centered horizontally in the connector body,as shown in Figure 37."



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Page: 173 Line: 1 Section: 7.6.1 Figure 40 Ref: 3688

Replace Original Figure

With New Figure below

A

4.6

0 -0.05

2.6+0.05

0

6.7

0 -0.05

2.6+0.05

05.

9±0.05

2-ø

P.T.H.

2.2 ±0.05

TYP

Signal and groundterminal pitch

0.5

0.5

4.45±0.05J10±0.05

0.05 A

0.25+0.05 0

0.05 A

0.25+0.05 0

TYPE m n J10

4X 1~8 1~9 16.45

12X 1~24 1~25 40.45 Recommended P.W.B. dimension

TYP

Detail C

S(1)

S(2)

G(1)

G(n)(9)

S(2m-1)(15)

S(2m)(16)

Edge of P.W.B.



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Replace Original Text Table 30 entries below

Table 30 Cable Assembly Electrical Requirements

Jca Jitter 0.25 UI per EIA 364-107 with Fibre Channel CJTPATstimulus until 1000 hits in max. 20 mV high jitterbox or equivalent, with equipment and fixture con-tribution de-embedded; worst case pair, with twophysically adjacent pairs on each side of that pair(if they exist) to be driven by an asynchronouscrosstalk source at 1.6 Vpp differential amplitude.A PRBS generator may be used for the crosstalksource at a minimum of 1.3 Gb/s. See Figure 49.

VCout Eye opening, volt-age

316 mV minimum differential peak to peak voltage for 1Vpp Fibre Channel CJTPAT stimulus until 1000hits in max. 20 mV high jitter box or equivalent,measured at board connector pins withequipment and fixture contribution de-embedded.See Figure 49.

TReye Eye opening, time 0.75 UI minimum time opening for 1 Vpp Fibre ChannelCJTPAT stimulus until 1000 hits in max. 20 mVhigh jitter bom or equivalent, measured at boardconnector pins. See Figure 50.



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With New Text Table 30 entries below

Page: 191 Line: 24 Section: 7.7.9.7.1 Ref: 3441

Replace Original Text "Detailed drawings of mating interface dimensions are shown in Figure 40."

With New Text "Detailed drawings of mating interface dimensions are shown in Figure 37."

Page: 193 Line: 29 Section: 7.7.9.7.3 Ref: 3443

Replace Original Text ...which is centered horizontally in the connector body.

With New Text "...which is centered horizontally in the connector body, as shown in Figure 37."

Table 30 Cable Assembly Electrical Requirements

Jca Jitter 0.25 UI per EIA 364-107 and IEEE-191-2003, with FibreChannel CJTPAT stimulus until 1000 hits in max.20 mV high jitter box or equivalent, with equip-ment and fixture contribution de-embedded; worstcase pair, with two physically adjacent pairs oneach side of that pair (if they exist) to be driven byan asynchronous crosstalk source at 1.6 V differ-ential amplitude. A PRBS generator or othersource may be used for the crosstalk source fordriving the adjacent pairs at a minimum of 1.3Gb/s, provided the risetime is no slower than 100ps. See Figure 49.

VCout Eye height 316 mV Fibre Channel CJTPAT stimulus with an eyeheight of 1V until 1000 hits in max. 20 mV highjitter box or equivalent, measured at boardconnector pins with equipment and fixturecontribution de-embedded; worst case pair, withtwo physically adjacent pairs on each side of thatpair (if they exist) to be driven by anasynchronous crosstalk source at 1.6 Vppdifferential amplitude. A PRBS generator or othersource may be used for the crosstalk source fordriving the adjacent pairs at a minimum of 1.3Gb/s, provided the risetime is no slower than 100ps. See Figure 49.

TReye Eye width 0.75 UI minimum time opening for 1 V Fibre ChannelCJTPAT stimulus until 1000 hits in max. 20 mVhigh jitter box or equivalent, measured at boardconnector pins. See Figure 50.

InfiniBandTM Architecture Release 1.1 Chapter 8: Fiber Attachment - 2.5 Gb/s August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 8: FIBER ATTACHMENT - 2.5 GB/S


Replace Original Text Modal bandwidth with overfilled launch (min)

With New Text "Modal bandwidth (min)"

new footnote a - "Overfilled launch bandwidth per IEC 60793-1- 41 or TIA/EIA455-204"

new footnote b - "Effective modal bandwidth for fiber meeting

TIA /EIA-492AAAC"

The updated table follows.

8.7 FIBER OPTIC CABLE PLANT SPECIFICATIONS

Table 51 Optical Fiber Specifications

Parameter SMF

(9 µm)MMF 50/125 µm MMF 62.5/125 µm Units

Nominal Fiber SpecificationWavelength

1310 850 850nm

Fiber Cable Attenuation (Max) 0.5 3.5 3.5 dB/km

Modal Bandwidth (Min) not applicable500a and

2000b 200aMHz.km

Zero Dispersion Wavelength λ0 nm

Zero Dispersion Slope S0 (Max) 0.093

0.11 for 0.11 for

ps/nm2.km

a. Overfilled launch bandwidth per IEC 60793-1-41 or TIA/EIA 455-204.b. Effective modal bandwidth for fiber meeting TIA /EIA-492AAAC

1300 λ0 1320≤ ≤ 1295 λ0 1320≤ ≤ 1320 λ0 1365≤ ≤

1300 λ0 1320≤ ≤ and

0.001 λ0 1190–( )

1295 λ0 1300≤ ≤

for

1320 λ0 1348≤ ≤ and

0.001 1458 λ0–( )

1348 λ0 1365≤ ≤for

InfiniBandTM Architecture Release 1.1 Chapter 9: Mechanical Specification Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 9: MECHANICAL SPECIFICATION ERRATA

no errata

InfiniBandTM Architecture Release 1.1 Chapter 10: Backplane Connector Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 10: BACKPLANE CONNECTOR ERRATA

no errata

InfiniBandTM Architecture Release 1.1 Chapter 11: Low Speed Electrical Signaling August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 11: LOW SPEED ELECTRICAL SIGNALING

no errata

InfiniBandTM Architecture Release 1.1 Chapter 12: Power / Hot Plug Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 12: POWER / HOT PLUG ERRATA

no errata

InfiniBandTM Architecture Release 1.1 Chapter 13: Hardware Management Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 13: HARDWARE MANAGEMENT ERRATA


Replace Original Text e. Required if non-Module xCA_ID (unless ChassisInfo Device is resent)

g. Required if non-Module Switch_ID (unless ChassisInfo Device is present)

h. Required if non-Module xCA_ID (unless ModuleInfo Device is present)

j. Required if non-Module Switch_ID (unless ModuleInfo Device is present)

With New Text e. Optional for non-Module xCA_ID only if ChassisInfo Device is present.Required for non-Module xCA_ID if ChassisInfo Device is not present.

g. Optional for non-Module Switch_ID only if ChassisInfo Device is present.Required for non-Module Switch_ID if ChassisInfo Device is not present.

h. Required for non-Module xCA_ID if ModuleInfo Device is not present.

j. Required for non-Module Switch_ID if ModuleInfo Device is not present.


Replace Original Text c. Required if the ModuleInfo Device feature is required per Table 84 ModuleFeature Requirements on page 393, but it is not implemented via address A0h.

With New Text c. Required if the ModuleInfo Device or ChassisInfo Device features arerequired per Table 84 Module Feature Requirements on page 393, but it is notimplemented via address A0h.

InfiniBandTM Architecture Release 1.1 Chapter 14: OS Power Management Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 14: OS POWER MANAGEMENT ERRATA


Replace Original Text MOn -> MStandby state transition = Hardware (WakeonIB or WRE)

MStandby -> MOn state transition = Software (Standby)

With New Text MOn -> MStandby state transition = Software (Standby)

MStandby -> MOn state transition = Hardware (WakeonIB or WRE)

The updated figure follows.

InfiniBandTM Architecture Release 1.1 Chapter 14: OS Power Management Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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Figure 165 Module Power State Diagram

Note: All software transitions shown are done through the BMSend.SetMod-ulePMControl operation. The “value” shown is the mnemonic representationof a state value.

MNoWake

MOn

MStandby

MOff

Auxiliary PowerNot Available

AuxiliaryPower Available

Bulk Con-

Bulk Con-

Bulk Con-VA_In(<Min

Hardware:WakeOnIBOR

Software:Standby

Hardware:VBxEn_LdeassertedHardware:

VBxEn_LassertedAND

VA_In(<Min

VA_In(<Min)

VA_In(>=

InfiniBandTM Architecture Release 1.1Chapter 15: Volume 2 Compliance Summary Errata August 2003VOLUME 2 - PHYSICAL SPECIFICATIONS ERRATA


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CHAPTER 15: VOLUME 2 COMPLIANCE SUMMARY ERRATA

no errata



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ANNEX A1: MECHANICAL ANNEX ERRATA

no errata



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ANNEX A2: IB-ML DESIGN GUIDELINES ERRATA

no errata



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ANNEX A3: HARDWARE MANAGEMENT EXAMPLES ERRATA

no errata



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ANNEX A4: HARDWARE MANAGEMENT INDEX OF TERMS ERRATA

no errata

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