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Novel reduced-size micromachined resonators and filters
Item Type text; Thesis-Reproduction (electronic)
Authors Tavernier, Christophe Antoine
Publisher The University of Arizona.
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UMI'
NOVEL REDUCED-SIZE MICROMACHINED
RESONATORS AND FILTERS
BY
CHRISTOPHE ANTOINE TAVERNIER
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
In Partial Fulfillment of the Requirements For the Degree of
MASTER OF SCIENCE
In the Graduate College
THE UNIVERSITY OF ARIZONA
2001
UMI Number 1404055
®
UMI UMI Microfomn 1404055
Copyright 2001 by Bell & Howell Information and Learning Company. All rights reserved. This microform edition is protected against
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Bell & Howell Infomnation and Learning Company 300 North Zeeb Road
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2
STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfilhnent reqiiirement for an advanced
degree at the University of Arizona and is deposited in the University Library to be made
available to borrowers under rules of the Library.
Brief quotations from this thesis are allowable without special permission,
provided that accurate acknowledgments of source is made. Request for permission for
extended quotation from or reproduction of this manuscript in whole or in part may be
granted by the head of the major department of the Dean of the Graduate College when in
his or her judgment the proposed use of the material is in the interest of scholarship. In all
other instances, however, permission must be obtained from the author.
SIGNED:
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
JomR ipapglymerou Date Professor of Electrical Engineering
3
ACKINOWLEDGEMENTS
I am particularly thankful to my professor and advisor John Papapolymerou who guided me and helped me carry out this project. I gained experience and skills through out two years of intense work.
I also wish to thank Rashaunda Henderson and Mike Hill who provided me with helpful information regarding mask design and cleanroom fabrication issues. Numerous scientific and advance discussions with them helped me develop successfiil methods for the research.
Throughout the entire projiect, the Center for Low Power Electronics (CLPE) and Motorola SPS supported financially my work. They are hereby thanked for their trust in me, particularly Prof. Vrudulha and Ms. Samuelson (CLPE) and Mr. Miller (Motorola SPS/AMMS).
Finally, I want to express my giratitude to the ECE people who provided the friendly environment necessary for my •^vbrk. I, particularly would like to thank Dr. R. W. Ziolkowski, Dr. S. Dvorak, Dr. V_ Wells, Ms. S. Dahl and Mr. C. Booth.
Last but not least, I was helped by different partners for the fabrication: • Astronomy Dept. (Laser etch - C. Walker, C. d'Aubigny - Bonding system — E. T.
Young) • Applied Laser Tech (silicon laser cut) and Raytheon (alumina cut — Krista Lange) • Coors (alumina provider) and Paratek Corp. (Ceramic materials) • University of Michigan (silicon wafers) • LSI Photomask • SPS Microelectronics Laboraftory (J. Baker, T. Botta) • Optical Science Dept. (O. Noirdman) and ECE Dept. Microelectronics Laboratory
They are hereby deeply thanked.
This work was supported by the NSF-S/IUCRC Center for Low Power Electronics (CLPE) under Gramt #EEC-9523338 and by Motorola, Semiconductor Products Sector.
4
DEDICATIONS
This thesis is dedicated to all women and men. of good will in the search of knowledge
and wisdom improvement through science.
Dediee a Pierre et Michelle bien sur,
Et mes amis Marcel, Celine, Robert, James, Boris et Honore presents le long du parcours.
"How well do you know your device ?"
Tom Myers
Engineering Manager Motorola SPS - Tempe.
5
TABLE OF CONTENTS
ABSTRACT 8
INDEX OF TERMS 9
LIST OF TABLES 10
LIST OF FIGURES II
1. INTRODUCTION 14 1.1. Motivation 14 1.2. State of the Art 17 1.3. Specifications 19 1.4. Principles 19 1.5. Prototyping method 22 1.6. Results Overview 23
2. TOOLS AND TECHNIQUES 24 2.1. Introduction 24 2.2. Theory 24 2.3. Simulation 34 2.4. Fabrication 38 2.5. Measurements 41 2.6. Results and Conclusions 45
3. CAVITY RESONATOR FILTER ON DUROID 47 3.1. Introduction 47 3.2. Principles 47 3.3. Fabrication Techniques 48 3.4. Measurements 52 3.5. Interpretations of Measured Results 64 3.6. Model 72 3.7. Conclusions 81
4. CAVITY RESONATOR FILTER ON SILICON 82
6
4.1. Introductioa 82 4.2. Principles 82 4.3. Fabrication Techniques 87 4.4. Measurements 93 4.5. Interpretations of Measured Results 108 4.6. Conclusion 112
5. CONCLUSIONS AND FUTURE WORK 113 5.1. Results Summary 113 5.2. Performances 115 5.3. Developed Techniques 115 5.4. Possible Applications and Improvements 115 5.5. Future Work 117
ANNEX 120
1. MICROMACHINED DIELECTRIC 2-POLE FILTER ON SILICON 120 1.1. Introduction 120 1.2. Principles and Simulations 121 1.3. Measurements and Conclusion 128
2. ADDITIONAL PLOTS AND MEASUREMENTS 129 2.1. Quality Factor Chart for Square Base Cavity 129 2.2. Slot Location Effect on the BST Cavity Response 130 2.3. Slot Size Effect on the BST Cavity Response 132 2.4. Air Gap Effect on the Response 134 2.5. Unloaded Cavity Measurement 137
APPENDICES 138
APPENDIX A. FILES AND PICTURES OF SIMULATIONS 139
APPENDIX B. PICTURES OF FILM AND GLASS MASKS 144
APPENDIX C. DATASHEET: BST, ALUMINA, SILVER EPOXY 146
APPENDIX D. FABRICATION TECHNIQUES - DUROID & SILICON 150
APPENDIX E. FABRICATION RECIPE FOR DUROID CAVITY FILTER 154
APPENDIX F. FABRICATION RECIPE FOR SILICON CAVITY FILTER 155
7
APPENDIX G. FABRICATION RECIPE FOR SILICON DIELECTRIC FILTER 161
APPENDIX H. PICTURES OF CIRCUITS 164
APPENDIX I. MEASURING AND FABRICATION EQUIPMENTS 167
REFERENCES 170
8
ABSTRACT
With an always-increasing need for higher integration, the wireless industry poses
challenges regarding miniaturization and high performance circuitry. In addition, the
solutions require compatibihty with the rest of the design for integration and
manufacturing.
The present work depicts the progress toward a novel, high quality, one-pole
filter-resonator operating in the 5.6-5.8 GHz range. Quality factors up to 640 are
demonstrated on silicon planar structures with volume of 177 mm^. Further size reduction
yielded a volume of 24.5 mm^ and a quality factor of 186.
9
INDEX OF TERMS
Alumina, BST, Duroid® cavity: Synonym for cavity filled with the corresponding material with first resonance in the 5.7-5.8 GHz range.
BNeT: Barium Neodymium Titanate. Ceramic type.
BST: Barium Strontium Titanate (Ba07Sr03)Ti03. Ceramic type.
CPW line: Coplanar Waveguide line. Three conductor planar structure supporting TEM mode.
EDM: Electronic Discharge Machining.
FEM: Finite Element Method.
^M: Micromaching.
PEC, PMC: Perfect Electric Conductor, Perfect Magnetic Conductor.
PR: Photoresist.
Q: Quality factor. Amount of energy stored in a device in comparison to the amount lost.
Radiation loss: Loss in the feed due to the microstrip lines proximity and inducing a cross coupling with each other. Also referred to cross coupling in opposition to direct coupling in the slots.
SAW: Surface Acoustic Wave. Technology widely used for filtering at 1.9 GHz in wireless Industry.
Tan(5): Loss tangent, synonym of dielectric loss in a material of this type.
ZTS: Zirconia Titania Stannic Oxide. Ceramic type.
10
LIST OF TABLES
Table 1 On-Chip or Off-Chip by Mitsubishi 15
Table 2 State of the Art by Agilent — 08/2000 18
Table 3 Specifications 19
Table 4 Results overview 23
Table 5 Duroid® feed wafer process 48
Table 6 Summary of Duroid®/Duroid® cavity results 64
Table 7 Summary of alumina/Duroid® cavity results 65
Table 8 Summary of BST/Duroid® square cavity results (stubs) 66
Table 9 Summary of BST/Duroid® square cavity results (vias) 67
Table 10 Summary of BST/Duroid® rectangular cavity results 68
Table 11 3-mode resonator PSPICE model - parameter change 76
Table 12 3-mode resonator PSPICE model — parameter effect summary 79
Table 13 Silicon feed wafer parameters and calibration 88
Table 14 Silicon feed wafer process 89
Table 15 Silicon cavity wafer process 90
Table 16 Silicon cavity wafer parameters 91
Table 17 Summary of alumina/Si cavity results 108
Table 18 Summary of BST/Si cavity results 110
Table 19 Results overview 114
Table 20 Theoretical dimensions and performances of BNeT and ZTS loaded cavities 116
11
LIST OF FIGURES
Figure 1-1 Receiver Module 19
Figure 1-2 Cavity resonator elements 21
Figure 2-1 Height and Sr effect on the quality factor 26
Figure 2-2 Conductivity effect on the quality factor 27
Figure 2-3 Tan(5) effect on the quality factor 28
Figure 2-4 Cavity size effect on the quality factor (alumina — 1mm thick) 30
Figure 2-5 Cavity size effect on the quality factor (BST- 1mm thick) 30
Figure 2-6 Necessary trade-off in Q versus miniaturization 33
Figure 2-7 H and bone shape coupling slots 37
Figure 2-8 Permittivity measurement 39
Figure 2-9 Loss tangent measurement 39
Figure 3-1 Duroid®-alumina cavity - feed dimensions (stubs) - Duroid® process 50
Figure 3-2 BST cavity - feed dimensions (stubs) — Duroid® process 50
Figure 3-3 BST feed dimensions (vias) 51
Figure 3-4 Duroid® device under test 51
Figure 3-5 Sn Duroid® cavity response 52
Figure 3-6 S21 Duroid® cavity response 53
Figure 3-7 Duroid® cavity response (detail) 53
Figure 3-8 Duroid® cavity weak coupling 54
Figure 3-9 Duroid® cavity low coupling (detail) 54
Figure 3-10 Alvmiina cavity measurement 56
Figure 3-11 Alumina cavity measurement (detail) 56
12
Figure 3-12 Alumina cavity simulation 57
Figure 3-13 Alumina cavity weak coupling measurement 57
Figure 3-14 Alumina cavity weak coupling measurement (detail) 58
Figure 3-15 BST square cavity measurement (stubs) 59
Figure 3-16 BST square cavity simulation (stubs) 59
Figure 3-17 BST square cavity measurement (vias) 60
Figure 3-18 BST square cavity simulation (vias) 60
Figure 3-19 BST rectangular cavity optimal coupling measurement 62
Figure 3-20 BST rectangular cavity weak coupling measurement 62
Figure 3-21 Electric field in the alumina cavity feed (stubs) 70
Figure 3-22 Electric field in the alumina cavity feed (vias) 70
Figure 3-23 BST cavity simulation with stubs 71
Figure 3-24 BST cavity simulation with vias 71
Figxire 3-25 Basic resonator PSPICE model schematic 72
Figure 3-26 Basic resonator PSPICE model response 73
Figure 3-27 Effect of parameter R9(Loss) on the basic resonator response 73
Figure 3-28 Effect of parameter CI l(Cvalue3) on the basic resonator response 74
Figure 3-29 3-mode resonator PSPICE model schematic 75
Figure 3-30 3-mode resonator PSPICE model response 75
Figure 3-31 Effect of parameter lOcouple on the 3-mode resonator response 77
Figure 3-32 Effect of parameter Cvalue6 on the 3-mode resonator response 77
Figure 3-33 Effect of parameter Cvalue3 on the 3-mode resonator response 78
Figiure 3-34 Effect of parameter Loss on the 3-mode resonator response 78
Figure 4-1 Feed wafer in silicon 83
Figure 4-2 Cavity wafer and dielectric material in silicon 83
Figiure 4-3 Alumina resonator in HFSS 84
Figure 4-4 BST resonator in HFSS 84
Figure 4-5 Electric field in the BST cavity 85
13
Figure 4-6 CPW to microstrip line transition - geometrTy 86
Figure 4-7 CPW to microstrip line transition- simulation 86
Figure 4-8 Silicon resonator structure 87
Figure 4-9 Alumina cavity - feed dimensions (stubs) — silicon process 92
Figure 4-10 Alumina cavity - feed dimensions (vias) —silicon process 92
Figure 4-11 BST cavity - feed dimensions (vias) - silicon process 93
Figure 4-12 TRL calibrated thru - measurement 94
Figure 4-13 Line terminated by via — measurement 94
Figure 4-14 Line parameters - measurement 95
Figure 4-15 Alumina cavity measurement 96
Figure 4-16 Alumina cavity measurement (detail) 97
Figure 4-17 Alumina cavity simulation 97
Figure 4-18 Alumina cavity simulation (detail) 98
Figure 4-19 Alumina cavity weak coupling measurem^ent 99
Figure 4-20 Alumina cavity weak coupling measurem'.cnt (detail) 99
Figure 4-21 Alumina cavity weak coupling measurem_ent— unbonded circuit (detail)... 100
Figure 4-22 BST rectangular cavity measurement 101
Figure 4-23 BST rectangular cavity simulation 102
Figiure 4-24 BST rectangular cavity measurement (detiail) 102
Figure 4-25 BST rectangular cavity simulation (detaiL) 103
Figure 4-26 BST weak coupling measurement 103
Figure 4-27 BST weak coupling measurement (detail]D 104
Figure 4-28 BST cavity optimal coupling measurememt— unbonded circuit 105
Figiu-e 4-29 BST cavity weak coupling measurement— unbonded circuit 105
Figure 4-30 BST cavity weak coupling measurement— unbonded circuit (detail) 106
Figure 4-31 BST cavity — weak coupling — simulatioo (detail) 107
Figure 4-32 Thru line - measurement 107
Figure 5-1 Packaging and mounting option of the resconator 118
14
1. INTRODUCTION
1.1. Motivation
Microwave and millimeter-wave components for wireless communication
systems and radars are traditionally built with waveguide technology which offers low-
loss and high quality factor circuits. This technology results in large size, weight, high
cost and incompatibility with monoHthic circuits and increased fabrication complexity
especially at higher frequencies.
1.1.1. Systems on-a-chip
These traditional techniques are incompatible with the development of systems
on-a-chip. As shown in the Mitsubishi document (Table 1), the system on-a-chip concept
is profitable for industrial application above 4 GHz.
15
1.4 On-Chip or Off-Chip Configuration?
Cost Size Frequency (Limited by)
500MHz IGHz 2GHz 5GHz lOGHz
AMTTSUBISHI ELECTRIC CXIRPORATION
Table 1 On-Chip or Off-Chip by Mitsubishi
1.1.2. New frequencies
The need for greater bandwidth directs the efforts toward higher frequency data
transmissions. Cellular and personal communication systems, with their growing
potential, requires greater access to increasing quantities of data. To a smaller extent,
space telecommunication systems rely on microwave frequencies for transmission and
reception as well.
Finally, this overview would not be complete without mentioniag military
applications. Li all simations, increasing the operating frequency can satisfy the demand
for wider bandwidth. The next generation wireless communication devices are developed
according to this fact. For the present work it will be restricted to the higher frequency
range of the H band.
16
1.1.3. Performances
Increasing the operating frequency generates the need for improvement of the RF
part components: resonators, filters, diplexers as well as the antennas and LNA's which
exist in transmitter and receiver modules. Performances of these devices have to at least
equal the 1.9 GHz GSM capacity of the early 2000 years systems. Since Surface Acoustic
Wave (SAW) filters remain frequency limited, an alternate solution must be explored
with the industry's golden motto: low cost, weight, and power consumption device which
can be economically manufactured.
1.1.4. Miniaturization
Portable devices associated with wireless systems require a high level of
miniaturization. Using material with high dielectric constant, it becomes possible to
withstand the electric field in smaller volume. An example extracted from the present
work emphasizes clearly this advantage: at 5.8 GHz, the volume for a BST filter-
resonator is 24.5 mm^, for the Duroid® it is 153.4 mm^ which is 6.3 times greater. With
air loading the cavity, the volume increases to 1711 mm^. Compared to the Duroid®
filled cavity, a reduction by factor 11 is achieved. Compared to the BST filled cavity the
reduction factor is 70. The interest in high permittivity material is therefore obvious for
the present application. In terms of permittivity, the volume reduction is calculated using
the following ratio:
— , theoretically capable of reaching several hundreds. reference
17
1.2. State of the Art
Development of smaller size resonators is driven by both an economical and
performance factors. Currently Surface Acoustic Wave device technology is widely used,
however it has low performance. The following sections present an overview and
comparison of the available techniques.
1.2.1. Technology comparison with FBAR technology (Agilent)
Table 2 summarizes the performance of the last Agilent product in comparison
with ceramic and SAW technology at 1,9 GHz. The Film Bulk Acoustic Resonator
(FBAR) [1] uses a Metal-Aluminimi Nitride-Metal membrane which produces acoustic
vibrations under AC source. Direct apphcation of the piezoelectric effect is implemented
for the feed. FBAR achieves quality factors up to one thousand. High performance is
reached at the price of more complexity, particularly the necessity of an alternating
electrical potential.
Ih comparison, the device developed in the present work aims toward fiill chip
integration. Scaling its dimensions at 1.9 GHz yields a volume of 178 mm^ for a quahty
factor of approximately 250. At higher frequency and with a proper dielectric choice, a
device of smaller size would be produced and is expected to compete more efficiently
with the FBAR resonator [Chapter 2], Finally, SAW filters have acceptable performance
and size but are limited in the 1.9 GHi range for the time being.
18
AgilentTsehnologie* b«*iglle»V*r
A quick comparison of the three technologies is presented below:
Ceramic SAW FBAR size (PCS duplexer)
675 mm' 140 mm-* (cellular band)
126 mm ; going to 42 mm
electrical (I.L, roll-off)
excellent good excellent
power handling best (>35 dBm @2 GHz)
fair (31 dBm @ 900 MHz)
good (>32 dBm @ 2 GHz)
temperature coefficient
Oto-5 ppm/C -23 to -94 ppm/C -20 to-30 ppm/C
frequency range filters: duplexers;
cellular/PCS celluIar/PCS
IF-cellular-PCS cellular/PCS?
cellular-PCS-mw cellular-PCS-mw
integration no Multi-Chip Module (MCM)
MCM; future full integration
Table 2 State of the Art by Agilent — 08/2000
1.2.2. Ceramic filter in multilayer technology
Dielectric materials on multilayer configuration exist in very small size at 1.9
GHz. S. Kobayashi and K. Saito propose a 3 x 2 x 1.5 mm^ filter made by alternating
high and low dielectric materials [2]. The device has less than 3dB-insertion loss but
extra capacitive and inductive effects produce the appearance of two poles out of the
band. Work from Arai, Ono and Ayusawa demonstrated quality factors up to 1000 and
4.3 dB insertion loss using ceramic [3].
1.2.3. RF chip module based on high dielectric material
S. Nagata and T. Ueda developed the RF part of a receiver at 820 MHz on GaAs
substrate. It is composed of an amplifier and mixer and was made possible by the use of a
Barium Strontium Titanate (Sr = 300) capacitor [4].
19
1.3. Specifications
The specifications in Table 3 will serve as a guideline for the demonstration of a
possible high Q resonator at a firequency of 5.8 GHz.
Low loss, narrow bandwidth High quality factor MonoUthic -avoid waveguide technology On-chip compatibility
Miniaturized Smallest dimensions Passive device Low power application
Compatibility with standard transmission lines hitegration
Table 3 Specifications
1.4. Principles
>jlFFiUe F Filtt
-RT PLL
IF FUter l&Q Ocmodulator
TF" PLL
Figure 1-1 Receiver Module
The diagram of a typical receiver module (Figure 1-1) locates the filter in the
design. After the antenna and before the LNA, the resonators used in the RF filters
determines the frequency of the application. In the present work, this is made possible by
using the properties of resonant cavities.
20
The device is a sandwich of a top and a bottom wafer, with a loading material
squeezed between the two. The top wafer also called the feed, couples electromagnetic
energy in the cavity which is micromachined in the bottom wafer. The Magnetic coupling
is ensured by two microstrip lines through two slots located in the ground plane of the top
wafer. These two apertures provide magnetic coupling by maximizing the Magnetic field
at their location. Bringing an electrical or a physical short next to the slot, between the
ground plane and the microstrip line minimizes the Electric field, equivalent to maximum
Magnetic field by energy conservation. The physical short uses metallized vias, while the
electrical short is a quarter wavelength open stub, which reflects an open into a short. In
the design of the last solution, flinging fields are taken into account and the physical
length might be shorter than the quarter wavelength. The bottom wafer, also called cavity
wafer, supports the high dielectric constant loading material and is attached tightly to the
feed wafer. Figure 1-2 represents the three separated elements.
The feed wafer is made out of a surface metalhzed semiconductor substrate in
order to allow field propagation. High resistivity sihcon substrates are preferred for
minimum loss. Finally, the cavity wafer is either a metal block or a machined piece of
material with metallized surfaces. The cavity size and the dielectric material inside
determine the resonant firequency of the device, whereas the cavity height and dielectric
loss impose the restriction on the quahty factor (cf. 2.2). These types of materials are
typically well-known [5][6] and their fabrication process is documented [7][8].
21
microstrip lines
coupling slots
feed-wafer ^ •
Top wafer
Loading material
tvwafer>
Bottom wafer
Figure 1-2 Cavity resonator elements
22
1.5. Prototyping method
Ih order to meet the specification, it is necessary to develop a method in several
steps limiting the complexity at every step. The design procedure will follow the path of
increasing Sr in the cavity. Since the resonant frequency is fixed by the specification, a
permittivity increase is also a miniaturization increment. Starting with low permittivity
produces a device comparable to previously demonstrated ones [9]. Similarly, as a first
approach, fabrication will be made easier by the use of sofl; material. Despite an increase
of dimension tolerances, it introduces more flexibility for timing. The response is
degraded but accurate fabrication techniques will be applied once the trends from
simulations are successfiilly established by experiment. The first step involves Duroid®
material for the feed and takes advantage of a closely related Sr in comparison with
silicon, which will be used, in the second step. Respective Sr values are 10.8 and 11.7.
In summary, several cavity resonators are proposed below with materials that
have a dielectric constant from 9.8 to 70 using Electrical Discharge Machining (EDM)
for Duroid®/Aluminum fabrication and Micromachining (fxM) techniques on silicon:
- 17.47x8.78x0.93 mm^, Rogers Duroid® filled, Sr = 10.8, tan(5) = 0.0023 with EDM.
- 17.47x8.78x0.88 mm^, Coors® alumina filled, Sr = 9.8, tan(5) = 0.0002 with EDM.
- 4.1x4.1x0.25 mm^, Paratek® BST filled, Sr = 70, tan(5) = 0.0024 with EDM.
- 7x3.5x0.25 mm^, Paratek® BST filled, Sr = 70, tan(5) = 0.0024 with EDM.
- 18.47x9.58x1 mm^, Coors® alumina filled, 8r = 9.8, tan(5)=0.0002 with jxM.
23
- 7x3.5x1 mm^, Paratek® BST filled, Sr = 70, tan(5) = 0.0024 with |xM.
EDM fabrication is associated with the Rogers Duroid® feed that is easily
attached on a block of aluminum including the cavities. Tolerance on Rogers Duroid® is
8r = 10.8+/-0.05. SMA connectors and the 3.5 mm measurement standards were used in
experiment. Micromachining (}iM) is a fiill silicon design with high level of precision
associated with planar probes and the 2.4 mm measurement standards.
1.6. Results Overview
Table 4 summarizes the theoretical, simulated and measiired results.
Cavity Dimensions
(mm^)
Fab. Type
Filler er/tan(6)
Fr Eq./HFSS/exp
(GHz)
Qu Eq./exp
Af exp.
(MHz)
S21 exp. (dB)
17.47x8.78x0.93 EDM 10.8/0.0023 5.82/5.74/5.53 270/232 137 -2.2
17.47x8.78x0.88 EDM 9.8/0.0002 6.1/6.1/6.16 626/382 137.5 -1.3
4.1x4.1x0.25 EDM 70/0.0024 6.18/5.84/5.68 120/26 400 -6.6
7x3.5x0.25 EDM 70/0.0024 5.73/5.72/5.82 138/128 350* -5.6*
18.47x9.58x1 joM 9.8/0.0002 5.63/5.6/5.65 693/640 36.5 -6.6
7x3.5x1 |xM 70/0.0024 5.73/5.67/5.92 252/186 81 -5.35
Table 4 Results overview
("•) value not corresponding to the same resonant frequency.
24
2. TOOLS AND TECHNIQUES
2.1. Introduction
Chapter 2 presents the theory used to characterize the resonator of Figure 1-2 by
linking its geometry to the performance. Several plots are presented in the discussion to
describe the weight of each parameter in the search of the best performance. Following
this analysis, techniques using Ansoft HFSS simulator will be presented. Similarly,
fabrication and measurement tools will be introduced.
2.2. Theory
2.2.1. Field and resonant frequency - independent of the cavity height
The field distribution [10] in the cavity for the TEioi mode is:
E, =^o.sin .sin 71JC . Tt.y
Z
25
The general discrete set of modes in the cavity can be described by their resonant
frequency.
With m, n, o eigenvalues (integers) and 1, h, w the length, height and width of the
cavity respectively. The formula shows that the first resonant mode (TEioi) has its
frequency independent of the cavity height. In addition, for a specific resonant frequency,
loading the cavity with a dielectric material of Sr > 1 involves decreasing the remaining
dimensions. This opens the way to device miniaturization with the use of high Sr material.
2.2.2. Quality factor - loaded, unloaded, and external
The Unloaded Quality Factor (Qu), which is a figure of merit for resonators, is the
ratio of the power stored to power lost in the cavity (also named Q in the following). The
losses occur through the conductive walls and the dielectric material. Moreover, the feed
circuit contributes its own losses that are described in the external quality factor (Qe).
This lowers the overall Q of the device, which is referred as loaded quality factor (Qi).
Generally, high quality factors are needed in order to achieve high selectivity and
low attenuation in the device. The mathematical expressions of the previous quantities
follow [11], starting with Qc, the cavity quality factor which only includes metal loss:
{kdw)' h rj (3)
26
With R = (4)
Where Rm is the surface resisitivity of the cavity walls, k the wave number, -n the
wave impedance and the conductivity cr = 4.1.10^ S / m typically for Gold coverage.
1 1 a = -i-i
a a (5) with TaniS) = (6)
Tan(5) takes into account the dielectric losses in the loading material. Its inverse
is referred as dielectric quality factor and should be maximized. The effect of height on
the quality factor can be seen in Figure 2-1 where the loss tangent is neglected. At
constant frequency, increasing the permittivity produces lower Q because of the length
and the width reduction in (2) and (3).
Q vs Ej, for various height at 5.6GHz 2000
1800 -
1400 -
1000 -
2 mm 800 -
IJ mm 1 mm 600 -
-— — 3.5 mm
J25 mm
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
Er
Figure 2-1 Height and Er effect on the quality factor
High Q results correspond to thicker cavities. Nevertheless the increase of the
dielectric constant lowers drastically this trend while for thinner ones it remains mostly
27
unchanged. On the chart, heights range from 0.25 to 2 mm. Unless specified, in the
following sections, results will refer to cavities with constant height of 1 mm.
2.2.3. Maximum Q (I) - highly conductive walls and low dielectric loss
Figure 2-2 shows the impact of the conductivity, the dielectric constant, and the
loss tangent on the quality factor.
Unloaded Q vs. conductivity of the cavity walls for the 18.47x9.58x1 mm^ (er = 9.8) and 7x3.5x1 mm' cavity (er = 70) with and without dielectric loss
4.0 4.5 5.0 5.5
Er « 9.8. un (delta) « 0 (upper trace) Er « 9 8. urn (delta) = 0.0002 (lower trace) Er s 70. tan (delta) » 0 (upper trace) Er » 70. tan (delta) » 0.0024 (lower trace)
6.S 7.0
Conductivity ( 10' S/m)
Figure 2-2 Conductivity effect on the quality factor
Ranging the conductivity from Gold (a = 4.1.10^S/m) to Silver (a = 6.17.10'S/m)
results in an almost linear increase of the unloaded quality factor in all cases.
Nevertheless the positive impact of a conductivity increase is drastically lowered by the
loss in the dielectric material (as visible comparing the plots with tan(5) = 0 or 0.0002 to
the plot with tan(5) = 0.0024). The design has to take into account the dominant losses as
can be seen on the lower trace. Also noticeable is the achievable Q when increasing the
28
dielectric constant. When neglecting the dielectric loss, a lower Sr results in a higher Q
despite the surface contact with the metallic walls being larger. This can be interpreted as
an increase of the current density dissipated at the material-wall interface when using
higher permittivity materials. The price of a higher Q is of course the size of the device.
Traditionally air, as a perfect dielectric, is used. Only metal loss is present and the
occurring quaUty factor can range in the thousands. In case the loading material is not air
dielectric loss needs to be modeled by using the loss tangent coefficient in equation (5).
This loss often dominates the metal loss, particularly when the dielectric constant
becomes high. The effect of the loss tangent at 5.8 GHz is shown Figure 2-3.
700
650
600
550
500
S 400
J 350
5 300
250
200
150
100
50
0.0000 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0.0035 0.0040 0.0045
can( delta )
• 17.5x8 8x0.93 mm3 - Er » 9.8 (upper trace) O 7x3 5x0.25 mm3 - Er « 70 (lower trace)
Figure 2-3 Tan(5) effect on the quality factor
2.2.4. Maximum Q (2) — square shape cavity and small area device
As written in 2.2.1, the cavity height does not affect the resonant frequency and
Figure 2-3 shows that an increase of the height results in a direct increase of the quality
Unloaded Q vs. dielecinc loss
yoooi °°Ooooooo^- ••••••. OOOOOOOOl Oooooooooo oooooooooooooo
factor for a constant dielectric loss. This relationship can be exploited to increase the
performance of the device keeping in mind the limitation due to the loss tangent
coefficient. In the plots, the thicker cavity is more affected by an increasing tan(5) than
the thinner one. Very low loss dielectric such as air or alumina are useful for thick
cavities. In order to optimize the filter performance, thin cavities or even films should be
used when the tan(5) gets too high. The trend being that higher Sr materials have higher
tan(5), a tradeoff can be foimd between the optimum size and performance. As an
example, restricting the BST cavity height to 0.453 mm ensures producing less than 20%
Q degradation in comparison to the unlossy material (*).
By forcing the frequency to remain constant in equation (2), a functional link
between the length and the width parameters of the cavity can be found. Substituting this
function in (3), allows plotting the Q for different cavity size at a given frequency.
(*) Valid for the 7 x 3.5 x height mm^ cavity with 8r = 70 BST loading material and Gold coverage.
Device Area & Q vs. Dimension - Alumina cavity
820
800
C <ii 780
es o es
35 15 20 25 30 40 10 5
device length ( in mm)
Figure 2-4 Cavity size effect on the quality factor (alumina — 1mm thick)
Device Area & Q vs. Dimension - BST cavity
660.0
640.0
620.0
c ^ 600.0
c 580.0,
cs
0.7
0,0 5 12 13 14 15 6 7 8 3 4 9 10 11
device length {in mm)
Figure 2-S Cavity size effect on the quality factor (BST— 1mm thick)
31
Figure 2-4 and Figure 2-5 show this relation for cases without dielectric losses
and show that a maximum Q is achieved for a square cavity. Showing that the square is
the minimum area satisfying expression (2) (cf. lower side of Figure 2-4 and Figure 2-5
and (**) at the end of section 2.2), this confers a particular interest for square cavities in
terms of miniaturization and best efficiency. In this condition, the TE102 and TEioi are
always degenerated.
Nevertheless, this can cause difficulties during the study of the cavity feed. The
geometry might get too small to handle the electromagnetic problem properly and a
length to width ratio equal to two is preferred in those cases (cf. 2.3 and 5.5). Particularly
when the permittivity of the cavity filler is high, the silicon substrate fi"om the
specification might not be suitable because the wavelength in the feed gets too long
making the feed lines look electrically too close which generates parasitic effects.
Similarly, the slot looks electrically too large and the cavity behavior is perturbed.
Consequently, a rise of the substrate Sr is recommended. Difficulties encountered later
(cf. 3.5.3 and 3.5.4) suggest that a ratio of 10 between X,feed and A.cavity not to be exceeded
for a square cavity.
s This is equivalent to < 10 .
^feed
As noted before. Figure 2-4 and Figure 2-5 emphasize again that higher Sr,
independently firom the dielectric loss, tends to decrease the quality factor for a specific
frequency. An 8r of 9.4 could produce Qs up to 820 whereas only 665 is achievable with
32
Sr of 70 at 5.7 GHz if the dielectric loss is neglected. A plot showing this trend is
available in part E. Finally, the dimension of the square cavity is obtainable from the
Q simplified equation of the resonance frequency, namely a = , — (7).
2.2.5. Maximum Q (3) — cubic shape
The height can possibly be increased until a cubic cavity is achieved. Beyond this
value, we no longer have a dominant mode. As an example, at 5.8 GHz, a cubic cavity
filled with alumina, covered with Silver, and including the dielectric loss would have a
theoretical Q of 2400 for a 11.7 mm side length. As shown later, practical results are
expected to be close to this value, hi practice, the height of the device is limited by the
substrate. Due to fabrication restriction, with the stubs particularly, a too compact design
presents the risk of radiation in the feed (cf. 3.5.5). Since the feed permittivity is imposed
in our design, it is convenient to increase the length between the feed by restricting a
length to width ratio of two for the cavity dimensioning. A few comments will be made
on the square cavity (cf. 3.5.4).
2.2.6. Maximum Q (4) and miniaturization — the necessary tradeoff
Using the optimal parameters established so far, one can see in Figure 2-6 the
emergence of an incompatibility. A maximum quality factor is achieved for the lowest Sr,
which is equivalent to wider cavity dimensions. Increasing the resonant frequency allows
for better Q's and smaller dimensions but the performance will be reduced if the device is
33
built with very high Sr in the cavity. Consequently, for high frequencies, the choice of
dielectric materials is restricted toward lower values. Nevertheless, at lower frequencies,
the performance is more stable and a wide range of dielectric materials are suitable for
the loading of the cavity. Therefore miniaturization is more effective.
Q vs 8 at 3,5.6,10, 20GHz and the corresponding cavity volume
1000-
900-
800 -
700 -
/ ,
O 600 -oa
rT- 500 e
O 80 -
70 -60 -
50 -40 -30 -20 -
10 • •
0
\
5.6GH2 5.6GHz 10GHz 10GHz 2DGHZ 20ghz
3GHz
I ' • I 1
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375
Figure 2-6 Necessary trade-off in Q versus miniaturization
In summary, miniaturization at low frequencies can be realized with very high
permittivity materials; when the frequencies get higher, they participate in the
miniaturization as well and material with lower permittivity suits better for acceptable
quality factor. Moreover this tradeoff is advantageous for solving the elecfromagnetic
problem in the feed.
(**) Demonstration: x.y = A, with x'~ + y"^ = K (constant) equivalent to x''.y"'=A with x" + = K (a). Minimum exists for dA = -y"'.x'*.dx — x"'.y'^.dy = 0 (b) using y = (K — x^)®"^, dy = -x.(K — x")'°"^.dx (b) is rewritten as: -(K — x*)'°"^.x'".dx — x"'.(K — x")''.(-l). (K - x^)'®"5.dx = 0. For (K — x")"®"^ -dx ?!= 0 (equivalent to a infinite one dimensional cavity), previous expression is - x'" - (K - x")"' = 0-> X = y
34
2.3. Simulation
First the microstrip line width is computed to produce 50 Q according to the
permittivity and the height of the substrate [11]. A combination of height and width is
found using equation (2). Square and rectangular cavity types are explored. The derived
geometry is plugged into the HFSS drawing environment. A surrounding box three
wavelengths wider than the device outer dimensions, restricts the size of the problem.
hi the materials setup environment, 3D objects are each assigned a material with
its properties, namely conductivity, permittivity and dielectric loss. As a first approach
materials are only defined as PEC or perfect dielectric. BST and alumina for the loading
material, air for the surroimding box and PEC for the cavity are assigned.
The boundaries are defined in the boundaries/source setup. Surfaces such as PEC,
PMC, and radiation can be described. Lines, ground planes, and the surrounding box are
PEC, the couphng slots, as apertures in the ground plane are PMC. The source is hereby
defined as well. Port 1 and 2 are located on the two surrounding box sides intersecting the
feed lines and are wide enough to launch the quasi TEM mode. Ports can be as wide as
the side.
Then the simulation setup allows solving for the port solution only. A fast result is
obtained and the field can be compared to the expected TEM one. The port impedance
should be 50. Later the solution parameters for the complete field are specified for a full
35
frequency range, a meshing frequency, an accuracy coefficient, a number of passes, and a
computational method (fast or discrete).
Based on the Finite Element Method, the software forms a mesh of the entire
geometry at a specified frequency and refines the number of cells, also called tetrahedras,
until the accuracy of the field matches the tolerance restricted by the accuracy coefficient.
For optimum results, the specified frequency corresponds to the fimdamental mode when
the maximum field is present in the cavity. The mesh is particularly dense at location
where the gradient of the field is high (like inside the cavity near the coupling slots) and
less dense in the PEC material where the field vanishes.
After several passes, the software exploits the resulting accurate meshing to
compute the field on each tetrahedra of the mesh for each specified frequency. Using
either the discrete or the fast sweep method, the field is either computed at each
frequency or generated using a Fast Fourier procedure based on the Fade method. The
benefit of the fast sweep is an improvement in the computation time and a possibility to
plot the 3D field on the geometry at each frequency. Unfortunately the method requires
high memory resources and high-density mesh can not be handled unless the discrete
sweep is applied. Therefore solving only for the meshing frequency brings the necessary
feedback before a longer simulation.
Finally the post-processing environment gives an overview of the device response
and the various parameters. 2D plots such as S parameters, phases. Smith charts, time
domain and also 3D plots on the geometry give good understanding of the device [cf.
36
Appendix A]. Animation of the field by displaying several constant phase pictures of the
field for various values of the phase helps visualizing the power flow.
Several simulations are run to determine the sensitivity of the device due to
changes of the coupling slot dimensions, shape and position, the length and the angle in
the bending of the stubs, and the presence of air gaps around the loading material. Macro
usage helps in this task [Appendix A].
According to simulations [Annex 2], the coupling slot position affects the
resonant firequency and the roll off. Closer to the center, along the cavity length, the
frequency shifts up and the roll off gets sharper at the price of an increased insertion loss.
Closer to the edge the roll off gets poorer and the resonant frequency shifts down. On the
other hand the insertion loss is reduced. Positioning the slot a quarter cavity length away
from each edge gives a satisfying tradeoff for roll off, resonant frequency and insertion
loss. A possibility of fine-tuning arises from this parameter making an extra size
reduction possible. Also, when the cavities get smaller and radiations tend to limit the
coupling from the feed into the cavity, a position closer to the edge reduces this effect.
Increasing the slot length and width generate stronger coupling and less insertion
loss but also wider bandwidth. The cavity looks electrically wider as well, which
decreases the resonant frequency. Choosing a length about half the cavity width, and a
length to width ratio of ten for the slot is a compromise for acceptable coupling and
bandwidth.
37
Even though the slots were assumed to be rectangular, their slot shape can be
optimized according to the field pattern. A maximum magnetic field is noticeable close to
the two width sides of the slot, at the extremities. This active area can be increased to
form a bone shaped slot and the former rectangular slot width can be decreased to keep
the slot area constant or even smaller. The consequence is an increase of the coupling.
The description follows on Figure 2-7.
Bone shapes
Figure 2-7 H and bone shape coupling slots
The quarter-wavelength stubs in the feed need to be adjusted in order to prevent
collision or coupling among each other. Bending the stubs with a 90° angle requires a
tapered side in order to smooth the transition. Recommendations [11] propose a ratio
between tapered side and microstrip line width of 1.8. Nevertheless, simulations show
very little sensitivity to this parameter.
Finally, due to tolerances, air gaps are likely to occur during fabrication.
Simulations show the strong impact when an air gap occur on the top, between the feed
and the cavity wafers. The resonant fi'equency shifts higher around 14 GHz for a 100 pun
38
gap. Air gaps on the side produce little effects. This result is expected when looking at
the field distribution, which show a maximum at the center of the cavity.
2.4. Fabrication
The sensitivity of the design to the loading material confers an importance to its
parameters. Parameters, namely permittivity and loss tangent, should be measured first to
ensure maximum similarity with the simulation which can be changed accordingly.
For the permittivity, a capacitor is fabricated by metallizing two sides of a
quadrilateral piece of the material to be tested. The area should be known accurately,
chosen not too small and the thickness of the piece limited as possible in order to reduce
the edge effect.
The expression of the capacitance is:
h
Where A and h are the material area and thickness, respectively. Once C is
measured with the precision LCR meter HP 4284A, the permittivity is extracted and
compared to expectation. For the BST, Sr of 69 instead of 70 is found corresponding to
1.4 % error at 1 MHz.
For the alumina. Figure 2-8 shows an Sr of 9.8 and measured with the HP 429IB.
The equipment also allows loss tangent measurements. Before metallization tan(5) =
0.0002 is obtained. Figure 2-9 shows a higher value due to the metal coverage and is
reproduced for information.
39
Freq [MttJ
Figure 2-8 Permittivity measurement
00020
00018
oxioie 00014
r 0D012 8> £ 00010 M
^ 00008
00006
00004
00002
ODDOO 10 0 200 30 0 400 50 0 800 70 0 80 0 800 1000
FrcqCMIt]
Figure 2-9 Loss tangent measurement
40
For any metallization process, care is given to the skin depth. The metal thickness
on the cavity walls has to overcome the penetration of the field, which decays by 37 %
after one skin depth.
With Gold coverage 6 = 2.6 [om at 5.8 GHz. Practically, three skin depth are
used. This rule is applied for any metallized surfaces and particularly for the coating of
the loading material. As a matter of fact, experiments have shown poor insertion loss
results when rel5^g on the cavity wafer to confine the field in the dielectric material with
the type of silicon fabrication presently used.
This is simply explained. In the fundamental mode, the electric field is maximum
at the center of the cavity where the top wafer presents an uneven electrical surface due to
the presence of the Silver Epoxy filled via surrounded by a Gold ground plane. The lossy
Silver Epoxy (c = 2.5.10^ S.m'^) constitutes a leakage area. On the other hand, the slope
of the cavity walls is expected to be less affecting (cf. 4.3).
The above suggests a full metallization of the filling material despite the location
of the two coupling slots. Electrically, the material acts as the resonant cavity and the
cavity wafer provides a carrier and a package with alignment marks.
Leakage at the interface of the feed and the cavity wafer represents also an
important issue that is overcome during the bonding. For the Duroid® process, clamping
tightly the circuits together ensures high pressure between the boards. For the silicon
41
wafer, the via fabrication involves Silver Epoxy edges coming out of the feed for DC
contact. They shall be limited as much as possible. The moimting at 10 kg/cm^ pressure
and 100°C baking of the Silver Epoxy paste completes the fabrication. Note that the
clamping might damage the ceramic in the Duroid® case.
Via width presents another issue: simulations show drastic increase of the
bandwidth when vias are made wider. Due to capacitive effects Af is enlarged by 15 % if
the via width increases from 300 [jm to 500 |J.m.
2.5. Measurements
The calibration of the equipment represents the first step of a measurement. It
consists of deembeding the losses and the phase distortion of the system up to a reference
plane defined by the user. Two main methods allow calibrating the Network Analyzer:
the SOLT method and the TRL method.
The Short Open Load Thru method is applied to deembed up to the connectors or
probes used in the measurement. A short, an open, a load and a thru are measured and the
response is automatically compared to the prerecorded one in the analyzer. The
calibration coefficients are computed from the variation and are stored in the memory.
Each measurement is corrected and displayed.
An SOLT caUbration does not take into account the losses due to the circuit,
particularly along the line and in the probe to circuit transition. Therefore, it is usefiil to
measure the insertion loss of an additional line the same length as the feeding line.
42
This measurement provides the constant loss added at any given frequency by the
line and the transition. It is removed by applying: dB(^Sn^^aevice))~^^^^^yaine)) (^®)-
The Thru Reflect Line method allows deembeding up to a reference plane located
on the wafer. The length of the reflect and the thru correspond to a section of open and
thru line one and twice the distance up to the reference plane, respectively, hi this work,
it will be the center of the coupling slots. Finally the line is defined a quarter wavelength
longer than the thru at 5.8 GHz.
hi our study, the precision of the TRL calibration is dedicated to silicon wafer
measurements. The accuracy and the presence of a CPW-microstrip Une transition justify
going into the longer process of the TRL calibration technique.
Once the caUbration is done, the feed is tested with a cavity where the loading
material is removed. Having an air filled cavity instead, simplifies the number of issues
which might cause the device to fail. If the results agree with the expected shift in higher
frequency due to air, a good starting point has been obtained and the feed is validated. As
an example, removing the BST from the 7 x 3.5 x 1 mm^ cavity will shift the resonance
to 44 GHz, while for the alumina cavity (18.47 x 9.58 xl mm^) it is shifted to 17.3 GHz.
An estimation of how the power distributes in the device can be an efficient tool
to separate the cause of failure. The power budget links the S parameters to the
percentage of power reflected, transmitted and radiated. High insertion loss typically
points out radiative power either through the cavity or in the feed. Radiations in the feed
can be observed by using a metal sheet to cancel the waves going through and to modify
43
the response. None modified response involves leakage in the cavity, either at the
interface feed and cavity wafer or through the cavity walls. At the interface, the bonding
is responsible; for the cavity walls, the metal coverage is either incomplete, or not thick
enough, or too lossy. The power budget is computed firom the measurement of the S
parameters:
Power reflected at port 1 is: = 10~''^"''''°.100%(11)
Power reflected at port 2 is: 100% (12)
Power going from port 1 to port 2 is: = 10"''^-'"'°. 100% (13)
If S^^ =S22,Piost to smallest value. If iS",, the
device is not symmetrical from fabrication. The feed presents an error or the cavity is
badly aligned. In this case, one port is better matched than the other one. The restriction
comes from the poorest port adding extra failures to the device. The expression of the
radiative power is:
= Minimum{P^,P^)- P^y (14) and has to be minimized.
The loaded quality factor is computed from the ratio of the resonant frequency
over the 3dB bandwidth. From the insertion loss and the previous value, the external
quality factor Qe is deduced. Finally, the unloaded Q is obtained from Qe and Qi.
Mathematically this is expressed in three equations as follow.
44
S„(rfB)=201og(^) (17)
_L 1_
a Q.
(18)
The numerical value of expression (18) has to be linked with the theoretical value
in 2.2. Experimental and mathematical results are compared for error and similarities.
Then, in order to get a direct measurement of the unloaded Q, it is necessary to produce
the largest external Q possible. This lowers the impact of the feed on the entire structure
and allows measixring the cavity and only the cavity. It is made possible by coupling little
energy in the cavity and is referred as a weak coupling measurement.
45
2.6. Results and Conclusions
Important tools and techniques were outlined in Chapter 2. First, several
parameters from the equations are emphasized:
• Electrical parameters like wall conductivity need to be maximized, loss
tangent should be minimized, 8r should be chosen according to frequency of operation for
best miniaturization efficiency keeping in mind that very high permittivity materials yield
lower quality factor at high frequency. Therefore these materials are suited particularly to
low frequency applications. Low permittivity materials are more convenient at high
frequencies for miniaturization and good quality factor.
• Geometrical parameters such as width and length should be adjusted to
form square or cubic cavities according to the frequency of operation. The height will
increase the quality factor with restrictions due to the loss tangent, the technology used
and the minimum of the two remaining cavity dimensions.
Then several parameters arise from simulations:
• Slot size and position control the coupling. Rule of thiunb is a half cavity
width for the slot length, a width equal to a tenth of the slot length, and a position a
quarter cavity length away from edge. Bone shape is a good alternative to improve
insertion losses.
46
• Stubs or vias can be implemented in the feed for electrical or physical
shorts above slot location. Vias remain a more complex technology.
In fabrication a relevant preparation work consists of measuring as many
accessible parameters as possible. Care should also be given to the skin depth. During
measurements, power budget and calibrations help to get accurate information from any
circuits.
These tools and techniques will be implemented in Chapter 3 and Chapter 4, in
order to provide efificient progress toward effective filter design.
47
3. CAVITY RESONATOR FILTER ON DUROID
3.1. Introduction
The work of Chapter 2 is implemented experimentally on rectangular and square
cavities in this chapter. Loading materials are Duroid®, alumina £ind BST [12]. The
Duroid® is soft, therefore easier to handle, but presents high dielectric loss like the BST
(0.0023 and 0.0024 respectively). In comparison, the alumina is very low loss (0.0002)
but very rigid and difficult to machine.
The following sections describe the different configurations explored, and the
effect of parameters change on the response. Measurements were done using the HP
8720C Network Analyzer using a 800 point SOLT calibration.
3.2. Principles
As mentioned before, the dielectric material sits in a cavity machined in an
Aluminum block by EDM machining. The Aluminum is advantageous for price, high
conductivity and relative smoothness for machining. Machining tolerances add 0.005
inch for the radius of the right angles in the cavity [Appendix H ]. The feed is made using
a Roger Duroid® board which is attached later on the Aluminum block with Nylon
screws.
48
3.3. Fabrication Techniques
3.3.1. Feed fabrication
Table 5 describes the nine steps for the fabrication of the feed (see Figure 1-2).
Legend
HHUHUHH Duroid® + Copper
Protect back with tape - Spin PR on top
BSiiiiiHHiHI Expose top mask
Etch copper
Remove tape and PR
MMUJfaiiiUkiy Drill alignment holes - tape the top
Spin PR on the back
Align and expose mask on the back using holes
miiiiiiPBiiVP Etch Copper - Remove PR and tape
Table 5 Duroid® feed wafer process
49
The feed wafer is printed on Roger Duroid®, 635 |im thick, using the lithography
process previously described and explained in more details in Appendix D and E.
Microstrip lines are 563 |im wide and an additional one is printed to estimate the losses
occurring in the feed and connectors.
A weak coupling feed is fabricated for accurate Q measurement by narrowing the
coupling slots or mismatching the line to the port. In the later case, the microstrip line
width is reduced from 563 jim to 400 |^m.
Once the lithography has been performed, vias are drilled at the end of each
microstrip line. A thin conductive wire is inserted thru the via and soldered on the ground
and at the end of the line.
3.3.2. Cavity wafer fabrication and assembly
Fabrication is based on EDM process. Cavities are machined in a 7.6 cm^
Aluminum block receiving connector support for 3.5 mm SMA ones [Appendix H].
The feed is then mounted on the Aluminum block, aligned using alignment holes,
then attached with nylon screws. Di addition, a piece of wood is clamped above the feed
to increase the pressxire.
3.3.3. Dimensions of the filter-resonators
The dimensions of the Duroid®-alumina cavity feed and the BST cavity feed are
shown in Figure 3-1 and Figure 3-2. Units are in mm. The BST was implemented in
rectangular and square configuration Figure 3-3.
50
Cavity with material
Microstrip feed line 17.47
Figure 3-1 Duroid®-alumina cavity - feed dimensions (stubs) - Duroid® process
Figure 3-2 BST cavity - feed dimensions (stubs) — Duroid® process
1
IO:
Figure 3-3 BST feed dimensions (vias)
Microstrip feed line Nylon screws
SMA connector
7.6 cm ~ ^ Bsx
Figure 3-4 Duroid® device under test
52
3.4. Measurements
3.4.1. The 17.47 x 8.78 x 0.93 mm^ cavity filled with Roger Duroid® Sr = 10.8, tan(5) = 0.0023 with EDM - stub solution
The S parameter charts for optimal coupling are shown in Figure 3-5, Figure 3-6
and Figure 3-7. They show a 2.48 % or 137.5 MHz bandwidth at 5.53 GHz and 2.2 dB of
insertion loss. The noticeable difference between S12 and S21 is due to a default in the
calibration. The S parameter results for weak coupling are shown in Figure 3-8 and
Figure 3-9. Finally, the TE102 mode in Figure 3-6 is only present in the experimental
response and is absent of the simulation. This mode has high insertion loss. It underlines
the risk of mode skipping when using HFSS.
S11 vs. frequency. Best coupling simulated and measured daias. 17.5x8.8x0.93 mm cavity loaded with Duroid.
0
-10
-20
-25
-30 2
meas. simu.
3 4 5 6 7 8 9 10 11
Frequency (GHz)
Figure 3-5 Sn Duroid® cavity response
53
S2l vs. frequency. Best coupling simulated and measured datas. 17.5x8.8x0.93 mm cavity loaded with Duroid.
-10
•20
-40
-50
-60
7 8 9 3 5 6 10 2 4 11 1
- simulated Frequency (GHz)
measured
Figure 3-6 S21 Duroid® cavity response
S param. vs. frequency. Best coupling measured datas (detail). 17.5x8.8x0.93 mm^ cavity loaded with Duroid.
-2
S22 s:i S12
S21
6.2 6.4
Frcqueacy (GHz)
Figure 3-7 Duroid® cavity response (detail)
54
S2l vs. frequency. Weak coupling measurement. 17.5x8.8x0.93 mm^ cavity loaded with Duroid.
-10
-20
-40
-50
10 2 3 9 1 1 4 5 6 7 8 1
Frequency (GHz)
Figure 3-8 Duroid® cavity weak coupiing
S param. vs. frequency. Weak coupling measurement (detail). 17.5 X 8.8 X 0.93 mm^ cavity loaded with Duroid 10.8.
-10
-20 a
-40
-50
4.S 5.0 6.2 6.4 5.2 5.4 5.8 6.0 4.6 5.6
221 Frequency (GHz) SI 1
Figure 3-9 Duroid® cavity low coupling (detail)
55
Figure 3-9 shows a 28.6 MHz bandwidth at 5.68 GHz and 17 dB of insertion loss.
This leads to Qi = 198.6 and Qu = 232. The frequency shift (5.53 to 5.68 GHz) can be
explained by the cavity looking electrically smaller with narrow slots which is the
condition of weak coupling.
Differences between Figure 3-8 and Figure 3-9 arise from the clamping
conditions and a more accurate calibration in the second case.
3.4.2. The 17.47 x 8.7 8x 0.88 mm^ cavity filled with Coors® alumina 8r = 9.8, tan(5) = 0.0002 with EDM - stub solution
The S parameter charts for optimal coupling are shown in Figure 3-10 and Figure
3-11.
Figure 3-12 shows a 2.23 % or 137.5 MHz bandwidth at 6.1625 GHz and 2.283
dB of insertion loss. From the loss along the line, 1 dB should be removed therefore
1.283 dB of insertion loss is achieved. The S parameter charts for weak coupling are
shown in Figure 3-13 and Figure 3-14. They show a 18.2 MHz bandwidth at 6.16 GHz
and 18.9 dB of insertion loss. This leads to Qi = 338 and Qu = 382.
56
S param. vs. frequency. Optimal coupling measured datas. 17.5 X 8.8 X 0.88 mm^ cavity loaded with Alumina.
0
-10
-20
a
£ -30 es 8 Q.
00 >40
•50
•60
2 3 4 5 6 7 8 9 1 0 1 1
Frequency (GHz)
Figure 3-10 Alumina cavity measurement
S param. vs. frequency. Optimal coupling measured datas (detail). 17.5 X 8.8 X 0.88 mm^ cavity loaded with Alumina.
-20 - - — - - - -• -
-22 —
-24 - •
26 ^
-28 -1 , , , 1 , , > 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6
|2? Frequency (GHz)
Figure 3-11 Alumina cavity measurement (detail)
S param. vs. frequency. Optimal coupling simulated and measured datas. 17.5 X 8.8 X 0.88 mm^ cavity loaded with Alumina.
0
-10
-20
-30
-40
-50
-60
Figure 3-12 Alumina cavity simulation
S param. vs. frequency. Weak coupling measurement. 17.5x8.8x0.88 mm cavity loaded with Alumina.
0
-10
-20
-30
-40
-so
-60 10 6 8 9 11 2 3 7 1 5 4
Frequency (GHz)
S11
S12
S22
S11 meas. S21 meas S11 simu S21 simu
9 10 11
Frequency (GHz)
Figure 3-13 Alumina cavity weak coupling measurement
58
S param. vs. frequency. Weak coupling measurement (detail). 17.5 K 8.8 X 0.88 cavity loaded with Alumina.
0
-10
-20
-40
-so
-60
f
Figure 3-14 Alumina cavity weak coupling measurement (detail)
3.4.3. The 4.1 x 4.1 x 0.25 mm^ cavity filled with Paratek® BST 8r = 70, tan(5) = 0.0024 with EDM - stub solution
The S parameter charts for optimal coupling are shown in Figure 3-15 and Figure
3-16. In comparison with previous cases, this cavity is much thinner therefore increased
bandwidths are expected.
The optimal coupling in Figure 3-15 shows 17.89 dB of insertion loss at 5.6375
GHz. The 3 dB bandwidth was not measurable. It is reproduced for information and will
be commented in 3.5. Figure 3-16 is the corresponding simulation. The resonance occurs
at 5.7047 GHz and presents 12.7 dB of insertion loss.
521 S11
522
6.2 6.4 6.6 6.8 7.0
Frequency (GHz)
59
4.1x4.1x0.25 BST cavity - z ~ 1 0 - stubs - measurement
0 ^
Frequency (GHz)
S12
S22
Figure 3-15 BST square cavity measurement (stubs)
4.1x4.1x0.25 BST cavity - £^=70 - stubs - simulation
-5 -
-10 -
-IS
-20
-25 -
-30
-35
-40
-45
) V,
\ I ... Li--. \} w
1 2 511
S21
512
• S22
9 10 11
Frequency (GHz)
Figure 3-16 BST square cavity simulation (stubs)
60
3.4.4. The 4.1 x 4.1 x 0.25 mm^ cavity filled with Paratek® BST Sr = 70, tan(5) = 0.0024 with EDM - via solution
The S parameters for optimal coupling are shown in Figure 3-17 and Figure 3-18.
4.1x4.1x0.25 BST cavity - z=10 - vias - measurement
0 -p-
-5 -
-10 --15 - -
-20 - -
.25 - -
^ -30 - -
i" -35 - -
1 ^5 -c. .50 - —
^ -55 -
-60 - -
-65 -
-70 -
-75 -
-80 - -
-85 - —
1
V
2 511
521
512
522
9 10 11
Frequency (GHz)
Figure 3-17 BST square cavity measurement (vias)
4.1x4.1x0.25 BST cavity - e=70 - vias - simulation
0
-5 -
-10 -
-15 -
-20 -
-25 -
-30 -
a -35 -
-40 c F -45 .
a -SO C/5 -55
-60
-65 -
-70 -
-75 -
-80 -
-65
-/-V —-/
2 S11
S21
S12
- - S22
9 10 11
Frequency (GHz)
Figure 3-18 BST square cavity simulation (vias)
61
Figure 3-17 shows a 400 MHz bandwidth at 5.675 GHz and 8.255 dB of insertion
loss. The loss along the line is 1.61 dB at 5.6 GHz. After correction the insertion loss is
6.645 dB. It is reproduced for information and will be commented on 3.5. Figure 3-18 is a
simulation for a similar configuration showing a 100 MHz bandwidth at 5.835 GHz and
5.75 dB of insertion loss. The corresponding quality factors are 26.5 for the experiment
and 120 for the simulation.
The coupling mechanism can be enhanced using wider slots. Previously, 2 x 0.2
mm^ were used. Measurement in Annex 2 shows the effect of increasing the slot area (2.8
X 0.36 mm^): the retum loss and the insertion loss get lower and the resonance frequency
shifts down.
3.4.5. The 7 x 3.5 x 0.25 mm^ cavity filled with Paratek® BST 8r = 70, tan(5) = 0.0024 with EDM - via solution
The S parameters for optimal and weak coupling are shown in Figure 3-19 and
Figure 3-20. Each plot corresponds to a different piece of BST material.
62
7x3.5x0.25 BST cavity - £,=70 - vias - measurement
2dO
•4d0
•«dO
-UdD
2dO
•4d0
•«dO
-UdD
2dO
•4d0
•«dO
-UdD
2dO
•4d0
•«dO
-UdD
^^ ""
2dO
•4d0
•«dO
-UdD
^«?aa •72 «
2dO
•4d0
•«dO
-UdD
2dO
•4d0
•«dO
-UdD
2dO
•4d0
•«dO
-UdD
V /
-M >aaQ« aaaiK^iiiM aw itou
Figure 3-19 BST rectangular cavity optimal coupling measurement
Figure 3-20 BST rectangular cavity weak coupling measurement
63
Figure 3-19 shows a resonant frequency at 8.3 GHz. Obviously, the effective
dielectric constant of the material is significantly lower than the expected 70, probably
around 33. It is most probably caused by the presence of an air gap. Nevertheless the
bandwidth is 354 MHz and the roll-off is lower than in the previous case. The insertion
loss attain 5.62 dB and the quality factor reach 50.3. In this fabrication, because the
cavity is placed close to one of the connectors, the lengths of the two feed lines are not
equal. A standing wave pattern arises in the long branch which is several Xeff long and
causes the observed ripples in 822-
This phenomenon is also visible for Si 1 and S22 in the square configuration which
has a symmetric feed; it gets more visible with frequency. The standing wave pattern is
initiated by the multiple reflections due to small mismatch at the connectors and at the
end of the line (via or stub). For the square configuration, the feed lines are 34.45 mm
long whereas Xeff = 20 mm at 5.6 GHz. Using a line shorter than A-cff could reduce this
effect.
Figure 3-20 present the measvirement of another BST cavity in a weak coupling
configuration. It shows a 47 MHz bandwidth at 5.82 GHz and 30 dB of insertion loss.
This leads to Qi = 124 and Qu = 128.
64
3.5. Interpretations of Measured Results
3.5.1. The 17.47 x 8.78 x 0.93 mm^ cavity filled with Roger Duroid® Sr = 10.8, tan(5) = 0.0023 with EDM - stub solution
Comparison with theory is shown in Table 6.
Theory (HFSS) Experiment Error % Resonant firequency (GHz) 5.73 5.53 3.5 Insertion loss (dB) -1.83 -2.2 20 Bandwidth (MHz) 105 137.5 31 Unloaded Q 270 232 14
Table 6 Summary of Duroid®/Duroid(S) cavity results
Table 6 shows good agreement between theory and experiment, taking into
account the low accuracy of the fabrication technique and the tolerance on the dielectric
constant. The latter is 10.8 ± 0.05 which potentially shifts the resonant firequency. The
fabrication explains the difference in the loss, bandwidth and quality factor.
65
3.5.2. The 17.47 x 8.78 x 0.88 mm^ cavity filled with Coors® alumina Er = 9.8, tan(5) = 0.0002 with EDM - stub solution
Comparison with theory is shown in Table 7.
Theory (HFSS) Experiment Error % Resonant frequency (GHz) 6.1 6.16 1 Insertion loss (dB) -2.5 -1.28 NA Bandwidth (MHz) 40 137.5 243 Unloaded Q 624 382 38.7
Table 7 Summary of alumina/Duroid® cavity results
The error in the resonant frequency of the optimal coupling comes froa poor
bonding and misalignment. The increase of the bandwidth and the decrease of the quality
factor are explained by the low accuracy fabrication technique, particularly leakage in the
side walls. The insertion loss from simulation is significantly lower than the experiment
and it is explained by a wider bandwidth in the measurement. In addition, computational
error might occur. Better fabrication technique is expected to enhance the bandwidth and
the quality factor.
66
3.5.3. The 4.1 x 4.1 x 0.25 mm^ cavity filled with Paratek® BST Sr = 70, tan(5) = 0.0024 with EDM - stub solution
Comparison with theory is available in Table 8.
Theory (HFSS) Experiment Error % Resonant frequency (GHz) 5.705 5.64 1.14 Insertion loss (dB) -12.7 -17.9 41 Bandwidth (MHz) 80 NA NA Unloaded Q 93 NA NA
Table 8 Summary of BST/Duroid® square cavity results (stubs)
This first measurement with square cavity presents similarities with previous
weak coupling measurement despite a wide bandwidth most probably caused by
inaccurate fabrication techniques. Close to the resonant frequency, the left side of the
response is very sharp and deep whereas the right side smoothly drops to a plateau, 15 dB
lower. The insertion loss is important and suggests that energy is being radiated into the
feed from one line to another. This radiated field, previously fringing field, is not coupled
through the slots but transmitted in the opposite line. In the model, these radiation losses
are present as a capacitor, which links the two transformers (cf. 3.6). Finally, the
fabrication difficulties increase with the small dimensions and the performance tends to
reduce.
From this conclusion, it is necessary to increase the 800 jjm gap between the two
feed lines. The stubs, despite simple fabrication, are inadequate. In order to reduce
radiation loss vias are implemented in the next step.
67
3.5.4. The 4.1 x 4.1 x 0.25 mm^ cavity filled with Paratek® BST Sr = 70, tan(6) = 0.0024 with EDM - via solution
Theory (HFSS) Experiment Error % Resonant frequency (GHz) 5.84 5.68 2.7 Insertion loss (dB) -5.75 -6.65 15.6 Bandwidth (MHz) 100 400 300 Unloaded Q 120 26.5 78
Table 9 Summary of BST/Duroid® square cavity results (vias)
In Table 9, despite the resonant firequency. Figure 3-17 and Figure 3-18 present
significant disagreements in the performance, particularly in the bandwidth. It is likely
caused by high loss due to the geometry getting too small for the type of fabrication and a
lossy Silver Epoxy layer used under the BST to prevent air gaps [Annex 2].
In the simulation, the theoretical quality factor is lower than the expected 140, the
reason is the length of the line which adds loss. It should also be noted that the expected
resonant frequency from equation (2) is 6.18 GHz. The shift visible in simulation and
experiment is caused by the perturbation of the slots which occupy 4.8 % of the top
surface with a permittivity seven times less than the filler. Therefore, the cavity looks
electrically different than a perfect 4.1 x 4.1 x 0.25 mm^ cavity (*).
Implementation of a rectangular shape follows. It allows the increase of one of the
cavity dimension which makes fabrication easier. The cavity surface gets wider (24.5
instead of 16.8 mm^) and the slot impact on the response is reduced (3.26 % surface
occupancy versus 4.8 %).
(*) Note: Since feed and filler have little permittivity difference, this effect is less visible in the Duroid® and alumina previous measurements.
68
3.5.5. The 7 x 3.5 x 0.25 cavity filled with Paratek® BST Sr = 70, tan(5) = 0.0024 with EDM - via solution
Comparison with theory follows in Table 10.
Theory (HFSS) Experiment Error % Resonant frequency (GHz) 5.715 5.82 1.8 Insertion loss (dB) -3 -5.62* NA* Bandwidth (MHz) 84 354* NA* Unloaded Q 138 128 7.25
Table 10 Summaty of BST/Duroid® rectangular cavity results
The optimal coupling had poor performance due to an air gap which shifted the
resonant frequency to 8.5 GHz. Since Figure 3-19 shows no resonance at 5.8 GHz, the
gap might occiu: on the bottom side of the cavity (see Annex 2). Consequently, the
resonant frequency of the weak coupling is reported in Table 10. Higher precision
fabrication is expected to enhance the results.
On the weak coupling measurement (Figure 3-20), line and port were mismatched
by narrowing the line up to 400 jam (560 f4.m previously) and only little pressure was
added. The error on the resonant frequency is acceptable in contrast to the fabrication
technique and the 1.4 % tolerance on the dielectric constant. From equation (2), the
resonant frequency is expected to be 5.73 GHz, the slot effect is therefore reduced.
Finally, the quality factors show good agreement between theory and experiment.
(•) value not corresponding to the same resonant frequency.
69
In conclusion for the BST cavity, when using stubs, the spacing between them
must be controlled in order to avoid radiation. The square and the rectangular BST cavity
do not permit enough spacing; therefore the via solution is implemented to provide the
required shielding of the field. Figure 3-21 and Figure 3-22 present the simulation for
alumina where the electric field crosses the empty space between the stubs and the
shielding effect when implementing vias. This effect is stronger in the BST case whose
responses are in Figure 3-23 and Figure 3-24 as seen by the reduction of insertion loss.
In the search of possible improvements, the simulations show that adding an air
groove after the stubs does not prevent coupling in the feed while adding a vertical PEC
wall instead only slightly improves the insertion loss while maintaining the roll off. Vias
remain therefore the best configuration.
Finally, the slot size can be a performance limitation when the feed and the filler
are chosen with very high permittivity for the filler and low permittivity for the feed.
Figure 3-21 Electric field in the alumina cavity feed (stubs)
Figure 3-22 Electric field in the alumina cavity feed (vias)
71
BST Cavity - simulation with stubs
9 10
Frequency (GHz)
Figure 3-23 BST cavity simulation with stubs
BST Cavity - simulation with vias
•-> ' i\ n ^—-
i •. \
- / K - /
\ i
/ '
. . . .
!i i]
1 1 — t — •
Frequency (GHz)
S12
S22
Figure 3-24 BST cavity simulation with vias
72
3.6. Model
3.6.1. First mode basic model
With the use of PSPICE and previous measurements (cf. 3.4), the RLC model in
Figure 3-25 shows the model of the device for the first resonant frequency.
1
PARAMETERS:
Lvalue 1n Cvalue 0 78p lOcouple 15
TX4
PARAMETERS PARAMETERS;
Loss 0.5
C11
Cvalue 1
Cvaiue2
Cvalue3
{Lvalue /3}
{CvalueS}
C3 R3
^1 VA— {Cvalue} {Loss}
TX5
0 0 lOQOu
R6
A-W-50
'0
Figure 3-25 Basic resonator PSPICE model schematic
Plotting the ratio of the output voltage and the input voltage on decibel scale
produces the response shown in Figure 3-26. Parameter L3 and C3 adjust the resonant
f r e q u e n c y . R 9 r e p r e s e n t s t h e l o s s a n d a f f e c t s t h e b a n d w i d t h a n d t h e i n s e r t i o n l o s s . C l l
increases or decreases the amount of radiation/coupling in the feed. TX4 and TX5 are
two transformers modeling the slots and their coupling efficiency is adjusted with
lOcoupIe parameter. R2 and R6 correspond to the two 50 Q feed lines. Figure 3-27 and
Figure 3-28 show the effect of increasing parameter R9(Loss) from 0.5 to 2 Q and
increasing parameter CI l(Cvalue3) from 1000 to 5000 (xF.
73
•tr
.20-
'31
SCHZ 68Hz •CHz ICHz 2CHZ X 2^1og-lO(U(R6:l)/ U(R2:2)) 116Hz
Figure 3-26 Basic resonator PSPICE model response
R9 (loss)= 0.5 Q R9 (loss)= 2 Q. C l l = lmF
-10-
•20-
-3t-
6CHZ ICHZ 5CKZ 76HZ 96HZ 11CHZ 2CMZ SCHZ o 2l*log1t(U(R6:1)/ V(R2:2)}
FrMUIMICM
Figure 3-27 Effect of parameter R9(Loss) on the basic resonator response
74
fiCKZ tCHZ ICHz
Cl l =5mF
Figure 3-28 Effect of parameter Cll{Cvalue3) on the basic resonator response
Compared to the reference (Figure 3-26), Figvire 3-27 shows the impact of
increasing the loss parameters: high loss tangent, low conductivity of cavity walls, low
resistivity of the silicon, lossy via configurations, mismatch of the line to the port
impedance tend to follow this trend. Figure 3-28 presents the configuration where a
strong parasitic capacitance occurs in the feed. It appears during weak coupling
measurement, or when stubs are to close to one another.
3.6.2. Three mode model
Cascading several blocks in parallel produces the higher order modes present in
the experimental response. Figure 3-29 presents the corresponding schematic. The
response follows in Figure 3-30.
75
Ctl
1 1 — (Cvalu«} {L.0SS} C70
CIO (Oralu *3 m o d *2] C13 R-t4 {Cmod*2} {Le«smed«2}
Q<y
Cv«iu«3mod«2 lOOu ia«oupi«2 .IS
{Cv«lu*3mod«3) TX10 II CCmod«3} tLo«BTiede3} -vw-
o<I-
Figure 3-29 3-inode resonator PSPICE model schematic
2I-
7r IICHS 1CHZ smz 7QHZ 9CKZ 29«logll(U<n9£l)/ UCR2:2)) Frtouencu
Figure 3-30 3-mode resonator PSPICE model response
76
The resonant frequency is 5.79 GHz, with —1.08 dB insertion loss and 65.4 MHz
bandwidth. Additional capacitor (Cvalue6) in the range 0.1 to 1 pF, parallel to the
transformers, models the slots position effect; 0.1 pF produces 5.7 GHz with Af = 60
MHz 0.5 pF gives fr = 5.4 GHz and Af = 49.3 MHz, 1 pF correspond to fr = 5.05 GHz.
0.001 pF has no effect and models the standard position (25% of cavity length). These
capacitors are also reducing the insertion loss, this can be corrected using the lOcoupIe
parameter which affects very little the bandwidth and resonant frequency. In addition to
the capacitors, an extra mode in the higher frequency range appears which reduces the
accuracy of the model above 15 GHz.
PSPICE parametric sweep gives the trend for increments of lOcouple, Cvalue3,
Cvalue6, and Loss. The corresponding plots follow on Figure 3-31, Figure 3-32, Figure
3-33, and Figure 3-34. Table 11 provides the parameter values used in the corresponding
plots.
Parameters lOcouple Cvalue6 Cvalue3 Loss Range 0.2 to 0.4 0.01 pF to 1 pF 1 |iF to 20 mF 0.3 to 3.8
Increment 0.05 0.2 pF 5 m F 0.5
Table 11 3-mode resonator PSPICE model — parameter change
77
-y-
-ie-S
1CHZ 7CHZ
Figure 3-31 Effect of parameter lOcouple on the 3-mode resonator response
zr
ii-
0.01 pF
6B'
?*• SCHZ 1CHZ 2CHZ SCHZ 7CHZ
Figure 3-32 Effect of parameter Cvalue6 on the 3-mode resonator response
78
20 mF
-70-3CHZ U(lt2:
7CHZ 16HZ • 29«l09lt{U(R19n)/ U(lt2:2))
6CKZ •6KZ 9CHZ •HZ 5CHZ
Figure 3-33 Effect of parameter Cvalue3 on the 3-mode resonator response
Q2
ItfiMZ 2CHZ 3CHZ X A r t o 2»«logll(U(f(l9:l)/ UCR2:2))
7CHZ 1CHZ o • SGHZ 6CKZ 9Cf(Z :l)/
Figure 3-34 Effect of parameter Loss on the 3-mode resonator response
79
3.6.3. Summary and enhancement of the model
Table 12 presents the correspondences between model and experimental
parameters.
Parameters lOcouple Cvalue6 Cvalue3 Loss Range 0.2 to 0.4 0.01 pF to 1 pF 1 |iiF to 20 mF 0.3 to 3.8
Increment 0.05 0.2 pF 5mF 0.5 Plot lower to upper right to left lower to upper upper to lower
Affects mostly 821, bandwidth, roll-off f r ,S2 ,
bandwidth, coupling, roll-off bandwidth, S21
Affects less fr roll-off fr Do not affect fr
Related geometry slot area. slots position smbs too close Vias too close
Related device param. Q, tan(5), cavity height, Er
radiation loss Q, tan(5), cr
Usage/plot opt. coupling tuning weak coupling lossy vias
Table 12 3-inode resonator PSPICE model — parameter effect summary
lOcouple and Loss parameters must be used accordingly in order to produce an
optimal coupling as in Annex 2, Fig.2. 5. This case jdelds wide bandwidth and low
insertion loss, it can be understood as a high coupling with a very lossy cavity. This is
caused by wide slots associated with a poor quality fabrication.
For each of the PSPICE circuit parameter, an equation linking it with the
experiment must be found [13]. Since a satisfying correlation between simulation and
measurement has been demonstrated in 3.4 and 3.5, a large set of results from a batch
processing in HFSS produces enough data points for enough geometrical configurations
to solve the following Nth order polynomial:
K = Oq + + (Z-, -X' + ... + .X"
80
Where Y is the PSPICE circuit parameter and X the experiment variable such as
tan(5), Sr, cs", via size and position etc...Applying a Least Mean Square method allows a
solution for the unknown coefficients an [14].
Although the description of the device with R, L, C elements and transformers
does not exactly match Van Duzer's method [15], it should be added that the slot,
modeled by the PSPICE perfect transformers have a different electric behavior at the
resonance of each mode. Consequently it is necessary to model them separately and
therefore to break the multimode cavity into parallel single mode cavities. By doing this
each mode has less effect on its neighbors and the simulation and measured plots can be
precisely matched.
81
3.7. Conclusions
Chapter 3 presented important experimental results that showed good agreement
between theory, simulation and measurement. The fabrication tolerance explains the
variations. Consequently the first steps of a model were proposed.
So far quahty factors of 380 and 128 were achieved for the alumina and the BST
cavities at 6.16 and 5.8 GHz, respectively. In the latter case, an optimal coupling
measurement was not possible. Square cavities, despite their theoretical good
performance did not yield the expected measurement. This is explained by the increased
sensitivity of the design to fabrication accuracy when decreasing the dimensions.
Therefore, square configurations are not implemented with silicon process in Chapter 4.
82
4. CAVITY RESONATOR FILTER ON SILICON
4.1. Introduction
After the optimistic results of Chapter 3, a more complex fabrication process was
implemented toward the design with silicon Micromachining Techniques. In order to
facilitate the task, the Duroid® prototype was defined so that the electrical and
geometrical parameters would be as close as possible to the silicon one.
4.2. Principles
The foundation of the resonator remains the same as in Chapter 3. In addition, a
CPW to microstrip line transition achieves the conversion of the coplanar mode,
necessary for measuring probes, into the quasi TEM mode of the microstrip line. Since
the transition requires vias, a more complex fabrication technique, this solution is
advantageously implemented in replacement of the stub for the alumina cavity (*).
Moreover, for further reduction of the dimension tolerances, the cavity will be made out
of the dielectric block by metallizing it. Figure 4-1 and Figure 4-2 show the feed and the
cavity wafer. The complete device, including the transition, the vias and all material
losses, is simulated in HFSS (Figure 4-3 and Figure 4-4).
(*) This configuration was implemented but yielded poor results due to coupling in the feed (see Figure 3-21)
Figure 4-1 Feed wafer in silicon
Figure 4-2 Cavity wafer and dielectric material in silicon
84
Figure 4-3 Alumina resonator in HFSS
Figure 4-4 BST resonator in HFSS
85
In the alumina case, virtual objects in the cavity help make the mesh more dense
in the area where the field is expected to be the strongest (see Figure 4-3).
The excitation is provided by a lumped gap source with additional calibration and
impedance line across the port. Ports are located between the begimiing of each
microstrip line and the transition. Their impedance is set to 50 Q.
For best output at lower firequency, the CPW to microstrip line is simulated and
fabricated with vias [Appendix B and H]. Above 10 GHz, vias are not required. Figure
4-6 and Figure 4-7 show the geometry and the simulated response.
Finally HFSS allows plotting of the electric field in the cavity as shown in Figure
4-5.
Figure 4-5 Electric field in the BST cavity
Figure 4-6 CPW to microstrip line transition - geometry
CPW 10 microstrip line transition - HFSS simulation
-5 -
.10
10 11 12 13 14 15 16 17 16 19 20
Frequency (GHz)
Figure 4-7 CPW to microstrip line transition- simulation
87
4.3. Fabrication Techniques
The process requires 4" Chrome masks using a quartz substrate [Appendix B].
One is dedicated to the top feed wafer, two masks are required for the back, and finally
two additional masks are used for the cavity wafer. Since vias and slots can be very close
to each other, the back needs two separate masks to ensure distinct definition so that the
slots do not get engraved during the silicon etch.
Moreover the use of an orientation dependant wet etch of the silicon leaves 54°
sloped walls. In order to match the dimensions for the loading material, the required input
dimensions of the cavity were increased. The feed being a time consuming process, the
corresponding mask maximizes the number of device feeds (6) on a quarter piece of 4"
wafer; the result is the collision of the cavities if they are all etched on the same wafer.
Consequently two separate cavity wafers are etched with two different masks referred as
type A and B.
For the exposure, feed, slots and vias masks are chosen with positive or negative
metallized patterns (clear or dark field) and an emulsion side (up or down). Figure 4-8
renders the slop effect due to etching along the 100 orientation of the silicon crystal.
Metalized dielectric 54 degree angle - 724uni gap
Silicon
feed
Figure 4-8 Silicon resonator structure
88
In addition to the device and calibration patterns, the masks present marks and
windows for visual and infrared alignment. IR is used on the MJB3 to align the vias and
slots masks pattern with the feed lines when fabricating the top wafer [Appendix I].
Visual marks are used when bonding the feed and cavity wafer together. To do so,
windows are etched on the silicon of the feed wafer and corresponding crosses patterned
at the surface of the cavity wafer.
Finally, HP ADS was used for mask layout and generates the requested ".dxf' or
".gds" file format from which the masks are fabricated.
4.3.1. Feed fabrication
Table 14 gives the eleven steps for the fabrication of the feed. The frrst row
depicts the process step.
The parameters for the feed wafer and calibration lines are in Table 13. Unit is mm.
Thru Reflect Line Microstrip line width Wafer thickness Resistivity 8.370 4.185 13.110 0.401 0.5 2 kQ/cm
Table 13 Silicon feed wafer parameters and calibration
89
hhsbbbi Legend
••HiH Si (high resistivity) + oxide •+• Ti/Au/Ti seedlayers
Spin PR on top - Expose feed mask
••••• Etch Ti - Plate Au 3|jin Remove PR - Etch Ti/Au/Ti seedlayers
Spin PR on top and back Expose via mask on back
•HHIH Etch the oxide- Remove PR
Spin PR on the back Expose slot mask (image reversal)
•nwiii Liftoff (1): Evaporate Ti/Au on the back
BHBPiiiii Liftoff (2): Remove PR
mrwiMi Etching the vias Plating Au 3fim on the back
Etching the oxide Plating Au 3 jam on the back
•P^Mi Filling vias with Silver Epoxy
Table 14 Silicon feed wafer process
90
4.3.2. Cavity wafer fabrication
The nine steps are pictured in Table 15.
••••• Silicon (low resistivity) + oxide
Spin PR on top - expose cavity mask (image reversal)
Liftoff (1): evaporate Ti/Au on top
Liftoff (2): remove PR
Etch the oxide 1
1 Etch the silicon
Bond bottom siHcon wafer underneath
Etch oxide
Evaporate seedlayer Ti/Au Plate Au 3(am on top
Table 15 Silicon cavity wafer process
91
The parameters for the cavity wafer are in Table 16 with dimensions in mm.
Height alumina cavity aperture size BST cavity aperture size Resistivity 1 19.923 X 11.033 8.453 X 4.953 low
Table 16 Silicon cavity wafer parameters
The cavity wafer type A contains one alumina optimal coupling location and two
BST locations for optimal and weak coupling. Type B corresponds to one alumina weak
coupling and two BST locations for optimal and weak coupling. For the assembly, the
Silver Epoxy paste, once baked, ensures adhesion between feed and cavity wafer.
4.3.3. Treatment of the dielectric loading material
alumina and BST materials are first diced to the specified dimensions with small
tolerance (<10 jjm) according to equation (2). The material is then thinly pohshed using
standard process applied for silicon wafer polishing.
The very flat surface is cleaned and a strongly adhesive seedlayer of Chrome and
Gold is applied on all the surfaces. Slots are then opened by lithography process and
etching of the metal prior to Gold platting. Detailed processing recipes are available in
Appendix D and F. Laser drilled via is another possible option [16].
4.3.4. Dimensions of the filter-resonators
The dimensions of the rectangular alumina cavity feed with stubs and vias are in
Figure 4-9 and Figure 4-10. The distance between the stubs is 3.2 mm. Dimensions in
mm of the rectangular BST cavity feed are shown in Figure 4-11.
i2.45i
Figure 4-9 Alumina cavity - feed dimensions (stubs) — silicon process
Figure 4-10 Alumina cavity - feed dimensions (vias) — silicon process
93
I i -0.8^ |pl
Figure 4-11 BST cavity - feed dimensions (vias) — silicon process
In addition to each circuit, the corresponding weak coupling structure is patterned.
The slot width decreases from 340 jam to 40 fxm.
4.4. Measurements
Measurements are taken using the HP 85IOC with the probe station after on wafer
TRL calibration is performed. The data is collected with the help of the program
"Multical" available on a PC. Datasets are restricted to 200 points with TRL calibration.
Figure 4-12 illustrate the TRL calibration on the measurement of the thru line.
This part of the circuit gets deembeded through the calibration and the reference point is
at the center of the slots. Figure 4-13 gives an idea of the amount of loss in the coupling
vias.
TRL Calibration - Thru measurement
-10 •
-20 -
-30 -
-40 -
-50 -
-60 -
•100 -I ^—, , , 1 1 1 1 1 —r- —4 1 2 3 4 5 6 7 8 9 1 0 1 1
Frequency (GHz)
S21
Figure 4-12 TRL calibrated thru - measurement
Line terminated by via - measurement
0.0
D 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0
^ ^ Frequency (GHz)
Figure 4-13 Line terminated by via — measurement
95
The response of the feed line and the coupling via is measured to produce the
remaining loss. The measurement is performed after the TRL calibration by applying a
short at the slot location using a metallized silicon wafer. Figure 4-13 shows 0.9 dB of
loss. Finally Multical allows plotting the parameters of the line as can be seen on Figure
4-14. The impedance of the line is 57.6 Q, the effective permittivity is 9.23 and the
attenuation 3.03 dB/cm at 5.65 GHz.
Line parameters - measurement
60
59
56
57
g 56 -
a 9 -• 8 -
7 -6 -
5 -4 --3 -2 -
5.0 5.1 5.2 5.3 5.4 Eeff Z (ohm) Attenuation (dB/cm)
5.5 5.6 5.7 5.8 5.9 6.0
Frequency (GHz)
Figure 4-14 Line parameters - measurement
Due to wafer bonding, it is not possible to repeat a measurement with the same
piece of dielectric material. For this reason potential variations from one response to the
other might arise, particularly between optimal and weak coupling.
96
4.4.L The 18.47 x 9.58 x 1 mm^ cavity filled with Coors® alumina 8r = 9.8, tan(5) = 0.0002 - via solution
The S parameter charts for optimal coupling are shown in Figure 4-15 and Figure
4-16.
Alumina Cavity - Optimal coupling measurement
0 - | — — ^ _ . .
; t
-10 - - - - -
-20 -
a 3 -30 - - - _ . -
5 e z I. -40 -
-50 - — * - - - -
-60 -
-70 -1 1 . < . . 1 1 1 —T : 2 3 4 5 6 7 8 9 1 0 1 1
Frequency (GHz)
521 522
Figure 4-15 Alumina cavity measurement
Figure 4-16 shows a 0.64 % or 36.5 MHz bandwidth at 5.69 GHz and 6.6 dB of
insertion loss. Also noticeable is a 1.2 dB loss along the line, which suggest that the
coupling via is more lossy than the expected 0.9 dB. Figiire 4-17 and Figure 4-18 present
the corresponding HFSS simulation.
97
Alumina Cavity - Optimal coupling measurement
0 -1 -2 -3
-5 -6
c -7 -a -a -9 ez -9
g. -10 C/5 -11
-12 -13 -14 -15 -16 -17
5.65 5.66 S t i S21
- S12 — S22
5.67 5.68 5.69 5.70 5.71 5.72 5.73 5.74 5.75
Frequency (GHz)
Figure 4-16 Alumina cavity measurement (detail)
Alumina Cavity - HFSS simulation
I2J Frequency (GHz)
S12 S22
Figure 4-17 Alumina cavity simulation
98
Alumina Cavity - HFSS simulation (detail)
Frequency (GHz)
Figure 4-18 Alumina cavity simulation (detail)
Simulations show a 0.34 % or 19 MHz bandwidth at 5.60 GHz and 2.32 dB of
insertion loss. In contradiction with equation (2) and measurement (Figure 4-15), the
TE201 mode is not visible in simulation (Figure 4-17) despite a very dense mesh of thirty
thousand tetrahedras. Consequently, Ansoft HFSS simulations can result in skipping
sharp modes, particularly in lossy cases. This remarks holds also for the Duroid® case
(cf. 3.4). The measured S parameters for weak coupling are shown in Figure 4-19 and
Figure 4-20.
0
Alumina Cavity - Low coupling measurement
-20 -
S -40 -e ee crt -50 -
-60 -
-70 -
-80 -t , , , , r 1 2 3 4 5 6
511 512 S21 S22
Figure 4-19 Alumina cavity weak coupling measurement
Alumina Cavity - Low coupling measurement
0 -1 . _ - . -
-2 . •3 . -4 - • -
-S . -6 . .7 —. .
-a --9
-10 . -n - . . .
-12 - - . . .
-13 X -14 . *
-15 . -16 -17 -18 . • -19 -20 /
N. -21 N. -22 . J," -23 - — V -24 —. . •• - —. - . - • . •
-25 . ,•
-26 . -27 — . -
-28 . . . . . .
-29 t 1 ' "1 r • ~ 1 ' '1 » ' f— ' — I - I •" 1 • I "I ~ r • ~ I ' ' I ••• I " • 5.60 5.61 5.62 5.63 5.64 5.65 5.66 5.67 5.68 5.69 5.70
Frequency (GHz)
S12 S22
9 10 11
Frequency (GHz)
Figure 4-20 Alumina cavity' weak coupling measurement (detail)
100
IFigure 4-20 shows a 12.5 MHz bandwidth at 5.656 GHz and 10.77 dB of insertion
loss. Thtis leads to Qi = 452 and Qu = 636. The external quality factor is 1563.
Hn addition, a weak coupling measurement with the wafer unbonded is performed.
Results are obtained using a metal screw dense enough to provide stiction between the
feed an!.d the cavity. Because of leakage, the external Q increases and the measurement
gets moore accurate as can be seen in Figure 4-21. In this case the 200 points TRL
calibratiion from previous measurement was used. The piece of alumina is the same as in
the prewious measurement.
Alumina Cavity unbonded - Low coupling measurement
S.60 S.62 S.63 5.64 S.6S 5.66 5.67 5.68 5.59 5.70
Frequency (GHz)
Figure 4-21 Alumina cavity weak coupling measurement— unbonded circuit (detail)
Figure 4-21 shows a 10.5 MHz bandwidth at 5.658 GHz and 16 dB of insertion
loss. T'his leads to Qi = 539 and Qu = 640.4. The external quality factor increases to 3340.
101
4.4.2. The 7 x 3.5 x 1 mm^ cavity filled with Paratek® BST Sr = 70, tan(6) = 0.0024 - via solution
The S parameter charts for optimal coupling are shown in Figure 4-22 and Figure
4-24.
0 -1
BST Cavity - Optimal coupling measurement
1 j 1
—-1-,^
i i 1 1
! ^
!
^ - - - - -
-30
-70
-80
1 2 3
sn S12 S21 S22
9 10 11
Frequency (GHz)
Figxire 4-22 BST rectangular cavity measurement
Figure 4-24 shows 55 MHz bandwidth at 5.924 GHz and 10.89 dB of insertion
loss. The corresponding simulation for optimal coupling is visible in Figure 4-23 and
Figure 4-25 . The response presents 3.2 dB of insertion loss with 72 MHz bandwidth at
5.67 GHz. From HFSS the quality factor is 256. The S parameters charts for weak
coupling are shown Figure 4-26 and Figure 4-27.
BST Cavity - HFSS simulation
\
/ '
--
-
f J
I2] Frequency (GHz) S12 S22
Figure 4-23 BST rectangular cavity simulation
BST Cavity - Optimal coupling measurement
-2 --3 --4 --5 -
-7 --8 -
-9 -10 -
-11 -
-12 -
-13 --14 - --15 --16 -
-17 - 1 8 -
5.85 5.86 5.87 5.88 5.89 5.90 5.91 5.92 5.93 5.94 5.95
Frequency (GHZ)
S12 S22
Figure 4-24 BST rectangular cavit>' measurement (detail)
BST Cavity - HFSS simulation (detail)
103
Frequency (GHz)
Figure 4-25 BST rectangular cavity simulation (detail)
BST Cavity - Low coupling measurement
9 10 11
Frequency (GHz)
Figure 4-26 BST weak coupling measurement
104
The results in Figure 4-27 show a 45 MHz bandwidth at 5.915 GHz and 16.54 dB
of insertion loss. This leads to Qi = 131.4 and Qu = 154.4. Similarly, unbonded
configurations have been explored which permit adjusting the wafers for better
alignment. Since the feed wafer can slide on the cavity wafer, an SOLT calibration with
800 points is completed so that probing is minimized. Optimal and weak coupling yielded
increased performance as can be seen on Figure 4-28, Figure 4-29 and Figure 4-30: the
insertion loss reaches 7.15 dB in optimal coupling at 5.78 GHz and, in weak coupling
configuration, the unloaded quaUty factor rises to 186 at 5.87 GHz. For the optimal
coupling measurement, two interpolations each side of the minimum insertion loss point
of the response were performed to evaluate the bandwidth which reaches 80.8 MHz.
Finally, it should be noted that the three last measurements were conducted with the same
piece of BST material.
0 -1 .2 -3
-5 •6 ' 7 -8 •9
^ -to -a -11 ^ -12 E -13
In -10 -19 -20 -21 -22 -23 -24 -25 -26
5.85 5.86 5.87 5.88 5.89 5.90 5.91 5.92 5.93 5.94 5.95
I2] Frequency (GHz) S12 S22
Figure 4-27 BST weak coupling measurement (detail)
BST Cavity - Low coupling measurement
105
g -30 -e
-50 - -/
-60
BST Cavity unbonded - Optimal coupling measurement
™ V=™
} --'r-f \
i \
\
. I - f! - ! 'I ' ! \ I
\ i ; I
\ ; [ i
\'
2 3 S l l
— S21 S12 S22
9 10 11
Frequency (GHz)
Figure 4-28 BST cavity optimal coupling measurement- unbonded circuit
BST Cavity unbonded -Weak coupling measurement
f. •I V
.,T*' ? /
2
521 S12 522
8 9 10 11
Frequency (GHz)
Figure 4-29 BST cavity weak coupling measurement— unbonded circuit
106
BST Cavity unbonded - Low coupling measurement (detail)
0
-5
-10
-15
a 3 -20
B C3 S -25 c. C/5
-30
-35
-40
-45 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5
I22 Frequency (GHz)
Figure 4-30 BST canity weak coupling measurement— unbonded circuit (detail)
The results in Figure 4-30 show a 38.75 MHz bandwidth at 5.871 GHz and 14.56
dB of insertion loss. This leads to Qi = 152 and Qu = 186.4. The external Q is 810.
From simulation, the weak coupling configuration presents low insertion loss.
Vias, due to the fabrication technique, can only be filled half air and half Silver Epoxy
and therefore participate in the coupling mechanism. This explains why the loading
material requires metal coverage. Figure 4-31 shows the response if the imperfect vias are
not shorted by fully metallizing the dielectric material.
Finally, the loss along the line is estimated using Figure 4-32 by measuring the
response of the thru after an SOLT calibration. And at the resonance, 1.8 dB of loss is
subtracted fi'om Figure 4-28. Insertion loss reach 5.35 dB, the reference point now being
located in the slots.
BST cavity - weak coupling - HFSS simulation (detail)
-5 -
-10
-IS -
-20 -
-25
.30
-35 -
-40
-45 -
-50
-55 5.0 5.1 5.2 5.3
S11 521 S12 522
5.4 5.5 5.6 5.7 5.8 5.9 6.0
Frequency (GHz)
Figure 4-31 BST cavity — weak coupling — simulation (detail)
Thru - measurement - SOLT calibration
5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0
Frequency (GHz)
Figure 4-32 Thru line - measurement
108
4.5. Interpretations of Measured Results
4.5.1. The 18.47 x 9.58 x 1 mm^ cavity filled with Coors® alumina Sr = 9.8, tan(5) = 0.0002 - micromaching fabrication- via solution
Parameters
Theory Experiment Error % (HFSS&
Opt. coup) Parameters Eq. HFSS Optimal coupling
Weak coupling
Error % (HFSS&
Opt. coup) Resonant frequency (GHz) 5.63 5.6 5.69 5.657 1.6
Insertion loss (dB) NA -2.32 -6.6 -16 184 Bandwidth (MHz) NA 19 36.5 10.5 92.1
Unloaded Q 693 1260 636 640 7.65
Table 17 Summary of alumina/Si cavity results
Table 17 summarizes the different measurements compared with theory for the
alumina cavity. Theoretical and measured resonant firequencies present good agreement.
From the Coors datasheet the tolerance on the alumina permittivity is 9.7 ±0.1 which
yields a firequency range from 5.63 to 5.69 GHz (cf. equation 2). Because of the existence
of the slots, HFSS is significantly lower (Sr = 9.8). Nevertheless, this result emphasizes
the necessary precise cut of the alumina piece in association with thorough metal
coverage. It should also be noticed that the alumina piece in optimal and weak coupling
were different, this might explain the difference of resonance frequency (recall that weak
coupling measurement have higher resonant frequency than optimal coupling case).
The poor insertion loss performance arise potentially from an uneven contact
between the dielectric material top surface and the feed wafer. At this interface, the vias
cormecting to the ground plane present a Silver Epoxy edge which might cause an air gap
to occur. Consequently, the feed wafer yields poor optimal coupling performance but
109
fimctions particularly well in weak coupling because of leakage. In addition, the
asymmetry of the response in the optimal coupling suggest a misalignment or a defective
via on one side (see Figure 4-16). Finally the feed is particularly lossy, after the TRL
calibration, 1.2 dB of return loss remains which once deembeded produce 5.4 dB
insertion loss.
The measured quality'" factor is enhanced compared to the Duroid® fabrication
and closer to theory. HFSS gives 1260 instead of 690 expected from equation (5). This
value extracted from Figure 4-18, is not reasonable. Adding open windows under the vias
in the ground plane increased the insertion loss to 4.5 dB and 22.5 MHz bandwidth. In
this case the quality factor in HFSS reach 615, which is more realistic.
In summary, this measurement demonstrated the sensitivity of the device to
alignment and via fabrication. Both aspects are important in the optimal coupling
performance. On the other hand, the need for metallization of the dielectric material was
established for good quality factor and resonant frequency. It should be noted that a
dielectric material piece not covered with metal will produce no resonance in the device.
110
4.5.2. The 7 x 3.5 x 1 mm^ cavity filled with Paratek® BST Sr = 70, tan(5) = 0.0024 with, micromaching fabrication- via solution
Parameters Theory Experiment Error %
(HFSS &) Parameters Eq. HFSS Bonded Unbonded Bonded Unbonded
Resonant frequency (GHz) 5.73 5.67 5.924 5.78 3.3 0.9 Insertion loss (dB) NA -3.2 -10.9 -5.35 NA NA Bandwidth (MHz) NA 72 55 81 NA 12.5
Unloaded Q 252 256 154 186.4 39 26
Table 18 Summary of BST/Si cavity results
Table 18 presents theoretical and experimental results for the BST cavity. The
values are obtained from equations (2) to (6), HFSS simulations, and bonded and
unbonded configiirations. The error is computed in reference to the equations when
available.
From the 1.4 % tolerance on the BST permittivity, the resonant frequency is
possibly in the range 5.73 to 5.77 GHz. The unbonded case is close to this range while
the bonded cavity resonates 150 MHz above this range at 5.924 GHz (Figure 4-24). In
comparison, the unbonded weak coupling measurement of the BST which resonates at
5.78 GHz in optimal coupling and at 5.87 in weak coupling, yielded a 5.915 GHz
resonance once bonded (Figure 4-27), which corresponds to a similar shift. From this
comparison, bonding issues are outlined. The previously mentioned misalignment and air
gap problems are emphasized due to the miniaturization process and explain the poor
results in bonded configuration: the area of the slots is four times smaller than the
alumina case, consequently the difficulty for alignment is increased. If we recall the
I l l
remark in 1.1.4, this surface ratio should be close to seven, however simulations did not
show a strong dependence on this choice. Wide slot is also easier to handle in fabrication.
During the unbonded tests, the BST material was hold tightly under the feed
wafer with a clamp. The air gaps and misalignments were therefore less likely to occur.
The insertion loss presents high experimental values. In addition the metal coverage is a
difficult part of the fabrication process. The dielectric material should be perfectly
covered. Because of miniaturization, the surface current density increases and a badly
covered area will have more impact on the response than for alumina. During fabrication,
adhesion problems were encountered with the Ti/Au seedlayer which was replaced later
by Cr/Au because of the roughness of the BST surface. The cleaning process was another
issue, the BST does not survive SCI and SC2 cleaning process and the air plasma asher
made the Low Temperature Cofired Ceramic become brittle. Therefore, the metallization
is expected to be weak and to lower the quality factor of the device when compared with
theory. Finally the measurements (Figure 4-30 and Figure 4-27) were performed on a 6
month intervals including different manipulations of the BST material, weakening the
metallic surface.
In summary, the experimental results presented the imperfection of the previous
fabrication with more impact due to miniaturization. Ways to ensure a finer metalhzation
and assembly are likely to produce better agreement with simulations. Fabricating the
vias by laser drilling and electro-plating [17] combined with the gluing of the material
below the feed is a suggested improvement.
112
4.6. Conclusion
Due to the complexity of the process, only geometries validated in Chapter 3 were
explored. Future work should investigate the potential of square and if possible cubic
features. The bonding can be further enhance for the BST case.
As a comparison with the exposed results, Kennerley and Hunter developed a
ceramic stripline filter using Zirconia Titania Stannic Oxide (ZTS) yielding a quality
factor of 300 at 5.2 GHz. The bandwidth was 200 MHz wide and 1.5 dB insertion loss is
achieved in a 12.5 Q configuration [18].
As a second comparison, the quality factor of the ^ microstrip line resonator on
silicon high resistivity substrate is theoretically 138 when including metal and dielectric
loss. At 5.65 GHz, the length of the microstrip line is 9 mm. Using the experimental
value in Figure 4-14, the quality factor is the very low value of 5.2. This is due to the
high attenuation of 3 dB/cm present along the line, probably caused by a resistivity loss.
In summary, a quality factor of 640 was demonstrated with alumina loading of the
cavity. The BST cavity achieved 186. This state of the art device presents a high level of
integrability.
113
5. CONCLUSIONS AND FUTURE WORK
A novel, miniaturized one-pole filter-resonator was demonstrated at 5.8 GHz. Its
monolithic, planar character on silicon ensures compatibility for on-chip integration, hi
addition its passive low loss design is advantageous for low power applications.
Key parameters for achieving good performance are emphasized. Several
features were built in order to strengthen the feasibility concept, jdelding satisfactory
fabrication process and a model development.
5.1. Results Summary
5.1.1. Theory
The presented work demonstrates that particular attention should be given to
square and cubic cavity shapes loaded with a dielectric material. It emphasizes the limits
imposed by its dielectric loss on the performance and the choice of a particular Sr with
respect to the operating fi-equency when designing cavity filters for the smallest possible
dimensions. The material should be chosen with minimum temperature coefficient of
resonant fi-equency (tcf) to ensure stability against temperature change [5] and covered
with the metal of highest conductivity.
114
5.1.2. Experiments
Table 19 summarizes the achieved results.
Cavity Dimensions
(mm^)
Fab. Type
Filler Er/tan(5)
Fr
Eq./HFSS/exp (GHz)
Qu Eq./exp
Af exp.
(MHz)
S21
exp. (dB)
17.47x8.78x0.93 EDM 10.8/0.0023 5.82/5.74/5.53 270/232 137 -2.2
17.47x8.78x0.88 EDM 9.8/0.0002 6.1/6.1/6.16 626/382 137.5 -1.3
4.1x4.1x0.25 EDM 70/0.0024 6.18/5.84/5.68 120/26 400 -6.6
7x3.5x0.25 EDM 70/0.0024 5.73/5.72/5.82 138/128 350* -5.6*
18.47x9.58x1 laM 9.8/0.0002 5.63/5.6/5.65 693/640 36.5 -6.6
7x3.5x1 ^iM 70/0.0024 5.73/5.67/5.92 252/186 81 -5.35
Table 19 Results overview
(*) value not corresponding to the same resonant frequency.
115
5.2. Performances
A resonator built with alumina inside a silicon structure yields a quality factor of
640 at 5.65 GHz. The corresponding volume is 177 mm^.
The corresponding device with Barium Strontium Titanate produces a quality
factor of 186 at 5.88 GHz. The corresponding volume is 24.5 mm^.
5.3. Developed Techniques
Despite their complexity, vias proved to be a superior fabrication technique for
coupling the energy in the cavity in comparison to the stub implementation. As a matter
of fact, vias do not require adjustment according to frequency and yield strong shielding
of the field necessary in the feed, particularly when aiming towards more miniaturization.
In addition, they solve the problems for parasitic effect and potential collision of the feed
lines.
Metallization of the dielectric material with strong adhesive seedlayer and
patterning ensured the best electrical definition of the cavity and continuity of the current
density.
5.4. Possible Applications and Improvements
In the effort toward higher dielectric material load, Coors® proposes a Barium
Neodymium Titanate (BNeT) substrate with Sr = 81.5 ± 3. This material was actually
used by S. Kobayashi and K. Saito in their filter [2], Characterized by a low loss tangent
(0.00025) it can be used with a thick cavity fed by narrow vias drilled by a laser system
116
to produce Qs close to 1000 with dimensions slightly smaller than the BST one. The
tolerance on the permittivity is overcome by adjusting the slot position in order to get the
specified resonant frequency. Finally the cavity coverage should be Silver.
A cubic cavity could be built with Zirconium Tin Titanate (ZTS) [5], which has
very low loss (0.000025) for an Sr = 36.5 ± 1.5. This value is low enough to provide
adequate spacing for the vias. At 5.8 GHz, Qs of 2000 can be achieved. Table 20
summarizes the possible performances and size.
Material 8r/tan(5) Dimensions (mm) Fr(GHz) Qu Barium 4.1 X 4.1 X 1 664
Neodymium 81.5/0.00025 4.1 X 4.1 X 2 5.73 923 Titanate 4.1 X 4.1 X 3 1060
Zirconium 6 x 6 x 2 1380 Tin 36.5 / 0.000025 6 x 6 x 4 5.8 1950
Titanate 6 x 6 x 6 2263
Table 20 Theoretical dimensions and performances of BNeT and ZTS loaded cavities
Dielectric losses are proved to be the limiting factor but decrease with
temperature. Low temperature applications provide the environment for very low
dielectric loss therefore small device with high performance [5].
Following Sengupta's research, the recipe of Barium Strontium Titanate can be
enhanced in order to reduce the loss tangent factor. Early work on BST [19] recommends
control of the level of oxide DI to adjust 8r and loss tangent. A 35% oxide weight ratio
would yield dielectric losses of 0.0006 and Sr = 530 at 1 kHz. Other work [20] noticed.
117
the addition of a relatively small amount of non-ferroelectric oxide caused the dielectric
losses to rapidly decrease. Lowering the concentration of Barium follows this trend as
well and is applied to bulk ceramic [21].
5.5. Future Work
5.5.1. Model
As mentioned in 3.6, the PSPICE model requires additional data points from the
simulation in order to establish the equation for each component and achieve accurate
modeling.
Additional capacitors should be added to model the air gaps around the dielectric
material. Particularly at the top and the bottom interface where the field is more dense,
they produce considerable degradation of the response and should be taken into account.
Numerical techniques such as Least Mean Square applied to polynomial
interpolation or advances in neural network programming can also lead to good
modeling.
5.5.2. Packaging
Development of the packaging is important as well. A proposed version is shown
in Figure 5-1.
118
grdiuijg
Figure 5-1 Packaging and mounting option of the resonator
The metallized cavity and the feed are attached together to form a block. Via
solution is implemented without transmission lines in the feed, which can be made out of
very thin siHcon wafer in order to make the vias thiimer. The block then receives an
insulator layer for mechanical and EM shielding.
Feed lines are provided by the external circuit where the assembled block is
flipped and attached by soldering. Pads at the via location ensure good contact. The
continuity of the field is ensured by removing the ground plane in the extemal circuit
underneath the filter location. If the height of the silicon in the feed and the one of the
extemal circuit are different, tapered matching sections may be necessary. Extemal vias
are needed to ensure proper grounding of the filter to the ground plane of the extemal
circuit.
5.5.3. Filter Design and Diplexer Application
The direct usage of resonators is the development of multi-pole bandpass or
bandstop filters. Cascading several identical cavities ia series and adjusting the coupling
119
through the slot dimensions and positioning changes the characteristic of the pass band:
typically, bandwidth, resonant frequency and ripples.
Knowing that presently the diplexer is one of the largest elements in a PCS
handset, the miniaturization capacity of the presented technology can be applied to a
micromachined diplexer developed at the University of Arizona [22].
120
ANNEX
1. IVnCROMACHINED DIELECTRIC 2-POLE FILTER ON SILICON
1.1. Introduction
In association with the University of Limoges - IRCOM [23], France,
micromachined dielectric resonator and 2-pole filter on silicon have been fabricated at the
University of Arizona. The fabrication takes advantage of a recently released laser system
in the department of Astronomy to etch accurately an air-silicon lattice.
Based on the Bragg's mirror condition, and by leaving a precise amount of silicon
unetched in the periodical structure, a confinement similar to the cavity in Chapter 3 and
Chapter 4 can be created. Geometrical parameters are adjusted for a 44 GHz resonance
and low insertion loss is ensured by the use of very high resistivity silicon. In addition,
the laser cut ensures very close to perfect vertical walls, in contrast to Chapter 4.
First, a one-pole filter is studied and simulated. The two-pole filter, based on
Tchebychev analysis, is composed of a pair of two "cavities" which intra coupling is
adjusted to produce the desired bandwidth and ripples.
(*) Due to the Gaussian shape of the beam, a 7 % sloped wall remains.
121
1.2. Principles and Simulations
The top view of the structure show a 12 x 12 square matrix constituted of air holes
(Fig.l. 1). Thickness of the Sr = 11.6 silicon substrate is 430 jj.m. Holes are 0.8 x 0.8 mm^
and 0.5 mm spaced. The cavity is 3.1 x 1.8 mm . Fig.l. 2 details excitation and
dimensions. Fig.l. 3 describes the coplanar excitation for probing in the middle of the
slot. The two-pole filter is built by juxtaposing two single-pole resonators and by
adjusting the distance between each resonant element.
Fig.l. 4 describes the evolution, Fig.l. 5 contains the parameters for the
excitation.
silicon
. Resonant vf b clement
Fig.l. 11-poIe filter grid
122
Ton view Excitation of the 1 pole filter 14.8 mm
<-
i.S mm
Coplanar excitation
Longitudinal cross section
T
r MSoim ~;r-^ 0.4S
1.5 mm 0.4^ mm
J/_ - OJ mm S' Eccfiins ia the ground plane
Fig.l. 2 Excitation of the 1 pole filter
0.05 mm
Metallisation
1.5 mm 0.3 mm
Fig.l. 3 Coplanar excitation dimensioning
123
TOD View
<^L _ _ • _ _ I I I
-e^ -e^ -e^ -e-> -«-» •«^-> -e^ •«-=•«-» -e^ -e-s- -«-?• b b b b b b b b b b b b b b b b
Longitudinal cross section a* 0.5inm .b« 0.8mm. substrate thickness <>0.43 mm
metallisation .
silicom ^ l l l l l l l l i l l l l l Fig.l. 4 2-pole filter grid
COPLANAR EXCITATION OF THE 2 POLE FILTER
15.1 mm
n,.- • i-srit??
i0^4.nim
,
Etebing in the grouDd plane
2.1 mm o.^mm 3 —
Eicbtsg m ibe ground
Fig.l. 5 Coplanar excitation dimensioning
124
Frequency (GHz)
Fig.l. 6 1 pole filter simulated response
CO
(Z1 (L> -15
"S g 2 -20 Ci3 o.
ST -25
'
S l l S l l
\ /
- /
S21
\ A V
!
•
-
1 1, II
( 1 1 t » •
42 43 44 45 46 47 48 49
Frequency (GHz)
Fig.l. 7 2 pole filter simulated response
125
Fig.l. 6 and Fig.l. 7 correspond to the simulated response of the single-pole and
two-pole filters using FEM code developed at the University of Limoges.
As a comparison, HFSS simulation is displayed in Fig.l. 9; Fig.l. 10 pictures the
electric field distribution in the high resistivity silicon substrate. 50 Q lumped gap source
provides the excitation at the slot location.
The corresponding 2 pole filter simulation and electric field distribution follow in
Fig.l. 11 and Fig.l. 12. The dielectric loss is neglected in simulation.
The picture of the fabricated device is shown in Fig.l. 8 with 1.3 magnification.
Fig.l. 8 One pole and two poles filters before laser cut
126
One pole bandgap filter - HFSS simulation
S -20
47 48 49 SO
Frequency (GHz)
Fig.l. 9 1 pole filter simulated response (HFSS)
).aooo««oo« I Z.SZ3C««<)04 ' 2.a47Z««Oa4 {.rK»««004 {.C944«<<)a4
j I.S17W«00« I 2.9«13«^4 I <>4Ulv«C04
2.3lt-»««00« 2.]U3««0(M
' <.>13S««004 I I>19»9»H104 I <.(M)X««e04 I <.00c7««004 ' l.91CU««004 I i.isia*«004 I l.Tr»4»»004 I ItiOtOv^OO* I l.A24«*«e04
1.34I3**0«4 I t.47ta*«a04 I i.}»94*«a04 I l.H90« '004 I t.242w«aa4 I t.tU3««a04 t.M9T«*004 I t.0U3««00< 1 •.]«93«'*003 I t.CSSt««003 T.«4t0v«003 T.ffTMv Om (.JU«««0(U I 4.7a4«e*001 4.ozos«*ea) >,lS*4e«e03 i.4Mi««o(n i.73a3««eoj «.«4io»«aos
Fig.l. 10 1 pole filter simulated Electric field (HFSS)
50
A6
tiS
ftVter
' v%,*.^
\-«f.*,l5< !•••* -OO*
-Si-^
X'S ' V.?J^:S
M m - M M l m . iM/ajMiaf; !;arii^ifW-ili: '^i|J|iii^kiH;V;iai«ia/ •] Jtf:
LO.V- *• oVe CvVter
ctric
128
1.3. Measurements and Conclusion
Due to a time constraint, the measurement of the one and two pole filters had not
been possible. The author presents his apologies for the inconvenience.
The project described an alternative technique for planar, easy to integrate silicon
filter. In contrast to the study of Chapter 3 and Chapter 4, the field is restricted between
discontinuous walls by applying the Bragg's mirror condition.
129
2. ADDITIONAL PLOTS AND MEASUREMENTS
2.1. Quality Factor Chart for Square Base Cavity
Q vs freq. - square cavity - 1 mm thick 1800
2x2 3x3 1600 4x4 5x5
. .., ., .-.-6x6 8x8
cavity size (mm)
1400
1200
3 a 1000
V '22
800 '50
600
400
200 5 10 15 20 25 30 50 35 40 45
Frequency (GHz)
Fig.2.1 Quality factor of square based cavity for selected permittivity
Fig.2. 1 shows the quality factor and the first resonant firequency of square based
cavity. Size varies from 2 x 2 to 8 x 8 mm^ for a constant 1 mm thickness and Aluminum
wall coverage. For simplicity, the loss tangent is not taken into account. Figures in the
130
chart give the corresponding permittivity. The plot gives a good overview of possible
achievement.
2.2. Slot Loc^ation Effect on the BST Cavity Response
Adjusting the location of the slots in the feed closer or further away from the
cavity edge along the microstrip line axis permits fine tuning of the response. Since the
cavity looks electrically different when this parameter is modified, resonant frequency,
insertion loss an<i roll off are expected to change. Fig.2. 3 presents the standard response
were slots are located 25% cavity length away from the edge. Closer to the edge, Fig.2. 2
shows poor roll off, lower resonant frequency but low insertion loss. Closer to the center,
Fig.2. 4 demonstrates sharper roll off, higher resonant frequency and higher insertion
loss. These simulation results are summarized in Table.2. 1.
Slot location effect on the response - location is 0.45 mm away from edge
-10
-20
"09
E -30 es S 5/3
-40
-50
-€0
1 2 3 4 5 6 7 8 9 1 0 1 1
fi? Frequency (GHz)
location effect on the response - location is 0.45 mm away from (Close to edge)
Fig.Z. 2 Slot location effect on BST cavity response — Slots close to edge
Slot location effect on the response - location is 1.58 mm away from edge (Standard location)
131
-20
S -30 -
9 10 11
Frequency (GHz)
Fig.2. 3 Slot location effect on BST cavity response — Standard positioa
Slot location effect on the response - location is 2.08 mm away from edge (Close to cavity center)
0
-10
-20
a
S -30 a a a.
-40
-50
-60
1 2 3 4 5 6 7 8 9 1 0 1 1
S2I Frequency (GHz)
•
i • •
; 1
^ • ; !
I' i 1. 1 it
Fig.2.4 Slot location effect on BST cavity response — Slots closer to cavity center
Dist. to edge (mm) S,, (dB) (GHz) Af(MHz) RoU off Slot closer to edge 2.08 -2.6 5.57 72 wide
Standard slot location 1.58 -3.1 5.63 61 fair Slot closer to center 0.45 -3.9 5.67 50 sharp
Table.2.1 Slot location effect on BST response — Comparative results
132
2.3. Slot Size Effect on the BST Cavity Response
In order to get better coupling efficiency, the slot size from 3.5.3 is increased. The
area, previously 2 x 0.2 mm^, is augmented to 2.8 x 0.34 mm^. The effect is pictured in
Fig.2. 5. The frequency shifts from 5.68 GHz to 5.15 GHz and the insertion loss decrease
from 8.26 from to 4.33 dB (loss due to the line not deembeded). In parallel, the
bandwidth increases from 400 MHz to 500 MHz. The fiirther increment of the slot size is
shown in Fig.2. 6.Frequency shifts dovm to 4.8 GHz.
4.1x4.1x0.25 BST cavity - z = 7 0 - widerslots - vias - measurement
Frequency (GHz)
S12 S22
Fig.2. 5 Augmented slot size in square BST cavity — vias
133
4.1x4.1x0.25 BST cavity - e^=70 - very wide slots - vias - measurement
0 •J
-5 -
-10 -
-15 -15
-20 .
a -25 -
-30
-35 e « c..
-30
-35 t/i
-40 -
-45 -
-50 -
-55 -
-60
V — - "V — .^• 7 il
I
2 3 4 S11 S21 S12 S22
8 9 10 11
Frequency (GHz)
Fig-2- 6 Incremented slot size in square BST cavity — vias
HFSS eigen solver simulation for the corresponding cavity are shown Fig.2. 7 and
Fig.2. 8. The perturbation due to feed can be observed in the resonant frequency which
shifts from 6.16 to 5.68. As seen previously, slot size increment led to 5.15 and 4.8 GHz.
yWSFTSJBSr
ctea
Fig.2. 7 Eigen solver simulation — BST square cavity (data)
134
Fig.2. 8 Eigen solver simulation — BST square cavity (plot)
2.4. Air Gap Effect on the Response
Air gaps occurring on the top or the bottom of the cavity generate significant shift
of the resonant firequency. A 100 (im air gap between the feed and the cavity load will
create an additional air cavity on the top of the d.ielectric material and. very little energy
will be receive by the alumina. Fig.2. 9 shows this effect with the alimiina loaded cavity
with silicon fabrication. The air cavity resonance appears at 17.14 GHz and produces 9.5
dB insertion loss. At 5.6 GHz, the alumina loaded cavity resonates with 39.5 dB insertion
loss. In addition, this measurement was performed with a feed implemented with stubs,
the shape of the response at the resonant frequencies is typical of this kind of structure
(cf. Figure 3-15).
135
18.47 X 9.58 X I mm^ - Alumina loaded cavity 100 fim air gap on top - measurement
0
-10
-20
a IT -30
I- -40
-50
-60
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
IjJ Frequency (GHz) S12 S22
Fig.2. 9 Alumina cavity with air gap — measurement
It should be noticed that, for the measurement of the BST resonators, the pieces
were glued inside the cavity using lossy Silver Epoxy (CT = 2.5.10^ S/m) in order to avoid
air gaps. This produces wide bandwidth and low Q (Fig.2. 5 and Fig.2. 6). La addition to
the frequency shift, air gaps make the material weak under pressure and it breaks easily.
For example, the case in Figure 3-20 yielded high Q because no Silver Epoxy was used.
Therefore only little pressure could be apphed and the low coupling measurement
became possible. This no air gap condition happened only once, the material then broke.
Consequently, to produce Figure 3-19, a different piece was used and air gap could not
be avoided. Finally, air gaps are also a lossy mechanism and increase the bandwidth as
can be seen in Figure 3-19 , but with less impact than the Silver Epoxy.
136
4x4x0.25 BST cavity - vias - measurement -No Silver Epoxy
0
-5 -10
-15
£• -20
3 ^ -25
1. -30 C/5
-35 ^0 -45
-50
1 2 3 4 5 6 7 8 9 1 0 1 1
1 Frequency (GHz) S21 S12 S22
Fig.2.10 Square BST cavity no Silver Epoxy - measurement
4x4x0.25 BST cavity - vias - measurement - No Silver Epoxy No air gaps
0
-5
-10
-15 S 3. -20
i -25 c. CO
-30
-35
-40
-45 1 2 3 4 5 6 7 8 9 1 0 1 1
Frequency (GHz) Fig.2.11 Square BST cavity no Silver Epoxy no air gap - measurement
The measurement corresponding to Figure 3-19 for the 4 x 4 x 0.25 BST
resonator is shown in Fig.2. 10. No Silver Epoxy was used, therefore the BST broke
under the pressure and air gaps produced the high resonance. Nevertheless the quality
137
factor went from 26.5 (cf. 3.5.4) to 68 after removing the loss from the line: typically S21
= -3.6 dB, Fr= 7.18 GHz, and F3dB= 370 MHz. A last measurement of the same cavity
filled with a different piece of BST and no Silver Epoxy is shown in Fig.2. 11. The
breaking did not occur and the resonant frequency reach 5.85 GHz. The insertion loss is
measured to be 8 dB (1.4 dB due to the line were removed). The bandwidth is 365 MHz.
2.5. Unloaded Cavity Measurement
In order to check for the efficiency of the feed, a first measurement of the alumina
cavity without filler is perfomied. The expected resonant frequency is 17.64 Hz. From
measurement, the resonant peak is at 17.2 GHz, and can be seen in Fig.2. 12. In parallel,
the BST cavity loaded with air would have a resonance as high as 48 GHz, which is
beyond the operating range of the measurement probes. It was therefore not measured.
-10
-20
-30
S -40 £ i -50 c.
CO -60
-70
-80
-90 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
I21 Frequency (GHz) S12 S22
Fig.2.12 Air loaded alumina cavity measurement
18-47x9.58x1 mm cavity loaded with air - measurement
z\
f __ r
1 1 ! 1 1 - 1 - I 1 I , • , -I. , — I 1 T t r
138
APPENDICES
APPENDIX A - FILES AND PICTURES OF SIMULATIONS
APPENDIX B - PICTURES OF FILM AND GLASS MASKS
APPENDIX C - DATASHEETS: BST, ALUMINA, SILVER EPOXY
APPENDIX D - FABRICATION TECHNIQUES
- FOR DUROID® SUBSTRATE
- FOR SILICON SUBSTRATE
APPENDIX E - FABRICATION RECIPE FOR DUROID CAVITY FILTER
APPENDIX F - FABRICATION RECIPE FOR SILICON CAVITY FILTER
APPENDIX G - FABRICATION RECIPE FOR SILICON DIELECTRIC FILTER
APPENDIX H - PICTURES OF CIRCUITS
APPENDIX I - MEASURING AND FABRICATION EQUIPMENTS
139
APPENDIX A. FILES AND PICTURES OF SIMULATIONS
A macro files contains HFSS recorded commands and is used to perform automatic task. Example follows:
UseCommandSet "Solve Setup" UseCommandSet "Emissions Setup" UseCommandSet "MatrixData" UseCommandSet "hfss" UseCommandSet "Default" UseCommandSet "modSview" UseCommandSet "modSproj" UseCommandSet "ModelerS" UseCommandSet "Generic Module"
#Clear space ClearAU ClearFunctions ExpClear If GT GetNumObjects 1 Select {"*"} SelClear end select { } selclear
# Change the dimension of the cavity assign L getdouble "enter the length of the cavity" assign W getdouble "enter the width of the cavity" assign lb sub 0 0.76 assign xb add (div(sub 4 L) 2) lb assign yb div(sub 0 W) 2 box pos3 xb yb 0.5 L W -0.25 "newcav"
# Move the holes position regarding the length of the cavity Assign odep 0.19 Assign k getdouble "factor of displacement (0~edge - 0.5~niiddle) " Assign dep_hole2 sub (mul k L) 0.76 Assign dep_holel sub 0 dep_hole2
# new sizes to redraw the geometry of the cavity
Assign newxl add -1.76 dep_hole2 Assign newx2 add 4.24 dep_holel Assign newLl add 6 (mul dep_hoIel 2) box pos3 newxl -6 0 newLl 12 2.5 "outer_region" boxposS newxl -6 0 newLl 12 0.5 "sur_cavity" box pos3 newxl -6 0.5 newLl 12 0.635 "dielectric" rectangle pos3 newxl -6 0.5 2 newLl 12 "gnd" 1 box pos3 xb yb 0.5 L W -0.25 "newcavl" subtract { \ 'sur_cavity' \ } { \ 'newcavl' \ }
#hoIes assign hole2x add -0.05 dep_hole2 assign holelx add 2.43 dep_holel rectangle pos3 hole2x -1.4 0.5 2 0.1 2.8 "hole2" 1 rectangle pos3 hole2x -1.4 0.5 2 0.1 2.8 "hoIe3" 1 rectangle pos3 holelx -1.4 0.5 2 0.1 2.8 "holel" 1 rectangle pos3 holelx -1.4 0.5 2 0.1 2.8 "hole4" 1 subtract { "gnd" } { "hole3" } subtract { "gnd" } { "hoIe4" }
# Design of the microstrip EditPIine "ustrip2" Addvert[-1.76, -0.2814, 1.135] Addvert [-1.76, 0.2814, 1.135] Addvert [0.05, 0.2814, 1.135] Addvert [0.05, 0.2814, 0.5] Addvert [0.05, -0.2814, 0.5] Addvert [0.05, -0.2814, 1.135] closepline EndPline EditPIine "ustripl" Addvert [4.24, -0.2814, 1.135] Addvert [4.24, 0,2814, 1.135] Addvert [2.43, 0.2814, 1.135] Addvert [2.43, 0.2814, 0.5] Addvert [2.43, -0.2814, 0.5] Addvert [2.43,-0.2814, 1.135] closepline EndPline
# Compute the displacement for holes & microstrip select {"H-ustripl"} move vec3 dep_holel 0 0 deselect {"*"} select {"+ustrip2"} move vec3 dep_hoIe2 0 0 deselect {"*"}
#Draw the surrounding box rectangle pos3 newxl -6 2.5 2 newLl 12 "top" 1
rectangle pos3 newxl -6 2.5 1 newLl -2.5 "left" 1 rectangle pos3 neAwxl 6 2.5 1 newLl -2.5 "right" 1 rectangle pos3 newxl -6 2.5 0 12 -2.5 "port2" 1 rectangle pos3 newx2 -6 2.5 0 12 -2.5 "portl" 1
FitAIlViews Save3d "e:/Ansoft_Projects/christophe/cavl00sh.pjt/cavl00sh.sni3" "?v" Exit
LaunchMaterials "modify"
materialselect "per^conductor" objectsetsolveinside "sur_cavity" "no" materialAssign { "sur_cavity" } "OCS" { "0.0" "0.0" "0.0" } { "0.0" "0.0" "0.0"
materialselect "ceram" materialassign { "newcav" } "OCS" { "0.0" "0.0" "0.0" } { "0.0" "0.0" "0.0" }
materialselect "vacuum" materialassign { "outer_region" } "OCS" { "0.0" "0.0" "0.0" } { "0.0" "0.0" "0.0
materialselect "newduroid" materialassign { "dielectric" } "OCS" { "0.0" "0.0" "0.0" } { "0.0" "0.0" "0.0" }
MaterialModuleExit "save"
Launchboundaries "modify" ClearAllBnds
TogglePickObjByName "top" setBndName "top" SetBoimdary "perfect_e" CreateB oimdary ClearSelection
TogglePickObjByName "right" setBndName "right" SetBoundary "perfect_e" CreateB oundary ClearSelection
TogglePickObjByName "left" setBndName "left" SetBoundary "perfect_e" CreateBoundary ClearSelection
TogglePickObjByName "portl" setBndName "portl" SetBoundary "port"
142
CreateB oundary ClearSelectioa
TogglePickObjByName "port2" setBndName "port2" SetBoundary "port" CreateBoundary ClearSelection
TogglePickObjByName "holel" setBndName "holel" SetBoundary "perfect_h" CreateBoundary ClearSelection
TogglePickObjByName "holeZ" setBndName "hole2" SetBoundary "perfect_h" CreateBoundary ClearSelection
TogglePickObjByName "gnd" setBndName "gnd" SetBoundary "perfect_e" CreateBoundary ClearSelection
TogglePickObjByName "ustripl" setBndName "ustripZ SetBoundary "perfect_e" CreateBoundary ClearSelection
TogglePickObjByName "ustrip2" setBndName "ustripl" SetBoundary "perfect_e" CreateBoundary ClearSelection
SaveBoundaries ExitBoundaries
SolveSetup SetSolutionType 11112 SetSolverComputation "all_fields" "dominant_mode" 1 SetFrequencyUnit "GHz" SetFrequency 5800000000 SetAdaptivelnfo 50 "conv_delta" 20
SetConvDelta 0.02
143
SetMeshType "initial" SetSweepInfo 2000000000 10000000000 100 SaveEditableSolveParms ExitSolveSetup SolveNominal PostMatrixPlot #Plot szgPlotKemelNew "cartesian" "freq" "S_r' 0 0 "dB" "none" 0 { 0 } SzgPlotKemelSave "Plot 1 ; S Matrix Data" "e:/Ansoft_Projects/christophe/cavlOOsh.pjt/plotscl.dat" szgplotkemelexit "save"
Pictures from simulation:
Fig-APX-1 E field distribution in BST cavity Fig.APX. 2 E field distribution in BST feed
Pioi 6:5 Matrix Oalo
r«e mnueenau
r u
Fig.APX. 3 AC Voltage response of the device (time domain)
Fig.APX. 4 CPW-microstrip line transition [28]
APPENDIX B. PICTURES OF FILM AND GLASS MASKS
Fig.APX. 5 3600 dpi film for alumina/Duroid® cavity feed (Cu positive etching process)
Fig-APX. 7 Feed glass mask (Si process)
Fig.APX. 6 3600 dpi film for BST/Duroid® cavity feed (Cu positive etching process)
Fig.APX. 8 Vlas glass mask (Si process)
145
Fig.APX. 10 Masks superposition - cavity filter Fig.APX. 9 Slots glass mask (Si process)
FigJVPX. 11 2-pole filter top glass mask (Si. process)
FigJ^X. 12 2-pole filter center glass mask (Si. process)
APPENDIX C. DATASHEET: BST, ALUMINA, SILVER EPOXY
•V TOdfiBI
FigAPX. 13 Paratek® BST datasheet
147
•: : •: : cfiavme<«riac/c« Unit
Tast Mailicid
ADS' »5
Super-atrale«
saff TIWO TO-3< TCMO TD-a2 ZTA ' •rV^a ' •' . -
YTW-Composition 99.5%
Afcimina 99.6%
Alumina Magnesium
Titanate Ztrconlum
Tin Titanate
Dibarfum Nano-
titanate
Barium Neodymhim
Tltanaie
Zlrconia-Toughened
Alumina
i' Vitrta ParHaBy
Slabllzed Zirconia
Color * '
White White Tan/ 8elge
Cream Tan Tan/ Russet
WMie Ivory •
Nominal Oensf^ g/cm^ ASTM C373 3.8B 3.87 3.8 5.17 4.57 5.72 4.07 6U)2 Surface Finish.
AS'flred Polished
Micro* Inches
CLA tRa)
Profltometer S 3
2 1
10 0.5
8 0.5
20 i 0.5
30 1 0.5
5 1
a 0.25
Average Grain Sze
Microns Intercept Mmtiod
<2.2 <\.a 4-7 3-5 4-5 3 k 30 fneedte)
2.5 (n| 1.5 W
1
Ftexurol Strength Kpsl ASTM F394 B3 90 15 25 25 15 65 130 Elastic Modulus •I0*psl ASTM Ca4B 54 54 - - - - 52.4 29 Coemcleni of Unoor Tl\enn«i Expartsfon
20*- ZOO'C
lo^rc ASTM C372
1 6.9 6.9 8.6 6.5 9.7 9.0 6.B 10.2
Thermal CanductMly
20-C
W/m-K Various 1
33.5 35.0 4.2 2.1 2.5 2.1 27 22 Ofeledric Constant
(Relative PermtttWity) 20*C « 4 GHz 1
ASTM 0150
9.9 *.1 1 9.91.1 19.5^1.0 36-5 * U 39.Sx^5 81.5 3.0 10.6 32.3 Q • 1 GHr _ _ 5.000 1 S.000 4.000 40.000 20.000 4.000 2.000 2.S00 Tempofalure CoeUIcIa^oT ResohahtV. Ff^uency.
1
0 t3 0± 2 2 t2 0t^2 ohm*cm
: ; "
: ASTM 02S7
>10" >10*« >10" >10" >10" >10« - -
Fig.APX. 14 Coors® alumina datasheet
148
DATA SHEET EPOTEK. H20E
Elactrically Conductw*, Silver Eooxy
R«v. Ill 4/00
TO-3 pacicBge. 2N30S5 chips. m«dtum power irerwistor-4 amp pulae vm9at 30arc/ looo hours
EPO-TEK H20e .
At 20crc/l000 hrs. EPO-TEK H20E stands alor>o. >1/' othmn
k» «ap kU tfU •
r^^vr^MvaiCAl^
. . - • - 'v. jxwpmmK gr»w
Scfi^SI^
H20E EXHIBITS SUPERIOR V„ PERFORMANCE.
,SAT
.vi«ruii>}i(^acon - •c:5T^hco«Wfcl<ntoPThni*H^P«iiilari^<CTE|
?B»io«».Ta';"— • - - • . • -j:5i jcio^mnorc: :-M20 it-JO? WinffC .
10 KO/3,400 psi:
- :--'^>«f^5%?^^ELEC*WCAfc^^ .
•W«lgiyi7i«ita.'aoorC^CroA>3..'^^:?'f .''- ^ '--
^>3AWAnrKj
EPO-TEK l 20E is a 100% solids, two component silver filled epoxy with a soft, smooth, thixotropic consistency designed spftcificaUy for cfUp bonding (n microetactronic and optoelectronic appUcations.
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EPO-TEK H20E Is especialty recommended for use In htg speed epoxy chip bonding systems wliere very fast cure; are highly deslrat>le. This cannot be ot>tair\ed with single component systems. Because EPO-TEK H20E can tM cured very rapidly, ft is an excellent materiai for maktnf fast circuit repairs. EPO-TEK H20E can be screen printed machirM dispertsed or stamped and can withstand win t)ondir>a temperatures in the range at 300 —400*C.
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PHONES 978.667.3805 I 800.277 ;?201 FJ^JC: 9/6.663.9782
^ tSnisffnarWaiiiliiiw m >^./aOkj8peaMoew*hi* li<itfriirtiii«iiaS<!?niiTt i iT».^-- . . c<4*iwdbcBd>dw«hEl^TB^tCOggBiti.lNciO^£L>:>: ^ ^ EiiiedfeDtaratrta»v. ,'i •)t]iDndMdCoa''OQl(trt - - — _ '^pMsr gcycjwis<t'dlin?62fC^ti6^2apCi^^ ^.
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Fig.APX. 15 Epo-Tek® Silver Epoxy datasheet page 1
149
SOME PHYSICAL & ELECTRICAL CHARACTERISTICS OF EPOTEK. H20E
Thermal resfstance of mediurrvpower, gofd*backed silicon chips of varying sizes mounted with eutacllc preforms (96% Au—2% SI) and EpoTek H20E silver epoxy.
EpoTek H20B Two-Pait Silver Epoxy - Lap Shear Strenoth as a function of temperature, epoxy cured at 150*C for 15 minutes.
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LEGEND a euTEcnc A 1 MIL THICK H20E EPOXT O 2 MILS THICK H20E EPOXY • 3 MILS THICK H20E EPOXY A 5 MILS THICK H20E EPOXY
40* 100x120 120x140
SIZE OF CHIP
X H-o
35 X CO a.
3
-80 -40 • 40 W 120
DEGREES CENTIGRADE
Epo-Tek H20E subjected to SOO'C for 1000 hours. Lap Shear Strength was determined to be between 375' X .750- X XI20' Alumina and 375' x .730' x .007' Nickel A.
\ T curve derived during a standardization bake at 200'C for 1000 hours using EpxJ-Tek H2DE for die attach.
&
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s X
C3
1.7
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1.4
1.3
1.2
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0 100 200 300 400 500 600 700 600 900 1000
HOURS
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1.4
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1^ A JS .4 .2
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io V OLTS A PPUED fl MIN. It lOtnA R, «1KD 3. JQmA__^mA R,«_!2JL-S0K 50 .2mA i 1 I L ...
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lOtnA R, «1KD 3. JQmA__^mA R,«_!2JL-S0K 50 .2mA i 1 I L ...
0 36 108 160 2G0 380 560
HOURS
Fig-APX. 16 Epo-Tek® Silver Epoxy datasheet page 2
150
APPENDIX D. FABRICATION TECHNIIQUES - DUROID & SILICON
ON DUROID SUBSTRATE:
• Preparing board
Trim Roger Duroid® board about 14 inch Isirger than circuit size. Remove plastic coverage and rinse with Acetone and IPA if necessary.
• Performing lithography
Center board on the spinner. Hold by putting vacuum on or using tape on the backside. Apply photoresist PR1915 at 2.5k rpm using pipette. Check coating uniformity, start over lithography if non uniform. Bake 1 min. at 110 degree C. Let cool down for a minute. Tape comer of the board on piece of thick glass, center and tape matsk emulsion side down over the board. Place the assembly on the exposing equipment, pump down 10~15 sec., expose 1 min. Take board out and develop for 30 sec. in AZ300 developer. Rinse in water 30~40 sec. Dry board with No gun.
• Etching Copper
Pour '/i inch of copper etch solution (FeCU) in flat plastic pan. Add lOOmL of hot water to increase etching rate. Add board. Stir for 10~25 minutes for complete etching. Rinse in water.
• Stripping photoresist
Pour '/* of PRS2000 (stripper) solution in Pyrex container the size of the board. Heat up solution to 80 degree C. Place board in hot solution for 1 min. Rinse in water.
• Fabricating vias
Drill 20-mil hole at the very end of the microstrip line all the way tirough the board.
151
Cut wire of same diameter about 14 inch long. Fill in the hole. Solder wire at the location of the ground plane and the microstrip line. Reduce size of the soldering on the ground plane using sandpaper. This will ensure smooth contact between board and cavity.
ON SILICON SUBSTRATE:
• Cleaning
Rinse >2min. in dedicated Acetone beaker. Rinse 2niin. In dedicated IPA beaker. Dry with Nitrogen (Nt) gim. Dehydrate bake-. Dry on hot plate, 130 degrees Celsius, Imin.
• Patterning with PR1827
Spin photoresist: Use smallest chuck. Spin HMDS, 30s. 3k rpm with new clean pipette each time liquid from pipette, then press start. Spin PR1827 30s. 3k rpm with new clean pipette each time liquid directly after previous cycle is finished, press start. B^e 105 degree Celsius, Imin. on hot plate with clean A1 foil. Expose: Clean mask using Acetone, then IPA above spinner drain. Expose 20s. after centering wafer on the wafer holder of MJB3. Develop: Develop 38s. using 351 developer. Rinse in water. Dry with N2 gim. Post-bake: 130 degree Celsius for Imin. Check thickness on AlphaStep equipment. Expect 3tmi. Note: HMDS is Hexamethyl-Disilazane.
• Protecting side of wafer with PRl 827
Use small chuck. Spin Photoresist on side to be protected: Spin HMDS, 30s, 3k rpm with new clean pipette each time (let go three drops in the spinner drain) Drop liquid from pipette, then press start. Spin PRl827 30s. 3k rpm with new clean pipette each time (let go three drops in the spinner drain). Drop liquid directly after previous cycle is finished, press start. B^e 130 degree Celsius, 2min. on hot plate with clean Al foil (hard bake).
• Patterning with PR5214 (image reversal) — used for liftoff process.
Spin Photoresist: Spin HMDS, 30s. 4.5k rpm with new clean pipette each time (let go three drops in the spinner drain). Drop liquid from pipette, then press start. Spin PR5214 30s. 4.5k rpm with new clean pipette each time (let go three drops in the spinner drain). Drop liquid directly after previous cycle is finished, press start. B^e 110 degree Celsius, 2min. on hot plate with clean Al foil.
(let go three drops in the spinner drain). Drop
(let go three drops in the spinner drain). Drop
152
Align: Clean, mask using Acetone, then IPA above spinner drain. On MJB3, try to keep same mask position on mask holder. Reset to central position X, Y and rotation (0) orientation of wafer holder. Using IR illumination and wafer holder X, Y, 0 orientation, match alignment marks. Expose: Expose 3.5s Dry: Bake 130 degree C, Imin. Flood Expose: Remove mask from mask holder. Expose 72s. Develop: 30s. in AZ300 pure. Post bake: 110 degree C, Imin.
• Removing photoresist
Use Acetone or heated PRS2000 at 130 degrees C. Rinse in clean water. Note: In the case of the liftoff process, Acetone is a slower process more indicated for smaller circuits linewidths. Also heated PRS2000 above 130 degree C will remove Silver Epoxy glue which is used in bonding circuits.
• Liftoff
Seat 30 min. at 100 degrees C PRS2000. Remove extra metal by squeezing Acetone on the wafer. Rinse. Note: small linewidths circuits or circuits with Silver Epoxy, use overnight Acetone.
• Aligning with MJB3
Align: Clean new mask using Acetone, then IPA above spinner drain. On MJB3, try to keep same mask position on mask holder. Reset to central position X, Y and rotation (0) orientation of wafer holder. Using IR illumination and wafer holder X, Y, 0 orientation, match alignment marks.
• Plating
Plate Au - X/jm: Pour Au solution in tank with stirrer. Connect probe. Set 55 degree C probe target, 150 rpm stirrer. Connect power supply, positive resistor, negative sample. Set current 5mA, voltage lOV. Rate is: 0.1|im/min. is plated on 1 cm^ surface if current is 2mA at 55 degrees C, Rinse in cascade (from back to front). Dry with Nt gun. Check thickaess on AlphaStep equipment. Note: if the level of the Au plating solution is too low, add water to compensate the evaporation. When plating is finished, clean and rinse very carefully (away from Acids danger).
• Etching Ti, Au and Cr
Remove Ti: Seat 5 s. in HF 1: 10 H20. Visible etching of Ti (bubbles). Rinse in cascade starting from the back (dirtiest water) to the front (cleanest water). Seat in clean water (front) for 2 min.
153
Dry with Nt gun.
Remove Au: Seat in Au etch solution (TFA). Rate is 1680A/niin. at 25°C. Rinse in cascade starting from the back to the front. Seat in clean water (front) for 2 min. Dry with N? gun. Remove Cr: Seat l~2min. in Cr etch solution (Ceric Ammonium Nitrate and Acetic Acid). Rinse in cascade starting from the back to the front. Seat in clean water (front) for 2 min. Dry with Nt gim.
• Etching the oxide
Etching: Use Buffered oxide Etch solution (BOE) 1:6 H20. With clean pipette, cover the vias with drops of BOE. Etch rate: 950[im/min. ~8min for 7000A. Check on microscope. Si is clear (white) out of brown photoresist frame. Hydrophobic effect, water is rapidly washing away on silicon (where oxide etch was performed). Rinse in cascade water.
• Etching the silicon
Prepare TMAH etching solution: Mix TMAH 1:2 H20 in 140mL dedicated glass beaker: 80mL of H20, 40mL of TMAH. Warm on hot plate using probe, target 90 degree C. Cover with A1 foil. Wait until solution stable, i.e. plate temperature is 140 degree C. Rate is lOOnm/3 hours. Etch of natural oxide (layer of oxide that forms on the wafer in contact with air): Use BOE 6:1 H20. ISsec. rinse quickly in the cascade, back to front. Store in 140mL-glass beaker filled with water. Si etch: Put wafer in warm TMAH. Notice bubbling effect at vias and windows location. When fuushed, seat wafer in clean water for a night. Rinse. Notel: 400(im wafer takes 8h20min. Caution: solution evaporates, add water at half of the process. Note2: TMAH is Tetramethylammonium Hydroxide
• Pouring vias with Silver Epoxy
Prepare Silver Epoxy: Mix Silver paste and epoxy paste, 1:1 on Al foil. Sharpen tooth peak with a cutter. Pour Silver Epoxy. using the tooth peak, pour gently the paste in the vias by only touching the walls, and in the case of vias close to slot, away from the slot. Check on microscope, remove extra Silver Epoxy with tooth peak using acetone if necessary. Bake in oven-, bake 130 degree C, 20 min. Cool down. Check conductivity: using DC multimeter.
154
APPENDIX E. FABRICATION RECIPE FOR DUROID CAVITY FILTER
• Preparing the board
• Performing lithography with PRl 915
• Etching Copper
Protect back side of the wafer using tape. Perform etching.
• Stripping photoresist
• Drilling holes
Use drill bit to perform thin holes through the board at previously patterned locations.
• Cleaning
• Performing lithography with PRl 827 on the back
• Etching Copper
Protect top side of the wafer using tape. Perform etching.
• Cleaning
• Fabricating vias
155
APPENDIX F. FABRICATION RECIPE FOR SILICON CAVITY FILTER
1. Feed wafer - top side
• Cleaning
Dice quarter piece of 4" high resistivity Si wafer (thickness: 400~500^m) with 7000A oxide layer (both sides look green) and Ti/Au/Ti (500A/2KA/500A) on top (look like Silver).
• Pattern with PRl 827
Spin photoresist. Expose. Develop. Post-bake.
• Etching the Titanium
Remove Ti.
• Plating
Plate Au 3iJm. Relative to surface to plate, rate is 3[im/10min. Screen indicate: 5mA, ~ TV for lOmin. This value is given as an indication — rate strongly depends of the area to plate (cf. previous appendix).
• Metal etching
Remove photoresist in Acetone or heated PRS2000. Rinse. Remove Ti. Remove Au. Remove Ti.
Note: Oxide layer becomes visible (green).
2. Feed wafer — bottom side
• Cleaning
• Protecting topside of the wafer with PRl 827
Cover topside with photoresist to protect oxide from being etched during the following step.
• Patterning using PR1827
Spin PRI827 on backside.
• Aligning withMJBS
Align. Expose. Develop. Post-bake.
• Etching the oxide
Etching using BOE. Remove photoresist.
• Cleaning
• Patterning with PR5214 for liftoff
Spin Photoresist on backside. Align on MJB3. Expose. Dry. Flood Expose Develop. Post bake.
• Evaporating
Store in wafer holder. Cover with Al foil to prevent UV light from damaging photoresist. Evaporate 500A Ti, 2KA Au, and 500A Ti.
• Liftoff
Do liftoff. Remove Ti.
• Plating
Plate .4u 2/jm.
• Etching the oxide
• Etching the silicon
157
Prepare TMAH etching solution. Etch natural oxide Etch silicon. Rinse.
• Etching the Titanium
Remove Ti.
• Pouring the vias with Silver Epoxy
Mix Silver Epoxy. Pour vias. Bake in ovens. Check conductivity.
3. Cavity wafer — wet etch option
• Growing oxide layer
Place Imm thick quarter pieces of 4" wafer in the furnace at 1000 degree C. Activate oxygen. For a 6000A thickness, leave ~ 10 hours depending on the position in the furnace.
• Cleaning
• Patterning using PR5214 for liftoff
Spin Photoresist on topside. Align on MJB3. Expose. Dry. Flood Expose Develop. Post bake.
• Evaporating
Store in wafer holder. Cover with AI foil to prevent US'" light from damaging photoresist. Evaporate 500A Ti, 2KA Au.
• Liftoff
Do liftoff.
• Protecting backside of wafer using PR1827
Cover backside with photoresist to protect oxide from being etched during the next step.
. • Etching the oxide
158
• Cleaning
• Etching the silicon
Prepare TMAH etching solution. Etch natural oxide Etch silicon. Rinse.
• Bonding etched wafer to carrier
Mix Silver Epoxy: On carrier wafer (Imm thick wafer, polished both side): using Q-tip drop gently the paste in fine spots away from alignment marks which will be used later IR alignment with feed wafer. Carefully adjust the previously etched wafer on the carrier wafer. Apply gentle pressure with Q-tip at different location to generate even contact. Seat on glass slide. Bake in oven.
• Protecting alignment marks
Protection against evaporation: Paste PR1827 at mark locations using Q-tip. Stick pieces of silicon on the wet photoresist. Bake in oven, 2min. 130 degree C.
• Evaporating
Evaporate 500A Ti, 2KA Au.
• Cleaning
The pieces of silicon are removed.
• Plating
Plate Au Zfjm.
4. Cavity wafer - laser etch option (presented difficulties to match dielectric filler dimensions due to very low tolerances)
• Covering with photoresist • Sending wafer + CAD files • Bonding etched wafer to carrier • Patterning • Evaporating • Lift-off • Plating
159
5. Cavity wafer - water etch option (did not result in enough accuracy in cavity comers)
• Sending wafer + CAD files
• Bonding etched wafer to carrier
• Patterning
• Evaporating
• Lift-off
• Plating
6. Dielectric material
• Dicing
Use diamante saw to dice material matching proper dimensions.
• Cleaning
• Polishing
Use silicon carbide sandpaper from grade 220 down to grade 1500 to polish all surfaces. Add water and sand thoroughly without adding pressure. Fim'sh polishing on a silicon Carbide disk with water and alumina powder.
• Cleaning
• Evaporating
Evaporate 700A Cr, 3KA Au.
• Patterning using PRl 827
Expose Imin.
• Metal etching
Remove Au (use syringe to drop precisely chemical at slot location) ~ 2.5min. Remove Cr (idem) ~ 2min.
• Plating
Remove photoresist in Acetone or heated PRS2000. Plate Au 5/oti.
• Cleaning
160
• Evaporating
Tape material on carrier wafer, previous face protected Evaporate 700A Cr, 3KA Au.
• Platting
Plate Au Sfmi.
• Cleaning
7. Assembling filter
• Spread Silver Epoxy on cavity wafer away from alignment mar5cs.
• Use DR. aligimient marks or the open windows in the feed waafer which match the marks on the cavity wafer.
• Bake in oven
161
APPENDIX G. FABRICATION RECIPE FOR SILICON DIELECTRIC FILTER
1. Cover wafer - top side
• Cleaning
Dice quarter piece of 4" low resistivity Si wafer (thickness: SOOjim) with 7000A oxide layer (both sides looks green) add Ti (500A) on top. Ti/Au on back (500/2BCa)
• Patterning using PR1827
Spin photoresist. Expose. Develop. Post-bake
• Etching the Titanium
Remove Ti.
• Etching the oxide
• Cleaning
• Etching the silicon.
Prepare TMAH etching solution. Etch natural oxide Etch silicon. Rinse.
• Cleaning
• Plating
Plate Au—l.5/jm:
162
• Cleaning
2. Feed wafer — top side
• Cleaning
Dice quarter piece of 4" very high resistivity Si wafer (thickness: 500|im) Ti/Au/Ti on top side (500A/2KA/500A).
• Spinning
• Patterning using PR1827
• Etching the Titanium
Remove TL
• Plating
Plate Au 1.5pm:
• Metal etching
Remove photoresist in Acetone or heated PRS2000. Rinse. Remove TL Remove Au. Remove Ti.
• Cleaning
3. Feed wafer — bottom side
• Cleaning
• Patterning using PR5214 for liftoff
Spin Photoresist. Align on MJB3 and match top marks using IR. Expose. Dry. Flood Expose Develop. Post bake.
• Evaporating
Store in plastic box with wafer holder. Cover with A1 foil to prevent UV light from damaging photoresist. Evaporate 500 Ti, 2KA Au, 500Ti.
• Liftoff
Do liftoff. Remove Ti.
• Plating
Plate Au If jm.
• Cleaning
4. LOW Cover wafer
• Cleaning
Dice quarter piece of 4" low resistivity Si wafer (thickness: 500[xm). Ti/Au on back (500A/2KA)
• Plating
Plate Au I fjm:
• Cleaning
5. Assembline filter
• Spread Silver Epoxy on feed wafer away from filter IR alignment marks and cavity area.
• Use the open windows in the top wafer to match the marks on the feed wafer.
• Bake in oven.
APPENDIX H. PICTURES OF CIRCUITS
CIRCUIT ON DUROID
t- IN -I
Fig.APX. 17 A1 block support for cavity Fig.APX. 18 AutocadZOOO design
Fig.APX. 19 Assembly with feed and connectors
165
CIRCUIT ON SILICON
Fig.APX. 20 Cavity wafer Gaser machining) Fig.AFX. 21 via — oxide, Au visible
Fig JVPX. 22 Silicon feed wafer top side Fig.APX. 23 Silicon feed wafer bottom side
FigAPX. 24 CPW-microstrip line transition FigAPX. 25 Bended stub
Fig.APX. 26 Coupling slot
167
APPENDIX I. MEASURING AND FABRICATION EQUIPMENTS
Fig.APX. 28 HP 8510C screen Fig.APX. 27 BCP 8510C Network Analj^er
Fig.APX. 30 Alpha Step Fig.APX. 29 MJB3 aligner
Fig.APX. 32 Oxide deposition furnace Fig.APX. 31 Au platting setup
Fig.APX. 33 Measurement setup Fig.APX. 34 Probe Station
FigAPX. 36 Circuit and probes Fig.APX. 35 Probe station and circuit
170
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