InGaAs PIN photodetectorsintegrated and vertically coupled withsilicon-on-insulator waveguides

Zhiqi WangChao QiuZhen ShengAimin WuXi WangShichang ZouFuwan Gan

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InGaAs PIN photodetectors integrated and verticallycoupled with silicon-on-insulator waveguides

Zhiqi Wang,a,b Chao Qiu,a Zhen Sheng,a,* Aimin Wu,a Xi Wang,a Shichang Zou,a and Fuwan Gana,*aChinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology, State Key Laboratoryof Functional Materials for Informatics, 865 Changning Road, Shanghai 200050, ChinabUniversity of Chinese Academy of Sciences, Beijing 100049, China

Abstract. Heterogeneous integration of III–V materials with silicon-on-insulator (SOI) waveguide circuitry by anadhesive die-to-wafer bonding process has been proposed as a solution to Si-based lasers and photodetectors.Here, we present the design and optimization of an InGaAs PIN photodetector vertically coupled with the under-lying SOI waveguide, which could be readily fabricated using this bonding process. With the help of gratingcouplers, a thick bonding layer of 2.5 μm is applied, which inherently avoids the risk of low-bonding yield sufferingin the evanescent coupling counterpart. An anti-reflection layer is also introduced between the bonding layer andthe III–V layer stack to relieve the accuracy requirement for the bonding layer thickness. Besides, by optimizingthe structure parameters, a high-absorption efficiency of 82% and a wide optical 1dB-bandwidth of 220nm areobtained. The analysis shows that the detection bandwidth of the present surface-illuminated photodetector isgenerally limited by transit-time in the i-InGaAs layer. The relationship of the detection bandwidth and the absorp-tion efficiency versus the i-InGaAs layer thickness is presented for the ease of choosing proper structure param-eters for specific applications. With the results presented here, the device can be readily fabricated.© 2014Society ofPhoto-Optical Instrumentation Engineers (SPIE) [DOI: 10.1117/1.OE.53.5.057101]

Keywords: heterogeneous integration; InGaAs PIN photodetector; silicon-on-insulator waveguide; grating coupler.

Paper 140006 received Jan. 2, 2014; revised manuscript received Mar. 9, 2014; accepted for publication Apr. 1, 2014; publishedonline May 5, 2014.

1 IntroductionPioneered by Soref, et al.1,2 over 20 years ago, silicon pho-tonics is attracting more and more attention from both aca-demic community and industry in recent years.3–7 Because ofthe large index contrast between Si and SiO2, it is possible toconstruct waveguides with submicron cross-sections8,9 andvery small bending radii10,11 based on silicon-on-insulator(SOI), which consequently leads to a high-integration den-sity of photonic devices. Besides, SOI offers an excellentplatform by integrating both electronic circuits and photonicdevices on a single chip using the high-quality and large-volume CMOS technology that greatly reduces the costand extends the applications of silicon photonics.

However, silicon is not a good candidate for both gener-ation and detection of light in the near-infrared region due toits intrinsic material properties. To detect light in the near-infrared spectrum (wavelength >1100 nm), III–V materialsand germanium are commonly used. Generally, germaniumphotodetectors show large dark current due to defects formedduring germanium epitaxial growth process.12 Besides,absorption coefficient of germanium drops greatly for wave-lengths beyond 1550 nm preventing their application in L-band.13 It is shown that high-quality III–V materials can beheterogeneously integrated on silicon by means of a low-temperature die-to-wafer bonding process with divinyldisi-loxane benzocyclobutene (DVS-BCB or BCB) as the bond-ing layer.14–17 In this process, unprocessed III–V dies(epitaxial layers down) are first bonded onto a processed

SOI substrate, and then the III–V substrate is removedthrough a combination of mechanical grinding and chemicaletching. After that, wafer-scale processes are applied to fab-ricate the III–V devices and lithographically align them withthe underlying SOI waveguides.

To couple light into the heterogeneously integrated III–Vphotodetectors from silicon waveguides, there are mainlytwo methods: a vertical coupling scheme assisted by gratingcouplers15 and an evanescent coupling scheme.18,19 Althoughthe latter avoids the trade-off between absorption efficiencyand transit-time-limited bandwidth when choosing the thick-ness of the intrinsic absorption layer by decoupling the opti-cal path and electric path, very thin bonding layer (typically<200 nm) is needed to achieve efficient coupling betweenwaveguides and photodetectors, which will be shown inthe following part. For such thin bonding layers, either non-planar wafer surfaces or particles present at the bondinginterfaces can seriously degrade the bonding yield.20 Toimprove the bonding yield, a thick bonding layer is prefer-able. Based on these considerations, InGaAs PIN photode-tectors vertically coupled with SOI waveguides with the helpof grating couplers are designed in this article. The structureparameters of the grating coupler are optimized in detailtoward high power-up efficiency. An anti-reflection layeris also introduced to relieve the accuracy requirement forthe bonding layer thickness. The design trade-off betweenthe absorption efficiency and the transit-time-limited band-width of the present surface-illuminated photodetectorswhen choosing the i-InGaAs layer thickness is illustratedand discussed.

*Address all correspondence to: Zhen Sheng, E-mail: zsheng@mail.sim.ac.cn;Fuwan Gan, E-mail: fuwan@mail.sim.ac.cn 0091-3286/2014/$25.00 © 2014 SPIE

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2 Design and DiscussionIn the evanescent coupling scheme, the coupling lengthbetween silicon waveguides and III–V photodetectors iscritical. We conservatively evaluate it by simulating the cou-pling between two parallel identical silicon waveguides withthe BCB bonding layer in between, as shown in Fig. 1(a).The silicon waveguides considered here are 3-μm wideand 260-nm thick. According to the coupled-mode theory,the mode-coupling effect between two parallel waveguidescan be analyzed by the superposition of the even (zeroth-order mode) and odd (first-order mode) modes.21 Also,the coupling length Lc can be written as: Lc ¼ π∕βe − βo,where βe and βo are the propagation constants of the evenand odd modes, respectively, which can be calculated bya finite difference method mode solver.22 It is found that cou-pling length exponentially increases as the thickness of BCBbonding layer increases as shown in Fig. 1(b), which isconsistent with the coupled-mode theory.

Figure 2 shows the schematic of an InGaAs PIN detectorintegrated on and vertically coupled with an SOI waveguide.The i-InGaAs layer, serving as the intrinsic absorption layer,is sandwiched between an n-InP layer and a p-InP layer.Silicon waveguides are fabricated on SOI wafers with260-nm-top silicon. Buried-oxide (BOX) thickness isoptimized in the following part to improve the device perfor-mance. Second order gratings are etched on SOI waveguidesto diffract light upward toward the III–V stack. Because ofthe vertical symmetry of the grating couplers, partial light isdiffracted downward.

To maximize the diffracted light upward, grating param-eters are optimized using cavity modelling framework(CAMFR),23 a two-dimensional fully vectorial simulationtool based on eigenmode expansion. In the simulation, a400-nm-thick perfectly matched layer condition is set onthe boundary of the simulation window, and the numberof mode considered for mode expansion is set to be 130.TE fundamental mode is launched into the waveguide asthe excitation. The top silicon thickness and the wavelengthconsidered here are 260 and 1550 nm, respectively. The cor-responding refractrive indices of Si, BOX (SiO2), BCB, andInP are 3.476, 1.44, 1.54, and 3.2, respectively. The period ofthe grating is first set to be 630 nm to match a central dif-fraction wavelength of 1550 nm.

For the ease of discussion, we define the following param-eters. Power-up and power-down efficiencies are defined asthe power diffracted upward and downward divided by thetotal input power, respectively. Directionality is defined asthe portion of the upward power over the total-diffractedpower. Because of the large index contrast between silica(n ¼ 1.44) and silicon (n ¼ 3.476), reflection at BOX/Sisubstrate interface would be as high as 8%. For differentBOX thickness, the reflected light may form constructiveor destructive interference, which then affects the power-up efficiency. At the beginning, we investigate the effectof the etch-depth with infinite BOX and BCB layer thick-ness, as shown in Fig. 3. One sees that as the etch-depthincreases, the maximum power-up efficiency at 1550-nmfirst increases accordingly and begins to degrade when theetch-depth is larger than 130 nm. This can be explainedas follows. When the etch-depth is very small (<60 nm),the diffraction is insufficient and lots of light transmitsthrough the grating. As the etch-depth increases (90 to150 nm), more power is diffracted and the power-up effi-ciency increases accordingly. However, when furtherincreasing the etch-depth, the vertical symmetry of the gra-tings reduces the directionality and consequently the power-up efficiency. For SOI wafers with 260-nm-top silicon, thehighest power-up efficiency is obtained at etch-depths of 110to 150 nm. An etch-depth of 110 nm is finally chosenbecause power-up efficiency is stable with the period variesfrom 590 to 710 nm, indicating a large fabrication tolerance.

Then, the thickness of BCB bonding layer and BOX areconsidered. As mentioned earlier, the reflection at the BCB/InP interface and that at the SiO2∕Si substrate interface hasgreat impact on the power-up efficiency. The power-up effi-ciency is maximal when light diffracted upward from the gra-ting constitutes a constructive interference with that reflectedby the SiO2∕Si substrate interface, while at the same timelight diffracts downward forms a destructive interferencewith that reflected by the BCB/InP interface. Figure 4(a)shows such a relationship. Several parameters can be chosento maximize the power-up efficiency. For example, deviceperformance is optimal with a BCB bonding layer of 2.5-μm thick and a BOX layer of 2-μm thick. Figure 4(b)shows the influence of the BCB bonding layer thicknesson power-up efficiency with BOX thickness fixed at2 μm. Power-up efficiency varies between 61% and 82%with different BCB thickness. Since it is tricky to controlthe bonding layer thickness precisely for the general bondingprocess, it is desirable to relieve such a requirement. For thisreason, an anti-reflection layer is added between BCB and

Fig. 1 (a) Schematic of two parallel identical silicon waveguides withthe BCB bonding layer in between. (b) The relationship between thecoupling length and the BCB bonding layer thickness.

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III–V layers. Considering the refractive index of BCB(n ¼ 1.54) and InP (n ¼ 3.2), SiN (n ¼ 2.0), a frequentlyused material in photonics, is selected as the anti-reflectionlayer. When choosing an optimal SiN thickness (i.e.,190 nm), the power variation is reduced to 7% as shownin Fig. 4(b), although the peak efficiency drops slightly,to about 79%. That is because the SiN anti-reflectionlayer influences the destructive interference of the light dif-fracted downward. For fabrication, the SiN layer can bedeposited onto the surface of the III–V material before bond-ing. It can also be easily etched by hot phosphoric acid with ahigh selectivity, during the following III–V processing ifnecessary.

With the above calculation and discussion, the optimalstructure parameters are summarized in Table 1. Then, theoptimal power-up efficiency against wavelength is calculatedand shown in Fig. 5(a). Power-up efficiency is over 70%from 1440 to 1620 nm, covering the whole S, C, and Lbands. The corresponding electric field distribution at1550-nm wavelength is shown in Fig. 5(b). One sees thatlight is diffracted upward effectively into the III–V layer.

The total absorption efficiency η can be expressed asη ¼ η1 · η2, where η1 is the power-up efficiency of thegrating coupler [see Fig. 5(a)] and η2 is the absorption

efficiency of the InGaAs layer. η2 can be written asη2 ¼ 1 − e−αL, where α and L are the absorption coefficient(which can be obtained from Ref. 13) and InGaAs layerthickness, respectively. The total absorption efficiency ηof the current photodetectors with different InGaAs layerthickness is shown in Fig. 6. For efficient absorption, the

Fig. 2 Cross section of an InGaAs PIN photodetector integrated on and vertically coupled with anunderlying silicon-on-insulator waveguide.

Fig. 3 Power-up, power-down efficiency and directionality at 1550 nmas a function of the etch-depth with infinite BOX and BCB layer thick-ness. The other structure parameters are: filling factor ¼ 50%,λ ¼ 1550 nm (fixed by tuning the grating period).

Fig. 4 (a) Dependence of power-up efficiency at 1550 nm on BCBbonding layer thickness and BOX thickness. (b) Dependence ofpower-up efficiency at 1550 nm on BCB bonding layer thickness with-out and with SiN anti-reflection layer (BOX thickness fixed at 2 μm).

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InGaAs layer thickness should be larger than 3 μm. Theabsorption efficiency for the wavelength of 1550 nm canreach 82% with the optimal structure parameters.

Finally, the bandwidth of the present photodetectors isdiscussed. There are two main factors limiting the bandwidthof the PIN photodetectors: the drifting time for the carriers totransmit across the absorption layer, and the inherent capaci-tance of the PIN diode. The 3-dB bandwidth can be approxi-mated by Ref. 24:

f3−dB ¼�

1

f2trþ 1

f2RC

�−12

¼��

L0.45ν

�2

þ�2πRεrε0A

L

�2�−12

; (1)

where ftr and fRC represent the transit-time and capacitance-limited bandwidths, respectively. L, vð¼ 6 × 106 cm∕sÞ,25Rð¼ 50 · ΩÞ, εrð¼ 13.9Þ,26 ε0ð¼ 8.854 × 10−12 · F∕mÞ andA are used to represent the InGaAs layer thickness, chargecarrier velocity, series resistance, relative dielectric constant,vacuum dielectric constant, and detector area, respectively.Using the above formula, the 3-dB bandwidth is calculatedand shown in Fig. 7. When the InGaAs layer is very thin(typically <500 nm), the bandwidth is RC limited. Orelse, it is transit-time limited. To illustrate the trade-offbetween bandwidth and absorption efficiency, the relation-ship between the absorption efficiency and the InGaAslayer thickness is also shown in the same figure. Forthe 2-μm-thick InGaAs absorption layer, the present PINphotodetector has a 3-dB bandwidth of 13.5 GHz whereasthe footprint of the photodetector shows little impact.

3 SummaryInGaAs PIN photodetectors integrated and vertically coupledwith SOI waveguides by using grating couplers are investi-gated. In contrast to the evanescent coupling scheme, a thickbonding layer inherently avoids the risk of low-bondingyield. The structure parameters of the grating coupler and

Table 1 Optimal structure parameters.

Parameter name Units Value

Filling factor of gratings 0.5

Etch depth of gratings nm 110

Period of gratings nm 630

Thickness of BCB layer nm 2500

Thickness of waveguide nm 260

Thickness of BOX nm 2000

Fig. 5 (a) The spectral response of the optimal grating coupler and (b)the electric field distribution of the device with optimal structure.

Fig. 6 Absorption efficiency of the photodetector with differentInGaAs absorption layer thickness.

Fig. 7 3-dB bandwidth and absorption efficiency of the present PINphotodetector as InGaAs layer thickness varies.

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the thickness of the i-InGaAs layer are optimized in detail.The absorption efficiency of the optimal photodetectorreaches 82%. Besides, an anti-reflection layer is introducedto relieve the thickness accuracy requirement of the BCBbonding layer. Bandwidth analysis of the PIN photodetectorshows that the bandwidth of the present surface-illuminatedphotodetector is generally limited by transit-time in the i-InGaAs layer. The relationship of the 3-dB bandwidth andthe absorption efficiency versus the i-InGaAs layer thicknessis presented for the ease of choosing proper structure param-eters for specific applications. With the results presentedhere, the device can be readily fabricated.

AcknowledgmentsThis work was supported in part by the Natural ScienceFoundation of Shanghai (No. 11ZR1443700), in part bythe Natural Science Foundation of China (No. 61106051,61107031, and 61275112), and in part by the 863 Project(No. 2012AA012202).

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