input/output organization
DESCRIPTION
Input/Output Organization. Outside the CPU. Computers must be able to communicate with the outside world Large variety of devices size speed distance Timing and electrical properties not the same as within CPU. Single bus structure. Processor. Memory. Bus. I/O device #1. - PowerPoint PPT PresentationTRANSCRIPT
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In1210/01-PDS 1TU-Delft
Input/OutputOrganization
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In1210/01-PDS 2TU-Delft
Outside the CPU Computers must be able to communicate
with the outside world Large variety of devices
- size- speed- distance
Timing and electrical properties not the same as within CPU
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In1210/01-PDS 3TU-Delft
Single bus structure
Processor Memory
I/O device #1 I/O device #n
Bus
............
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In1210/01-PDS 4TU-Delft
Multiple buses
Processor
Memory
I/O device #1 I/O device #n
I/O Bus
............
memorybus
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In1210/01-PDS 5TU-Delft
Buses and interfaces
Bus contains generally three bitstrings: Data lines to transport data Address lines to identify devices Control lines that take care of correct
transfer of data
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In1210/01-PDS 6TU-Delft
Interfaces
Devices are coupled to bus through interface: Address decoder
- for detection if data is for device Data registers
- to store incoming and outgoing data Status and control registers
- to certify status of device- to control transfer
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In1210/01-PDS 7TU-Delft
Interface organization
AddressDecoder
Data andStatus registers
Control circuits
Address lines
Data lines
Control lines
I/Ointerface
Device
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In1210/01-PDS 8TU-Delft
Video terminal
CPU
DATAIN
SIN SOUT
DATAOUT
Video terminal
Keyboard Display
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In1210/01-PDS 9TU-Delft
Operation(1)
READWAIT Branch to READWAIT if SIN=0Input from DATAIN to R1
WRITEWAIT Branch to WRITEWAIT if SOUT=0Output from R1 to DATAOUT
Move DATAIN, R1Move R1, DATAOUT
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In1210/01-PDS 10TU-Delft
Operation(2)
SIN SOUT
012
IOSTATUS
DATAIN
DATAOUT
READWAIT Testbit #1, IOSTATUS Branch=0 READWAIT
Move DATAIN, R1
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In1210/01-PDS 11TU-Delft
I/O Instructions Memory-mapped I/O
- The registers of the devices have addresses in the same space as main memory locations
- Normal instructions can be used» Move DATAIN, R1
I/O instructions- special instructions for I/O
» IN device, data
» OUT data, device
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In1210/01-PDS 12TU-Delft
Memory and register structure
IOPROC1 IOPROC2
......
Mem
CPU
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In1210/01-PDS 13TU-Delft
Address spaces
CPU CPU
IOPROC1
IOPROC1
Mem
0 IOPROC1
IOPROC1
Mem...... ......
memory mapped separate address spaces
12345
6
012012
0
012
012
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In1210/01-PDS 14TU-Delft
I/O and Programming
There are two basic mechanisms for I/O Programmed I/O Non-programmed I/O
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In1210/01-PDS 15TU-Delft
Programmed I/O By executing of special program in CPU Unconditional I/O
- No synchronization with I/O device Passive signaling
- synchronization between CPU and Device by programmed interrogation by CPU
Active signaling- synchronization between CPU and Device by
active interrupt of Device
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In1210/01-PDS 16TU-Delft
Non-programmed I/O
I/O is done by separate active entity Direct Memory Access (DMA)
- some intelligence in device takes care of data transport
Special I/O processors
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In1210/01-PDS 17TU-Delft
Interrupts
...
..............
i i +1
1
M
Compute routine Print routine
Interrupt
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In1210/01-PDS 18TU-Delft
Service Routines I/O device alerts CPU by hardware signal
called interrupt signal Usually special line in control group of IO
bus is used for this: interrupt request line CPU aborts program and starts executing
service routine Much like executing subroutine Exception: routines have nothing in
common ! !
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In1210/01-PDS 19TU-Delft
Handling interrupts Device raises interrupt request Processor interrupts program in
execution Interrupts are disabled Device is informed of acceptance and in
turn lowers interrupt Interrupt is handled by service routine Execution of interrupted is resumed
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In1210/01-PDS 20TU-Delft
Multiple devices How can processor distinguish devices ? How can processor obtain appropriate
starting address service routine ? Should we allow new interrupt while
another is being served ? How do we handle simultaneous
interrupts ?
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In1210/01-PDS 21TU-Delft
Interrupt line
CPU
INT1 INT2 INTn
INTR = INT1 + INT2 + .... + INTn
Finding device by POLLING :- search for device with IRQ bit set in status register
interrupt request
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In1210/01-PDS 22TU-Delft
Vectored Interrupt Device sends identification code on bus Called interrupts vector Issued after GRANT signal from CPU
CPU
INT1 INT2 INTngrant
interrupt request
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In1210/01-PDS 23TU-Delft
Interrupt priority
CPU
INT1 INT2 INTngrant1
priority circuit
grant2
grant3
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In1210/01-PDS 24TU-Delft
Bus arbitration(1)
CPU
grant
interrupt request line (req_i)
bus release line (rel_i)
bus is free iff (rel_1 • rel_2 • ..... • rel_n) =1
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In1210/01-PDS 25TU-Delft
Bus arbitration(2) Request: set req_i <- 1 Acquire: if grant=1, then set rel_i <- 0 and
req_i <- 0 Release: set rel_i <- 1
grant = (req_1 + req_2 + ..... +req_n) •(rel_1 • rel_2 • ..... • rel_n)
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Question
Why does the previous scheme not always work ?
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In1210/01-PDS 27TU-Delft
PowerPC interrupt structure
EE PR SE EP
EE = External interrupt enablePR = Privilege level
SE = Single step trace exception enableEP = Exception prefix
EP=0 -> address service starts at 000001F4 EP=1 -> address service starts at FFF001F4
MSR = Machine State Register
16 17 21 250 31
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In1210/01-PDS 28TU-Delft
PowerPC PowerPC has two special Save/Store
registers: SRR0 and SRR1 After interrupt:
PC
SRR0
MSR
SRR1
Clear Interrupt enable bit in MSR
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Example
SIN SOUT
012
STATUS
DATAIN
6
IE
interrupt
keyboard interface
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In1210/01-PDS 30TU-Delft
Memory Layout
32 K I/O space
32 K program space
1F4
STATUSDATAIN
address READ
LINE ...............
READ .....
buffer area
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In1210/01-PDS 31TU-Delft
Initialization (1)
INTVEC EQU $1F4 Interrupt vector address(location where start address of interrupt routine is stored)
INTEN EQU $40 Keyboard interrupt enableINTDIS EQU 0 and disable masks
(will be stored in status register of device)
NEWMSR EQU $8000 Desired contents of MSR(external interrupt enable)
RTRN EQU $0D Code Carriage Return(for checking end-of-line)
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In1210/01-PDS 32TU-Delft
Initialization (2)
START ADDI R2,0,READ Get address of serviceSTW R2,INTVEC(0) routine and store at
interrupt vector location
ADDI R2,0,LINE Get address of LINESTW R2, PNTR(0) and store at PNTR
ADDI R2,0,INTEN Store interrupt enableSTW R2,STATUS(0) in STATUS register
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In1210/01-PDS 33TU-Delft
Initialization (3)
ADDI R2,0,NEWMSR Store new MSRMTSRR1 R2 in SRR1
ADDI R2,0,MAIN Store new PCMTSRR0 R2 in SRR0
RFI Return From Interrupt
(use new MSR and PC)
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In1210/01-PDS 34TU-Delft
Program (1)
MAIN <main program>.....
READ ..... Save registers
LBZ R30,DATAIN(0) Get input character
LWZ R31,PNTR(0) Load value at PNTRSTBU R30,1(R31) Store character
in bufferSTW R31,PNTR(0) Update PNTR for
next character
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In1210/01-PDS 35TU-Delft
Program (2)
CMPWI CR1,R30,RTRN Check for CR (end ofBNE CR1,DONE line)
ADDI R2,0,INTDIS Store interrupt disable
STW R2,STATUS(0) mask and clear STW R2,STATUS(0) in STATUS register
BL TEXT Call subroutine fordealing with line
DONE .... Restore saved registersRFI Return from interrupt
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In1210/01-PDS 36TU-Delft
Other interrupts Not only I/O devices can cause interrupts Recovery from errors
- Illegal OP code use- Division by 0
Debugging Privilege exception
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In1210/01-PDS 37TU-Delft
Operating Systems(1) In general interrupts controlled by
Operating System CPU in user mode or supervisor mode Privileged instructions only allowed in
supervisor mode- Starting of I/O operations- Setting of priorities- Setting of clock values
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Operating Systems(2) Process: program in execution
- Program- Data- Status: PC, Registers, etc
State of process: running, runnable, blocked
Multi-tasking Time-slicing
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In1210/01-PDS 39TU-Delft
Operating Systems(3) Context switch: change of processes After clock interrupt: dispatcher chooses
suitable process Device drivers: service routines for
devices System Call: call to OS service routine
- printf (“%d\n”,a)- fscanf (file,”%d\n”,&a)
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OS init, services, scheduler
OSINIT Set interrupt vectorsTime slice clock <- SCHEDULERTrap <- OSSERVICESVDT interrupts <- IODATA...
OSSERVICES Examine stack to determine requestCall appropriate routine
SCHEDULER Save current contextSelect runnable processRestore saved context of new processReturn from interrupt
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I/O routines
IOINIT Set process status to BlockedInitialize memory buffersCall device driver to initialize deviceReturn from subroutine
IODATA Poll devices to determine sourceof interruptCall appropriate driverif END=1 then set process to RunnableReturn from interrupt
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In1210/01-PDS 42TU-Delft
VDT driver
VDTINIT Initialize device interface (e.g. baud rate)Enable interruptsReturn from subrouine
VDTDATA Check device statusIf ready then transfer characterIf character = CR then set END=1
else set END =0Return from subroutine
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In1210/01-PDS 43TU-Delft
Direct Memory Access
012
Status &Control
Wordcount
30
R/W
DMA interface
Done
31
IRQ
IE
Start address
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In1210/01-PDS 44TU-Delft
Bus structures
Specification of bus Number of data lines Address space Multiplexing discipline Control structure Synchronous versus asynchronous Physical properties: connectors, pinning,
electrical properties
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Synchronous Bus
Bus clock
Address
Data
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Asynchronous Bus(1)
Address
Data
Ready
Accept
Input Cycle
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Asynchronous Bus(2)
Address
Data
Ready
Accept
Output Cycle
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SCSI bus Small Computer System Interface (SCSI) ANSI X3.131 Up to 25 meter 50-wire cable Up to 8 devices to bus Initiator and target connection Target controls data transfer
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In1210/01-PDS 49TU-Delft
SCSI bus signals Data DB(0),..., DB(7), DB(P) Phase: BSY, SEL Information: C/D, MSG Handshake: REQ, ACK Direction: I/O Other: ATN, RST
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In1210/01-PDS 50TU-Delft
Typical sequence-DB2
-DB5
-DB6
-BSY
-SELfree arbitration select
2 retreats
target
initiator
initiator
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In1210/01-PDS 51TU-Delft
Computer System
Processor Memory Par. intface
Printer Terminal
Ser.intface
SCSIcontroller
Diskcontroller
Disk1 Disk2
CD-ROMcontroller
CD ROM drive
processor bus
SCSI bus