instruction set revised

8/8/2019 Instruction Set Revised

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Data transfer instructions

Allows the microprocessor to communicate with the

outside worldvia the input and out put instructions.

They also provide means formoving data into andout of memory and between the CPU registers.

The operand is always written in the form of

destination, source.

The data moved can be a byte or a word

The destination and the source can not both specify

memory locations

The flags are unaffected by this group of instructions


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Special data transfer instructionDo not use the MOV mnemonics

XCHG instruction perform a register to register or a

register to memory swap that takes the place of threeMOV instructions.

The 8 low-order flag bits can be stored in or loaded

rom reg s er us ng e ns ruc ons anLAHF

IN/OUT a byte or a word of data can be input oroutput but must pass through the accumulator.

AL must be used as the source or destination for 8-bitI/O operations.


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Port address can be specified in two ways:

direct mode: the instruction supplies the address butis limited to ports 0 255 (one byte)Indirect mode: registerDX holds the 16-bit portaddress allowing access to all 65,536 ports

Example

I/O ports 8004H and 8005H.

Solution

MOV DX, 8004H ;point DX at the port address

MOV AX, BX ;data must be in AX

OUT DX, AX ;output the data


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The LEA (Load Effective Address) instruction will

loadpointer and index registers with the effectiveaddress of the labels

LEA BX, MEMBDS

Will load register BX with effective address ofMEMBDS. We would not have to know this address.

LES (load pointer using extra segment) instructions

are intended forloading entirely new address,

including the segment register.

They load the 16-bit destination register and ES orDS segment register with the contents of the double-

word memory operand.


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LEA SI, MEMDWDS

LDS BX DWORD PTR SI

Example

Assume that MEMDWDS defines a double wordbeginning at address 1000H in the data segment as

shown in the figure. What physical address will BX be

pointing to after the following instruction sequence?

E0

0080

10

1003H

1002H

1001H

1000HMEMDWDS


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Loads BX and DS with the contents of the double

word pointed at by SI.

In this case BX=8010 and DS=E000H. The physical

address pointed to by BXBX=E0000H+8010H=E8010H.

Note the single instruction

LDS BX, MEMDWDScould be used with thesame effect.

The last instruction XLAT is useful for extracting datafrom a table using register AL as the offset into the

table.


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Segment override Table below shows the default register

assignments


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The four segment override prefix instructions are

CS:, DS:, ES:, and SS:.Note that the segment override is in effect for the one

instruction onlyand thus must be specified for each

instruction to overridden.A typical application for the segment override is to

allow data to be stored in the code se ment.

Example CODE SEGMENT

COUNT DB 0FFH

MOV AL, CS:COUNT

The variable COUNT is defined with in the code

segment, requiring the MOV instruction to use the

CS: override to access this memory location


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String Instruction

For moving large blocks of data or strings.

For all this instructions the memory source is DS:SI

and the memory destination is ES:DI.

Segment override can applied only to the source

.

The offset memory pointers, DI and SI, are

automatically incremented or decremented

depending on the state ofDFby 1 for bytes or by 2

for words.


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STOS (store string byte or word) and LODS (loadstring byte or word) instructions transfer a byte orword from the accumulatorto memoryor from thememoryto the accumulator

MOVS (move string byte or word) instructioncombines these two operations, transferring the byteor word from the memory source to the memory

es na on.SCAS (scan string byte or word) and CMPS(compare string byte or word) instructions allows thedestination byte or word to be compared with theaccumulator(SCAS) or the memory source(CMPS).


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After execution the flags are setto reflect the

relationship of the destination to the source

element.

The conditionaljump instructions can then be used

to make decision such as jump if AL is greater

than the memory byte or jump if the destination

.


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Repeat prefix

Preceding the instructions STOS orMOVS with theREP (repeat) instruction causes these instructions tobe repeated a number of times equal to the contentsof the CXregister.

By loading CX with the number of words or bytes tobe moved a sin le strin instruction and REP

prefix) can move up to 65,536 bytes.Example

write the 8086 program required to fill the 1000D

byte of memory in the extra segment beginning ataddress BLOCKwith the data byte 20H.

Note the DFis assumed to be 0.


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Solution

MOV AL, 20H ;AL holds the data byte

LEA DI, BLOCK ;DI holds the address of block

MOV CX, 03E7H ;load CX with 1000D

REP STOSB ;store AL at ES:DI, increment

;DI, and repeat 1000 times

The REPE/REPZ (repeat while equal or zero) and

REPNE/REPNZ (repeat while not equal or not zero)

forms of the REP prefix are intended for use with theSCAS and CMPS string instructions. They allow the

string operation to be repeated while equal

(REPE/REPZ) or while not equal (REPNE/REPNZ).


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Logical Instructions Refers to the Boolean logical functions, such as AND,

OR, NOT, exclusive OR, and to the rotate and shift

instructions. These instructions are all performed in the ALU and

usuall affect all the fla s.


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Boolean function Each function is performed bit by bitbetween thesource and destination operands.

CFand OFare reset.

Example

e erm ne e con en s o reg s er an e s a e othe flags after the following instructions are executed.

MOV AL, 6DH

MOV BH, 40HAND AL, BH


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Solution

write the register contents in binary:

01101101 (AL)

01000000 (BH)01000000 =40H (AL)

the flags are affected as follows:

CF = 0 ;CF is reset by the AND instructionPF = 0 ;40H has an odd number of logic 1s

AF = x ;AF is undefined

ZF = 0 ;the result is not zero

SF = 0 ;bit is reset

OF = 0 ;OF is reset by the AND instruction


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The applications ofAND

1.The destination operand can be forced lowby

choosing those bits as 0 in the source operand.

2.To consider the source operand a mask for testingselected bits of the destination operand.

In the above example all bits are masked except bit 6.

if this bit is 0, the result is zero, if it is 1, the result isnon zero.

the instruction sequence

AND AL, BHJZ START

will transfer control to memory location START if bit 6

of register AL is a 0


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using the AND instruction results in a destructive

bit test because the contents of the destinationoperand is altered by the instruction.

TEST: this instruction performs the same functionas AND instruction, but doesnt alter the source or

destination o erand.

This is a particular handy instruction to use whenseveral bits must be tested.


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The OR instruction can be used to force selected bits

high. Example

OR AL, 80H

will force bit 7 of AL high with out changing any ofthe other bits in this register.

complement selected bits.

Example

XOR AL, 80H

will complement bit 7 of register AL with out

changing any of the other bits.


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Shift and rotate instructions The rotated quantity can be an 8-bit or a 16-bitCPU

register or memory location.

The main difference between a shift and a rotate is

that the shifted bits fall off the end of the register,

.

With in the shift group of instructions there are both

arithmetic (SAL and SAR) and logical (SHL and

SHR) shift instructions.

The arithmetic shifts operate so that the sign bit (bit

7 or bit 15) doesnt change when the shift occurs.


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The SAL instruction in effect multiplies the data by 2

(maintaining the correct sign), and SAR divides thedata by 2.

The overflow flag (OF) will be set if the shifted

quantity exceeds the limits for an 8- or 16- bitregister (+127 to -128 for bytes and +32767 to -

32768 for words)

The shift and rotate instructions can be repeated upto 255 times by loading register CL with the desired

count.

Example MOV CL, 5RCL DX, CL will rotate the contents of

register DX left 5 times through the carry


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Arithmetic instructions

the 8086/88 can add and subtract 8- and 16- bit

numbers in any of the general CPU registers,

and using certain dedicated registers, performmultiplication and division of signed or unsigned

numbers.

Addition and subtraction instructionThere are two forms of addition and subtraction

instructions. One includes the carry and the other

doesnt .


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Suppose we wish to add the 32 bit number in register

BX:AX to the 32-bit number DX:CX.BX AX

+DX CX

DX CX

Although there are no 32-bit addition instructions, the

instruction

Example ADD CX, AX ;CX CX + AX

ADC DX, BX ;DX DX + BX + CF


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The first instruction does not include the carry, asthere is no carry in at this point.

If the addition ofAX and CX sets CF, the secondaddition will add this to the sum of the DX and BX.

The SUB (subtract) and SBB (subtract with borrow)instructions work similarly, with CF representing the

orrow con on.

When adding or subtracting one from a memorypointerorcountervariable, the INC (increment) andDEC (decrement) instructions should be used.


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The NEG (negate) instruction forms the 2s

complement of the destination operand, effectivelyreversing its sign. This is done by subtracting the

destination from 0.

ExampleDetermine the value ofAL and the value of the

flags following the instruction sequence

MOV AL, 5NEG AL


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Solution

AL = 00000000 - 00000101 = 11111011 = FBH = -5.the flags are affected as follows:

CF = 1 ;NEG sets CF except when the operand is 0

PF= 0 ;FBH has an odd number of logic 1s

AF= 1 ;there is a borrow out of bit 4

=

SF= 1 ;bit 7 is set

OF= 0 ;there is no overflow condition

The CMP (compare) instruction is useful for determiningthe relative size of two operands. Normally it is

followed by a conditional jump instruction such as

jump if equal or jump if greater than or equal.


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Multiplication and division

Multiplication and division can be performed onsignedorunsignednumbers.

The source operand can be a memorylocation or aCPU register, but the destination operand must beregisterAX (and registerDX for 32-bit results)

Note that the immediate operands are not allowed.


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Example

write a program to input two 8-bit unsignednumbers from input ports A0H and B0H and output

the product to 16-bit output port 7080H.

Solution

,

MOV BL, AL

IN AL, 0B0H

MUL BL

MOV DX, 7080H

OUT DX, AX

Di i i b f d th d i AX th


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Division can be performed on the word in AX or thedouble word in DX:AX. The divisor can be an 8-bitora 16-bitmemory location or CPU register.

Note that the remainder is returned in registerAH orDX when the result does not come out even.

Example

indirect I/O port 8000H by 500D. Determine the resultif the input data is 56,723.


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Solution

MOV DX, 8000HMOV BX, 01F4H

IN AX, DX

DIV BX

The result is AX=int(56,723/500) = 113=71H

And DX=mod(56,723/500)=223=00DFH

The integer multiplication (IMUL) and division (IDIV)

instructions are similar to the unsigned forms exceptthat the most significant bit represents the sign of the

number


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The register usage is shown


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Transfer of control instruction

All programs execute in a sequential manner (fetch

instruction whose address is in IP, increment IP,

and execute the instruction.) however, there are times when it is necessary to

the next instruction in sequence.


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Examples

Group of instructions that must be

executed repeatedly

Groups of instructions that are shared

throughout a program (subroutine)

Conditional transfers based on the state of

e ags, an

Software interrupts.


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Unconditional jump instruction There are five forms of the jump instruction. Three of them are unconditional, (control is

transferred to the target address with out regard forthe state of flags)

When a program control is transferred to a newa ress re a ve o e va ue n , s ca e nearorrelative jump (direct form).

When the target address is within -128 to +127 bytesof IP, it is called short jump

One byte of object code can be saved.

Because one less byte is required the short form is


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Because one less byte is required , the short form is

best. In fact, when assembling your program, theassembler will automatically generate a short jump if it

can determine that the target address is located within

-128 to +127 bytes.

ADDR HEX CODES LABELS OP-CODE OPERANDS

0000 B3 04 MOV BL, 04H

0002 E5 06 REPEAT: IN AX, 06H

0004 F6 F3 DIV BL

0006 E7 9A OUT 9AH, AX

0008 E9 F7 FF JMP REPEAT

000B

Fig. Assembly language program demonstrating the near jump

instruction

ADDR HEX CODES LABELS OP CODE OPERANDS


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ADDR HEX CODES LABELS OP-CODE OPERANDS

0000 B3 04 MOV BL, 04H0002 E5 06 REPEAT: IN AX, 06H

0004 F6 F3 DIV BL

0006 E7 9A OUT 9AH, AX0008 E9 F8 JMP SHORT REPEAT

000A

Fig. program rewritten using the JMP SHORT instruction.One byte of code is saved.

The memory indirectand registerindirect forms

of the jump instruction specify the actual 16-bittarget address.

These two forms are not thus relative.

E l


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Example

JMP SHORT REPEAT instruction can be replacedwith two instruction.

MOV BX, 0002H

JMP BX

Note using indirect jump,

Any address within the code segment can bespecified.

An extra instruction is required to set the target

address.

Wh t l i t f d t t t dd i


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When control is transferred to a target address in a

new code segment, it is called a far jump. Againdirect and indirect forms are possible but neither form

is relative.

The direct form requires the assembler operatorFARPTR to identify the label as being in a new code

se ment.

The indirect forms must specify a double word for thenew CS and IP values.


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C diti l j


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The conditional jump instructions perform a short

jump based on the condition of the status flags.

Table below lists all the testable conditions.

Usuall a conditional um instruction is laced after

Conditional jump

an arithmetic or logical instruction, transferring controldepending on the result of that instruction.


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Example


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Example

Explain the operation of the following program.MOV BL, 47H

IN AL, 36H

CMP AL, BL

JE MATCH

JA BIGJMP SMALL

Note: MATCH, BIG, and SMALL must be locatedwithin -128 to- +127bytes of the corresponding

conditional jump instruction

Solution


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Solution

The program inputs a data byte from input port 36Hand then compare it with 47H.

If a match occurs, control is transferred to the

program beginning at address MATCH.

If the input byte is >47, control is transferred to the

.

If none of these conditions are met, control is

passed to the program beginning at address

SMALL.


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In summary, the conditional jump instructions are

among the most important in the processors

instruction set. Because they allow the processor

to make decisions based on program condition.

Loop instructions


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Loop instructions

To set up a group of instructions to execute severaltimes.

They combine the decrement counter and transfer ofcontrol instruction

Decrement re ister which holds the loo count b

1 at the end of each loop JNZ (jump if not zero) instruction transfers control

back to the start of the loop if the counter registeris not zero


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Example

i th l i t ti it t


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using the loop instruction, write a program segmentto out put 256 bytes from data table beginning ataddress TABLE to out put port A0H.

Solution

LEA SI, TABLE

MOV CX, 0100H

AGAIN: LODSBOUT 0A0H, AL

LOOP AGAIN

assume DF=0

The LOOPE orLOOPZ (loop if equal or zero) and


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LOOPNE orLOOPNZ (loop if not equal or notzero) instructions test CX and ZF.

For example, LOOPE loops while equal this

means that if CX0 and ZF=1, the loop will berepeated.

NoteAll forms of the loop instruction repeat until CX=0,

this means that the loop will be repeated 65,536

times if CX=0 initially.

Push and pop instructions


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Push and pop instructions It uses stack area of the memory.

Recall SS is a 64K-B memory segment whose base

address determined by SS register. Two CPUregisters SP, and BP normally points into this area.

SS segment is LIFO type of memory.

Data is pushed onto the stack by the PUSH sourceinstruction

The POP destination instruction causes the data

currently on top of the stack to be popped into thedestination operand.

Note the stack actually grows downwardwith eachsuccessive PUSH instructions.

Example


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Example

PUSH CX

PUSH BX

1000HSP

CLBH

BL

0FFEH0FFDH

0FFCH

SP

SP

Registers should be popped off the stack in the


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reverse order in which they were pushed on. Before using the stack it is important that register SP

be initialized to a high memory location allowing

room for the stack to grow.

,

processor flags to be stored on the stack.This can be useful with interrupts and subroutines as

the entire state of the machine (all CPU registers and

flags) can be saved and then restored later.


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Call and return instructions


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Call and return instructions

The CALL and RET instructions allow the programmer

to use a group of instructions as a subroutine or

procedure that can be executed several times fromwith in the main program.

jump except that the value ofIP is pushed onto thestack. Control then transfer.

The subroutine must end with a RET instruction, which

causes the top of the stack to be popped into IP,neatly returning control to the instruction in the main

program with which it left off.

The farCALL differs from the nearCALL in that the


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value ofCS (in addition to IP) is saved on the stack.For this reason a farRET instruction is used to pop

CS and IP from the stack when the far procedure has

ended. Like the near jump instructions, the near CALL can be

. ,

allowing the subroutine to be located within +32767 to-32768 bytes of the address in IP. There are no short

forms.

The indirect forms specify the absolute address in amemory location or CPU register.

A direct far CALL requires the operatorFAR PTR to


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tell the assembler that the subroutine is located inanother segment.

The direct forms require a double word to specify

the new CS and IP values


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Software interrupts


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p

An interrupt is a request of the processor to suspend

its current program and transfer control to a new

program called the interrupt service routine (ISR).

software.

For the 8086/88, applying a logic 1 to the INTR or

NMI input lines will initiate the interrupt requests.

Software interrupts are initiated by giving the


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Software interrupts are initiated by giving the

instruction INT type. the processor responds by

pushing the flags, CS , and IP on to the stack.

It then loads new value for CS and IP from an

interrupt jump table located in absolute memory

from 00000 003FFH. These 1KB allow 256

different software interrupt request


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Fig.

Stack area after executingan INT type instruction

FlagsH

FlagsL

SP

SP is the new value of

registerSP

SP

CSHCSL

IPH

IPL

If an INT 23H is executed,the processor will multiplyType32-255

open

003FFH


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23H by 4 (rotate left twice),resulting in the jump tableaddress 0008CH.

CS and IP will then be

loaded with the doubleword stored in 0008CH

Type-4

overflow

Types 5-31

Reserved

by Intel

00010H

00014H

00080H

1 K-B

higher order word, IP in thelower order word)

When ISR has finished, theIRET instruction should beexecuted to pop the flagregister from stack (inaddition to CS and IP).

Type-0

Type-1

Single-step

Type-2

NMI

Type-3

break point

00000H

00004H

00008H

0000CH

4 byte


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Processor control instruction


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Used to control the operation of the processor and set

or clear the status indicators.

DF, IF, and TF are processor control bits

The STD (set direction flag) and CLD (clear direction

flag) instructions are used to set or clear this flag.

STI (set interrupt enable flag) and CLI (clear interrupt

enable flag) enable or disable mask-able interrupts on

the INTR input line. Clearing this bit blocks all

interrupts on INTR effectively masking this input.

There is no instruction for setting or resetting TF


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(trap flag), but the following sequence of instructionscan be used to set TF.

PUSHF

MOV BP, SPOR BYTE PTR[BP+1], 01H

The HALT instruction will stop the processor and

cause it to enter an idle loop. However, once halted it

can be restarted only via a hardware interrupt or

system reset


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instruction set revised

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