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International Journal of Advanced Research in Engineering and Technology (IJARET) Volume 9, Issue 6, November-December 2018, pp. 78–96, Article ID: IJARET_09_06_009
Available online at http://www.iaeme.com/IJARET/issues.asp?JType=IJARET&VType=9&IType=6
ISSN Print: 0976-6480 and ISSN Online: 0976-6499
© IAEME Publication
INTEGRATE & FIRE NEURON AND
DIFFERENTIAL PAIR INTEGRATOR SYNAPSE
INTERCONNECTION– COMPUTATION &
ANALYSIS IN 180NM MOSFET AND CNFET
TECHNOLOGY
Sushma Srivastava
Research Scholar, PAHER, Udaipur& Associate Professor, SAKEC, Mumbai
Dr. Gajendra Purohit
Director, Pacific Science College, Udaipur
Dr. S S Rathod
Professor & Head, Electronics Engineering Department,
Sardar Patel Institute of Technology, Mumbai
ABSTRACT
Neuromorphic Engineering deals with hardware implementation of the biological
neural networks in silicon. The hard ware analog VLSI circuits and systems,
specifically within the imposed constraints of low power and area, find applications in
implants and prosthetics. The silicon neurons and synapses form the basic building
blocks of these networks. The biological plausibility of the neuromorphic networks
largely depends upon the efficiency of their basic building blocks in terms of area and
power consumption. It is thus necessary for the basic components to be compact and
highly energy efficient if the magnificence of biological networks is to be attained in
these hardware neuromorphic networks.
The silicon neuron and synapse circuits are largely benefitted, both in terms of
area and power requirements, from the advancement in semiconductor technology
with constant scaling of the MOSFETs. But in this era, with the approaching end to
MOSFET scaling there is a quest to find a replacement for MOSFETs in the circuits
which may carry forward the inheritance of Moore’s law in future. The Carbon
Nanotube Field Effect Transistors (CNFET) are one of the probable contenders
capable of substituting MOSFETs in circuits owing to their superior electrical
properties, lower power requirements as compared to MOSFETs.
In this works we have transferred a low power Integrate and Fire neuron circuit
and a differential pair integrator static synapse circuit, already reported in literature,
to 180nm MOSFET technology. The circuit simulations are carried out using Cadence
software toolset for varying circuit parameter values to study and analyse their effect
on the outputs. The same circuits are then ported to CNFET technology and simulated
Integrate & Fire Neuron and Differential Pair Integrator Synapse Interconnection–
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using HSPICE software tool for variable circuit parameter values to ensure the
viability of CNFET technology in implementation of analogVLSI neuromorphic
circuits. The differential pair integrator circuit is then connected to the Integrate and
Fire neuron circuit and simulated in 180nm MOSFET as well as CNFET technology
to investigate the communication and signal transfer between them. A comparison of
power consumption in the circuits is carried out for all the simulation accomplished in
180nm MOSFET and CNFET technologyto ascertain the advantage of low power
requirements of circuit implementations in CNFET technology.
Keywords: Neuromorphic, Synapse, Neuron, Analog VLSI
Cite this Article: Sushma Srivastava, Dr. Gajendra Purohit and Dr. S S Rathod,
Integrate & Fire Neuron and Differential Pair Integrator Synapse Interconnection–
Computation & Analysis In 180nm Mosfet and CNFET Technology, International
Journal of Advanced Research in Engineering and Technology, 9(6), 2018, pp 78–96.
http://www.iaeme.com/IJARET/issues.asp?JType=IJARET&VType=9&IType=6
1. INTRODUCTION
Human brains are the most efficient computing systems that perform massively parallel
simple to complex tasks at an expense of very little power and space. Even the best Von
Neumann architecture [1] based supercomputing digital systems of today cannot simulate the
thalamocortical activity in real time. Unlike the conventional Von Neumann digital machine
brain operates on analog principles and uses asynchronous signallingunder variable and noisy
environment. John von Neumann himself foresaw computer designers benefiting from basing
their designs on the brain when he published "The computer and the brain” in 1957 [2].
The superiority and robustness of the biological systems in execution of various intricate
tasks led Carver Mead, at Caltech in mid 1980s, to propose basing the design of
computational systems on the principles of operation in mammalian brain. Further, he
observed that the MOSFET characteristics in the subthreshold regime resembled the physical
properties of protein channels in biological Neurons [3]. He thus, suggested utilization of the
subthreshold region of operation of MOSFETs in implementation of low power circuits. The
analogVLSI (aVLSI) implementation benefits the circuits in terms of area as fewer transistors
are required as compared to digital approaches in emulating neural circuits and systems.
Carver Mead named this novel field of electronics that deals with the implementation of
hybrid analog / digital VLSI circuits and systems based upon the operational and
organizational principles of biological neural networks and systems as ‘Neuromorphic
Engineering’ [3].
The large scale biological neural networks in brain are formed by connections of large
population of neurons through even larger number of synapses. The neurons are the basic
signalling units in brain which are responsible for generation of signals, the nerve impulse or
the action potential, and synapses are the communication links between the neurons.There are
around 100 billion neurons and there may be a few hundred or as many as 200,000 synaptic
connections to each neuron in the human brain. Synapses are the connections between
neurons for the transmission of nerve impulses [4].
There have been many mathematical models reported in literature based upon the
functional and operational properties of the biological neurons. The aVLSI circuit
implementation of these mathematical models results into very compact and low power
neuron circuits. The Integrate and Fire neuron model [3] and conductance-based neuron
model[5]are the two widely used mathematical models of biological neurons. The Integrate
and Fire neuron model is a physiological model that results into the most compact, simple and
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low power aVLSIsilicon neuron circuit [6]. On the other hand, the conductance-based neuron
model emulates all the ion channel conductances of biological neuronand is more relevant
biologically. But the aVLSI circuit implementation of conductance based model [7] needs
more resources leading to increased area and power consumption. Therefore, the Integrate and
Fire model based neuron circuits are the most widely used circuits in implementation of dense
large scale neuromorphic networks and systems.
Synapses are crucial part of a biological as well as an artificial neural system for
computation and transfer of information between neurons. The synapse circuit is responsible
for the transfer of the signal from the presynaptic neuron to the post synaptic neuron. The
synapses can be static with a constant gain or dynamic with modification in gain during
computation. There are various CMOS aVLSI implementation of a pulse-based silicon static
synapse circuits of which the differential pair integrator synapse circuit has linear filtering
propertyand generates sufficiently large charge packets to be sourced into the membrane of
the post synaptic neuron [9]. The synapse circuit translates presynaptic voltage pulses into
post synaptic currents to be injected into the membrane of the target neuron with a constant
gain referred to as synaptic weight. These circuits are implemented with devices operating in
the sub-threshold regime thus maintaining low subthreshold current and hence low power
consumption in the circuit [9].
The large scale neuromorphic networks comprising of densely connected silicon neurons
and synapse circuits are continually benefitted in terms of both the area and power
consumption over the years with the progress in semiconductor technology and device
scaling. But now as the MOSFETs are approaching their physical scaling limits and further
scaling is not possible. Hence, there is quest for a replacement of MOSFETs in the circuits
which can carry the legacy of Moore’s law [10] further.
Carbon Nanotube Field Effect Transistor (CNFET) is a probable replacement of
MOSFETs in the circuits owing to its superior electrical properties, low power requirements,
fabrication feasibility and scaling possibility [11]. The CNFETs, when used in
implementation of neuromorphic circuits, may support the scale of synthetic cortex. The
carbon nanotubes have been shown to induce minimum immune system reactions in living
tissues, thus making carbon nanotube prosthetic devices desirable [12]. Hence, there seems to
be lot of scope of incorporating this device in neuromorphic circuits which may be benefiting
the circuit performance in terms of area and power consumption. The HSPICE software used
in this work for simulations in CNFET technology is based upon the Stanford CNFET
modelproposed by Jie Deng [13, 14]. It is a complete circuit compatible model includes the
practical device non idealities.
2. CIRCUIT DESIGN
In this work a low power Integrate and Fire neuron circuit and a pulse based static differential
pair integrator synapse circuit are implemented in 180nm MOSFET and CNFET technology.
The circuit modules are then integrated to study and analyse the communication between
them.
2.1. Integrate and Fire Neuron Circuit
The Integrate and Fire neuron Circuit design, shown in Fig.1, comprises of thirteen transistors
and three capacitors. It uses a trans conductance amplifier, with PMOS transistors forming the
differential pair connected to a current mirror formed by NMOS transistors, linked to a pair of
inverters, a discharge circuitry and positive capacitive feedback [7]. The circuit implements
an adjustable threshold voltage, spike pulse width and refractory period.
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Figure 1Integrate and Fire neuron Circuit diagram [7]
The input injection current Iinj charges up the capacitor Cmem resulting in an increase in the
membrane voltage Vmem which is fed as input to the transconductance amplifier. The
transconductance amplifier is built up with transistors MP1 to MP3 forming the differential
pair and MN1 to MN2 implementing the current mirror circuit. In the differential pair,
transistor MP1 is used as a current source with bias voltage Vpb controlling the bias current Ib.
The bias voltage Vpb is set such that the transistor works in the saturation region of sub-
threshold regime. The sharing of the bias current between MP2 and MP3 depends on their
respective gate voltages Vmem and Vthr. The differential pair is connected to a current mirror
formed by NMOS transistors MN1 and MN2.
When the membrane voltage Vmem exceeds the threshold voltage Vthr, the output of the
transconductance amplifier goes high. The output of the transconductance amplifier is fed as
input to two inverters formed by transistors MN3, MP4, MP5 and MN4, MN5, MP6
respectively which are connected in series. As a result, the output voltage Vout swings up to
Vdd. The bias voltage Vpb controls and limits the current in both the transconductance
amplifier as well as the first inverter in the subthreshold regime and the same is achieved by
setting up the refractory period control voltage Vrfr in the second inverter. The capacitors Cfb
and Cmem form the capacitor divider fraction which provides a positive feedback to Vmem and
prevents errors at the output in case of any fluctuations in Vmem due to noise around Vthr. The
positive feedback through the capacitor divider formed by the Cmem and Cfb increases Vmem by
an amount proportional to����� [3],
����� = ��
(����� �)��� (1)
The capacitor Cmem starts discharging when Vout goes high through the discharge path
provided by transistors MN6 and MN7 at a rate set by the pulse width control voltage Vpw. As
Vmem goes below Vthr the output of the transconductance amplifier goes to ground potential.
As a result, output of the first inverter switches to Vdd. The PMOS transistor of the second
inverter switches off and the NMOS transistor switches on. The presence of discharge
capacitor Cr at the output node, which charges up to Vdd during a pulse, prevents
instantaneous change of the output voltage Vout to ground potential. Instead, the discharge
capacitor and hence the output voltage Vout discharge through transistors MN4 and MN5 at a
rate set by the bias voltage Vrfr which sets the refractory period of the output.
The inter spike interval, i.e. tlow is inversely proportional to the input current, Iinj. It is the
time it takes for Iinj to charge Vmem by ΔVmem[3],
t��� = ���
����V�� (31)
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The pulse duration period or high time, thigh, is the time it takes to discharge
Vmem by ΔVmem and is given as [3],
t���� = ���
–(����!�")V��(34)
Differential pair integrator Synapse Circuit
The synapse circuit converts the presynaptic voltage pulses into post synaptic current which
serves as the input injection current to the membrane of the postsynaptic neuron in large scale
neuromorphic network. TheaVLSI synapse circuits are implemented with the devices
operating in the saturation region of the sub-threshold regime. The differential pair integrator
synapse circuit ofFig.2includes four n- type transistors MN1- MN4, two p- type transistors
MP1- MP2 and a capacitor C1. The transistors MN1- MN4 form a differential pair and branch
current Ib of the differential pair act as the input to the synapse during the charging phase [9].
The transistor MN1 switches on in presence of an input spike pulse.This results into bias
current Iw, controlled by the weight control bias voltage Vw,to flow in the branch. If Iw>Iτ,
capacitor C1 discharges and voltage V1(t), that drives p-type transistor MP2, decreases. This
leads to an increase in the output current Id[9]. In absence of a pulse at the input capacitor C1
charges towards Vddat a rate set by bias current Iτ, which is controlled by the control voltage
Vτ, and therefore Iddecreases.
Figure 2 Differential pair integrator synapse circuit [9]
The differential pair integrator synapse circuit thus implements low pass filter with linear
transfer function under the assumption Iw>Iτ. It enables the circuit to generate sufficiently
large charge packets to be sourced into the membrane capacitance of the post synaptic neuron.
The low power consumption in the circuit is retained as all the currents are maintained in sub-
threshold regime [9].
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3. CIRCUIT IMPLEMENTATION AND ANALYSIS
3.1. Integrate and Fire Neuron Circuit implementation in 180nm MOSFET and
CNFET technology
The Integrate and Fire Neuron circuit of Fig.1has been implemented at 180nm technology and
simulated in Cadence software at schematic level as well as layout level. The aspect ratio of
all the MOSFETs are retained at a value of 2.22 and the capacitive feedback ���
�#$#� ��� of 0.1
is maintained in the circuit. The circuit is implemented with a supply voltage of 1.8V keeping
all the parameter values below the threshold voltage of the MOSFETs to ensure sub-threshold
operation of the circuit. The schematic circuit level diagram and corresponding mask layout
diagram of the Integrate and Fire neuron circuit implemented in 180nm technology in
Cadence software is shown in Fig.3(a) and Fig.3(b) respectively. The Assura LVS for the
Integrate and fire neuron circuit in Cadence software showed no errors.
(a) Schematic (b) Layout
Figure 3 Integrate and Fire neuron circuit Implementation
The Integrate and Fire Neuron circuit of Fig.1 is then ported to CNFET technology and
simulated using HSPICE software. The circuit topology is kept same and all the MOSFETs in
the circuit of Fig.1 are replaced by CNFETs. All the CNFETs in the circuit contain one single
walled Carbon nanotube bridging the distance between the source and the drain regions of the
device. The HSPICE software used for carrying out CNFET based circuit simulations is based
upon the Stanford CNFET model proposed by Jie Deng [13, 14].
The technology parameters used in the Stanford CNFET model are as follows: the
CNFET device and circuits performance is evaluated at the 32 nm node with 0.9 V power
supply. The gate length Lg= 32nm. All CNTs are assumed to be semiconducting carbon
nanotubes with chirality (19, 0), 1.5 nm diameter and threshold voltage of 0.29V. The Fermi
level of doped S/D, Ef0 is 0.6 eV. The thickness of high-k top gate dielectric material HfO2,
Tox = 4.0 nm and its dielectric constant k1=16. It is present on top of 10 μm thick SiO2 in the
device. The metal work function and CNT work function are assumed to be the same as equal
to 4.5 eV [13, 14].
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3.1.1. Effect of pulse width control bias voltage on output spike pulses
The Integrate and Fire neuron circuit has been simulated for variable Vpwvalues keeping all
other circuit parameter values constant. The input injection current Iinj in these simulations is
kept constant at 5nA.Fig.4 and Fig.5 show the simulation outputs of the circuit in 180nm
MOSFET and CNFET technology respectively. The simulation outputs in both the
technologies illustrate that the output voltage spike pulse width decreases with the increasing
values of Vpw.The increased values of Vpw increase the rate of discharge of membrane
capacitor Cmem which results in faster decrease in the membrane voltage Vmem.This thus leads
to decrease in the pulse width or high time thighat the output. The experimental and the
theoretical values of output voltage spike pulses and the inter spike pulse duration are
presented in Table 1 and Table 2 in 180nm MOSFET and CNFET technology respectively.
Schematic Simulation Outputs Layout Simulation Outputs
(a) Vpw= 220mV
(b) Vpw= 240mV
Figure 4Integrate and Fire Neuron Circuit (180nm MOSFET technology) Simulation
Outputs - Effect of varying Vpw on thigh of Vout (Iinj= 5nA, Vpb= 1.5 V, Vthr= 1.5
V, Vrfr= 380mV)
Table 1Effect of Varying Vpw On Vout
(Iinj= 5nA, Vpb= 1.5 V, Vthr= 1.5 V, Vrfr= 380mV)
S.
No.
Pulse
Width
Control
Voltage
Vpw (mV)
Simulation
level of
abstraction
Theoretical values Experimental Values
Discharge
Current Ir
(nA)
Pulse width
duration of
Vout thigh
(µS)
Inter
Pulse
Duration
tlow(µS)
Pulse width
duration of
Vout thigh (µS)
Inter Pulse
Duration
tlow(µS)
Average
Power
consumption
(µW)
1. 220 Schematic 19.659 61.396 180 62.832 189.56 0.796
Layout 19.472 62.189 180 62.94 190.32 0.796
2. 240 Schematic 32.759 32.422 180 33.89 196.24 0.784
Layout 32.775 32.403 180 33.86 197.9 0.783
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Vpw= 150mV Vpw= 160mV
Figure 5 Integrate and Fire Neuron Circuit Simulation Outputs (CNFET Technology) -
Effect of varying Vpw on thigh of Vout (Iinj= 5nA, Vpb=0.7V, Vthr=0.65V, Vrfr=0.28V)
Table 2 Effect of Varying Vpw On Vout
(Iinj= 5nA, Vpb=0.7V, Vthr=0.65V, Vrfr=0.28V)
S.
No.
Pulse
width
control
voltage
Vpw (mV)
Theoretical values
Experimental Values
Discharge
Current Ir
(nA)
Pulse width
duration of
Vout thigh (µS)
Inter Pulse
Duration
tlow(µS)
Pulse width
duration of
Vout thigh (µS)
Inter Pulse
Duration
tlow(µS)
Average
Power
consumption
(µW)
1. 150 6.54 292.207 90 293 91 0.055
2. 160 9.4 102.272 90 102 95 0.029
3.1.2. Effect of Input injection current on output spike pulses
The Integrate and Fire neuron circuit simulation outputs for variable input injection current
Iinjwith all other circuit parameters maintained at constant values are shown in Fig.6 and Fig.7
in 180nm MOSFET and CNFET technology respectively. As noticed in Fig.6 and Fig.7 the
frequency of the output voltage pulse train increase with the increasing value of the input
injection current Iinj.This is because the rate of charging of membrane capacitor Cmem
increases with the increased value of the dc input injection current Iinj. The membrane voltage
Vmem attains value above the threshold voltage of the transconductance amplifier, Vthr, faster
resulting in an increase in the frequency of the output voltage pule train. The Table 3 and
Table 4depict the effect of Input injection current on the frequency of the output voltage spike
pulses in 180nm MOSFET and CNFET technology respectively.
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Schematic Simulation Outputs Layout Simulation Outputs
(a) Iinj= 2nA
(a) Iinj= 8nA
Figure 6Integrate and Fire Neuron Circuit (180nm MOSFET technology) Simulation Outputs
- Effect of varying Iinj on Vout (Vpb= 1.5 V, Vthr= 1.5 V, Vrfr= 380mV, Vpw=
220mV)
Table 3 Effect of Varying Iinj on the Frequency of Vout
(Vpb= 1.5V, Vthr= 1.5V, Vrfr= 380mV, Vpw= 220mV)
S.
No
.
Input
Current
Iinj (nA)
Simulation
level of
abstraction
Theoretical values Experimental Values
Discharge
Current
Ir(nA)
Pulse width
duration of
Vout thigh (µS)
Inter Pulse
Duration
tlow(µS)
Output
Pulse
TrainFreq
uency
(KHz)
Pulse width
duration of
Vout thigh (µS)
Inter Pulse
Duration
tlow(µS)
Output
Pulse Train
Frequency
(KHz)
Average
Power
consumption
(µW)
1. 2 Schematic 19.977 50.064 450 1.99 52.225 483.34 1.867 0.744
Layout 19.690 50.876 450 1.996 52.17 486.38 1.856 0.744
2. 8 Schematic 19.742 76.647 112.5 5.2868 79.164 117.211 5.092 0.859
Layout 19.442 78.657 112.5 5.231 79.43 117.7 5.073 0.859
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Table 4 Effect of Varying Iinj on the Frequency of Vout
(Vpb= 0.7V, Vthr= 0.65V, Vrfr= 0.28V, Vpw= 0.2V)
S.
No.
Input
Current
Iinj (nA)
Theoretical values Experimental Values
Discharge
Current Ir
(nA)
Pulse
width
duration
of Vout
thigh (µS)
Inter
Pulse
Duration
tlow(µS)
Output
Pulse
Train
Frequency
(KHz)
Pulse
width
duration
of Vout
thigh (µS)
Inter
Pulse
Duration
tlow(µS)
Output
Pulse
Train
Frequency
(KHz)
Average
Power
Consumption
(µW)
1. 2 32.9 14.563 225 4.174 15 263 3.597 0.0735
2. 8 32.9 18.0722 56.25 13.455 19 62 12.346 0.0344
(a) Iinj= 2nA (b) Iinj= 8nA
Figure 7 Integrate and Fire Neuron Circuit Simulation Outputs (CNFET Technology) –
Vout for varying Iinj values (Vpb= 0.7V, Vthr= 0.65V, Vrfr= 0.28V, Vpw= 0.2V)
3.1.3. Effect of refractory period control bias on output spike pulses
The Integrate and fire neuron circuit is finally simulated with variable values of the refractory
period control voltage Vrfr and other circuit parameters retained at constant values. The
increased value of Vrfr increases the rate of discharge of Cr resulting in faster decrease in the
membrane potential Vmem and the output voltage Vout. This results into a decrease in the
refractory period of the output with an increase in the value of Vrfras observed inthe
simulation outputs of Fig.8and Fig.9 in 180nm MOSFET and CNFET technology
respectively.
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Figure 8Integrate and Fire Neuron Circuit (180nm MOSFET technology) Simulation Outputs
– Vmem and Vout for varying Vrfr values (Iinj= 5nA, Vpb=1.5V, Vpw=220mV,
Vthr=1.5V)
(a) Vrfr= 0.22V (b) Vrfr= 0.25V
Figure 9Integrate and Fire Neuron Circuit Simulation Outputs (CNFET Technology) – Vout
for varying Vrfr values (Iinj= 5nA, Vpb= 0.7V, Vpw= 0.17V, Vthr= 0.65V,)
3.2. Differential pair integrator synapse
The schematic and layout level implementation of the differential pair integrator synapse
circuit of Fig.2 is shown inFig.10(a) and Fig.10(b) respectively in 180nm MOSFET
technology using Cadence software toolset. The LVS check of the circuit showed schematic
netlist completely matching with the layout netlist.
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(a) Schematic (b) Layout
Figure 10Differential pair integrator synapse
3.2.1. Effect of variation in Vw on the synaptic output current
The differential pair integrator synapse circuit simulation results for variable synaptic weight
control voltage Vware shown in Fig.11 and Fig.12 in 180nm MOSFET and CNFET
technology respectively. The increase in the value of Vwleads to an increasein currentIwthus
increasing the rate of discharge of capacitor C1. The node voltage V1 thus decreases to a
lower potential resulting into a higher synaptic current at output with each subsequent input
pulse.The increase in value Vwtherefore results in an increasedgain and the steady state
synaptic current output of the circuit as observed in the simulation outputs of Fig.11 and
Fig.12.The time constant of the circuit same in all the simulations as the rate of discharge of
the output current is constant due to constant value of Vτ.
(a) Schematic
(b) Layout
Figure 11 Effect of variation in Vw on the synaptic output
current (Vτ= 1.64V, Vth= 0.30Vand 50Hz
input voltage pulse frequency)(180 nm
MOSFET Technology)
Figure 12 Effect of variation in Vw on the
synaptic output current (Vτ= 0.7V,
Vth= 0.15V and 50Hz input voltage
pulse frequency)(CNFET
Technology)
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3.2.2. Effect of variation in Vτ on the synaptic output current
The increase in the value of the bias voltage Vτ results into an increase in the gain and the
time constant of the circuit as observed in thesimulation outputs of Fig. 13 and Fig. 14,in
180nm MOSFET and CNFET technology respectively, for variable Vτand all other circuit
parameters at constant values. This is due to the fact that increased value of Vτleads to
decrease in the current Iτwhich decreases the rate of charging and increases the rate of
discharging of the capacitor C1 consequently increasing the steady state value and time
constant of the synaptic output current Id.
(a) Schematic
x
(b) Layout Figure 13 Effect of variation in Vτ (= 1.62V, 1.63V, 1.64V) on
the synaptic output current (Vw= 0.24V, Vth= 0.30V and 50Hz
input voltage pulse frequency)(180 nm MOSFET Technology)
Figure 14Effect of variation in Vτ
on the synaptic output current
(Vw= 0.26V, Vthr= 0.15V and
50Hz input voltage pulse
frequency)(CNFET Technology)
3.2.3. Effect of variation in the frequency of input spike pulse voltage Vspk on the
synaptic output current
The simulation outputs of Fig. 15and Fig. 16 for variable frequencies of the presynaptic input
spike pulse voltage Vspk and other circuit parameters at constant values, in 180nm MOSFET
technology and CNFET technology respectively, demonstrate higher values of steady state
synaptic current Id for higher input frequencies. At lower input spike pulses frequencies node
V1(t) charges to a higher potential, towards Vdd, in absence of the spike pulse at the input.
The voltage at node V1 at the end of the input spike pulse therefore is higher resulting in a
lower steady state synaptic current Id.
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(a) Schematic
(b) Layout
Figure 15Effect of variation in frequency of Vspk on
the synaptic output current (Vτ= 1.65V, Vw= 0.26V,
Vth= 0.30V)(180 nm MOSFET Technology)
Figure 16Effect of variation in the frequency
of input spike pulse voltage Vspk on the
synaptic output current (Vτ= 0.7V, Vw=
0.26V, Vth= 0.15V)(CNFET Technology)
3.3. Differential pair Integrator synapse and Integrate and Fire Neuron
interconnection
The signal transmission in aVLSI neuron circuits via synapses is examined by connecting
Integrate and Fire neuron circuit to the static differential pair integrator synapse circuit with
the neuron circuit being driven by the synaptic output current of the synapse circuit. The
circuit has been implemented in 180nm MOSFET and CNFET technology using the
differential pair integrator synapse circuit module of Section 3.2 and the Integrate and Fire
Neuron circuit module of Section 3.1. The circuit parameter values are adjusted to ensure
proper communication between them keeping the circuits currents in the sub-threshold range.
The spike input voltage pulsesVspk of different frequencies from a presynaptic neuron are
passed to a postsynaptic Integrate and Fire neuron via differential pair integrator Synapse.
Fig.17(a) and Fig.17(b) respectively show the schematic and layout level connections of the
differential pair integrator synapse module to the Integrate and Fire neuron module
implemented in Cadence software at 180nm technology. The Assura LVS for the static
excitatory synapse circuit integrated with Integrate and Fire neuron circuit in Cadence
software showed no errors.
Sushma Srivastava, Dr. Gajendra Purohit and Dr. S S Rathod
http://www.iaeme.com/IJARET/index.asp 92 [email protected]
(a) Schematic (b) Layout
Figure 17 Connection of a Differential Pair Integrator Synapse to an Integrate and Fire
Neuron Circuit in Cadence software toolset (180nm MOSFET technology)
The Fig.18and Fig.19 show the simulation output of the differential pair integrator
synapse circuit connected to the Integrate and Fire neuron circuit modules for the input spike
pulses of frequencies of 50Hz and 100Hz applied to the input of the synapse circuit in 180nm
MOSFET and CNFET technology respectively.
(a) Schematic (b) Layout
Figure 18 Connection of a Differential Pair Integrator Synapse to an Integrate and Fire
Neuron; Simulation outputs (180 nm MOSFET Technology): Vspk and Vout for
frequencies of 50Hz and 100Hz (Vτ= 1.7V, Vw=0.21V, Vpw=0.3V, Vpb=1.5V,
Vthr=1.5V, Vrfr= 0.38V)
Integrate & Fire Neuron and Differential Pair Integrator Synapse Interconnection–
Computation & Analysis In 180nm Mosfet and CNFET Technology
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(a) Vspk= 50Hz (b)Vspk= 100Hz
Figure 19Connection of a Differential Pair Integrator Synapse to an Integrate and Fire
Neuron: Schematic Simulation Outputs(CNFET Technology): Vspk and Vout for
frequencies of 50Hz and 100Hz (Vτ= 0.85V, Vw=0.16V, Vth= 0.22V,
Vpw=0.245V, Vpb=0.85V, Vthr= 0.65V, Vrfr= 0.28V)
The output waveforms of Fig.18and Fig.19 show that the connection of a differential pair
integrator synapse to an Integrate and Fire neuron set with the specified circuit parameter
values can efficiently pass signals of different frequencies between neurons via differential
pair integrator synapse in 180nm MOSFET as well as CNFET technology respectively.
The simulation output waveforms of Fig.20and Fig.21show expected variation in the
refractory period of the neuron circuit with varying refractory period control voltage Vrfr in
the Integrate and Fire neuron circuit in 180nm MOSFET as well as CNFET technology
respectively. The refractory period increases with the decrease in the value of Vrfr.
(a) Schematic (b) Layout
Figure 20 Connection of a Differential Pair Integrator Synapse to an Integrate and Fire Neuron:
Simulation Outputs for Vrfr= 0. 1V and Vs frequency of 50Hz (Vτ= 1.7V, Vw=0.21V, Vpw=0.3V,
Vpb=1.5V, Vthr=1.5V)
Sushma Srivastava, Dr. Gajendra Purohit and Dr. S S Rathod
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Vrfr= 0.08V (b) Vrfr= 0.05V
Figure 1: Connection of a Differential Pair Integrator Synapse to an Integrate and Fire Neuron:
Schematic Simulation Outputs in HSPICE software- Vs and Vout for frequencies of 50Hz for varying
Vrfr (With higher capacitor values in neuron circuit and (Vτ= 0.85V, Vw=0.16V, Vth= 0.22V,
Vpw=0.245V, Vpb=0.85V, Vthr= 0.65V)
4. RESULTS AND DISCUSSION
The Integrate and Fire neuron circuit and the differential pair integrator synapse circuit from
literature were ported to 180nm MOSFET technology and CNFET technology in this work
for study and analysis. The Cadence software toolset has been used for MOSFET circuit
simulations and CNFET circuits are simulated using HSPICE software. A comparison of
average dc power consumption in these circuits implementations in both the technologies is
presented in Table 5.
Table 5 Average Power Consumption
S.
No. CircuitImplementation
Average Power
Consumption(µW)
180nm
MOSFET
technology
CNFET
technology
1. Integrate and Fire neuron circuit (with PMOS
differential pair, Iinj= 5nA) 0.796 0.029
2. Integrate and Fire neuron circuit (with NMOS
differential pair,Iinj= 4nA) 30.50 [15] 0.069 [16]
3. Differential pair integrator synapse 10 0.00481
4. Differential Pair Integrator Synapse and Integrate and
Fire Neuron interconnection (Vs= 50Hz) 0.062 0.034
5. Current Mirror Integrator Synapse and Integrate and Fire
Neuron interconnection (Vs= 50Hz) [15] 177.30 3.08
The power consumption in the Integrate and Fire neuron circuit, with the
transconductance amplifier being constituted using PMOS transistors in differential pair and
the NMOS transistors forming the current mirror is reduced by two orders of magnitude as
Integrate & Fire Neuron and Differential Pair Integrator Synapse Interconnection–
Computation & Analysis In 180nm Mosfet and CNFET Technology
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compared to the Integrate and fire neuron circuit reported in [15] which comprises of a
transconductance amplifier with differential pair formed by NMOS transistors and the PMOS
transistors forming the current mirror. The reason behind this is that the circuit with PMOS
differential pair has lower bias currents in the circuit as the bias current is fixed up by a
PMOS transistor. The same circuit when implemented in CNFET technology consumes even
less power which an order of magnitude is smaller than an equivalent implementation in
180nm MOSFET technology. The CNFET circuit simulation outputs obtained using circuit
compatible HSPICE software are agreement with the calculations obtained using same
mathematical model which has been used to explain MOSFET based Integrate and Fire
neuron circuit characteristics.
The average dc power consumption in differential pair integrator synapse circuit is
approximately three orders of magnitude smaller when the circuit is implemented and
simulated in CNFET technology as compared to the implementation in 180nm MOSFET
technology. The circuit also shows lower power consumption in both the technologies as
compared to the current mirror integrator synapse circuit reported in [15].
The simulation results show successful passage of presynaptic input pulse,Vspk, provided
at the input of the differential pair integrator synapse circuit to the postsynaptic neuron as the
output Vout of the neuron circuit in 180nm MOSFET as well as CNFET technology. Further,
the results also indicate that the average power consumption in the differential pair integrator
synapse connection to an Integrate and Fire neuron circuit with PMOS differential pair in
180nm MOSFET and CNFET technologies have smaller values as compared to the current
mirror synapse circuit and Integrate and fire neuron circuit with NMOS differential pair
integration.
The average power consumption of CNFET based neuron circuits and the synapse circuits
and their connections is quite low as compared to equivalent implementations in MOSFET
technology. There is a possibility of CNFET device scaling which would increase the area
efficiency of the circuits implemented in this technology. All these features together confirm
the feasibility of implementation of dense large scale neuromorphic networks in CNFET
technology.The results therefore reflect the possibility of implementing neuromorphic
networks in CNFET technology and achieving a comparable performance with added
advantages of CNFET technology in terms of power consumption and area occupancy.
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