Integrated Systems LaboratoryMicroelectronics Design Center

Research Review 2011

Qiuting Huang Vanessa Wood Mathieu Luisier

Hubert Kaeslin Norbert Felber

2

Contents

Contents 2Introduction 5New Research Activities at IIS 7Organization 10Representative Figures 11Staff 13Partners and Funding Agencies 15Awards 20Research Projects: IC and System Design and Test 21

Compressed Sensing for Passive Bistatic Radar 22Approximate Message Passing for Audio Restoration 22Computational Stereo Camera System 23Full-HD Video Rendering System 23High-Dimensional Sparse Linear Solver on FPGA 24Metric Omnidirectional Optical Flow 24High-Speed Network Interfaces and 100 Gbps Payload Encrytion 25Hardware Evaluation of Third Round Secure Hash Algorithm Candidates 25Comparing ECDSA Hardware Implementations Based on Binary and Prime Fields 26

Research Projects: Analog and Mixed-Signal IC Design 27A 12-bit High-Speed Folding and Interpolating Analog-to-Digital Converter 28Multi-Mode A/D and D/A Converters for High-Performance Wireless Links 28Multi-Band Receiver Design for LTE Mobile Communication 29Multi-Band Transmitter Design for LTE Mobile Communication 29Low Noise Multi Standard Frequency Synthesizer in Nano Scale CMOS 30Multichannel Front-End for Biomedical Applications 30Real-Time Testbed for Advanced Mobile Transceiver Development 31Hardware Efficient Interference Cancellation Algorithms for the GSM Evolution 31Digital Front-End Design for 3.5G Mobile Receiver 32Interference Cancellation-aided Equalizers/Detectors for TD-HSPA 32Channel Coding and Hybrid ARQ for TD-HSPA 33Trade-offs in the VLSI Implementation of LDPC Decoders 33

Research Projects: Technology CAD 35TCAD Study of Tunnel FETs 36Microscopic Modelling of Nanoelectronic Tunneling Devices 36Trap-Assisted Tunneling in InAs-Si Nanowire Heterojunctions 37An Adaptive Multi-Wavelet Solver for High-Dimension Transport Equations in Semiconductor Devices 37Combining Spherical Harmonics Expansion and Haar-Wavelets to Solve the Boltzmann Transport Equation 38Full-Band Monte Carlo Simulation of Single Photon Avalanche Diodes 38Investigation of thermal transport degradation in rough Si nanowires 39Atomistic nanoelectronic device engineering with sustained performances up to 1.44 PFlop/s 39Performance comparison of GaSb, strained-Si, and InGaAs double-gate ultra-thin-body n-FETs 40Ultimate device scaling: performance comparisons of carbon-based, InGaAs, and Si FETs for 5 nm gate length 40Modeling leakage currents of advanced CMOS devices induced by extended defects in silicon 41

Research Projects: Physical Characterization 43Two-Dimensional Dosimetry Techniques in Polymers 44EBXLINK3D: A Monte Carlo Simulator for 3D Dose Distributions in Electron Beam Processing of Electric Cables 44In Situ Screening Techniques for Automotive Devices 45Synthesis of Scanning Electron Microscopy Images by High Performance Computing 45Development of an Efficient Methodology for Electro-thermal Simulation of High-frequency Gallium Nitride 46Monte Carlo Simulation of Scanning Electron Microscopy Images with Complex Meshed Geometries 46Reliable Die Attach Technologies for High Power Switching Devices 47

Research Projects: Bio-Electromagnetics and Electromagnetic Compatibility 49Enhanced Simulation of Waveguide Structures combining FDTD, FEM and MM 50Robust FDTD Simulations in Non-Linear Media 50Optimization of a Multi-GPU Accelerated FDTD Solver for HPC Hardware Architectures 51Simulating EM-Neuron Interaction 51

Contents

3

Comprehensive Broadband Database of EM and Thermal Tissue Parameters 52HPC Enabled Large Scale Simulations of Focused Ultrasound in Complex Anatomies 52Modular Framework for Large Scale Parallelized FEM Simulations 53Generation of High Quality Anatomical Tet-Meshes from Large, Noisy Segmentation Data 53Topological Morphing 54Analysis of Power Frequency Magnetic Field Exposure Using Multiple High Resolution Anatomical Models 54Body Effect on the GPS Antenna of a Wearable Tracking Device 55Bridging Long Distances in the FDTD Method 55Autoregressive Moving-Average Estimator for FDTD 56Automated Fitting of Dispersive Material Parameters 56TF/SF Excitation of 3D Gaussian Beams via Huygens Source Formulation 57Mechanisms of Radiofrequency Electromagnetic Field Absorption in Human Hands and Fingers 57Stability of Optical Modes in FDTD 58Deep Brain Ablation: Optimized Spatial Control Using Novel RF Catheter Array 58Novel Time-Domain E&H-Field Probes 59ELF Exposure from GSM and UMTS Mobile Phones 59Exposure Assessment of Wireless Power Charging Systems 60Exposure Evaluation of Therapeutic Magnetic Field Mats 60Novel Mini-Reverberation Chamber Exposure System for Mice at 2.45 GHz 61Exposure System to Assess the Potential Toxicity and Carcinigenicity of Mobile Phone Radiation 61Brain Exposure Evaluation Using Standard SAR Test Systems 62Worst-Case SAR Assessment from Multi-Transmit MRI Coils 62Necessity for Improved SAR Averaging Volume by Regulatory Committees 63Thermal Damage Tissue Models Analyzed for Different Whole-Body SAR and Scan Durations for MR Body Coils 63

Education Program: Student Semester and Master Projects 64Acoustic Radar Demonstrator for Compressed Sensing Algorithms 67FFT Optimization for Compressed Sensing 67Disparity Estimation with Cost Filter Aggregation 68Line Detection using the Hough-Transform 68HD Video Processing Platform for Saliency Estimation 69FPGA-based Image Feature Detection 69Truecrypt on a Chip - Transparent Harddisk Encryption 70Iterative Detection and Decoding with MMSE-PIC and LDPC 70High-Performance SOVA Decoder Architecture Optimized for 3GPP-HSPA 71Reduced-State Sequence Estimation for Evolved EDGE 71Efficient Channel Shortening for Higher-Order Modulation 72Channel Equalization for TD-SCDMA 72Joint Multiuser Equalization and Detection for 3GPP TD-SCDMA 73Co-Channel Interference Cancellationwith RX Diversity 73Adjacent Channel Interference Detection and Filtering 74Cell Search & Synchronization Concepts for 3GPP TD-HSPA 74Embedded Control System for Wireless ECG Monitoring Device 75Physical Layer Interface Development for GSM Protocol Stack 75Successive Approximation Register Analog-to-Digital Converter 76OTA Design for a 2 MSample/s Algorithmic ADC in 130 nm CMOS 76Optimization of a Comparator in a Level-Crossing ADC 77High Speed Serial Interface Circuits for DigRF 4G 77Virtual Analog Synthesizer by Digital Signal Processing 78Tube Amplifier Emulation on Digital Signal Processor 78High-Efficiency Low-Power DC-DC Converter for Optical-Additives-Supported Light Power 79Performance Improvement of Automatic Target Recognition Algorithm in Laser Trackers 79Fabrication of Through-Silicon Vias with RF Capability by Magnetic Assembly of Nickel Wires 80Wireless ECG Monitoring System 80

PhD Theses – Abstracts 81Lectures 83Microelectronics Design Center (DZ) 86Joint Research Cooperation with the IT’IS Foundation 89Papers 90Conference Presentations 93

4

5

The year 2011 led to many changes for the Integrated Systems Laboratory (IIS). Two professors left and two new assistant professors started. Unexpectedly, the founder of the lab, Prof. Wolfgang Fichtner, decided to go to early pension. The head of IIS, Prof. Qiuting Huang, and the senior staff of IIS had to deal with this situation and to lead the laboratory with the aid of the Department of In-formation Technology and Electrical Engineering (D-ITET) through this period. A second severe loss for the lab and for ETHZ is the leave of Prof. Andreas Burg, who built up a very successful research group and started many proj-ects in the last years. He had to follow his call to EPFL as assistant professor with tenure track. He took most of the projects with him, and his PhD students partly followed him, partly stayed at the digital and the analog and mixed signal groups of IIS.On the positive side, Prof. Vanessa Wood and Prof. Ma-thieu Luisier started their new research activities at our laboratory. At the end of 2011, the two groups had already 3 and 1 projects with 3 and 3 PhD students and one tech-nician. These new groups could already attract students for two semester projects and three Master projects.Besides the Integrated Systems Laboratory, this report also presents the academic and research activities of the IT’IS Foundation at ETHZ (page 89) and the Microelec-tronics Design Center (DZ) of the D-ITET (page 86) for the year 2011.

PhD StudentsIn 2011, 4 PhD students finished their doctoral studies successfully. IIS offers an excellent and highly stimulating research environment that permits PhD students to work on very attractive topics and, nevertheless, to finish their thesis in a comparatively short time. However, it is still an ambitious challenge to find highly qualified PhD students from all over the world. We try our best to overcome this situation by an appropriate salary policy and by focusing the student activities on scientific work in order to reduce the administrative and educational overhead.

IC and System Design and Test GroupIn the IC and System Design and Test Group, the research on sub-Nyquist rate sampled signal processing, called Compressed Sensing (CS), led to a collaboration with ar-masuisse aiming to applications of CS for passive radar detection. CS has also successfully been demonstrated in other fields, e.g. to restore corrupted audio signals. The collaboration with Disney Research Zurich resulted in a computational stereo camera system that enables the investigation of algorithms running in real time for future 3D high-definition video applications. Several hardware implementations on FPGAs and ASICs for critical image processing steps could be demonstrated. The Swiss Na-no-Tera project QCrypt with the Group of Applied Physics (GAP) of the University of Geneva, the Reconfigurable & Embedded Digital Systems (REDS) Institute of the Uni-versity of Applied Sciences of Western Switzerland (HES-SO) at Yverdon, and the Swiss company idQuantique led to the demonstration of 100Gb/s encryption on the com-plex prototype PCB. The hash function BLAKE, that has been co-invented by Luca Henzen was selected as one of the five finalists in the NIST SHA-3 competition. In order

to demonstrate the hardware quality of all five algorithms, an ASIC with two implementations of each candidate, de-signed by IIS and researchers of the George Mason Uni-versity, has been realized.

Analog and Mixed Signal IC Design GroupFor the Analog and Mixed Signal Integrated Circuit De-sign (AMIC) Group of Prof. Huang, the year 2011 has shown a continuation of work around the group’s focus in the field of RF and base-band analog, mixed signal and digital circuit design for telecommunications application, and a return to activities related to biomedical circuits. Main research outcomes have been the successful im-plementation of critical building blocks for an LTE trans-ceiver and of a versatile EEG/ECG/EMG front-end circuit for bio-medical data acquisition. The Group has pub-lished two digital circuits, one on turbo-decoding for LTE and one on soft-input soft-output MIMO detection in the IEEE Journal of Solid-State Circuits. The projects from the Swiss Nano-Tera initiative with focus in bio-medical monitoring and advanced circuits for telecommunication systems have also led to a first demonstrator system with biomedical data acquisition and subsequent transmission of data over a wireless link to a displaying device (such as a laptop or tablet PC). The possibility to do practical work in the context of demonstration activities resulted in a positive impact on student projects within the Group.

Nano Electronics and Nano Photonics GroupThe new Laboratory for Nanoelectronics (LNE) of Prof. Vanessa Wood focuses on the study of charge transport in nanoscale systems and the application of these findings to the design of devices such as solar cells, batteries, and light emitting devices. A more detailed description is given in the next chapter “New Research Activities at IIS”.

Nano-TCAD GroupThe Nano-TCAD Group is composed of three different entities: (i) the Nano-Device Physics Group, (ii) the Com-putational Nanotechnology Group, and (iii) the Computa-tional Optoelectronics Group.The Computational Nanotechnology Group (CNG) was formed in August 2011 when Prof. Mathieu Luisier joined the ETHZ as an SNF-professor for Computational Nano-technology after 3.5 years as a post-doc at Purdue Uni-versity, USA. The research activity at the CNG focuses on the development of novel quantum transport models and their implementation into a physics-based computer design tool called OMEN. The objective is to provide ex-perimentalists with a fast, accurate, and reliable simulator in order to accelerate the innovation of novel nanoscale devices. More information on this new group can be found in the next chapter “New Research Activities at IIS”.Research in the Nano-Device Physics Group focused on the development of a new direct solver of the Boltzmann equation which uses wavelets as basis functions. The combination of the discontinuous Galerkin method with a multi-wavelet basis (MWDG) enables modern compres-sion and adaptation techniques. NIN device simulations in a three-dimensional phase space have demonstrated that the number of coefficients can be compressed to about

Introduction

6

1% compared to other modern solvers. In order to further reduce the number of necessary coefficients, the MWDG has been generalized to high polynomial orders. To take advantage of wavelet adaptation in semiconductor trans-port simulations, it turned out that the distribution function should be computed in separated sub-spaces containing either the energy and density information or the current information, respectively.In the EU-ICT project ATEMOX (Advanced Technology Modeling for Extra-Functionality Devices) models of the leakage current in ultra-shallow junctions caused by ex-tended defects (EDs) are developed for future integration into commercial TCAD tools. The connection between the influence of the EDs on the electronic properties like band structure and the effect on carrier life times is explored. The Nano-Tera project ENABLER (Enabling Energy Ef-ficient Tunnel FET-CMOS Co-design by Compact Model-ing and Simulation) provides the basis for a close coop-eration between the Nano-Device Physics Group and the “Beyond Conventional Devices” group at IBM Research Zurich. TCAD studies of the Si-InAs tunnel FET technol-ogy led to new insight and a number of joint publications. Prof. Andreas Schenk is also WP leader in the FET Pi-lot Flagship project “Guardian Angels for a Smarter Life” which aims at systems powered with energy taken from their immediate environment by combining ultra low-power electronics with new sources of energy production (http://www.ga-project.eu).In the Computational Optoelectronics Group single pho-ton avalanche diodes were studied by means of the full-band Monte Carlo technique. These detectors enable a variety of interesting applications in medicine, biology, and physics. Compared to controversial results in the lit-erature it was found that the breakdown probability exhib-its a steeper rise versus reverse bias for smaller multipli-cator sizes and that the time to avalanche breakdown and its jitter decrease with smaller multiplicator widths.

Bio-Electromagnetics GroupIT’IS, the “Foundation for Research on Information Tech-nologies in Society” (headed by ETH adjunct Prof. Niels Kuster), a non-profit research institution supported by ETH Zurich, established its scientific and technical work in close collaboration with our laboratory.The research activities of IT’IS are in the domain of the interaction of electromagnetic radiation with biological organisms, in advanced measurement equipment for electromagnetic radiation, and health risk assessment. Research projects and PhD students at IIS are funded by the global wireless communications industry, several governmental agencies, and the Commission of the Eu-ropean Union. The collaboration with IT’IS is very fruitful and a benefit for both institutions (see page 49).

EducationNext to research, teaching occupies a central role in our activities. IIS contributes with lectures and exercises, PPS (Projects, Practicals, Seminars), group projects, se-mester projects and master projects to the education of students at the department Information Technology and Electrical Engineering, as well as at other departments. For a list of lectures see page 83ff. The chapter on stu-dent projects starting at page 67ff gives an overview on the large number of master theses and semester proj-ects. The description of several outstanding semester

and master projects that contribute to our research are to be found in the chapters on Research Projects. See also page 64ff (edu intro) for more information.

Equipment and ComputersElectronic measurement equipment and computers are most relevant tools in teaching and research at IIS. A list of the equipment for electronic test and physical char-acterization can be found on www.iis.ee.ethz.ch/Equip-ment. A short introduction to our computer infrastructure is given at www.iis.ee.ethz.ch/Computers.

Partners and Funding AgenciesThe activities of our laboratory were only possible through the support from the governing board of our uni-versity, and several national and international institutions and industrial parties. Special thanks go to our school, to the computing services of ETH Zurich, as well as to the Department of Information Technology and Electrical Engineering and its services and administration.Finally, we would like to express our gratitude to the Swiss Commission for Technology and Innovation (KTI/CTI), the Swiss National Science Foundation (SNF), the Swiss Nano-Tera initiative, the Swiss State Secretariate for Education and Research (SER), the Commission of the European Union, and the Hasler Stiftung for their fi-nancial support. Just as much, we would like to thank all our partners supporting us in many projects or with in-formation and presentations in our teaching efforts. They are listed in the chapter Partners and Funding Agencies starting on page 15.

7

This chapter lets the two new professors at IIS, Vanessa Wood and Mathieu Luisier, introduce their new fields of research started in 2011.

Nano Electronics and Nano Photonics GroupResearch at the Laboratory for Nanoelectronics (LNE) fo-cuses on the study of charge transport in nanoscale sys-tems and the application of these findings to the design of devices such as solar cells, batteries, and light emitting devices. Over the past two decades, incredible progress has been made on the synthesis and preparation of na-noscale materials. Because of their small size, nanoscale materials often exhibit novel optical and electronic proper-ties that could improve the performance of optoelectronic and energy storage systems; however, the electronic transport in these nanomaterials remains poorly under-stood, leaving significant room for improvement in the way these nanoscale materials are integrated into devices.

Education“Solid State Electronics” is an introductory condensed matter physics course for 5th semester students covering crystal structure, electron models, classification of metals, semiconductors, and insulators, band structure engineer-ing, thermal and electronic transport in solids, magnetore-sistance, and optical properties of solids.“Organic and Nanostructure Electronics” is a MSc level course providing students with the knowledge and practi-cal experience to begin research in organic or nanostruc-tured materials and understand the key challenges in this rapidly emerging field. Organic molecules and colloidal quantum dots are presented as archetypical nanomateri-als. Beginning with an overview of solid state physics, the course outlines absorption, emission, and charge trans-port in amorphous thin films before exploring how the opti-cal and electronic properties of these nanomaterials can be leveraged to create lasers, chemosensors, light emit-ting devices, solar cells, and transistors. In two laboratory sessions students gained hands-on experience by syn-thesizing colloidal quantum dots, performing experiments to investigate solvatochromic shifts and Förster energy transfer, and fabricating and characterizing organic LEDs.

ResearchOur laboratory spaces were completed in summer 2011, and the months since then have largely been focused on the set-up and characterization of the laboratory infra-structure. Activities related to optoelectronic materials and devices take place in the ETZ building on the Zentrum Campus located in downtown Zürich. Our energy stor-age work is done at the new Binnig and Rohrer Nano-technology Center located just outside of the city center in Rüschlikon. Projects requiring cleanroom facilities are completed in the cleanroom at the Binnig and Rohrer Nanotechnology Center. Four key capabilities have been set-up.1. Nanoparticle synthesis. To enable synthesis of a variety of materials, we have a Schlenk line setup up and micro-wave reactor. We have successfully synthesized nanoma-terials such as CdSe, PbS, ZnO, LiFePO4.

New Research Activities at IIS

8

2. Thin film device fabrication. We designed an inte-grated growth system consisting of interconnected N2-glove boxes and a transfer line to accommodate up to four high vacuum deposition systems. Currently, samples can be transferred robotically from the gloveboxes to ei-ther a 4 magnetron, DC and RF sputterer and a 8 boat, 2 source thermal evaporator. This system enables rapid and sequential solution phase deposition of nanoparticle thin films through dipcoating or spin casting and physical vapor deposition of metals, ceramics, and organics thin films. which can be transported between chambers and gloveboxes without exposing the layers to atmosphere. Using this setup, we have now successfully fabricated LEDs, solar cells, and transistors.

3. Optoelectronic characterization. Our characterization setups make use of custom sample holders that are suit-able for high voltage and low current measurements be-tween 4 K and 500 C, the temperature range accessible in our custom cryostat that also contains a Pelletier element. The cryostat has an optical window and is designed to mount on an inverted microscope, enabling simultaneous (CW or pulsed) optical excitation and (AC or DC) elec-trical biasing. The optical signal from the device can be collected and fed to a home-built confocal microscope for single photon spectroscopy, a visible-NIR spectrometer, or a Streak camera for time-resolved spectral measure-ments. We can characterize absolute quantum yields of materials and luminescent efficiencies of devices using an integrating sphere. A solar simulator and monochrom-eter makes it possible to measure power collection effi-ciencies and spectral dependent efficiency of solar cells.

4. Battery assembly and characterization. Our electro-chemical energy storage activities take place at the Bin-ning and Rohrer Nanotechnology Center in R. There, we have built up capabilities for fabricating porous electrodes (including ball milling, shear mixing, doctor blade depo-sition, and electrode punching), assembling half- and full-cells, and performing temperature controlled galva-nostatic and potentiostatic cycling as well as impedance spectroscopy.

Computational Nanotechnology Group (CNG)The Computational Nanotechnology Group (CNG) was formed in August 2011 when Prof. Mathieu Luisier joined the ETHZ as an SNF-professor for Computational Nano-technology after 3.5 years as a post-doc at Purdue Uni-versity, USA. The research activity at the CNG focuses on the development of novel quantum transport models and their implementation into a physics-based computer design tool called OMEN. The objective is to provide ex-perimentalists with a fast, accurate, and reliable simulator in order to accelerate the innovation of novel nanoscale devices.In 2011, lots of efforts were invested into the improve-ment of OMEN’s numerical algorithms. As a result, while simulating a realistic InAs high electron mobility transis-tor (HEMT), OMEN could sustain a performance of 1.44 PFlop/s on 221,400 cores, reaching more than 55% of the peak performance of Jaguar, the former CRAY-XT5 supercomputer at Oak Ridge National Lab. As an indi-cation, typical codes reach less than 20% of the peak performance of the machine they are running on. Such an achievement made OMEN the first petascale engi-neer application. This work was selected as a finalist for the prestigious Gordon Bell Prize at the Supercomputing Conference SC11 held in Seattle, USA where OMEN fi-nally won an honorable mention.To extend its physical models, ballistic phonon transport capabilities were added to OMEN, allowing for thermal transport simulations through bulk, quantum well, and nanowire structures. To describe the phonon properties, a modified valence-force-field method was used going be-yond the simple Keating model and including four types of bond interactions. The transport problem was solved in the framework of the Wave Function and Non-equilibrium Green’s Function formalisms. To illustrate the potential of the new model, the effect of surface roughness on the thermal conductivity of Si nanowires with different crystal orientations and diameters was studied.As a direct application of OMEN, the possibility of replac-ing Si by III-V materials for high-performance transistors was investigated. Since it is well-known that conventional

9

III-V semiconductors such as InGaAs suffer from a low density-of-states effective mass that partly compensates the benefit of a high electron velocity, a different material system was investigated, GaSb. The idea is to use chan-nels originating from the L valley and possessing a high velocity to boost the total current. Full-band numerical simulations showed that this device configuration works well and gives higher current than InGaAs and strained-Si as long as only ballistic transport is considered. However, when electron-phonon scattering is turned-on, as in real-istic situations, the performance of the GaSb field-effect transistors starts to deteriorate. This phenomenon can be explained by the presence of multiple energy sub-bands that favor electron-phonon scattering.

10

DZ

Mic

roel

ectro

nics

Des

ign

Cen

ter (

Dep

t. IT

ET)

Hub

ert K

aesl

inS

taff:

4

IT'IS

Foun

datio

n fo

r Res

earc

h on

Info

rmat

ion

Tech

nolo

gy in

Soc

iety

Nie

ls K

uste

r(a

ssoc

iate

d to

ETH

)

Inte

grat

ed S

yste

ms

Labo

rato

ry I

IS

Qiu

ting

Hua

ng

V

anes

sa W

ood

Mat

hieu

Lui

sier

Sta

ff: 5

5

ETH

Züric

hDe

partm

ent I

nfor

mat

ion

Tech

nolo

gy a

nd E

lect

rical

Eng

inee

ring

D-IT

ET

Ana

log

and

Mix

ed-

Sig

nal T

est L

ab

Thom

as K

leie

rTe

ch. P

erso

nnel

: 1

Ana

log

and

Mix

ed-

Sign

al IC

Des

ign

Qiu

ting

Hua

ngTh

omas

Bur

ger

(Coo

rd)

Res

earc

h A

ssoc

iate

s: 1

Pos

t Doc

s: 2

PhD

Stu

dent

s: 1

2

Res

earc

h P

roje

cts:

5

Org

aniz

atio

n

Adm

inis

tratio

n

Adm

in. P

erso

nnel

: 3

IC a

nd S

yste

mD

esig

n an

d Te

st

Nor

bert

Fel

ber

Res

earc

h A

ssoc

iate

s: 1

Pos

t Doc

s: 0

PhD

Stu

dent

s: 4

Res

earc

h P

roje

cts:

4

Nan

o TC

AD

Mat

hieu

Lui

sier

And

reas

Sch

enk

Res

earc

h A

ssoc

iate

s: 1

Pos

t Doc

s: 1

PhD

Stu

dent

s: 7

Res

earc

h P

roje

cts:

5

AS

IC T

est a

ndE

lect

roni

c La

b

Nor

bert

Fel

ber

Tech

. Per

sonn

el: 1

Bio

Ele

ctro

-m

agne

tics/

EM

C

Nie

ls K

uste

r

Res

earc

h A

ssoc

iate

s: 0

Pos

t Doc

s: 1

PhD

Stu

dent

s: 1

Res

earc

h P

roje

cts:

1

Phy

sica

lC

hara

cter

izat

ion

Lab

Mau

ro C

iapp

a

Nan

o La

b

Mar

io M

ückl

ich

Tech

. Per

sonn

el: 1

Com

pute

r Sys

tem

s

Chr

isto

ph W

icki

Tech

. Per

sonn

el: 3

Nan

o El

ectr

onic

sN

ano

Phot

onic

s

Vane

ssa

Woo

d

Res

earc

h A

ssoc

iate

s: 0

Pos

t Doc

s: 0

PhD

Stu

dent

s: 4

Res

earc

h P

roje

cts:

3

Phys

ical

C

hara

cter

izat

ion

Mau

ro C

iapp

a

Res

earc

h A

ssoc

iate

s: 1

Pos

t Doc

s: 0

PhD

Stu

dent

s: 2

Res

earc

h P

roje

cts:

2

Org

aniz

atio

n

11

Representative Figures

Staff

Number of FTE (full-time equivalent) job positions at the Integrated Systems Laboratory from 2002 to 2011.

PhD Theses

Number of completed PhD theses per year at the Integrated Systems Laboratory from 2002 to 2011. Abstracts of PhD theses: see page 81.

12

Papers and Presentations

Number of papers and presentations by the Integrated Systems Laboratory from 2002 to 2011. References: see pages 90ff.

IIS Reserach Projects

Number of research projects with external funding at the Integrated Systems Laboratory from 2002 to 2011. Overview of research projects: see pages 21ff. Partners and funding agencies: see pages 15ff.

13

Professors

Fichtner Wolfgang, Dr., Professor for Electronics, 1 Sep 1985 – 30 Apr 2011Huang Qiuting, Dr., Professor for Electronics, Head of Institute since 1 Jan 1993Luisier Mathieu, Prof., Dr., dipl. El. Ing. ETH since 1 Aug 2011Schenk Andreas, Prof., Dr., Dipl.-Phys., Senior Scientist since 1 Aug 1991Wood Vanessa, Prof., Dr., MSc EE amd CS since 11 Aug 2010

Microelectronics Design Center

Kaeslin Hubert, Prof., Dr., Dipl. El.-Ing. ETH, Head since 1 Jan 1986Gürkaynak Frank, Dr., Dipl. El.-Ing since 1 Jun 2008Muheim Beat, Dipl. El.-Ing. ZHAW since 1 Aug 2008Schöni Daniel, Ing. für elektronisches Design since 1 Oct 2009

Scientific Staff

Aemmer Dölf, Dr., Dipl. Phys. ETH, Senior Scientist 1 Sep 1985 – 28 Feb 2011Areshkin Denis, Dr., MSc EE since 15 Oct 2011Badawi Karim, MSc since 1 Nov 2010Belfanti Sandro, MSc EE since 1 Jul 2011Benkeser Christian, Dr., Dipl. El.-Ing. ETH since 15 Sep 2004Bettini Luca, MSc since 1 Jun 2010Blattmann René, Dipl. El.-Ing. ETH since 1 Apr 2009Bozyigit Deniz, MSc EE ETH since 1 Nov 2010Burger Thomas, Dr., Dipl. El.-Ing. ETH, Senior Scientist since 1 Oct 1994Calderara Mauro, Dipl. Phys. ETH since 15 Oct 2011Carnelli Dario Albino, MSc EE 15 Nov 2008 – 31 Oct 2011Chen Yangjian, Dr., El.-Ing. since 1 Oct 2007Ciappa Mauro, Dr., Dipl. Phys. since 1 Jan 1998Dolgos Denis, Dipl. Phys 1 Jan 2008 – 30 Sep 2011Ebner Martin, MSc ETH MNS since 1 Jan 2011Egerer Thomas, Dipl.-Ing. 1 Mar 2011 – 31 Oct 2011Esposito Aniello, Dr., Dipl. Phys. ETH since 15 Aug 2005Fateh Schekeb, Dipl. El.-Ing. ETH since 6 Jun 2009Felber Norbert, Dr., Dipl. Phys. ETH, Senior Scientist since 1 Jul 1987Greisen Pierre, Dipl. El.-Ing. ETH since 1 Jan 2009Keller Christoph, MSc EE ETH since 11 Jan 2010Kernert David, Dipl. Phys. since 1 Nov 2011Kröll Harald, Dipl.-Ing. since 15 Jun 2010Kuehn Sven, Dr., Dipl.-Ing. Inf. since 1 Mar 2011Kupec Jan, Dipl.-El.-Ing. 1 Jan 2008 – 31 Mar 2011Mächler Patrick, Dipl. El.-Ing. ETH since 1 Sep 2008Malandruccolo Vezio, Dipl. El.-Ing. 1 Mar 2008 – 28 Feb 2011Mangiacapra Luigi, Dipl. Phys. 1 Apr 2007 – 31 Jan 2011Martelli Chiara, Dr., Dipl. El.-Ing. since 17 Jan 2001 – 31 Mar 2011Meier Hektor, Dipl. El.-Ing. ETH 20 Apr 2009 – 28 Feb 2011Mühlberghuber Michael, Dipl.-Ing. since 1 Oct 2011Nadakuduti Jagadish, MSc EE since 8 Jun 2009Ozsema Hasene, ing.él. dipl. EPFL since 22 Sep 2010Peikert Vincent, Dipl. Phys. ETH since 1 Feb 2009Rhyner Reto, MSc EE ETH since 11 Oct 2010

Staff

14

Roth Christoph, MSc EE ETH since 1 Sep 2009Scheinemann Artur, Dipl. Phys. since 1 Oct 2010Schönle Philipp, MSc EE since 15 Oct 2011Sporrer Benjamin, MSc EE since 1 Jul 2011Stefanski Tomasz, Dr., El.-Ing. 1 Sep 2009 – 28 Feb 2011Szabó Áron, MSc Eng. Phys. since 1 Nov 2011Treichler Jürg, Dr., Dipl. El.-Ing. ETH since 1 May 2003Ulrich Roger, Dipl. El.-Ing. ETH 1 Aug 2009 – 31 Oct 2011Yarema Olesya, MSc Chemie since 1 Sep 2011Zwicky Stefan, MSc EE ETH since 14 Jan 2010

Computer Staff

Feigin, Adam, Dipl. El.-Ing. since 1 May 2006Kunz Fredi, Reallehrer since 15 Aug 2009Wicki Christoph, Dipl. El.-Ing. ETH since 1 Oct 1985

Technical Staff

Gisler Hansjörg, Industriespengler since 1 Aug 1989 Kleier Thomas, Dipl.-Ing. (FH) Nachrichtentechnik since 1 Jun 2005Mücklich Mario, Feinmechaniker since 1 Mar 2011

Administrative Staff

Bakanova Alexandra, dipl. Betriebsökonomin BVS, (70%) since 1 Jan 2010Fischer Bruno, Dipl. El.-Ing. HTL since 14 Apr 1992Haller Christine, Betriebsökonomin HWV (95%) since 8 Mar 1993 Roffler Verena (50%) 1 Sep 1999 – 31 Mar 2011

15

ABB Semiconductors ABB Semiconductors AG CH-5600 Lenzburg, SwitzerlandACP ACP Advanced Circuit Pursuit AG CH-8702 Zollikon ZH, Switzerlandarmasuisse armasuisse CH-3602 Thun, SwitzerlandATEMOX Consortium Centre National de la Recherche Scientifique, Paris, France Eidgenössische Technische Hochschule Zürich, CH-Zürich, Switzerland Exico France, Genevilliers, France Ion Beam Services, F-Rousset, France Probion Analysys SARL, F-Bagneux, France Semilab Felvezeto Fizkai Laboratorium Reszvenytarsasag, Budapest, Hungary ST Microelectronics Crolles 2 SAS, Crolles, France ST Microelectronics S.A., Montrouge, France Synopsys GmbH, Aschheim, Germany Synopsys Switzerland LLC, Zürich, Switzerland University of Newcastle Upon Tyne, Newcastle Upon Tyne, United Kingdomaustriamicrosystems austriamicrosystems AG A-8141 Unterpremstätten, AustriaBBT Bundesamt für Berufsbildung und Technologie (Federal Office for Professional Education and Technology, a Swiss Government Agency) CH-3003 Bern, SwitzerlandCGL-ETHZ Computer Graphics Laboratory ETH Zürich, CH-8092 Zürich, SwitzerlandCVG-ETHZ Computer Vision and Geometry Group ETH Zürich, CH-8092 Zürich, SwitzerlandCSEM Centre Swiss d’Electronique et Microicrotechnique CH-2002 Neuchâtel, SwitzerlandDisney The Walt Disney Studios (Schweiz) GmbH Disney Research Zurich CH-8008 Zürich, SwitzerlandDITET-DZ DITET Microelectronics Design Center ETH Zürich, CH-8092 Zürich, SwitzerlandEMPA EMPA Eidgenössische Materialprüfungs- & Forschungsanstalt CH-9015 St. Gallen, SwitzerlandEPFL Ecole Polytechnique Fédérale de Lausanne EPFL, CH-1015 Lausanne, SwitzerlandETHZ Eidgenössische Technische Hochschule Zürich (Swiss Federal Institute of Technology Zürich) ETH Zürich, CH-8092 Zürich, SwitzerlandHans Eggenberger Stiftung Hans Eggenberger Stiftung CH-8802 Kilchberg, SwitzerlandHasler Hasler Stiftung CH-3011 Bern, SwitzerlandHuber+Suhner Huber+Suhner AG CH-8330 Pfäffikon, SwitzerlandIBM Research IBM Research GmbH CH-8803 Rüschlikon, SwitzerlandidQ id Quantique S.A. CH-1227 Carouge, SwitzerlandIIS-ETHZ Integrated Systems Laboratory ETH Zürich, CH-8092 Zürich, SwitzerlandIKT-ETHZ Institut für Kommunikationstechnik (Laboratory for Communication Technology) ETH Zürich, CH-8092 Zürich, SwitzerlandIMEC Interuniversity Microelectronics Centre B-3001 Leuven, BelgiumInfineon Infineon Technologies Austria AG A-9500 Villach, Austria

Partners and Funding Agencies

16

Innodul Innodul AG CH-8045 Zürich, SwitzerlandIRB Bellinzona Istituto di Ricerca in Biomedicina CH-6500 Bellinzona, SwitzerlandIT’IS • IT’IS Foundation for Research on Information Technologies in Society ETH Zürich, CH-8092 Zürich, Switzerland • CH-8004 Zürich, SwitzerlandIT’IS Partners AGC Automotive, Ypsilanti, USA Antia Therapeutics, Switzerland AIT, Austrian Institute of Technology, Seibersdorf, Austria Aristotle University of Thessaloniki, Thessaloniki, Greece Asher Sheppard Consulting, Santa Rosa, USA BAG, Bern, Switzerland BASEXPO Consortium, Europe BfS, Federal Office for Radiation Protection, Salzgitter, Germany BIWI-ETHZ, Zurich, Switzerland (Computer Vision Laboratory, ETH Zurich) BORL-USZ, Zurich, Switzerland Boston Scientific Cardiac, St. Paul, USA Boston Scientific Neuromodulation, Valencia, USA Campus of Ravenna, University of Bologna, Bologna, Italy Cancer Research UK, Beatson Laboratories, Glasgow, United Kingdom Centro de Biologia Molecular “Severo Ochoa” CBMSO, Madrid, Spain Chalmers University of Technology, Göteborg, Sweden Children’s Hospital, Arkansas, USA Consiglio Nazionale delle Ricerche, Institute of Biomedical Engineering, Milan, Italy Charité, Berlin, Germany CTIA, Washington DC, USA DCR-VPH Uni Bern, Bern, Switzerland Dialogik GmbH, Stuttgart, Germany EMFields Ltd., Trellech, United Kingdom EPFL, Lausanne, Switzerland Erasmus MC Rotterdam, Rotterdam, The Netherlands Exponent Inc., Menlo Park, CA, USA FAU Erlangen, Erlangen, Germany FDA, Washington DC, USA Field Imaging, Meudon, France Forschungsgemeinschaft Funk e.V., Bonn, Germany Fraunhofer ITEM, Hannover, Germany FRONIUS International GmbH, Thalheim bei Wels, Austria GE Healthcare, General Electric Company, Milwaukee, USA GSM-Association, Genève, Switzerland Health Protection Agency, Chilton, London, United Kingdom Hirslanden Clinic, Zurich, Switzerland Hospital de la La Chaux-de-Fonds, Switzerland IBT-ETHZ, Zurich, Switzerland IFA-ETHZ, Zurich, Switzerland IFH-ETHZ, Zurich, Switzerland IITRI, Illinois Institute of Technology Research Institute, Chicago, USA Image Guided Therapy, France Imricor Medical Systems, USA IMTEK, Freiburg, Germany Incos Boté Cosmetic GmbH, Mainz, Germany Imperial College, London, United Kingdom Institute for Pharmacology & Toxicology, Zurich, Switzerland Instituto de Biología Molecular y Celular del Cancer (IBMCC, CSIC/USAL), Salamanca, Spain INTEC, Gent, Belgium Interdisciplinary Institute for Broadband Technology, Gent-Ledeberg, Belgium International Agency for Research on Cancer, Lyon, France IPM, Stockholm, Sweden IPT-UNIZH, Zurich, Switzerland ISTB, University of Bern, Bern, Switzerland Karolinska Institute, Huddinge, Sweden Kantonsspital Aargau, Switzerland

17

University Children’s Hospital, Zurich, Switzerland Laboratoire IMS, Uni Bordeaux, Bordeaux, France Laboratoire Clarins, Paris, France Massachusetts Institute of Technology, Cambridge, USA McGill University, Montreal, Canada MCL, London, United Kingdom Medical University of Vienna, Austria MMF, Brussels, Belgium Motorola, Ft. Lauderdale, USA National Technical University of Athens, Athens, Greece NCCR Co-Me, Zurich, Switzerland NIEHS, Research Triangle Park, USA NIST, Gaithersburg, USA NOKIA NRC, Helsinki, Finland Philips Medical Systems, Best, The Netherlands Phonak Communications AG, Murten, Switzerland Qualcomm, San Diego, Switzerland SBB, Swiss Federal Railways, Bern, Switzerland SECO, State Secretariat for Economic Affairs, Switzerland Siemens Medical Solutions AG, Erlangen, Germany SPEAG, Schmid & Partner Engineering AG, Zurich, Switzerland Swiss Tropical and Public Health Institute, Basel, Switzerland Toronto University, Toronto, Canada Technical University of Athens, Athens, Greece Torptronics, Göteborg, Sweden THESS, Thesaloniki, Greece ULP, Université Louis Pasteur, Strasbourg, France University Children’s Hospital, Zurich, Switzerland University of Aalborg, Department of Electronic Systems, Aalborg, Denmark University of Basel, Basel, Switzerland University of Bern, Bern, Switzerland University of Geneva, Geneva, Switzerland University of Gent, Gent, Belgium University of Miami, Miami, USA University of Uppsala, Uppsala, Sweden University of Veterinary Medicine, Hannover, Germany University of Vienna, Vienna, Germany University of Zurich, Zurich, Switzerland University Hospital, Zurich, Switzerland Vodafone UK Ltd., Newbury, United Kingdom Volvo Car Corporation, Göteborg, Sweden Vratis Ltd, Wroclaw, Poland Weizmann Institute of Science, Department of Biological Regulation, Tel Aviv, Israel York EMC Services / University of York; York, United Kingdom Zejiang University, Hangzhou, China Zurich Med Tech, Zurich, Switzerland ZonMW, The Hague, The NetherlandsKTI Kommission für Technologie und Innovation (Commission for Technology and Innovation, a Swiss Government Agency) CH-3003 Bern, SwitzerlandKTH KTH Royal Institute of Technology SE-100 44 Stockholm, SwedenLeica Leica Geosystems AG CH-8152 Glattbrugg, SwitzerlandLTR-ETHZ Labor für Transportprozesse und Reaktionen ETH Zürich, CH-8092 Zürich, SwitzerlandMIT Massachusetts Institute of Technology Research Laboratory of Electronics Cambridge, MA 02139, USAMRC-ETHZ Material Research Center ETH Zürich, CH-8093 Zürich, Switzerland

18

NANOSIL Consortium INPG Entreprise S.A., Seyssinet Pariset, France Institut Polytechnique de Grenoble, Grenoble, France The University of Warwick, Coventry, United Kingdom Rheinisch-Westfälische Technische Hochschule Aachen, Aachen, Germany Kungliga Tekniska Hogskolan, Stockholm, Sweden Consorzio Nazionale Interuniversitario per la Nanoelettronica, Bologna, Italy Universite Catholique de Louvain, Louvain-La-Neuve, Belgium Interuniversitair Micro-Electronica Centrum Vzw, Leuven, Belgium Commissariat a l’Energie Atomique, Paris, France ST Microelectronics Crolles, Crolles, France Institut Superieur d’Electronique et du Numérique, Lille, France Université Paris-Sud, Orsay, France Gesellschaft für Angewandte Mikro- Und Optoelektronik mbH, Aachen, Germany Forschungszentrum Jülich GmbH, Jülich, Germany Qimonda Dresden GmbH & Co. OhG, Dresden, Germany Technische Universität Braunschweig, Braunschweig, Germany Universität Stuttgart, Stuttgart, Germany National Centre for Scientific Research Demokritos, Aghia Paraskevi Attikis, Greece University College Cork - National University of Ireland, Cork, Ireland Politechnika Warszawska, Warszawa, Poland Universidad Rovira i Virgili, Tarragona, Spain Chalmers Tekniska Hoegskola Aktiebolag, Göteborg, Sweden Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland Eidgenössische Technische Hochschule Zürich, Zürich, Switzerland Synopsys Switzerland LLC, Zürich, Switzerland The University of Glasgow, Glasgow, United Kingdom University of Liverpool, Liverpool, United Kingdom The University of Newcastle Upon Tyne, Newcastle upon Tyne, United KingdomNCCR-QSIT National Centre of Competence in Research, Quantum Science and Technology ETH Zürich, CH-8093 Zürich, SwitzerlandNSF-USA The National Science Foundation Arlington, Virginia 22230, USAOptical Additives Optical Additives GmbH CH-5603 Staufen, SwitzerlandREDS REDS, HEIG-VD/HES-SO CH-1401 Yverdon-les-Bains, SwitzerlandSamsung Samsung Electronics Co., LTD. Giheung-Eup, Yongin-City, Gyeonggi-Do, KoreaSNF Swiss National Science Foundation CH-3012 Bern, SwitzerlandSynopsys • Synopsys Switzerland LLC CH-8050 Zürich, Switzerland • Synopsys Inc. Mountain View, CA 94043, USA • Synopsys Inc. (former SIGMA-C GmbH) D-81737 München, GermanyTCL-EPFL The Telecommunication Circuits Laboratory CH-1015 Lausanne, SwitzerlandToshiba • Toshiba Corporation Isogo-ku, Yokohama 235-0017, Japan • Toshiba Corporation Minato-ku, Tokyo 105-8001, JapanTU Graz Technische Universität Graz Institute for Applied Information Processing and Communications (IAIK) A-8010 Graz, AustriaUni Bologna Università degli Studi di Bologna Dipartimento di Elettronica Informatica e Sistemistica I-40126 Bologna, ItalyUni Bordeaux Université de Bordeaux Laboratoire de l’Intégration du Matériau au Système F-33405 TALENCE CEDEX, FranceUni Cagliari Università degli Studi di´Cagliari Dipartimento di Ingegneria Elletrica et Elettronica I-09123 Cagliari, Italy

19

Uni Genève Université de Genève GAP Optique CH-1211 Genève 4, SwitzerlandUni Kassel Universität Kassel Computational Electronics Institute D-34121 Kassel, GermanyUni Mason George Mason University Fairfax, VA 22030, USAUni Parma University of Parma Dipartimento di Ingegneria dell’Informazione I-43100 Parma, ItalyUni Purdue Purdue University West Lafayette, Indiana 47907, USAUni Rice Rice University Houston, TX 77005, USA24M 24M Technologies Inc. Cambridge, MA 02139, USA

20

Mathieu Luisier, Timothy Boykin, Gerhard Klimeck, and Wolfgang Fichtner

received the

“ACM Gordon Bell Prize”

for

“Atomistic nanoelectronics device engineering with sus-tained performances up to 1.44 PFlop/s”

Honorable Mentioned

at the SC11 International Conference for High Performance Computing, Net-working, Storage and Analysis in Seattle, WA, USA, November, 2011.

Awards

21

Research Projects

IC and System Design and Test

Coordinator:

Norbert Felber

22

Passive radar uses illuminators of opportunity like TV or radio broadcasters and processes the reflections from moving targets. This allows for low cost and simple ra-dars since no additional transmitters are required. In this project, WiFi base stations are used as illuminators for local area surveillance. Earlier experiments have shown that the detection of moving cars and persons is possi-ble, however, with large difficulties to distinguish closely spaced objects. We therefore investigated the potential of compressed sensing techniques to improve target detec-tion.Compressed sensing (CS) allows to improve detection accuracy when the scene is sparse, i.e. only a small num-ber of objects are present. Since this is often the case in radar applications, CS can be used whenever suit-able training signals are transmitted. Indeed, we could show by simulations that WiFi frames are suitable for CS measurements. Using wireless base stations transmit-ting 802.11a/g/n OFDM frames, CS algorithms allow to resolve closely spaced objects better than approaches based on correlation. Also, an advanced scheme taking into account the signal from several base stations was developed, which increases resolution up to four times.It is also possible to reduce the number of acquired mea-surements for 802.11b Direct Sequence Spread Spec-trum frames, while keeping the resolution constant. This might be interesting for energy-starved sensor nodes in a passive radar network.

Top: Passive radar setup with one moving target.Bottom: Comparison of correlation- and compressed-sens-ing-based detection of 6 targets with different reflectivity (measurement of 40 OFDM training symbols).

Compressed Sensing for Passive Bi-static Radar

Personnel: Patrick Mächler

Funding: armasuisse

Approximate message passing (AMP) is a new and very promising algorithm to solve compressed sensing prob-lems. This involves reconstructing a signal from fewer measurements than the dimension of the signal would re-quire. The under-determined reconstruction can only be successful if the signal is known to be sparse (i.e. most coefficients are zero).In this project, AMP is applied to an audio restoration problem. Audio signals can be corrupted by short ‘clicks’, for example, when they are played from old, scratched phonograph recordings. These clicks are of typically very short duration, which means that they have a sparse sup-port in time domain. Music and speech, on the other hand, is known to be often approximately sparse in the cosine transform domain. Using these sparsity properties to dis-tinguish the two signal contributions, the clicks can be separated from the original sound. This signal separation problem can efficiently be solved by the AMP algorithm.An ASIC performing signal separation using AMP was de-signed. The most important block of the hardware is a fast discrete cosine transform (DCT) for vectors of size 512. An efficient and fast DCT was designed by transforming the problem into a fast Fourier transform (FFT). The final chip is fast enough to process multiple audio channels with standard CD quality. Clicks are successfully removed by signal separation and the audio signal sounds much clearer after processing.

Top: Audio signal corrupted by clicks and after signal sepa-ration. Bottom: Floorplan of AMP chip.

Approximate Message Passing for Au-dio Restoration

Personnel: David Bellasi, Marc Liechti (students), Patrick Mächler, Christoph Studer

Funding: ETHZ

Partners: Uni Rice

23

Computational Stereo Camera System

Although stereoscopic 3D (S3D) movie production has seen a recent revival due to successful film productions and S3D sports broadcasting, there are still numerous unresolved challenges in the S3D pipeline. A significant threat to the S3D trend is the lack of visually appealing S3D content, which, in turn, results from the fact that it is still hard and expensive to acquire good S3D content. In particular, for live broadcasting scenarios or productions with a small budget, there is no time or money for postpro-cessing S3D content and therefore, S3D acquisition must be first-time-right.In order to simplify and automate the S3D acquisition pro-cess, we design and implement a computational stereo camera that closes the loop between stereo video pro-cessing and camera operation. To automate the currently cumbersome process of setting stereo parameters, such as interaxial distance or focus, a controller sets the pa-rameters based on information extracted from the video streams in real-time. Various video processing and com-puter vision algorithms are therefore implemented in the system.The stereo processing is partitioned on a high-perfor-mance computing system featuring an FPGA, a CPU, and a GPU. The FPGA efficiently handles stream processing tasks, such as noise removal, geometric correction and basic depth estimation, while the GPU is engaged with high-level, memory intensive processing tasks. The CPU handles system control tasks such as initiating data trans-fers and calculating/sending the camera settings. The system processes two full HD streams at 30 frames per seconds.

Left: CAD drawing of the custom mirror-based stereo rig. Right: Image of the stereo camera system with touch screen, stereo rig with 2 full HD image sensors, and a PC system (not in the picture).

Personnel: Pierre Greisen, Simon Heinzle

Funding: ETHZ, Disney HPCC

Partners: Disney

References: [D1.]; [D4.]

Full-HD Video Rendering System

The transition from standard definition (SD) to high defi-nition (HD) video enhances the viewer experience, but also increases computational complexity of related video processing tasks. Our particular application is non-linear video rendering, where each frame is warped into a new frame with an arbitrary per-pixel non-linear warping func-tion. We targeted a real-time rendering system that is able to process full HD (1920 x 1080) video at 30 frames per second. The rendering system comprises an ASIC per-forming the actual rendering operation, and a PCB that contains the ASIC and associated components, such as HD video interface and memory blocks.In this first part of the project, we designed and imple-mented the rendering ASIC. The functionality is based on a previous ASIC semester thesis where the EWA splat-ting algorithm has been implemented. The main focus of this work was to extend the design to support full HD and to add interfaces to commercially available components such as QDRII SDRAM and DVI. The design has eight parallel splatting cores running at up to 180 MHz and delivering a rendering performance of 72 Msplats/s. Two clock domains decouple the high-performance rendering part from the fixed-rate DVI interface. The inputs of the ASIC are streamed via a high-speed connector from an FPGA base-board.

“VESPER” chip layout: The video rendering ASIC has been fabricated in a 130 nm CMOS process with 256 pins. It achieves full HD performance at 30 frames per second at 180 MHz.

Personnel: Richard Emler, Patrice Guillet (students) Pierre Greisen, Frank K.Gürkaynak

Funding: ETHZ, Disney HPCC

Partners: Disney

24

High-Dimensional Sparse Linear Solver on FPGA

A lot of optimization problems can be expressed as lin-ear systems under the well-known form Ax = b, where x is a vector containing the unknowns to solve for, and A and b are the constraint matrix and the constraint vec-tor, respectively. For image processing applications, x usually represents the image, and the resulting system is extremely large, in some cases exceeding 1 million. Hardware-based solutions can typically handle the large amount of computations for such systems, however they are slowed down by large memories required to store the results.The goal of this project was to implement a real-time solver for large sparse linear systems. The matrix is as-sumed to be sparse, that is, only a few entries per row are non-zero. First, we investigated and evaluated the large number of existing solver algorithms and classified them according to the quality of results produced by the solver and to its hardware capability. Second, we devised a cor-responding FPGA architecture of the best performing al-gorithm. Due to the large size, direct solvers are impracti-cal and therefore, an iterative solver has been selected. Our architecture supports 5 non-zero entries per matrix row and achieves 2000 iterations per second for vectors of size 60’000.

Top: Linear sparse system overview.Bottom: High-level system overview: an FPGA is fed with constraint matrix A and vector b, and outputs the solution vector x.

Personnel: Patrice Guillet (student); Pierre Greisen, Frank K. Gürkaynak

Funding: ETHZ, Disney HPCC

Partners: Disney

Metric Omnidirectional Optical Flow

The goal of this Master thesis was a prototype for the ex-traction of velocities from image sensor signals at high update rates. Target applications are autonomous sys-tems, such as micro air vehicles (MAV), that require ro-bust position and velocity values at high update rates in their control loop. This thesis originated in pixhawk (pix-hawk.ethz.ch), a large student and research project that is involved in the development of autonomous MAVs. Image-based optical flow measurements, scaled by the metric distance between camera and object in the scene, provide the metric velocity of the object relative to the camera movement. A stereo video stream can be used to calculate real-time velocity values of a moving system by combining optical flow and depth estimations. A crucial point in feed-back systems, such as self-stabilizing MAVs, is a high update rate of the loop variable. To be able to calculate the computationally intensive depth estimation and optical flow at the required frame rates, an FPGA is used.The FPGA based platform calculates real-time metric op-tical flow at 120 frames/s and 376 x 240 resolution. Radial distortion compensation, image rectification, disparity es-timation and optical flow calculations are performed in a low-cost FPGA without external memory resources. Due to light weight and low power consumption, the platform is perfectly suitable for mobile robot or MAV applications.

Top left: Metric flow results compared with VICON measure-ments. Top right: example of a disparity map obtained by the system. Bottom: overview picture of the system with VICON markers for validation purposes.

Personnel: Dominik Honegger (student); Pierre Greisen; CVG-ETHZ: Lorenz Meier, Petri Tanskanen

Funding: ETHZ

Partners: CVG-ETHZ

References: IROS 2012

25

High-Speed Network Interfaces and 100 Gbps Payload Encrytion

Quantum Key Distribution (QKD) ensures attack-resilient exchange of chipher keys, while classical encryption provides secure transmission of information at highest data rates. The research task of ETHZ, with support from HESSO, in the nano-tera project QCRYPT focuses on the development of a 100 Gb/s link encryptor. It will provide a variety of optical interfaces on the plain-text side and a 100 Gb/s optical link to bridge large distances between encryptor pairs.During the second year of the project, the main focus lay on the test and verification of the hardware prototype. The hardware platform can host up to ten 10 Gb/s opti-cal interfaces. A CFP module enables the transmission of 100 Gb/s encrypted data through one single fibre. As a lower-cost alternative and for short distances, a CXP ‘active cable interface’ is available. It transmits 100 Gb/s through ten parallel fibre pairs in each direction. For the encryption and network processing, a Stratix IV FPGA by Altera is mounted on the PCB.Alongside with the development of the PCB, the VHDL design for the FPGA has been developed. It includes the AES encryption, a TDM encoding, the 10 Gb/s Ethernet blocks and the 100 Gb/s Ethernet part (802.3ba). The PCB has been successfully tested and debugged. Some minor changes had to be done to ensure correct working. Further on, the VHDL design is being verified. Special focus was set on the network interfaces. The 10 Gb/s Ethernet interfaces are working correctly and, with the second board at hand, the verification of 100 Gb/s interfaces can start now.

Photograph of the fully assembled PCB with the regulators for the power supplies at the right side, the FPGA below the fan in the center, and the different network connectors at the top edge.

Personnel: Christoph Keller, Norbert Felber

Funding: Nano-Tera QCRYPT

Partners: idQ, Uni Genève, REDS

Hash functions are commonly used in cryptographic ap-plications to take an arbitrarily long input message and generate a digest of limited size. For good cryptographic hash functions, it should be difficult to find two messages that produce the same digest (collision resistance) and it should not be trivial to come up with a message that gen-erates a given digest (pre-image resistance).In 2007, the American National Institute of Standards and technology (NIST) launched a competition to replace their older standard hashing algorithms, SHA-1 and SHA-2 which are thought to have some weaknesses. This public competition attracted 51 algorithms from different reser-achers. In a first step, the field was reduced to 14 candi-dates, and in 2011, NIST announced 5 finalist algorithms (Blake, Grøstl, JH, Keccak, Skein). Following the third SHA-3 candidate conference in March 2012, the final al-gorithm is expected to be announced in summer 2012. From the beginning, members of IIS have been active-ly involved in this process. Luca Henzen, former Ph.D. student at IIS, is one of the co-authors of Blake, one of the finalist algorithms. In addition, the IIS has assumed a leading role in evaluating the ASIC performance of SHA-3 candidate algorithms. For the third round, an ASIC has been designed using a 65 nm CMOS technology. This ASIC contains two versions of all finalist algorithms, as well as reference SHA-2 implementations.

Top: The layout of the Shabziger ASIC. The 65 nm CMOS ASIC contains a total of 12 independent hash functions, the fastest capable of delivering more than 20 Gb/s throughput.

Hardware Evaluation of Third Round Secure Hash Algorithm Candidates

Personnel: Christoph Keller, Frank K. Gürkaynak, Beat Muheim

Funding: ETHZ, Nano-Tera QCRYPT

Partners: Uni Mason

References: Third SHA-3 Candidate Conference 2012

26

Comparing ECDSA Hardware Imple-mentations Based on Binary and Prime Fields

Throughout the last decade, digital signatures have be-come at least as important as their analog counterpart. Signature generation and verification based on Elliptic Curve Cryptography (ECC) is currently the state-of-the-art technique with regard to low-resource requirements. This is due to the fact that, compared to traditional public-key cryptosystems like RSA, ECC requires a much short-er key length to provide the same level of security.One of the most popular standardized digital signature algorithms based on ECC is the so-called Elliptic Curve Digital Signature Algorithm (ECDSA). Although various implementations of the ECDSA published in literature ex-ist, it is quite difficult to compare them, because designs can differ in many layers of abstraction (Underlying finite field, representation of the point coordinates, chosen el-liptic curve, etc.).Within this work, two ECDSA designs have been imple-mented, one based on a binary field and the other one based on a prime field. Both elliptic curves being used are standardized by the National Institute of Standards and Technology (NIST), namely the B163 and P192, respec-tively. The two implementations are capable of performing a signature generation according to the ECDSA, as well as the verification part.The designs have been fabricated using the 150 nm tech-nology by LFoundry GmbH and can be clocked with up to 100 MHz. Signature generation for the binary-field-based version requires 42 kcycles whereas the prime-field-based one needs 220 kcycles. The verification process for both designs takes up to 560 kcycles.Investigations in this project showed that, because bina-ry-field arithmetics are more suitable for hardware imple-mentations than prime-field arithmetics, using binary fields as the underlying finite fields for ECC is more suit-able.

Combined chip layout of both the prime- (left) and the binary-field- (right) based implementation of the ECDSA, fabricated using the 150 nm technology by LFoundry.

Personnel: Michael Muehlberghuber (student) Frank K. Gürkaynak TU Graz: Michael Hutter

Funding: ETHZ

Partners: TU Graz

27

Research Projects

Analog and Mixed-Signal IC Design

Coordinator:

Qiuting Huang

28

Modern wireless communication systems require novel analog-to-digital converter (ADC) techniques to meet the demand of high data rate and high effective resolution of up to 12 bits. ADCs represent the interface between the analog and digital domains and particularly in the re-ceiver, the analog signal performance plays a crucial role in determining the characteristics of the digital baseband signal, such as data-rate, signal-to-noise ratio, linearity, and bit error rate.Folding and interpolating ADCs employ a parallel archi-tecture consisting of open-loop folding amplifiers. This is a prerequisite for fast conversion, since the high-speed benefits of modern CMOS technologies can be optimally exploited in such circuits. A drawback of this architecture is its limited accuracy due to its non-linear behavior, which is directly related to the matching characteristics of the transistors. Averaging, which is a well-known approach to alleviate the matching requirements, and calibration tech-niques in the digital domain can be applied to compen-sate for the non-linearity errors. This project has focussed on the development of a medi-um-resolution high-speed ADC targeting a precision of 12 bits. A dedicated start-up calibration algorithm is imple-mented on-chip to reduce the non-linearity distortion. Cor-responding reference currents are provided by a bandgap circuit which operates at 2.5 V supply voltage. The ADC is designed to operate at a sampling frequency of 300 MHz from a 1.2 V supply voltage.

Layout view of the 12-bit folding and interpolating ADC im-plemented in a 130-nm general purpose standard CMOS technology.

A 12-bit High-Speed Folding and Inter-polating Analog-to-Digital Converter

Personnel: Schekeb Fateh

Funding: ETHZ

The increasing demand for smart phones, internet tablets and other communications devices has led, in the last de-cade, on the one hand to the definition of always new wire-less standards culminated with IMT- and LTE-Advanced, and, on the other, has produced an enormous effort in the research of hardware solutions capable to support these standards. Nevertheless, GSM continues to be the most popular and widespread standard worldwide.This forced coexistence has initiated the investigation of highly-flexible multi-standard solutions, both for portable terminals and base stations, capable of supporting the bandwidth requirements of 4G standards such as IMT- and LTE-Advanced while providing backward compatibil-ity to 2G and 3G. High-performance A/D and D/A con-verters are critical building blocks in such reconfigurable solutions, that can limit the performance of the entire transceiver while determining its power consumption. In this research project, a multi-standard current-steering DAC and a reconfigurable DS ADC have been imple-mented in 130 nm CMOS. The D/A converter covers three programmable signal bandwidths (1.5 MHz, 5 MHz and 10 MHz), and is thus compatible with the 3GPP LTE stan-dard. It is designed for an effective resolution of 10 bits for the highest bandwidth, with a scalable power con-sumption between 6 mW and 10 mW. The DS modulator features between 13.2 bits and 10.4 bits of resolution for signal bandwidths between 100 kHz and 20 MHz, which makes it suitable for 4G communication standards.

Layout of the implemented DAC (left). The area occupation is 0.25 mm2 for both the I and Q channels. Chip micrograph of the Sigma-Delta ADC (right).The core size is 0.31 mm2.

Multi-Mode A/D and D/A Converters for High-Performance Wireless Links

Personnel: Luca Bettini

Funding: Nano-Tera PlaCiTUS, ETHZ

Partners: EPFL, CSEM

29

Multi-Band Receiver Design for LTE Mobile Communication

Wireless internet access and social media are becoming more and more important in our daily life. A mobile phone is not primarily a wireless phone anymore. It is rather a lifestyle device connecting the user to the whole world. New generations of smart phones and tablet computers make this online experience possible everywhere. As a consequence, mobile communication is shifting from voice- to data-oriented systems. To meet the increasing requirements, the 3rd Generation Partnership Project (3GGP) has developed the 3G Long Term Evolution (LTE) as a new standard. LTE is a flat, IP-based network archi-tecture. The introduction of new features like modulation schemes up to 64 QAM and MIMO operation increase the achievable data rate.This project sets the focus on the baseband filtering of the down converted signal. The most important task of the baseband filter is to suppress the unwanted blocker signals. For proper signal reception the filter has to be highly linear and provide low noise. The developed multi-mode baseband filter supports all six LTE bandwidths and also WCDMA, TD-SCDMA and GSM operation. Band-width and gain tunability are realized by programmable capacitors and resistors. Power efficiency in the lower bandwidth modes is maintained by scaling down the gain bandwidth product of the operational amplifiers. The de-signed baseband filter has been fabricated in a 130-nm CMOS process.

Layout view of the multi-band receiver baseband filter, im-plemented in a 130nm CMOS technology.

Personnel: René Blattmann

Funding: KTI 9836.1 ERT

Partners: ACP

Multi-Band Transmitter Design for LTE Mobile Communication

The trend in cellular networks is following the increasing demand of higher speed and extended link flexibility to-wards a new standard, called Long Term Evolution (LTE), which combines the advantages of OFDM systems and MIMO antenna techniques. This paves the way to the next generation (4G) of cellular networks and increased integration in transceiver chip design with lower supply voltage, fewer off-chip components and more functional-ity on a smaller die.LTE introduces significant changes as far as signal band-width and digital processing is concerned, resulting in increased complexity of the transmitter, especially when off-chip SAW filters are removed. In addition, keeping backward compatibility with HSPA, WCDMA and GSM together with the bandwidth programmability required by LTE has a strong impact on area and power consumption of the baseband filter in a direct conversion Tx architec-ture. As a consequence, novel techniques have been ad-opted in order to enhance efficiency and performance of the resulting transmitter. For example, the use of tunable amplifiers leads to a significant power reduction when lower bandwidth signals are processed.In this contribution, a transmitter baseband filter that sup-ports LTE, WCDMA, TD-SCDMA and GSM operation has been designed and fabricated in a 130nm CMOS technol-ogy. Particular attention was given to obtain a power and area efficient design with a large range of programmable bandwidth.

Layout view of the multi-band transmitter baseband filter, implemented in a 130nm CMOS technology.

Personnel: Dario Albino Carnelli

Funding: KTI 9836.1 ERT

Partners: ACP

30

Low Noise Multi Standard Frequency Synthesizer in Nano Scale CMOS

Wireless communication industry is a rapidly growing market, with a movement toward the integration of mul-tiple communication standards from different genera-tions. Recently, novel 4G technologies have been intro-duced. However, legacy standards like 2G (GSM) and 3G (WCDMA) still hold a large market share. Modern mobile terminals are thus required to operate in multiple stan-dards to serve new generations of standards while being backward compatible with existing standards. With such a need, multi mode RF transceivers become indispensable for wireless communication systems. And these trans-ceivers require multi mode RF frequency synthesizers. The cost effective solution to this requirement is a single chip multi-standard RF synthesizer. The synthesizers should have wide tuning range and need to fulfill stringent specifications on aspects such as spectral purity, frequen-cy accuracy and switching speed.This project aims at developing low noise high perfor-mance multi mode RF frequency synthesizers of fraction-al-N architecture. The architecture employs high order sigma-delta modulation to curb the quantization noise in the output spectrum. The voltage controlled oscillator (VCO) core involves two VCOs to cover the wide tuning range. A charge pump linearization technique and supply voltage partitioning are used to meet the stringent phase noise requirement. All designs are being implemented in 0.13 μm CMOS technology.

The simplified block diagram of a sigma-delta fractional-N frequency synthesizer architecture with supply voltage par-titioning.

Personnel: Hasene Gülperi Özsema

Funding: Nano-Tera PlaCITUS, ETHZ

Partners: EPFL, CSEM

Multichannel Front-End for Biomedical Applications

Different biomedical applications, such as electroenceph-alography (EEG), electromyography (EMG), and electro-cardiography (ECG), require analog multi-channel sensor front-ends for amplification and digitalization of the sig-nals sensed by the electrodes.This signals are of low frequency and low amplitude. Typi-cally EEG signals are in the frequency range of 1 - 100 Hz and have a peak-to-peak amplitude of up to 100 mV. Such a low signal level demands for low noise circuitry. Further, the differential electrode offset (DEO) is typically several orders of magnitude higher than the signal level and time-varying, which requires a high-pass filter with a very low cut-off frequency, typically around 0.5 Hz.In this project, we implemented an 8-channel analog front-end ASIC which consists of a low-noise chopped amplifier with programmable gain and a DS ADC which is shared by the 8 channels. The decimation filters are programma-ble, which allows to choose the output sample rate in the range of 1 - 8 kHz. High-pass filtering is done by periodi-cally compensating the DEO with a current-steering DAC.The IC achieves an SNDR of 33 dB for a typical sinu-soidal test signal of 100 mV peak-to-peak amplitude in a 1 - 100 Hz frequency.

Chip micrograph of the 8-channel sensor front-end IC called CEREBRO for typical biomedical applications, such as EEG.

Personnel: Roger Ulrich Thomas Burger Philipp Schönle

Funding: Nano-Tera i-IronIC, ETHZ

Partners: EPFL, EMPA, IRB Bellinzona

31

Real-Time Testbed for Advanced Mobile Transceiver Development

In this project, a GSM/EGPRS2 testbed has been devel-oped for verification of our baseband signal processing algorithms under real-world conditions and in real-time. The core of the testbed consists of two FPGA boards (re-fer to Figure below): the RF TRX Support Board is re-sponsible for interfacing the RF chip and distributing the baseband samples. The ML605 evaluation board of Xilinx hosts a large Virtex6 FPGA, which can run computational demanding algorithms.Synchronization in frequency and time is a crucial point which must be verified on the testbed, since it requires real-time interaction with the RF chip what is difficult to test by simulation. To this end, we employed a standard compliant base-station (BTS) emulator to generate and transmit a GSM broadcast signal which is used by mobile stations to synchronize to a base-station. The BTS emu-lator in our setup comprises of OpenBTS and GNU radio software running on Computer #1, and a USRP Board with antenna to transmit the signal over the air to the TRX Support Board.The digital baseband processing of a GSM/EGPRS2 transceiver has been implemented in VHDL and mapped to the Virtex6 FPGA. Intermediate results of the signal processing chain are collected and sent over a UDP/IP link to Matlab running on Computer #2. Our setup enables an in-depth analysis of the algorithms, as intermediate signals are often more meaningful than raw output bits.

Top: Block diagram of the real-time testbed. Bottom: Three main parts of the testbed: ML605 Eval board (right), RF TRX Support board (bottom left) and USRP box (top left).

Personnel: Stefan Zwicky Christian Benkeser

Funding: KTI 11376.1 SharperEDGE

Partners: ACP

Hardware Efficient Interference Cancel-lation Algorithms for the GSM Evolu-tion

With the latest standard extension EGPRS2, GSM can provide downlink data rates up to 1.2 Mb/s. Such perfor-mance improvements demand tight constraints regarding transmit power and signal to interference ratio compared to legacy GPRS receivers. Especially in urban areas to-days cellular networks are interference limited rather than noise limited. Interference in cellular radio systems can be divided into co-channel interference and adjacent channel interference. The latter is mainly arising from us-ers being served by the same base station, while the for-mer arises from users of neighbor base stations.The introduction of mobile station receive diversity in the latest GSM specifications (DARP phase 2), is helpful in order to achieve the high performance requirements. Re-ceive diversity enables sophisticated interference cancel-lation concepts to be applied, which are computationally more demanding than single antenna interference can-cellation approaches. Although baseband algorithms run-ning on dedicated hardware are suited for computation-ally intense tasks, hardware efficiency remains the main motivation.In this project algorithms for interference-aware receiver design have been simulated and evaluated. In particular a fruitful combination with existing channel estimators, channel shortening filters and equalizers was found. FPGA hardware implementations on a GSM testbed dem-onstrate the suitability for future ASIC implementations.

Inteference scenario: Presence of interference from users in the same cell and from base stations and users of sur-rounding cells.

Personnel: Harald Kröll

Funding: KTI 11376.1 SharperEDGE

Partners: ACP

32

Time division synchronous code division multiple access (TD-SCDMA) is a 3G standard currently emerging from China. It combines an advanced TDMA/TDD system with and adaptive CDMA component. As opposed to the Euro-pean UMTS standard, which uses FDD, the TDD nature of this standard allows asymmetric up- and downlink. Since the traffic becomes more and more asymmetric due to the recent popularity of mobile internet applications this leads to a more efficient usage of the available bandwidth. The latest evolution of TD-SCDMA, called multicarrier TD-HS-DPA, can use up to three parallel carriers to enhance the transmission rate, which enables peak data rates of up to 10 Mbps. This standard uses up to three parallel carriers to enhance the transmission rate.In this project different algorithms for the digital front end (DFE) for single carrier TD-HSDPA were explored. The DFE is the part of the receiver which processes the received samples from the analog-to-digital converter (ADC) before they are passed to the equalizer.The DFE contains the digital filters, the down-conversion and the synchronization in time and frequency. Further-more, non-idealities of the receiver like the DC-offset and the sampling point offset of the ADC have to be evaluated and, if needed, to be corrected.This research project has evaluated different signal pro-cessing algorithms for the DFE with focus on future ex-pansion to multicarrier systems.

The impact of a maximum DC-offset of 200% on the uncod-ed bit error rate without and with two different compensation algorithms for a 16QAM modulation test case.

Digital Front-End Design for 3.5G Mo-bile Receiver

Personnel: Sandro Belfanti

Funding: Hasler, ETHZ

Partners: ACP

Interference Cancellation-aided Equal-izers/Detectors for TD-HSPA

TD-HSPA is a standard that emerged from China initially known as TD-SCDMA, which was later adopted by 3GPP. It uses a TDMA channel access method combined with an adaptive synchronous CDMA component on 1.6 MHz slices of spectrum, allowing deployment in even tighter frequency bands than TD-CDMA.It exhibits a flexible TDD asymmetric nature giving it an advantage over other 3G standards, where up- and down-link resources are flexibly assigned according to traffic needs, and a flexible data rate upto 2.8Mbit/s is provided.TD-HSPA operates over physical channels in multipath propagation conditions, hence, severe inter-symbol inter-ference is experienced by the User Equipment (UE) at high mobility speeds upto 120 km/h.In order to bring this to practice, clever multiuser detec-tion and equalization techniques have to be deployed at the UE. However, the realization of the optimal exhaustive search algorithms in an environment such as that of the TD-HSPA standard (deploying higher order modulation up-to 64-QAM and multiplexing of up-to 16 users) is not feasible due to prohibitive complexity.In this project, novel and well-known techniques have been implemented and investigated with focus on their performance/complexity tradeoff and their limitations in realistic conditions subject to the standard definitions. The findings of this project recommends several performance-optimized and power-efficient candidate algorithms.

Evaluation of MLSE, MLSGD, MMSE, and ZF equalizers for 4 users with QPSK mapping and standard-defined propaga-tion channel of case 2.

Personnel: Karim Badawi

Funding: Hasler, ETHZ

Partners: ACP

33

Channel Coding and Hybrid ARQ for TD-HSPA

Modern mobile cellular communication standards rely on high-performance error-correction schemes to deliver high average data rates and good quality of service re-quired to serve the ever-increasing number of mobile us-ers. Therefore, turbo coding has firmly established itself as the forward-error correction coding of choice in many recent standards including the 3GPP standard suite. In addition to this strong class of channel codes, the HSPA evolution of 3GPP further specifies the use of Hybrid ARQ (HARQ), which allows for rapid retransmission of errone-ously received data packets. This key feature is a crucial mechanism to adapt to rapidly varying mobile channel conditions and thus enables the mobile terminal to main-tain a high average throughput.In this project, we have started to investigate the HARQ operation in terms of performance and silicon complexity, targeting a fully integrated receiver baseband solution op-timized for 3GPP TD-HSPA downlink. To this end, a stan-dard-compliant model of the decoding chain was imple-mented in Matlab. As shown in the figure below, the main principle of HARQ is to combine the soft information of re-quested retransmissions of an erroneously decoded data packet. This process improves the effective information about the data packet and enables the channel decoder to successfully deliver the packet with a high probability.It turns out that the high storage capacity required to pro-vide the HARQ operation is the main challenge and thus the major focus for further optimizations.

Top: Multiplexing and channel coding chain as specified for the terminal side of the TD-HSPA downlink. Bottom: Princi-ple of the Hybrid ARQ operation: soft-information of retrans-mitted packets is combined to increase decoding probability.

Personnel: Christoph Roth

Funding: Hasler, ETHZ

Partners: ACP

Trade-offs in the VLSI Implementation of LDPC Decoders

Besides turbo codes, low-density parity-check (LDPC) codes are among the best performing channel codes known today. Due to their suitability for implementation in modern CMOS technologies and due to their favorable IP-licensing situation, LDPC codes are gradually replac-ing well-established forward error-correction schemes.The goal of this project was to provide a general overview on the state-of-the-art in the design of LDPC decoders tak-ing into account the most prominent application examples existing today. To this end, we first introduced a measure that approximates the computational effort required to de-code the different LDPC codes, revealing that all consid-ered standards essentially require the same effort, while, however, the throughput requirements across standards may vary by more than 3 orders of magnitude. We found that this gap in complexity (together with other factors such as energy-efficiency concerns or need for reconfigu-rability) is the main driver for the architectural choices that can be found in the open literature. Furthermore, we high-lighted that there is one general prototype (full-parallel) architecture allowing the designers to efficiently bridge this gap by performing architectural transformations such as resource sharing and iterative decomposition resulting in more (row-parallel) and more (block-parallel) sequen-tial architectures. Sticking to this classification, we then collected data points from the state-of-the-art implemen-tations and highlighted the various trade-offs implied by these different architectural choices.

Top: Computational effort and throughput overview of typi-cal standards using LDPC codes. Bottom: Area trade-offs in state-of-the-art implementations. Interestingly, the high gap in throughput is bridged at roughgly constant AT-product.

Personnel: Christoph Roth, Christoph Studer EPFL: Alessandro Cevrero, Andreas Burg

References: IEEE ISCAS 2011

34

35

Research Projects

Technology CAD

Coordinators:

Wolfgang Fichtner Andreas Schenk

Dölf Ämmer Mathieu Luisier

36

TCAD Study of Tunnel FETs

Tunnel FETs (TFETs) are considered as the most promis-ing “post-CMOC” switches with potential < 0.5 V thresh-old voltage and sub-thermal slope. Hetero structures like Si-InAs are used to maximize the ON-current and sup-press the OFF-current. Band-to-band tunneling (BTBT) in TFETs is either in-junction or off-junction tunneling, depending on the doping profile and the applied gate bias. When using calibrated TCAD models for the border materials of an Si-InAs TFET it turns out that the tunnel path is in either case contained in the small-gap material. Sentaurus-Device parameters were calibrated to ballistic tight-binding NEGF results for bulk-like InAs homo diodes. Within the NanoTera project ENABLER the doping values at the InAs side of Si-InAs wire Esaki diodes produced at IBM Research Zurich could be determined by reverse modeling. Hetero wire TFETs based on these diodes were studied in detail varying certain design parameters. It was shown that in-junction BTBT in TFETs can never give a slope steeper than 60 mV/dec. This is because the tun-neling carriers are thermally excited as result of the drop of the quasi Fermi levels over the junction (see figure). However, strong vertical fields e.g. under the gate corners lead to off-junction BTBT with a sub-thermal “point slope” minimum of 25 mV/dec. The explanation for this effect is the sudden onset of BTBT when conduction and valence band edges overlap energetically beneath the drain-side gate corner. The current level in the voltage range where sub-thermal slope occurs is in the atto to pico Ampere/mm range only. The ON-current of the Si-InAs TFET is limited to ~ 3 mA/mm because the BTBT generation rate has a principle upper boundary in any semiconductor.

Electron (red) and hole (blue) BTBT generation rates in a Si-InAs hetero junction. The tunnel path is located between the peaks of the rate distributions. Red dashed curve: electron quasi Fermi level, black curves: band edges.

Personnel: Andreas Schenk

Funding: ETHZ, NanoTera ENABLER

Partners: IBM Research, EPFL

Microscopic Modelling of Nanoelec-tronic Tunneling Devices

The focus of semiconductor transport simulations has long been on models using classical or semiclassical de-scriptions based on the Drift-Diffusion picture or the more rigorous Boltzmann equation. Here, quantum-mechanical effects are incorporated with certain quantum correction terms. Because of the aggressive scaling of semiconduc-tor devices close to the atomic range and the hope for upcoming devices like tunnel nanostructures which oper-ate not despite of quantum mechanical effects, but rest upon them, more sophisticated transport models have to be used. The usage of a three-dimensional, atomis-tic full-band quantum transport solver is necessary to di-rectly include and accurately describe all the underlying effects like quantum confinement, tunneling, coherence, and others. However, the implementation of those more appropriate solvers also causes a substantial increase of the computational burden. Particularly the modelling of inelastic interactions like electron-phonon scattering is computationally very challenging.The purpose of this project is to investigate the impact of electron-phonon scattering in nanoelectronic tunnel de-vices in the framework of atomistic full-band simulations, formulate and implement computationally viable models, investigate various tunnel nanostructures numerically, and validate the simulation results with experimental data. The latter are either taken from literature or provided by IBM Research via the Nano-Tera project ENABLER.

Simulated reverse IV characteristics of a Si ultra-thin body (3nm) tunneling structure (p=1e20cm-3, n=1e20cm-3) in the atomistic full-band framework. Comparison of different sim-plifications of el-ph scattering.

Personnel: Reto Rhyner Cedric Bessire Andreas Schenk

Funding: ETHZ, Nano-Tera ENABLER

Partners: IBM Research, EPFL

37

An Adaptive Multi-Wavelet Solver for High-Dimension Transport Equations in Semiconductor Devices

The Multi-Wavelet (MW) Discontinuous Galerkin Meth-od (MWDG) has been developed at IIS for the solution of 6-dimensional semiconductor transport equations (Boltzmann Transport Equation (BTE), Wigner Equa-tion). The main advantage of wavelets are their hierar-chical compression and adaptation properties enabling an adaptive solution with a fraction of the coefficients that are necessary with a conventional basis (simula-tions show compression rates of over 99 %). Since the advantages of wavelets increase in higher dimensions, they could enable uniquely accurate TCAD tools for 2- and 3- dimensional devices. In order to further reduce the number of necessary coefficients, the MWDG has been generalized to high polynomial orders. Simulations show that high polynomial orders in physical space and energy directions can further reduce the number of coeffcicients significantly (by up to 90 %). However, to take advantage of wavelet adaptation in semiconductor transport simula-tions, the distribution function should be separated into a subspace which contains the energy and density infor-mation and a subspace that contains the current infor-mation. The energy is a density-normed quantity. Hence, the contribution of the wavelets to the density-normed L2 norm should be chosen as adaptation criterion in order to guarantee an accurate energy everywhere in the device. The current, on the other hand, is of absolute relevance, so that the wavelet contribution to the simple L2 norm is a good adaptation criterion and, consequently, very high compression rates are possible.

Top: Part of the solution containing the current information (enabling high compression rates).Bottom: Density normed part of the solution containing the energy information.

Personnel: Vincent Peikert Andreas Schenk

Funding: ETHZ, Toshiba

Partners: Toshiba

References: [T15.]

Trap-Assisted Tunneling in InAs-Si Nanowire Heterojunctions

The Tunnel FET is a promising candidate for low power applications due to its potential sub-thermal swing. The choice of material is InAs-Si, to benefit from the higher tunnel probability in InAs and to enable very low off-state currents with a large bandgap material such as Si. Such a heterostructure system can only be realized at the nano-meter scale, because of the lattice mismatch of 11.6 %. This may induce strain or defects at the heterojunction where the tunneling takes place. For electrical investi-gation of the tunneling, InAs NWs were grown on highly doped Si substrates to fabricate tunnel diodes (TDs; inset C). A high-resolution TEM analysis revealed a dislocation network with periodicity of 3.6 nm at the InAs/Si hetero-interface as a consequence of strain release (B). The second derivative of the TD current was measured with a highly sensitive lock-in technique to investigate changes in the conductance (C). Peaks appear mainly in the for-ward direction and can be related to tunneling via trap levels that form within the band gap due to the disloca-tions at the hetero-interface. At higher voltages, in reverse bias, no peaks are observed. TCAD modeling has been applied to calculate the band-to-band tunneling (BTBT) rate (A). It shows that in forward direction and at smaller reverse bias the BTBT takes place at the junction. Here, electrons can also tunnel via trap states if they appear in the right energetic window. However, in reverse direction the BTBT shifts completely into the InAs, away from the heterointerface, where no traps are present.

(A) Simulated band edge diagram for the InAs-Si hetero-junction. (B) TEM image indicating dislocation network at heterointerface. (C) Second derivative measurement of TD current showing peaks related to trap-assisted tunneling.

Personnel: Cedric Bessire Andreas Schenk

Funding: ETHZ, NanoTera ENABLER

Partners: IBM Research

38

Combining Spherical Harmonics Ex-pansion and Haar-Wavelets to Solve the Boltzmann Transport Equation

The Spherical Harmonics (SHs) Expansion Method (SHE) became by far the most popular deterministic method in science and industry to solve the Boltzmann Transport Equation (BTE) for semiconductor devices. However, one drawback of the SHE method is that the Finite Volume method (FVM) is used to approximate the SHs coeffi-cients so that the number of necessary coefficients scales exponentially with the dimension. Consequently, even for simple 2- or 3-dimensional semiconductor devices, the method requires very coarse meshing and the accuracy is not sufficient anymore. The idea of this project is to ap-ply Haar-Wavelets (HWs) for the FVM instead of the usual piecewise constants. HWs offer hierarchical compression and adaptation techniques whose advantages even in-crease with the dimension. Furthermore, SHs also show strong hierarchical properties so that compression tech-nics can be applied to the full 6-dimensional phase space. Studies show that even in 1-dimensional devices about 99 % of the coefficients could be easily omitted with this new ansatz. However, it turns out that the special cou-pling between the even and odd SHs (which are defined on different grids) cause problems if the FVM is used un-der wavelet compression. The problem can be overcome by an interpolation ansatz and is softened in high dimen-sions and with increasing SHs orders. However, since the Multi-Wavelet Discontinuous Galerkin Method - also developed at IIS - performs superior, it is currently the method of choice.

Top: SH coefficients in energy direction. Bottom: Com-pressed and compressed-FVM solutions in energy and velocity directions. High compression rates are possible, however the compressed-FVM behaves oversensitively.

Personnel: Vincent Peikert Andreas Schenk

Funding: ETHZ, Toshiba

Partners: Toshiba

Full-Band Monte Carlo Simulation of Single Photon Avalanche Diodes

Single or few photon detection has become an important feature in optoelectronic systems and enables a variety of interesting applications in medicine, biology, and physics. At present, the full-band Monte Carlo (FBMC) solution of the Boltzmann transport equation (BTE) is the most prom-ising theoretical tool for high-field carrier dynamics within semiconductor physics of semiclassical charge transport. The particles propagate classically in the phase space whereas quantum mechanics is involved in the compu-tation of the dispersion relation and carrier scattering. A computationally efficient formulation of the scattering rates, while keeping the main physical features, renders the CPU-intensive calculation of the breakdown charac-teristics of single photon avalanche diodes (SPADs) fea-sible. On the deca-nanometer length scale nonequilibrium effects like the velocity overshoot, the dead-space, and the nonlocal impact ionization become important and are naturally covered by the Monte Carlo technique. CarloS, our FBMC simulator, built from scratch, is applied to the high-field charge dynamics of the multiplication process in SPADs. Compared to previous works employing simple charge transport models, the solution of the BTE and the incorporation of the full-band structure puts the evaluation of the breakdown probability, the time to avalanche break-down and its jitter on deeper theoretical grounds. The ex-amined multiplication layers, having widths between 55 nm and 500 nm, are made of gallium arsenide, indium phosphide, or indium aluminium arsenide.

Breakdown probability vs. reverse bias for SPAD multiplica-tion regions made of GaAs. Inset: Breakdown probability vs. excess bias.

Personnel: Denis Dolgos

Funding: ETHZ

References: [T2.]

39

Thermal transport through <100> and <110> rough Si nanowires is investigated using an atomistic quantum transport approach based on a modified Keating model and the Wave Function formalism. The thermal conduc-tance, resistance, and conductivity are calculated for dif-ferent nanowire lengths ranging from 20 to 150 nm, diam-eters (3 and 4 nm), and root mean square of the rough surfaces. The simulation results show that thermal trans-port is diffusive in rough nanowires without surrounding oxide layers. Its degradation, as compared to ideal struc-tures, cannot be attributed to phonon localization effects, but to the properties of the phonon bandstructure. Phonon bands with an almost flat dispersion cannot propagate through disordered structures due to mode mismatch between adjacent unit cells. Hence, several modes are reflected back to their origin and do not contribute to the overal energy current, leading to lower thermal conductiv-ity when interface roughness is present.

(a) Schematic view of a rough Si nanowire structure in the x-y plane. (b) Thermal conductance Gth of rough Si nanow-ires (d=4 nm, Drms=0.15 nm). (c) Thermal conductivity kth of 50nm long rough Si nanowires.

Investigation of thermal transport deg-radation in rough Si nanowires

Personnel: Mathieu Luisier

Funding: SNF PP00P2-133591 MED-NS NSF PetaApps 0749140

A multi-dimensional, atomistic, quantum transport simu-lator called OMEN has been developed over the last 6 years to investigate the performance of realistic na-noscale transistors with various geometries and material compositions. The central computation consists in solv-ing the Schrödinger equation with open boundary condi-tions several thousand times. To do that, a Wave Function approach is used since it can be relatively easily paral-lelized. To further improve the computational efficiency, three additional levels of parallelization are identified, the work load is optimally balanced between the CPUs, computational interleaving is applied where possible, and a mixed precision scheme is introduced. Hence, while simulating the I-V characteristics of two different device types, a high electron mobility and a band-to-band tunnel-ing transistor, OMEN could read sustained performances up to 1.28 PFlop/s in double precision (55% of the peak performance of the machine) and 1.44 PFlop/s in mixed precision on 221,400 cores on the CRAY-XT5 Jaguar at Oak Ridge National Lab (ORNL).

(a) Schematic view of a single-gate, multi quantum well In-GaAs high electron mobility transistor (HEMT) (b) Walltime and sustained performance of OMEN up to 221,400 cores for the simulation of the HEMT structure above.

Atomistic nanoelectronic device engi-neering with sustained performances up to 1.44 PFlop/sPersonnel: Mathieu Luisier

Tim. B. Boykin (University of Alabama) Gerhard Klimeck (Purdue University) Wolfgang Fichtner

Funding: SNF PP00P2-133591 MED-NS NSF PetaApps 0749140

40

Using a full-band and atomistic approach based on the nearest-neighbor tight-binding model and the Non-equi-librium Green’s Function formalism, (111)/<110> GaSb, (100)/<110> strained-Si, and (100)/<100> In0.53Ga0.47As n-type double-gate ultra-thin-body field-effect transistors designed according to the ITRS specifications for 2020 are simulated in the ballistic limit of transport and with electron-phonon scattering. It is found that at an EOT of 0.59 nm, the GaSb device offers the highest ballistic ON-current, at a fixed OFF-current of 0.1 mA/mm, due to the projection to the G point of bands originating from the bulk L-valley and possessing a low transport effec-tive mass. It is followed by the strained-Si FET and fi-nally the In0.53Ga0.47As FET, the latter suffering from its small density-of-states in the channel despite very high electron velocities. However, when electron-phonon scat-tering is taken into account, the presence of multiple en-ergy subbands, as in GaSb and strained-Si, increases the probability of backscattering for electrons and so that the current of these devices does not exceed that of the In0.53Ga0.47As FET by more than 13%.

Schematic view of double-gate ultra-thin-body n-FETs (Lg=10.7 nm, tbody=5 nm). (a) GaSb, (b) strained-Si, and (c) In0.53Ga0.47As. (d) Transfer characteristics Id-Vgs of the three n-FETs above at Vds=0.05 and 0.68 V.

Performance comparison of GaSb, strained-Si, and InGaAs double-gate ultra-thin-body n-FETsPersonnel: Mathieu Luisier

Funding: SNF PP00P2-133591 MED-NS NSF PetaApps 0749140

We use a single, multi-dimensional, and atomistic quan-tum transport simulator to investigate how far carbon nanotube, graphene nanoribbon, InGaAs, and strained-Si ultra-thin body and nanowire n-type field-effect transistors (FETs) can be scaled and to understand the mechanisms that limit their miniaturization. Despite multiple leakage paths (intra-band and band-to-band tunneling, hole in-duced barrier lowering), non-planar devices with a multi-gate architecture and an extremely narrow cross section can be expected to still work as good switches, even with a 5 nm gate length, provided that they exhibit a large enough band gap and transport effective mass and that their gate contact can modulate the electrostatic potential of the source and drain extensions to effectively increase the gate length. This can be achieved, for example, by carefully engineering the dielectric layers separating the gate contact from the semiconducting channel, as shown in the Figure below.

Top: Spectral current distribution in CNT FETs with the same EOT=0.64 nm, but different dielectric configurations.Bottom: Transfer characteristics Id-Vgs for a CNT (left) and a Si NW FET (right) with the same dielectrics as above.

Ultimate device scaling: performance comparisons of carbon-based, InGaAs, and Si FETs for 5 nm gate lengthPersonnel: Mathieu Luisier

Mark Lundstrom (Purdue University) Dimitri Antoniadis (MIT) Jeffrey Bokor (UC Berkeley)

Funding: SNF PP00P2-133591 MED-NS NSF PetaApps 0749140

41

Modeling leakage currents of advanced CMOS devices induced by extended defects in silicon

Today’s aggressive processing conditions lead to non-negligible amounts of extended defects in the junction re-gions of the devices. Since thermal budgets are reduced and doping gradients increase significantly, it has become unavoidable that extended defects remain in the deple-tion region in the fabricated device. In order to reliably predict the resulting leakage currents, studies of the rela-tion between the presence of extended defects and the electrical properties of the silicon crystal are necessary.Though first approaches to find atomistic models are un-dertaken, so far there is no model that accounts for the specifics of extended/topological defects. Especially no connection between the influence of the EDs on the elec-tronic properties like band structure and the resulting im-plication on carrier life times has been established. It is to be expected, that even transition metal impurities, which are known to form point like recombination centers will show different properties and behavior when correlated with extended defects. The research work focusses on:• Analysis of electrical properties of extended defects in silicon and derivation of a model to describe the influence that extended defects impose on the physical properties of the silicon crystal.• Development and implementation of numerical models to be plugged into existing TCAD solutions in order to ac-count for altered electrical properties due to existence of extended defects.

Top: 3D simulation of the investigated pn-junction structure with complex cocktail implants of many different doping spe-cies. Fully processed device shows significant and bias de-pendend leakage increase.

Personnel: Artur Scheinemann, Andreas Schenk

Funding: EU-ICT-258547 ATEMOX

Partners: ATEMOX Consortium

42

43

Research Projects

Physical Characterization

Coordinators:

Wolfgang Fichtner Mauro Ciappa Dölf Ämmer

44

Comparison of the simulated dose depth curves (lines) along the 0°, 30°, 60°, and 90° directions in the dose map (top) with the related TMA dose depth measurements.

Two-Dimensional Dosimetry Tech-niques in Polymers

Personnel: Mauro Ciappa, Luigi Mangiacapra H+S: Maria Stangoni, Stephan Ott CSM Instruments: Fanny Ecarla

Funding: KTI-9561.1 EBXLINK

Partners: Huber+Suhner

The quantitative prediction of the deposited dose is a pri-mary task when designing the enhanced mechanical and thermal properties of electron beam crosslinked cables to be used in critical applications like railway traction, auto-motive, and solar. In addition, accurate dosimetry makes possible to define new irradiation schemes for better en-ergy efficiency and throughput of the accelerators, as well as to shorten the design cycle of new products. In this project, the Monte Carlo based simulation code EBXLINK3D has been developed. Compared with previ-ous codes, relevant progresses in terms of model accu-racy and calculation time. EBXLINK3D is a 3D process simulator for cables and accelerator geometries of what-ever complexity, which takes into consideration the full ir-radiation process. Conveyors are modeled in real scale, including irradiation schemes as racetrack, figure of eight, rotation, and the mixed mode. The irradiation field of each accelerator and the related distribution of the electron flu-ence are calibrated based on experimental data that are collected according to standardized protocols and proce-dures.For the sake of usability, EBXLINK includes simplified simulation modes that imply calculation times of some few minutes on a typical workstation. Thanks to the use of sophisticated parallelization procedures, even the most accurate and complex irradiation configurations can be completed within a typical calculation time of five hours.

In the simulation of an irradiation process by the figure-eight mode, dozens of partial Monte Carlo simulations (e.g. a-d) are added up to obtain the total dose distribution in the poly-mer (d).

EBXLINK3D: A Monte Carlo Simulator for 3D Dose Distributions in Electron Beam Processing of Electric CablesPersonnel: Luigi Mangiacapra, Mauro Ciappa

H+S: Maria Stangoni, Stephan Ott

Funding: KTI-9561.1 EBXLINK

Partners: Huber+Suhner

Dosimetry techniques with high spatial and volume reso-lution are increasingly needed in radiation processing of materials. This is for instance the case in medical devic-es, where tools are required for dose mapping in electron beam processed bioresorbable polymers with complex three-dimensional geometries. An additional application field, where both spatial and volume resolution are re-quired, is the calibration and validation of the Monte Carlo simulation tools.In this project micro-indentation (MHT) and thermo-mechanical analysis (TMA) have been used to acquire two-dimensional (2D) maps of the local dose-dependent visco-elastic properties in cross-linked polymer samples. Special attention is paid to two-dimensional dose map-ping in electron beam processing of cables and to the use of both techniques to calibrate and validate the Monte Carlo simulation tool EBXLINK3D. TMA applied to a mul-tilayered sample has been shown to provide the required lateral and volume resolution. This has also been the case of MHT, carried out at room temperature on poly-ethylene samples. In the latter, some limitations have been observed due to the reduced dynamics of the signal and the random noise introduced by the different phases. However, such limitations can be easily resolved by MHT measurements close to the melting point of the polymer.

45

All modern automotive applications fully depend on elec-tronic systems for their basic operation. In recent years, due to the implementation of efficient design-for-reliability strategies, wear-out failures almost disappeared in inte-grated devices during the typical life cycle of a car ranging from 10 to 15 kilo-hours. Stated otherwise, the majority of the reliability issues that are observed at present in prop-erly designed products, integrated into well matching and well controlled processes, mainly occur due to processing incidents and process-related defects, e.g. in the form of particles, lithography errors, or defects. Consequently ef-ficient screening procedures are needed to reach the very low levels of residual defectivity required by the “zero-defect strategies”. In this project, four main results have been achieved. The first development is aimed to improve the procedures to control the defectivity of gate oxide in LDMOS transistors with an original solution called Built-In Gate Stress. The scope of the second achievement is to screen out defects in the shallow trench insulation of LD-MOS transistors with an original procedure called Built-In Drain Leakage Test. With the third development a novel approach is proposed to screen out defective capacitors used in Successive Approximation Register (SAR) Ana-log-to-Digital Converters. Finally, with the fourth accom-plishment a novel built-in ∆IDDQ testing technique for the screening of low voltage transistor of the SAR logic, has been developed, which is based on the concept of the background current compensation.

Schematics and layout of the solution proposed to stress and to test the banks of Vertical Parallel Plate Capacitors in-tegrated into in Successive Approximation Register Analog-to-Digital Converters for automotive applications.

In Situ Screening Techniques for Auto-motive Devices

Personnel: Vezio Malandruccolo, Mauro Ciappa Infineon: Hubert Rothleitner

Funding: ETHZ, Infineon

Partners: ABB Semiconductors

The on-going miniaturization in micro-electronics requires measurement techniques that are capable of analyzing images of device features with nanometer (nm) dimen-sions. Scanning electron microscopy (SEM) metrology has been the preferred technique of choice addressing the major concerns of scanning speed, non-destructive-ness and minimum heat-dissipation. With the lack of available alternatives, however, SEM systems will con-tinue to be employed for 1D, 2D, and 3D in-line metrology of devices at the nm scale. For a reliable analysis of realistic microelectronic pattern, the interpretation of SEM results through currently avail-able MC models is unsatisfactory for several reasons. The prohibitive computing expense of present MC imple-mentations and the lack of proper physical modelling of charging phenomena have rendered an extension to 2D and 3D metrology impossible.In this framework, preliminary work has been carried out to implement a set of efficient algorithms to reduce the problem complexity to a tractable problem on modern high-performance computing environments. In particular, the existing Monte Carlo simulation tool has been adapted to include efficient problem-oriented parallelization strate-gies for the reduction of the computing time and ported on the CrayXT5 of the Swiss National Supercomputing Center.

Simulated SEM images of a FINFET,length 220 nm. The gray scale is the intensity of secondary electrons signal as acquired by a lateral (left), to (center), and 2π detector. This is the result of the 10 billions of primary electrons simulation.

Synthesis of Scanning Electron Mi-croscopy Images by High Performance ComputingPersonnel: Aniello Esposito, Mauro Ciappa

Funding: ETHZ, SNF 200021-134985 SASEM

46

Compared to silicon, gallium nitride (GaN) has many ad-vantages. Among these, GaN has a wider band-gap, low-er on-resistance and higher electron-mobility. Therefore, GaN power devices present an unprecedented potential to extend miniaturization and enhance efficiency of power supply circuits. When GaN power devices are used in fast switching circuits, it is necessary to model accurately the electro-thermal behavior, since the electrical performanc-es are strongly affected by self-heating effects.In this project, an efficient methodology for electro-ther-mal simulation of GaN devices switching at frequency has been developed. In a first step, the thermal imped-ance of the devices has been modeled by the Foster and Cauer type compact thermal circuits, where the related circuit parameters have been extracted by 3D transient simulation finite element simulation of the whole device. In a second phase, the Curtice model has been assumed, where drain-source current and some internal capaci-tances have been modeled as a function of temperature. Finally, the thermal and electrical compact models have been combined in a circuit simulation environment in or-der to obtain an integrated electro-thermal model. Electri-cal and thermal performances have been simulated up to a switching frequency of 1 GHz. The simulation show that under typical operating conditions, the junction tempera-ture of the device during on-state can reach up to 60°C, by resulting in a substantial decrease in the drain-source current.

Temperature distribution in GaN power device operated in thein steady-state (top).Transient electro-thermal simulation results at 1 GHz (bottom).

Development of an Efficient Methodol-ogy for Electro-thermal Simulation of High-frequency Gallium NitridePersonnel: Mauro Ciappa

Toshiba: Satoshi Ono, Shigeru Hiura

Funding: Toshiba

Partners: Toshiba

Scanning electron microscopy (SEM) is still the technique of choice for imaging and for in-line measurement of criti-cal dimensions and overlay accuracy in most of the core technology processes. In particular, critical dimension microscopy provides information about design template matching and edge placement errors through links with design having proven beneficial effects on process yield and product reliability. Up to now, the definition of the tar-get geometry in Monte Carlo codes for the simulation of SEM images based on basic bodies (e.g. blocks, cylin-ders spheres, etc.). Of course, this simple approach is not suitable for the simulation of realistic structures as they occur in semiconductor processing. This is the case for instance of photoresist structures, where the complexity of the 3D geometry and the surface roughness play a rel-evant role.To solve this limitation, a new tracking engine has been implemented to work in conjunction with the state-of-the-art object oriented package ROOT. With this new configu-ration, the simulation tool is able to import not only user-defined geometries but also device structures generated by a TCAD process simulator (e.g. Sentaurus Process). In this case, the geometry is generated and meshed (tet-rahedra) by means of the TCAD tool. Since the tracking engine makes uses of octrees, this has just a limited im-pact on the simulation time, even for densely meshed structures.

Photoresist line, PMMA on the top of a silicon substrate gen-erated and meshed by Sentaurus Process (left). Simulated secondary electron SEM image of the structure with a lat-eral (right top) and 2π (right bottom) detector.

Monte Carlo Simulation of Scanning Electron Microscopy Images with Com-plex Meshed GeometriesPersonnel: Aniello Esposito, Mauro Ciappa

Synopsys: Lars Bomholt

Funding: ETHZ, SNF 200021_134985/1 SASEM

Partners: Synopsys

47

High power semiconductor technology is under great pressure to increase device performance. New applica-tions require a higher switching frequency, higher work-ing temperature and higher cycling capability. Some ma-jor limiting factors of standard devices are given by their packaging technologies and not by the semiconductor. Furthermore new environmental regulations also put a great pressure to develop new packaging technologies using materials and processes, which are more respect-ful of the environment.One of the key processes in packaging is the mechani-cal and/or electrical connection of the silicon device to an housing and/or to an external circuit. This process is com-monly called die attach. Die attach can simply be defined as the process in which the silicon die is mounted on a supporting structure. It can be done by different means like soldering or gluing. Presently, the state of the art in die attach is still a soldering process. The soldering al-loys have considerably evoluted in the past few years and many options exist to replace the commonly use tin-lead eutectic alloy. The scientific challenge of this project is to realize a bonding layer with the standard metals already used in high power semiconductor technology having a low formation temperature, a high melting point and also to stop or limit the diffusion of the different metal species in order to obtain a stable bonding layer.

Optical micrograph (1000x) of a cross-section through a non-optimized die attach showing crack propagation within the silicon die after thermal stressing.

Reliable Die Attach Technologies for High Power Switching Devices

Personnel: Franc Dugal, Mauro Ciappa

Funding: ETHZ

Partners: ABB Semiconductors

48

49

Research Projects

Bio-Electromagnetics and Electromagnetic Compatibility

Coordinator:

Niels Kuster

(Titularprofessor of Information Technology and Electrical Engineering)

50

Enhanced Simulation of Waveguide Structures combining FDTD, FEM and MM

Up to date, the finite different time domain (FDTD) tech-niques been successfully applied to a wide variety of both academic and industrial electromagnetic problems ranging from radiating/guiding microwave devices, EMC, optics, to bio-medical applications. Despite the versatility achieved with this pool of FDTD solvers, we are convinced that improving the balance between efficiency, accuracy and generality requires a step forward into hybridization. A platform that tackles each part of the problem with the most suitable method and process the specific outputs into the overall result. A great part of the structures en-countered in microwave applications, given its resonant nature, constitute a challenging test field for this ap-proach. Therefore, this project developed a new state-of-the-art solvers based on the Mode Matching Technique (MM) and the Finite Element Method (FEM) for the simu-lation of passive waveguide structures. This solver has been integrated into the existing simulation framework to provide the user with a common simulation environment that will abstract the method in which the solver has been implemented. This new module has been tested through a set of benchmarks including dual-mode filters with rect-angular and elliptical cavities.

Top: Simulated and measured return loss response of an Orthomode Transducer . Bottom: Slice and vector views of the E-field distribution at 14GHz (V-polarization, left) and at 17.5GHz (H-polarization, right).

Personnel: Bryn Lloyd, Nicolas Chavannes, Niels Kuster; SPEAG: Pedro Crespo-Valero Erdem Ofli; EPFL: Michael Mattes, Ioannis Koufogiannis, Apostolos Sounas

Project: CTI Poseidon

Partners: IT’IS, SPEAG, EPFL

Robust FDTD Simulations in Non-Lin-ear Media

The purpose of this work is to calculate a non-linear op-tics result using the FDTD method, and compare it to the analytical solution. The setup concerns the reflection and transmission of a plane polarized TE-wave crossing a lossless nonlinear dielectric film. The film is between two semi-infinite media which are assumed to be homoge-neous, non-absorbing and non-magnetic isotropic.

This particular problem provides an interesting opportu-nity to test the accuracy of the SEMCAD FDTD numerical solver in Kerr-like media. The reason is that this nonlinear phenomenon has the rare instance of an analytical solu-tion, as shown by H.W. Schürmann et al. at University of Osnabrück.

At this stage, the numerical calculation of the analytical solution has been completed using Mathematica. The re-sults are in concordance to the work done by the group at Osnabrück. Current status of the project is at the set-up stage of proper model structures to be simulated in SEMCAD. The relevant results to be compared with the analytical solution are the reflectivity, the transmissivity and the phase shift on reflection. Of particular interest is the inflection point of the reflectivity (R=0.0), and the bi-stability of the reflectivity with respect to the scaled mag-nitude of the incident E-field and the film thickness.

An optical ring resonator, a device that enhances optical nonlinear phenomena. These resonators are used in the implementation of compact and ultra-fast optical process-ing circuits.

Personnel: Nicolas Chavannes, Niels Kuster SPEAG: Guillermo Del Castillo, Stefan Schild

Project: CTI Poseidon

Partners: IT’IS, SPEAG, EPFL

51

Optimization of a Multi-GPU Acceler-ated FDTD Solver for HPC Hardware Architectures

Using graphics processing units (GPUs) for accelera-tion of numerical tasks has become a widely used ap-proach in scientific computing. The release of NVIDIAs compute unified device architecture (CUDA) in 2006 has significantly reduced the complexity of implementing gen-eral purpose code. The Finite-Difference-Time-Domain (FDTD) algorithm with its underlying grid-based modeling methods is perfectly suited for application on such hard-ware.In this project, an existing 3D Multi-GPU accelerated FDTD solver has been optimized with respect to relevant CUDA performance parameters such as block-size, thread-size and memory types. There are mainly three different types of memory available: global memory, shared memory and registers, with memory access efficiency increasing and resource availability decreasing in the same order. While using less global memory increases the number of float-ing point operations per memory access, allocating too many registers per thread decreases the occupancy (i.e. the number of parallel executed threads on the device) for a given (block-size,thread-size) combination. Since the ideally suited parameter set strongly depends on the physics of the underlying problem and the hardware specifications, an optimization algorithm has been em-ployed that determines the optimal parameters before the actual start of the simulation.

Shown above is an NVIDIA Tesla C2070 card, series 20 CUDA enabled GPU. Image courtesy of NVIDIA Corpora-tion.

Personnel: Tom Stefanski; Zhen Chen Nicolas Chavannes, Niels Kuster SPEAG: Manuel Guidon, Stefan Benkler

Project: CTI Poseidon

Partners: IIS, IT’IS, SPEAG, EPFL

Simulating EM-Neuron Interaction

Exposure to strong low-frequency electro-magnetic (EM) fields can result in unwanted nerve stimulation or inhibi-tion causing safety concerns. Neuroprostheses, on the other hand, use active interference with neural signaling to compensate for lost sensory or motoric functionality. Deep brain stimulation uses electrodes implanted in spe-cific brain areas to modulate neuronal activity in order to treat, for instance, chronic pain, Parkinson’s disease, tremor and dystonia. EM-neuron interactions are also central regarding neuromotoric incapacitation (‘Tasers’) whose mechanism and risks are poorly understood.The objective of this project is to provide a simulation platform for investigating the interaction of EM fields with nerves. It utilizes the EM solvers of SEMCAD X and cou-ples the resulting field to a description of neurons con-sidering factors such as membrane channel dynamics, synaptic input, or temperature dependences. The latter is achieved by interfacing with the NEURON simula-tion software which is widely employed in computational neuroscience (www.neuron.yale.edu). Recordings of ar-bitrary membrane parameters over time allow the analy-sis of whether and at which neuronal segment spiking is initiated, signal propagation inhibited or the firing pattern of multiple neurons synchronized. From these reaction patterns the selectivity of nerve recruitment can then be inferred. Eventually, the model is used at optimizing an existing neuroprosthesis or a novel treatment in terms of safety and efficacy.

Neuron from rat hippocampus (provided on ModelDB) stim-ulated by a monopolar point electrode with a step waveform. Bottom: Time plot of transmembrane potential at soma cen-ter.

Personnel: Johanna Wolf, Bryn Lloyd Nicolas Chavannes, Niels Kuster ZMT: Esra Neufeld

Project: Sim4Life

Partners: IT’IS, ZMT

52

Comprehensive Broadband Database of EM and Thermal Tissue Parameters

This study was designed to create standardized values for thermal and dielectric tissue parameters used for the assessment of electromagnetic (EM) wave absorption by the human body and the potential influence on human health. Based on a critical review of existing literature, key inconsistencies were resolved and missing values approximated. The thermal tissue property parameters provide infor-mation on blood flow, thermal conductivity, heat capac-ity, density and heat generation rate. Data was drawn from an intelligent analysis of credible studies. The EM tissue properties are based on the work of Gabriel and colleagues (Report N.AL/OE-TR- 1996-0037) who mea-sured the dielectric properties for a frequency spectrum ranging from 10 Hz to 100 GHz for several tissues and organs and fitted the values to a 4-Cole-Cole expression.The culmination of this study was the creation of a com-prehensive, reliable, and up-to-date database of param-eters intended to ease the access to reliable values and provide a forum for discussion. In addition to the param-eter values, the database contains information on the spread and standard deviation of the parameter values enabling the evaluation of the uncertainty of those param-eters. The database is available for free for the research community (www.itis.ethz.ch/database) and is regularly updated.

Left: Dielectric Assessment Kits (DAK) for measuring the dielectric properties of liquids and solids. Right: High-res-olution whole-body models of an adult and a child, typically used in numerical assessment of EM exposure.

Personnel: Marie-Christine Gosselin Philippe Hasgall, Nicolas Chavannes Niels Kuster; ZMT: Esra Neufeld

Project: IT’IS

Partners: IT’IS

HPC Enabled Large Scale Simulations of Focused Ultrasound in Complex Anatomies

Focused ultrasound (FUS) under MR guidance is increas-ingly employed in many treatment modalities.A dedicated acoustic solver has been developed to handle the complexity of ultrasound wave propagation in highly inhomogeneous anatomies. Full 3D simulations account-ing for effects such attenuation, reflection, interference and nonlinearity can be performed in large anatomical models while a GPU hardware accelerated version has been implemented allowing up to 36x speedup in com-parison to CPU variants.The solver has been integrated into our modeling and dis-cretization framework and can make use of our existing Virtual Population anatomical models or models gener-ated through our image segmentation tool. It can also be coupled to our thermal and flow solver to study effects such as tissue heating and acoustic streaming.The acoustic solver has been used in real-life applications with our research partners to model focused ultrasonic ablation of renal and hepatic tumors, microthalamotomy for neuropathic pain treatment, sonication of the brain in animal models for BBB disruption modeling, and for de-sign optimization of a novel transducer used for superfi-cial tumor ablation.The full 3D wave acoustic solver will strengthen our ac-tivities in the computational life sciences and allow us to investigate a wide variety of modalities and applications.

3D model of simulation replicating an experimental setup of hepatic tumor ablation in live sheep (left). The resulting pressure distribution through the geometric focus of the transducer.

Personnel: Adamos Kyriacou, Nicolas Chavannes Niels Kuster; ZMT: Esra Neufeld

Project: CO-ME III

Partners: IT’IS, ZMT

53

Modular Framework for Large Scale Parallelized FEM Simulations

A flexible framework for solving partial differential equa-tions arising from many types of physical problems has been developed. The main motivation is continuously growing demand for computer simulation based evalua-tions of performance and safety of ever more sophisti-cated medical devices. The numerical backbone of the framework is the Portable, Extensible Toolkit for Scientific Computation (PETSc), which is a suite of data structures and routines for the scalable solution of scientific appli-cations. PETSc supports high performance computing and provides a wide range of solvers, graph partitioning algorithms, preconditioners and more. A framework user is only responsible for providing functions to calculate the coefficient matrices. Everything else, from disk IO, mesh partitioning and distribution, matrix assembly, the actual solving procedure, and saving the solutions back to disk is handled transparently by the framework. The framework interfaces Python which allows flexible script-ing, coupling of arbitrary solvers, and boundary conditions involving complex expressions. Visualization and data analysis are implemented using Numpy, Matplotlib and VTK. Currently we have implemented three finite element solvers using this functionality: a fluid solver, a convec-tion-reaction-diffusion solver and a mechanical solver, all being actively applied to problems involving whole body anatomical models. The framework is portable across a range of computer architectures from low-end desktop PCs (cross-platform) to cluster based hybrid supercom-puters (e.g., Cray systems).

Blood flow in a cranial aneurysm as calculated using the HPC flow solver (with Schur complement preconditioner) implemented in the framework.

Personnel: Dominik Szczerba, Nicolas Chavannes Niels Kuster; ZMT: Esra Neufeld

Project: Sim4Life

Partners: IT’IS, ZMT

Generation of High Quality Anatomical Tet-Meshes from Large, Noisy Segmen-tation Data

CAD models of the human anatomy have become more accepted and widely used by industry and regulatory bodies such as the FDA. This trend has been enabled by increasingly realistic and detailed models obtained from image data. These models generated from medical image data, seg-mented into different tissue types. A surface represen-tation is typically obtained using methods like Marching Cubes and then further processed (smoothing and sim-plification). In order to discretize the geometry and gener-ate a tetrahedral mesh for a simulation, either the surface model or the original segmented data is used. This work presents an approach to generate tet meshes directly from segmented image data using an octree technique.This technique first constructs an octree with an adaptive resolution based on the distance to the domain surface and the curvature or local shape of the domain. The verti-ces of the octree are then used to construct a tetrahedral mesh by subdividing the octants. The main novelty in our approach is the extension to multiple domains. Specific problems which must be solved for multiple domains in-clude junctions or interfaces between more than two do-mains and efficient computation of the hugely increased number of subdivision cases. We pre-compute frequent cases, while others are computed on the fly. Sharp fea-tures, often originating from multi-domain junctions, are added via a mesh line intersection approach.

An adaptive multiple-domain tetrahedral mesh generated from an image segmentation of a pig stomach.

Personnel: Bryn Lloyd, Artur Choryczewsk Dominik Szczerba, Nicolas Chavannes Niels Kuster; ZMT: Esra Neufeld

Project: Sim4Life

Partners: IT’IS, ZMT

54

Topological Morphing

Real world problems often require sophisticated tools to create realistic models for simulation and analysis. This abstract presents an implementation of a concept, which we call topological morphing. It is based on interpolating a displacement field from a regular grid of control points. The control points can be selected and moved in 3D space interactively. The interpolated deformation field is then applied to the vertices of a model, typically a surface mesh. The same solution could be applied also to tetrahe-dral and other finite element meshes.

We implemented three different methods to interpolate and extrapolate the displacement field: tri-linear, tri-cubic and B-spline (different degrees possible). While the cubic interpolation scheme works well for a whole model, the B-spline interpolation allows local deformations, which go to zero away from the control points. To enable detailed local deformations at a smaller scale than the model ele-ments (triangles, etc.), the model can be refined to a user prescribed level. For very large models consisting of large numbers of elements we provide the possibility of using a coarse version of the model for interactive modeling and visualization.

Example applications include wrapping a patch coil an-tenna around an object, modeling local deformations and variations in human models and many more.

A morphed patch coil model warped onto the arm of a hu-man body model. The red spheres represent the control points.

Personnel: Chung-Huan Li, Bryn Lloyd Dominik Szczerba, Nicolas Chavannes Niels Kuster; SPEAG: Erdem Ofli ZMT: Esra Neufeld

Project: CTI Poseidon

Partners: IT’IS, SPEAG, ZMT

Analysis of Power Frequency Magnetic Field Exposure Using Multiple High Resolution Anatomical Models

This study investigates the electric fields induced in the central nervous system of a human body when exposed to 50 Hz uniform magnetic fields. A robust and efficient numerical technique based on the quasi-static approxi-mation, finite element method and a conjugate gradient solver is employed in the computations of induced fields. The results are given in terms of the exposure-guideline-recommended spatially-averaged electric field values in-duced in various cerebral tissues due to the exposure to 50 Hz uniform magnetic fields in three orthogonal orienta-tions. The employed high resolution anatomical models include an adult male, an adult female, an obese male, a 5-year-old girl and an 8-year-old boy. By computing and comparing the induced field values, the effects of grid size variation, spatial averaging (length of 5 mm or volume of 8 cubic mm) and 99th percentile value on cerebral tis-sue dosimetry are investigated. The results suggest that the spatially-averaged peak values will become grid-in-dependent provided that sufficient grid resolution is ap-plied. Compared to the spatially-averaged peak value, the 99th percentile value may underestimate the exposure by more than a factor of two for the evaluated uniform expo-sure scenario, this is expected to be more pronounced in the case of localized exposures.

Example of the induced electric field distributions in the CNS (central nervous system) of a 5-year-old girl anatomi-cal model.The region of high induced field can be identified.

Personnel: Vick Chen, Nicolas Chavannes Niels Kuster SPEAG: Stefan Benkler

Project: CTI Poseidon

Partners: IT’IS, SPEAG,EPFL

References: Submitted to Bioelectromagnetics Journal

55

Body Effect on the GPS Antenna of a Wearable Tracking Device

In this study, the performance of a GPS antenna (invert-ed-F) design integrated in a portable tracking device is investigated when the device is placed on flat torso and dog-shaped phantoms. A prototype of the device is con-structed to validate the proposed antenna design in free space condition with both measurement and simulation. Following that, the effects of body loading to the antenna are examined through numerical simulations to achieve an optimum orientation of the device with respect to the actual operating condition (with body loading). The results from this study indicate that for a wearable GPS tracking device, the device orientation for the best free space up-per hemisphere radiation/ reception performance might not correspond to that of the body loading condition. This is in contrast with the common engineering practice which assumes that for a body-mount antenna, the antenna should be placed on a body with the side of the least radiation (observed in free space condition) facing the body. For the investigated antenna configurations, when the device is placed next to a dog phantom, the antenna orientation which is optimum in the free space condition results in a lower peak gain (by 6 dBi) compared to the peak gain achieved with optimized antenna orientation for body-mount condition. This investigation clearly indi-cates that, for a body-worn monopole type GPS antenna with small ground plane, the optimum free space antenna configuration cannot be used as a basis to derive the op-timum body-mount antenna configuration.

Top: The operation of a wearable GPS tracking device on a domestic pet. Bottom: Simulated 3D gain of the GPS an-tenna at 1575 MHz for a dog phantom.

Personnel: Chung-Huan Li IT’IS: Vick Chen, Nicolas Chavannes Niels Kuster

Project: CTI Poseidon

Partners: IT’IS, SPEAG

References: EuCAP Conference 2012

Bridging Long Distances in the FDTD Method

The Finite-Difference Time-Domain (FDTD) Method has proven to be of great value for investigating electromag-netic interactions with a human body and to assess its ex-posure. If the distance between a source and the human body is electrically large, the FDTD algorithm reaches to its limits due to the minimal number of cells per wave-length needed. This study implements a new scheme, bridging the distance between the source and the human body under the assumption that the distance is complete-ly embedded in a homogeneous media.The algorithm uses the surface equivalence principle on the source side to calculate the incident field around the human body to excite a Huygens source (see “The Power of Generalized Huygens Wave Excitation” in Re-search Review 2008), a total-field scattered-field (TFSF) FDTD source. In detail, a sensor completely enclosing the source is used to calculate the surface current, which builds the basis to calculate the field at any location in the surrounding homogeneous media (similar to Method of Moment’s final integration step).The described algorithm has been further generalized: the scattered field of the human body simulation can be re-injected into the source simulation (via another Huy-gens source) to account for the back-scattering. This it-erative algorithm (source > human body > source > hu-man body > etc.) is continued until the field values do not change up to a predefined tolerance.

The surface equivalence principle is applied in the direction (B)-(C) and (D)-(A). The TFSF simulation is processed from (A)-(B) and (C)-(D). After 9 iterations, the EM fields have converged to -100 dB.

Personnel: Nicolas Chavannes, Niels Kuster SPEAG: Stefan Benkler, Mar Minana THESS: George Tsanidis Theodoros Samaras

Project: CTI Poseidon

Partners: IT’IS, SPEAG,THESS

56

Personnel: IIS: Chung-Huan Li IT’IS: Nicolas Chavannes, Niels Kuster SPEAG: Stefan Schild

Funding: CTI Poseidon

Autoregressive Moving-Average Esti-mator for FDTD

A time-domain algorithm, like FDTD, is not efficient in simulating structures with large quality factors. A long simulation time is required to dissipate the stored energy. On the other hand, some techniques in signal process have been established for estimating frequency response of a linear system with early-time results. Among several techniques, auto-regressive moving-average (ARMA) has been successfully applied to and shown to be supe-rior for FDTD simulations.Base on the ARMA technique, a process for estimating the frequency response, named ARMA Analysis, has been implemented in SEMCAD-X. The ARMA Analysis in SEMCAD fully automatically estimates the optimal order of the transfer function of any given sensor and provides both frequency as well as time-domain signal estimations on the fly.The performance of the entire process as been studied with several benchmarks in order to devise a reliable con-vergence criterion that allows the choice between early simulation termination and accuracy. Speedups between 4 and 30 times have been achieved, while the ARMA tech-nique has improved accuracy compared to the inverse fourier transformation of the arbitrarily cut-off time-domain signals. Additionally, because the ARMA Analysis runs in parallel to the simulations, the user is able to monitor the evolution of the frequency-domain estimation, which typi-cally shows the main resonances at a very early stage.

Birdcage simulation with very high quality factor and its frequency response estimation. The speed gain due to the ARMA Analysis is around 30 times faster.

Personnel: IT’IS: Nicolas Chavannes, Niels Kuster SPEAG: Stefan Schild, Mar Miñana

Funding: CTI Poseidon

Automated Fitting of Dispersive Mate-rial Parameters

State-of-the-art finite-difference time-domain (FDTD) sim-ulations are in most cases run as broadband simulations. Because many applications deal with materials such as human tissue that exhibit frequency dependent param-eters, the broadband excitation signals need dispersive material models. Those models have a specific math-ematical form which can be written in a finite-difference formulation and applied to the FDTD kernel.Because the material parameters are available as either measured data or in some other parametrized form that is not directly convertible to the FDTD dispersive mate-rial model, a curve fitting process is necessary that tries to match the available data with the dispersive material equation used in the FDTD kernels.Because of the nonlinear shape of the dispersive equa-tions, this is not a straightforward task. A specialized search algorithm has been developed that can automati-cally determine the range of viable values for the param-eters as well as the order needed to fit the input data. The high level of automation is necessary to be able to fit dispersive curves of large numbers of media for different frequency bands.

The human body contains more than 80 different tissue types which have distinct material parameters for each frequency band of interest. Only a high level of automation can enable to perform such simulations in broadband.

57

Personnel: IT’IS: Nicolas Chavannes, Niels Kuster SPEAG: Stefan Schild, Mar Miñana

Funding: CTI Poseidon

TF/SF Excitation of 3D Gaussian Beams via Huygens Source Formula-tion

For many applications in optics the underlying assump-tion of an infinitely extended plane wave for conventional total-field/scattered-field (TF/SF) source excitations in EM simulations is unfit to deal with all aspects of certain simu-lation types. For example, the common case of a particle placed upon a (infinite) substrate breaks the requirement of free space that is around the scatterer in all directions.In such cases, it is desirable to have another type of wave for the simulation excitation. The case of a scatterer on a substrate is best investigated by illuminating it with a beam-like wave coming from the upper halfspace, while using the TF/SF idea to record the scattered part only in the region above the source plane.It has been shown that the huygens source excitation can handle those cases by injecting a gaussian beam in its focal plane. Given a substrate with enough absorption, such a beam exhibits zero field strengths away from it’s focal point. Thus, the huygens approach can handle the injection of a gaussian beam by only using on plane of the entire source box as the focal plane, i.e. the active plane of the huygens box.This yields the scattered field in the space above the ac-tive plane of the huygens box with very high accuracy.

Illumination of a nanoparticle on a substrate. The right side shows the gaussian beam in TF/SF form in free space, the left side the TF/SF result with the particle and the sub-strate.

Mechanisms of Radiofrequency Elec-tromagnetic Field Absorption in Human Hands and Fingers

The peak spatial specific absorption rate (psSAR) aver-aged over any 10 g of tissues (psSAR10g) is limited to 4 W/kg for general public exposure of the hands of a person. A standardized test method has recently been defined in IEC 62209-2 for evaluating compliance with this limit in a user’s hand holding a wireless device. The test method calls for measurements in a well-defined flat phantom. The standard document acknowledges that the use of a flat phantom lacks supporting data, and our initial simula-tions of psSAR10g in anatomical hand models found that, in some cases, the flat phantom can underestimate the SAR in the hand. This study aims to fill some of the knowl-edge gaps in this area. The absorption of electromagnetic fields in the hand is investigated over the 900 to 3700 MHz frequency range. This enables the determination of the envelope of the psSAR in the hand. It also provides a basis for deriving measurement procedures for evaluat-ing compliance of wireless devices with SAR limits in the hands. Both plane waves and dipole antennas are used to investigate the pattern of RF absorption in hand and finger tissue models for far-field and near-field exposures. The results demonstrate that absorption enhancements are found in the hand that are not present in a standard-ized flat phantom. Enhancements of several dB are ob-served, depending on the model parameters. A method to conservatively estimate the exposure in the hand based on flat phantom measurements is proposed.

Left: Hand and dipole models used in this study to exam-ine the psSAR10g in the hand compared with a defined flat phantom. Right: Shaded boxes showing the range of 5th to 95th percentile of the five fingers.

Personnel: IIS: Chung-Huan Li; IT’IS: Mark Douglas Nicolas Chavannes, Niels Kuster SPEAG: Erdem Ofli

Project: Standardization

Partners: IIS, IT’IS, SPEAG

58

Personnel: IIS: Aurelian Jaggi, Thomas Walti IT’IS: Nicolas Chavannes, Niels Kuster SPEAG: Stefan Schild, Mar Miñana

Funding: CTI Poseidon

Stability of Optical Modes in FDTD

Unlike modes of conventional metallic waveguides that are confined to a finite region of space, the modes of di-electric or plasmonic waveguides pose unique challenges to electromagnetic solvers. The accuracy of a simulation involving dielectric waveguides depends on several pa-rameters such as:• Lateral distance of absorbing boundaries• Dispersive material description• Excitation• Electric size of the simulation • Grid homogeneity• Grid resolutionThis study aimed at providing the information necessary to develop novel excitation scheme, e.g. using a huygens box approach, for dielectric and plasmonic waveguides.Using analytical results from 2D mode solvers, the stabil-ity of a propagating mode was investigated as well as the distance necessary between source and probe to ensure that spurious modes have vanished.

E-Field pattern (real modulus) of a dielectric slab wave-guide coupling into a ring resonator. To assess artefacts from badly excited or spurious modes, the modal propaga-tion behavior needs to be understood in detail.

Deep Brain Ablation: Optimized Spatial Control Using Novel RF Catheter Array

Ablative stereotactic neurosurgery has a long history. By selective lesions in the deep structures of the brain disabling symptoms like tremor, rigidity, or dystonia can be effectively treated. Safety issues and limitations of the lesioning approach were primarily driving the move from lesional to non-lesional strategies (deep brain stimulation (DBS)). However, lesional therapies are still performed in many countries where non-lesional therapies are not af-fordable. To overcome the existing issues with RF ablation in neu-rosurgery the goal of this project is to investigate the fea-sibility of a new approach we propose to ‘enhance the spatial shaping’ of RF ablation. The means to achieve the enhanced spatial shaping is a multi-channel RF abla-tion catheter allowing steering of the focus at the ablation area. To develop and analyze a multi-channel catheter, we have extended our numerical tools to include tissue damage models as well as the feedback of tissue damage (change of thermal and dielectric properties) on the EM and ther-mal simulations by weak coupling. A numerical parameter study has been conducted to optimize the catheter de-sign with respect to frequency, phased-steering, number of electrodes, placement etc.

Top: Spatial shaping capability of a catheter array design in radial direction (top) and axial direction (bottom). Steering in radial direction is achieved by modification of the relative phases and in axial direction by changing the frequency.

Personnel: Sven Kühn, Theodoros Samaras Esra Neufeld, Niels Kuster

Funding: Hans Eggenberger Foundation

Partners: IT’IS, Aristotle University of Thessaloniki

59

Novel Time-Domain E&H-Field Probes

There is an increasing demand for miniature optically iso-lated radio frequency (RF) field probes for time domain measurements for various applications. Due to increasingly dense packaging requirements and multiple wireless communication systems within mobile devices, manufacturers are faced with more and more problems related to electromagnetic compatibility (EMC) and interference at a system and chip level. Today simu-lation techniques are unable to reliably predict these ef-fects. Also existing experimental tools lack a sufficiently small spatial resolution combined with a high sensitivity and electrical isolation for near-field EMC measurements. Another important application of those probes is in the characterization of all sorts of RF transmitters, in par-ticular MIMO systems and MRI birdcages. For near-field measurements, optical isolation and the ability to mea-sure the full complex wave-form is of great desire.Within this project we have extended our active optical RF sensor platform with new miniaturized sensors for measurements of E- & H-Fields. Due to the optimized flat frequency response of these probes over a bandwidth of more than 6GHz they are ideal for measurements in the time and frequency domains.Prototype versions of our novel sensors are already be-ing used for large-scale chip level EMC qualification and characterization of MRI birdcage multi-transmit coils by our industrial and research partners .

Microscopic pictures of the miniaturized active optical time domain sensor heads (left: E-field, right: H-field). The sen-sor heads are optically isolated with respect to energy sup-ply and and RF signal transfer.

Personnel: Sven Kühn, Martin Wild, Martin Lanz Niels Kuster

Funding: Hans Eggenberger Foundation

Partners: IT’IS, SPEAG

ELF Exposure from GSM and UMTS Mobile Phones

Over the past decade, the majority of mobile phone expo-sure assessment studies focused on the exposure to the strong RF EMF generated by the phone’s antenna oper-ating at frequencies between 400 MHz and 3 GHz. How-ever, LF EMF, i.e. lower than 20 kHz, are also generated, e.g., by the supply currents or the audio speaker. There are considerably fewer studies dealing with the charac-terization of exposure to these fields from mobile phones.The aim of this study is to evaluate the maximum and the average usage-dependent induced electric fields and currents due to the exposure to LF magnetic fields from mobile phones operated at the human head. The objec-tive is to establish a scientific basis to compare the overall LF and RF exposure of different mobile communication technologies (GSM and UMTS). B-field measurements were performed on each side of 10 mobile phones of various types (lip phone, slide phone, bar phone, smart phone) and manufacturers (Nokia, Sony Ericsson, Motor-ola, HTC, Apple, Samsung, LG). With the custom imple-mentation in the DASY 52 NEO scanner using the Python scripting interface, the time-domain signal was evaluated for each measurement point, giving maximum flexibility for the data analysis, both in terms of B and dB/dt.The low-frequency B-field distribution generated in close vicinity of the mobile phones was modeled, as a first ap-proximation, by a current loop. Further investigation is needed to find the optimal representation of the experi-mental results, which will then be used to assess the ex-posure at the head of anatomical phantoms.

Left: DASY52 NEO scanner. Right: LF B-field probe at a distance of 1 mm from the mobile phone surface (LG Opti-num 3D P920).

Personnel: Marie-Christine Gosselin, Sven Kühn Niels Kuster

Funding: FSM, Hans Eggenberger Foundation

Partners: IT’IS

60

Exposure Assessment of Wireless Power Charging Systems

Wireless power charging systems (WPCS) are becoming ubiquitous with applications in charging portable electron-ics, medical implants, near field communications, etc. WPCS contain transmitter and receiver coils coupled by magnetic induction for transferring power to an external load. Recent advances in this technology have improved the coupling power efficiency by introducing resonances in both transmitter and receiver coils in order to operate WPCS at larger separation distances. In the close proxim-ity of most WPCS, reference levels for incident magnetic fields [ICNIRP, IEEE C95.1] are usually exceeded requir-ing the assessment of basic restrictions. Basic restrictions in the safety standards are provided in terms of induced current density or induced electric field for frequencies below 10 MHz to prevent nerve stimulation and in terms of specific absorption rate between 100 kHz and 10 GHz to prevent excessive localized tissue heating.Due to the lack of standardized procedures for testing compliance of WPCS (operating below 10 MHz) with electromagnetic safety limits, in this study, we have de-veloped scientifically sound procedures using a combi-nation of numerical simulations on anatomical models and experimental validation. Since the exposure levels are heavily dependent on the location and orientation of anatomical models relative to WPCS, a new methodology was developed to determine compliance distance using homogeneous body and limb phantoms having dielectric properties similar to human tissues at the intended oper-ating frequency. Subsequently, compliance distance esti-mation can be used to demonstrate safety if the humans under normal usage conditions stay clear by this distance from the WPCS for the intended application.

10g peak spatial SAR distribution in a 2-D slice passing through the peak location for an anatomical model in a sit-ting posture when the WPCS is in the center of the table..

Personnel: Jagadish Nadakuduti, Mark Douglas Andreas Christ, Niels Kuster

Funding: Qualcomm (USA)

Partners: IT’IS, Qualcomm (USA)

Exposure Evaluation of Therapeutic Magnetic Field Mats

Magnetic therapy is a type of alternative medicine in which the body is exposed to static or time-varying mag-netic fields. Several products exist, such as whole-body therapeutic magnetic mats (TMMs) or smaller cushions, which are placed on or near the body. The peak mag-netic field strength can vary significantly, depending on the product and application. For products emitting time-varying fields, the frequencies can be quite different from one product to another, ranging from a few Hz to several kHz. Some products produce pulsed magnetic fields, so the frequency spectrum can be complex. The evalua-tion of TMMs to ensure compliance with ICNIRP limits for electromagnetic safety is inadequate. Additionally, a recently-published study found that the incident fields sig-nificantly exceed the ICNIRP reference levels for some TMMs. Therefore, a thorough investigation of the induced fields in people is needed.Three TMMs available on the Swiss market have been evaluated. Validation of the numerical simulations against measurements was conducted. The TMMs were modeled with high-resolution anatomical models of two adults, a child and a pregnant woman in three gestational phases. Several positions of the body lying on the mat were in-vestigated. The simulated results show that the induced fields in the body can be significantly above the ICNIRP basic restrictions for some TMMs under some conditions. The results also highlight significant problems with the implementation of ICNIRP 2010 guidelines. Further work is ongoing to propose solutions to these problems.

Induced electric field distribution inside an anatomical male model lying on a therapeutic magnetic mat at 50 Hz.

Personnel: Valerio De Santis, Mark Douglas Jagadish Nadakuduti, Stefan Benkler Niels Kuster

Funding: BAG

Partners: IT’IS

61

Novel Mini-Reverberation Chamber Ex-posure System for Mice at 2.45 GHz

The European Project SEAWIND investigates the dramat-ically increased public exposure to electromagnetic fields in the radio frequency spectrum due to the exponential growth of wireless network device usage in homes, of-fices and schools. The project is developing biological models and experimental procedures to sensitively and quantitatively measure transient and persistent molecular and cellular responses to electromagnetic (EMF) expo-sures. The IT’IS Foundation has developed the system and equipment used for the in-vivo exposure of up to six mice per exposure group for the ex vivo analyses of cells with genotoxicity and genomic instability as endpoints. The exposure environment is a small reverberation cham-ber allowing free roaming mice and hence extended daily exposure periods. Both numerical dosimetry using a male mouse model with weight of 27.8 g with the mesh size of 0.2 mm and experi-mental dosimetry have been performed to determine the SAR sensitivity. Further dosimetry using posable models allowed the variation in SAR with posture changes to be evaluated and hence the additional uncertainty. The twin stirrer reverberation chamber design provides good ex-posure homogeneity for free roaming animals and also incorporates an RF safe automatic watering system. The performance across all the criteria of the reverberation chamber for animal exposure is excellent. The perfor-mance of this exposure environment is comparable to the best exposure setups using constrained animals. The system can provide whole body SARs up to 10 W/kg with signals of 15 dB peak to average ratio, any complex signal type is possible with base bandwidths up to 25 MHz with the signals are dynamically changing to mimic real com-munications scenarios.

Left: The completed reverberation chamber and its excita-tion and control system. Right: SAR distribution in a mouse.

Personnel: Yijian Gong, Myles Capstick, Niels Kuster

Funding: EU (FP7/2007-2013), SEAWIND Project No. 244149

Partners: IT’IS, Fraunhofer ITEM

Exposure System to Assess the Po-tential Toxicity and Carcinigenicity of Mobile Phone Radiation

National Institute of Environmental Health Sciences (NIEHS) has funded a study within the National Toxicol-ogy Program (NTP) to identify potential toxicity and car-cinogenicity of cell phone radio frequency (RF) radiation. The study will chronically expose rodents (rats and mice) over a full life cycle to 2nd and 3rd generation mobile te-lephony standard RF radiation, namely Global System for Mobile (GSM) and IS95 a Code-Division Multiple Access (CDMA) standard at frequencies of 900 and 1900 MHz. The exposure environment is based on a reverberation chamber so that the animals are free running and have the same exposure whatever the posture or orientation. The design encompasses both the electrical and animal housing issues including water provision, ventilation and lighting. Key to the electrical design was the ability to achieve the required shielding, fully welded construction, and excellent field uniformity with two mode stirrers. One of the main engineering challenges was the development of a water system for the rodents that could be installed in the chambers and provide a safe environment with no excess exposure. Key to any study is the accurate and fully characterised analysis of the RF dose to the rodents including a full un-certainty analysis. For this, a number of anatomical rat and mouse models with high resolution and flexible pos-tures have been developed, to allow the life time dose and variation to be assessed along with the variation introduced by different postures. These results for the whole body and organ specific SAR along with the uncer-tainty predictions provide an accurate reference for the further long term biological studies.

Sprague-Dawley Female Rat Model and SAR distribution.

Personnel: Yijian Gong, Myles Capstick, Niels Kuster

Funding: NIEHS, NIH, USA

Partners: IT’IS, NIEHS, IITRI, NIST

62

Brain Exposure Evaluation Using Stan-dard SAR Test Systems

The maximum spatial peak specific absorption rate (SAR) of each commercial mobile phone is determined from standardized compliance testing and is publicly available. However, this maximum value does not give any informa-tion about brain-region specific exposure, which is a key parameter for epidemiologic studies.In a previous section of this study, we have used a ma-trix of generic sources and numerically evaluated factors to correlate the exposure of some regions of the homo-geneous SAM to the exposure of brain regions of four anatomical models (Gosselin et al., Bioelectromagnet-ics, Sept. 2011). The aim of this part of the project was to implement the previously developed approach into the dosimetric assessment system DASY52 (SPEAG, Switzerland). The implementation allows the estimation of region specific SAR in the heads of the Virtual Family models from full hemispherical volume measurements in the SAM head. Advanced extrapolation algorithms were also implemented to allow for an estimation of the brain-region specific SAR based on standard compliance test measurement procedures: a 2D scan at the internal sur-face of the SAM head and a small 3D volume scan at the peak locations of the 2D scan. Additional evaluation allowed the assessment of the uncertainties associated to scans of limited volumes during compliance tests as well as the uncertainties associated with the determina-tion of the SAR on the SAM head from exposure to mobile phone rather than on various realistic heads.For the first time, this novel implementation allows the us-ers of mobile phones as well as epidemiologists to com-pare different types of mobile phones with respect to their exposure of the various regions of the human head.

TWIN-SAM measurement phantom (blue) with SAM phan-tom (yellow) and surface scan.

Personnel: Marie-Christine Gosselin, Sven Kühn Pedro Crespo-Valero, Niels Kuster

Funding: SNF NFP57

Partners: IT’IS, SPEAG

Worst-Case SAR Assessment from Multi-Transmit MRI Coils

Safety standards regulating the exposure to radio-fre-quency (RF) electromagnetic fields (EMF) during MRI scans are mainly based on work using conventional ar-ray configurations. However, multitransmit coils are being increasingly employed, particularly in the context of high field MRI. They can lead to an increase in whole body and local specific absorption rate (SAR) compared to conventional volume transmitting coils excited in circular polarization for the same total input power. The aim of this project is to assess the potential increase of the specific absorption rate (SAR) from multitransmit coils.A (generalized) eigenvalue approach has been imple-mented to investigate the enhancement of the peak spa-tial SAR (psSAR), the whole-body SAR (wbSAR), and the ratio of psSAR over wbSAR from numerical simulations. Three anatomical models (one average male, one aver-age female, one obese male) and a 16-channels array have been used for the numerical assessment with the simulation platform SEMCAD X.Current scanning procedures are limiting the input power of the coil such that the estimated wbSAR of the patient does not exceed 4W/kg (first level control). With this in-put power, the maximum psSAR in multitransmit coil can reach 600 W/kg, i.e. the exposure by multi-transmit coils must be rigidly monitored to avoid internal burns.

For each location, worst-case increase of the local averaged SAR from the multiphase coil compared to the maximum of right and left circular polarization. Left: average male. Right: obese male.

Personnel: Marie-Christine Gosselin, Esra Neufeld Manuel Murbach, Niels Kuster

Funding: KTI MRI+

Partners: IT’IS, SPEAG, Siemens, GE, Philips

63

Necessity for Improved SAR Averaging Volume by Regulatory Committees

The exposure of children to mobile phones has been a concern for years, but so far the conclusions with respect to compliance with safety standards are based only on simulations. Regulators have requested that these con-clusions be supported by experimental evidence.The objectives of this study are 1) to test if the hypoth-esis that the specific anthropomorphic mannequin (SAM) used in standardized compliance testing is also conserva- tive for homogeneous child heads and 2) to validate the numerical prediction of the peak spatial SAR (psSAR) in child heads. To achieve these, head phantoms of 3- and 8-year-old children were developed and manufactured. The results confirm that SAM is also conservative for chil-dren, and that the agreement between numerical and ex-perimental values are within the combined uncertainty of 0.9 dB provided that the actual peak spatial SAR (psSAR) is determined. However, the results also demonstrated that the currently suggested numerical SAR averaging procedures may underestimate the actual psSAR by more than 1.3 dB and that the currently defined limits in terms of the average of a cubical shape mass are imprac-tical for non-ambiguous evaluations, i.e., for achieving inter-laboratory repeatability.

Local SAR distribution in the 8-year-old child in the plane containing the mouth and ear canal points as well as the center of the phone. Exposure to the generic phone at 900 MHz (top) and 1800MHz (bottom) in the touch position.

Personnel: Marie-Christine Gosselin, Sven Kühn Niels Kuster

Funding: SNF NFP57 (CH), ZonMW (NL)

Partners: IT’IS

Thermal Damage Tissue Models Ana-lyzed for Different Whole-Body SAR and Scan Durations for MR Body Coils

Usage of magnetic resonance imaging (MRI) is rapidly in-creasing due to its excellent soft-tissue contrast, superior diagnostic capabilities, and the absence of ionizing radia-tion. However, adverse health effects from whole-body and local tissue heating by the absorbed radiofrequency (RF) energy must be carefully managed.This study investigates the peak temperature dose as a function of exposure level and local thermoregulation ca-pabilities for anatomically correct human models in differ-ent landmark positions. The electromagnetic simulations are validated by experimental skin temperature measure-ments in human. A tissue damage model is employed, based on cumulative equivalent minutes (CEM43).In the First Level Controlled Operating Mode (4 W/kg whole-body averaged specific absorption rate, wbSAR), peak local temperatures of up to 43°C were computed for a thermoregulated perfusion model (maximum in pelvis imaging position). Experimental validation was performed in upper sternum imaging position, where the skin tem-peratures were estimated to reach up to 41°C. Measure-ments showed 39.7°C near the estimated hotspot.The high estimated and observed temperature rise indi-cates the necessity of considering thermal dose models that take into account exposure time and temperature.Special considerations might be necessary for patients with impaired or dysfunctional thermoregulation abilities (e.g. elderly and diabetic patients).

Left: Numerical prediction of the skin temperature distribu-tion with the anatomical model ‘Duke’. Right: Experimental temperature measurement near the hotspot location (T1 thermally isolated, T2 non-isolated) and comparison.

Personnel: Manuel Murbach, Esra Neufeld Michael Oberle, Sven Kühn, Niels Kuster

Funding: MRI+ EUREKA Project, KTI Zurich MedTech

Partners: IT’IS, IBT-ETHZ, Philips, Siemens, Eras-mus Medical Center, INTEC, Uni Athens, Charité Berlin, FDA, SPEAG

64

Education Program

Student Semester and Master Projects

Coordinator:

Norbert Felber

Teaching microelectronics is one of the core activities of the Integrated Systems Laboratory. Shortly after the laboratory was founded in 1986, it started to offer projects in IC design to master students (during the 7th semester of the studies; in the following, the term “student” is used for students in the Master Course – 7th to 10th semester). Probably as the first European university, ETH Zürich financed the fabrication of student chips. This gave students the opportunity to carry out a VLSI design project from the specification to the test of their own silicon chips. Still today, many of the semester projects at IIS are in practical chip design, and many Master projects include the realization of integrated circuits or the development of components as contribution to research ASICs. Since the first VLSI course offered by IIS, around 600 engineering students have had the chance of designing real silicon.

Education in MicroelectronicsDuring the first four semesters, students are motivated towards microelectronics by several PPS (Practicals, Projects, Semi-nars) (http://www.iis.ee.ethz.ch/stud_area/pps.en.html). In semester 5 and 6, practical training (Fachpraktika, http://www.iis.ee.ethz.ch/stud_area/fachpraktika.en.html) offered by IIS aim at the same goal.The three VLSI lectures in the 6th to the 8th semester, described on page 83ff, form the main block in microelectronics education by the Integrated Systems Laboratory. Students who want to further deep-en their experience in microelectronics often choose a Master thesis in the framework of a research project of IIS as culmination of their education. Some then stay in these research fields for a PhD thesis.

ASIC Design ProjectsStudents who have decided to realize an integrated circuit will learn a professional design flow with the same tools as used in research and by our main industry partners. They realize an often challenging and complex project. Despite the hard work with many traps and complications, almost all chips finally work as intended.During the 14 weeks of a semester project, the design students put ‘official’ 50 % of their work load into the realization of the chip, often considerably more. First-time-right digital ICs of industrial complex-ity level often result: This is only possible due to the sound VLSI education and an excellent support for design and test offered by the PhD students of our Laboratory and the Microelectronics Design Center of the Department of Information Technology and Electrical Engineering (see page 86ff and http://dz.ee.ethz.ch). The harvest from 2010 is shown on the next page.

Other Student Projects at IISNext to digital ASIC design – mostly for signal-processing tasks –, students are offered projects in HW and SW system design, as well as in the fields of all other research groups of IIS and IT’IS. This regards analog and mixed-signal IC design, TCAD tool development and applications, physical characterization of semiconduc-tor devices, optoelectronics device development and simulation, as well as tool, measurement and experiment contributions in bio-electromagnetics. The graphics above gives an overview over the number of student projects at IIS (blue bars) during the last ten years with emphasis to VLSI student projects (yellow bars).

Organization of this ChapterOn the following pages, student projects are reported in the order mentioned in the paragraph above. A special case are some student projects which are direct and especially successful contributions to research projects. This work is included in the corresponding research sections on pages 22 (right), 23 (right), 24, and 26.As a last remark, it is worth to mention the student papers of some of the proj-ects that have been accepted in international conferences and presented by the students as their first contribution to the research community. In the header of the project descriptions, references to the student’s publications are given. The figure to the left illustrates the development of the number of papers with major student contributions.

Student projects at IIS during the last ten years. The yellow bars indicate the number of students which did a digital VLSI project during the indicated year. The blue bars include also the semester and master projects in the other research groups of IIS.

Conference contributions by students from semester and Master projects at IIS.

67

Acoustic Radar Demonstrator for Com-pressed Sensing Algorithms

Scenes observed by radar are often only sparsely popu-lated. Although many measurements must be taken to achieve a sufficient resolution, at the end, only the co-ordinates of a few detected objects are of interest. Com-pressed sensing (CS) offers a class of signal processing algorithms which can exploit sparsity to reduce measure-ments. In order to test new signal processing algorithms, we designed an acoustic radar platform. This setup al-lows to test similar signal processing algorithms as used in radar systems based on electromagnetic waves, but at far lower hardware complexity. Acoustic radars are also known as sonars.The developed acoustic system involves a printed circuit board (PCB) and an FPGA board. A loudspeaker, con-nected to the PCB, transmits probing sequences. 16 small microphones, placed in a linear array on the PCB, record the reflections of the transmitted sequence. This allows for two dimensional localization. The received sig-nals are sampled and stored on the FPGA.The setup allows either to send the stored signals to a PC for further processing, or to perform real-time processing on the FPGA. The implemented real-time processing cor-relates the recorded signals with expected responses in order to localize reflectors in front of the microphone ar-ray. A background subtraction is performed before corre-lation. The result is shown on a display connected to the FPGA. The flexible setup enables tests of already pub-lished and new signal processing approaches.

PCB with a line array of 16 microphones and the loudspeak-er. The PCB is connected to the FPGA board for real-time signal processing.

Personnel: Michael Bieri, David Bellasi, Marc Liechti, Matthias Mock; Assistants: Graeme Pope, Patrick Mächler

Thesis: Semester & Group Project

Partners: IKT-ETHZ

FFT Optimization for Compressed Sensing

Fast Fourier transforms (FFT) are at the heart of many compressed sensing (CS) algorithms. CS allows to re-duce the number of measurements when signals can be sparsely represented. In many CS applications, the mea-surements are performed in time domain and the signal has a sparse representation in frequency domain, or vice versa. When the measurements are strongly reduced, or when only a limited number of frequency components are of interest, FFT pruning can reduce the number of opera-tions. To perform an FFT, many operations of the same structure (called butterflies) need to be executed.Unfortunately, there is no easy way to reduce the FFT complexity when the neglected components are not sys-tematically distributed. The amount of butterfly operations that can be pruned depends on the FFT structure, the number, and the distribution of the important coefficients. Thus, software was written, which determines which but-terfly operations can be skipped for a given situation. It turned out that an input or output sparsity below 10% is required to obtain significant savings for a random input/output distribution.The developed software not only analyzes the FFT struc-ture, but also generates a program that executes the op-timized FFT in dedicated hardware. An efficient split-radix FFT was designed for a Xilinx Spartan 3 FPGA, which executes the generated program and performs only those butterfly operations which are truly necessary.

Partial signal flow graph of a 256-point split-radix FFT with pruned in- and outputs. Each cross represents a butterfly operation.

Personnel: Michael Leibl; Assistant: Patrick Mächler

Thesis: Semester Project

68

Disparity Estimation with Cost Filter Aggregation

Depth estimation or disparity estimation from stereo-scopic video streams has been extensively treated in the research community and also in industry. Both, efficient algorithms and real-time capable systems have been pre-sented in recent years. However, the gap between fast execution with low estimation quality and slow execution with good estimation quality is still considered an open research challenge. Good quality is currently obtained for algorithms that employ costly global optimization tech-niques, whereas real-time variants employ poorer-per-forming local or semi-global methods.Recently, a new approach to local depth estimation has tried to close the gap. The key idea behind these new types of algorithms is to apply local filtering instead of global optimization by imposing data constraints on the matching costs. Thus, in a first step we calculate match-ing costs as in traditional local-window methods, and in a second step we filter the 3D costs with a data-dependent filter (a guided filter in our case). Finally, standard winner-take-all selection is performed to find the minimal cost and hence the disparity. The disparity estimation algorithm with cost filtering has been implemented in 180 nm CMOS. The main challenge was the high memory requirement of the cost filter.

Chip layout of the disparity estimation design in 180 nm CMOS.

Personnel: Andreas Kettner, Joël Smely; Assistants: Pierre Greisen, Frank K. Gürkaynak

Thesis: Semester Project

Line Detection using the Hough-Trans-form

Line detection in images is useful for various applications in image processing and computer vision. A popular line detection algorithm is based on the Hough transform. The Hough transform uses a parametrized representation of lines, that allows to replace the line search in the original image with a maximum search in the Hough space. That is, coordinates from the input image are transformed into sinusoidal curves in Hough space that intersect if several points lie on the same line.The line detection ASIC designed in this semester thesis applies the Hough transform to extract lines from video sequences. In a first step, a binary edge map is extracted that provides line candidate points. Next, each candidate point is transformed into Hough space with a CORDIC for the sinusoidal terms. The obtained Hough points are accumulated in a large 2D array (SRAM macro) to pro-duce the Hough space representation of the input image. Finally, the maximal accumulation scores above a certain threshold represent the detected lines.The ASIC has been sent for fabrication in a 180 nm CMOS process and is able to process image sequences at reso-lutions of up to 1024 x 1024 at 60 frames per second.

Background: example of Hough-transform based line detec-tion: The red lines are the results of the line detection algo-rithm. Left corner: Chip layout.

Personnel: Reto Odermatt, Thomas Sutter; Assistants: Pierre Greisen, Frank K. Gürkaynak

Thesis: Semester Project

69

HD Video Processing Platform for Sa-liency Estimation

Understanding the content of an image or a video is a key challenge in computer vision and related applications. As an example, tools that provide information from scene content are saliency estimation algorithms. A salient ob-ject is a visually important object, i.e., an object that some-how pops out of its surroundings. In recent years, several approaches to automated saliency estimation have been proposed. Unfortunately, saliency is inherently based on human perception, which makes it difficult to objectively rate the estimation quality of a specific algorithm.In this project, a platform is set up for estimating and dis-playing visual saliency in real-time. In a first step, existing saliency estimation algorithms were evaluated and sub-jectively compared to find the best suited candidate for implementation. The Quaternion Fourier Transform (QFT) algorithm, which is based on 2-dimensional Fourier trans-forms, was found to provide good results. Next, a video processing platform was designed that streams video from a high definition camera to an FPGA board and displays the output via DVI on a screen. A high-performance memory controller and an arbiter were implemented that enable efficient buffering of HD images for the I/O handling and for the saliency estimation stage. In particular, the 2D Fourier transform of HD images re-quires matrix transposition operations for matrices with around 1000-by-1000 entries, which poses a significant challenge to the memory bandwidth.

Comparison of different algorithms for estimating visual im-portance, called saliency, in images. High intensity indicates high visual saliency.

Personnel: Fabian Gut; Assistants: Pierre Greisen, Frank K. Gürkaynak

Thesis: Master Thesis

Partners: Disney

FPGA-based Image Feature Detection

Image feature detection has proven to be a useful tool in various image processing and computer vision applica-tions. An image feature point is an abstract concept and denotes a point that is discriminative within its neighbor-hood. Various types of features exist: simple ones, such as edges, corners, intensity gradients, or more elaborate ones that require a collection of image processing filters and tools to find the key points. Application scenarios of features are large and include tracking, image registra-tion, or stereo mapping, to name a few.In this work, we looked at the particular class of multi-scale feature detection algorithms, which are very robust against geometric and other changes but, also computa-tionally intensive. Our target application is disparity esti-mation, i.e., we match the same features within a stereo image pair to get sparse disparity maps.In a first step, we evaluated the classical SIFT and SURF multi-scale feature detection algorithms (and some re-lated variations) with emphasis on hardware efficiency. In a next step, an efficient FPGA architecture of the SURF algorithm was realized. It supports image resolutions of up to 720p at 25 frames per second and searches for fea-tures on 8 scales. The architecture is scalable to higher resolutions and frame-rates.

Example of detected SURF features. The size of the circles indicates the scale on which the feature point has been found.

Personnel: Rafet Ogul Türkel; Assistants: Pierre Greisen, Christoph Keller, Simon Heinzle

Thesis: Master Thesis

Partners: Disney

70

Iterative Detection and Decoding with MMSE-PIC and LDPC

Iterative detection and decoding is the holy grail of mul-tiple-input multiple-output (MIMO) communications since such receivers enable operation very close to the theo-retical performance limit. The basic idea of this type of receiver is to carry out MIMO detection and channel de-coding in an iterative fashion, while exchanging reliability information between the two components. Unfortunately, the corresponding process is associated with consider-able complexity which is much higher than even that of an advanced conventional receiver. Very recently, hardware- efficient algorithms and architectures have been proposed to implement the individual iterative receiver components (especially the complex soft-in soft-out MIMO detector). However, so far, no complete iterative receiver has been described, though the combination of the individual com-ponents is not at all trivial. In this project, we have de-veloped a complete iterative MIMO receiver, comprising an MMSE-PIC MIMO detector and an LDPC decoder for quasi-cyclic LDPC codes. Both components were pre-viously developed at IIS and have been modified and adapted during this project. The main contribution of this work are the optimization of various system parameters of the iterative receiver, the development of a new, low-latency decoding schedule, and the design of the overall iterative receiver architecture. With the new schedule, the iterative receiver design is suitable, for example, for the popular IEEE 802.11n WLAN standard, or can easily be adapted to also support other standards such as WiMAX.

Iterative receiver: Block diagram with chip photos of previ-ous stand-alone components. Performance results: Trade-off between latency and SNR for 1% PER for a hardware configuration with one LDPC and one MMSE-PIC unit.

Personnel: Nicholas Preyss; Assistants: Christoph Studer, Andreas Burg

Thesis: Master Thesis

Partners: TCL-EPFL

Truecrypt on a Chip - Transparent Hard-disk Encryption

Goal of this project was to develop a fully transparent harddisk encryption system. The idea was to place a device in-between the SATA controller and the harddisk. This device then should encrypt the payload of the SATA stream while leaving the SATA commands unencrypted.In the first step, a complete analysis of the SATA protocol was done. During this process, several problems were encountered, mostly timing issues. Possible solutions were developed.In the second step, the hardware platform, a Xilinx ML605 board with a Virtex 6 FPGA, was set up for the task and first tests were conducted. This FPGA demo board pro-vides a variety of connectivity interfaces, such as SATA, Ethernet, SFP.In the final step, an architecture for the decryption and en-cryption had to be found. XTS, an XEX(xor-encrypt-xor)-based tweaked-codebook mode with ciphertext stealing, was chosen as mode of operation for the AES. The main reason for this choice was that this mode is used in many available encryption software tools, such as Truecrypt or DiskCryptor, and that compatibility to these tools can be provided. Then, an AES architecture had to be real-ized which is capable to de- and encrypt a data stream at 1.5 Gb/s for SATA 1.0 up to 6 Gbps for SATA 3.0.

Scheme of a fully transparent encryption. Both, the hard disk controller and the hard disk drive don’t recognize the encryption hardware in the SATA link.

Personnel: Michael Hotz; Assistants: Christoph Keller, Frank Gürkaynak

Thesis: Master Thesis

71

High-Performance SOVA Decoder Ar-chitecture Optimized for 3GPP-HSPA

The current 3G mobile communication systems rely on turbo codes to enable reliable communication at high data rates. In order to adapt to varying transmission environ-ments, many transmission modes in terms of code-block size and code rate are usually defined, creating the need for flexible decoder hardware solutions. At the same time, the fact that these circuits are operated on mobile bat-tery-powered devices asks for area- and energy-efficient implementations.The turbo decoder is usually one of the most critical parts of a 3G baseband chip in terms of silicon area and power consumption. Several decoding algorithm variants exist today, but it is not obvious how these algorithmic variants compare when area, power consumption, and error-cor-rection performance is taken into account.In this semester project, the use of the soft-output Viterbi algorithm (SOVA) as component decoder for turbo decod-ing was to be evaluated. As opposed to the convention-ally employed max-log-MAP algorithm, the SOVA implies reduced implementation complexity but also worse error-correction performance. In the first part of the project, al-gorithmic optimizations were performed, closing this gap in error-correction performance to less than 0.1 dB. In the second part, an efficient SOVA architecture was devised. Lastly, two decoder cores were implemented in 180 nm CMOS, one being optimized for the throughput require-ments of 3GPP-HSPA (180 MHz) and the other being tuned for maximum throughput (500 MHz).

Layout view of the SOVA decoder chip. Highlighted are the two SOVA decoder cores optimized for 180 MHz and 500 MHz, respectively, as well as the I/O Interface control-ling the two cores.

Personnel: Adrian Schoch, David Sommer; Assistants: Christoph Roth, Christian Benkeser

Thesis: Semester Project

Partners: Hasler, ACP

Reduced-State Sequence Estimation for Evolved EDGE

Evolved EDGE (E-EDGE) is proposed as the next exten-sion of the GSM/EDGE standard and it is supposed to further close the capacity gap to 3G networks by increas-ing the spectral efficiency of existing 2G networks. A key feature is the introduction of the higher-order modulation modes 16-QAM and 32-QAM, allowing to transmit 4 and 5 bits per symbol. Unfortunately, wireless transmission over a typical GSM channel suffers from severe inter-symbol interference (ISI) and detecting the correct symbol be-comes very challenging as the number of possible candi-dates increases to 16/32.Channel equalization and detection in ISI affected chan-nels is typically done by traversing a trellis and searching the most likely transmitted sequence of symbols. How-ever, the number of trellis states explodes with increasing symbol alphabet. Making early decisions based on deci-sion feedback equalization helps to reduce the number of states to an acceptable level, resulting in a so-called reduced-state sequence estimation (RSSE).In this semester project, a RSSE that requires only 16 states was implemented as an ASIC in 180 nm CMOS technology. It supports all four modulation types required by E-EDGE. The architecture minimizes the number of multiplications by storing intermediate results of the branch-metric computation. Furthermore, the number of instantiated multipliers is minimized by using the same hardware for complex-valued convolution and norm com-putation.

Left: Layout of the 16-state RSSE ASIC implementation.Right: Diagram showing the connections of the trellis for the case of 32-QAM.

Personnel: Abiraam Varathan, Hirad Rezaeian; Assistants: Stefan Zwicky, Christian Benkeser

Thesis: Semester Project

Partners: KTI, ACP

72

Efficient Channel Shortening for High-er-Order Modulation

Trellis-based channel equalization for GSM/EDGE with 8 PSK modulation requires pre-filtering to achieve high performance at acceptable complexity. Since correspond-ing implementation complexity grows with the modulation order, the introduction of 16/32 QAM in the latest 2G stan-dard Evolved EDGE requires new solutions to preserve the low-cost attribute of EDGE-enabled devices.In this master thesis, a novel efficient pre-filter algorithm based on homomorphic filtering has been developed. Compared to other existing techniques the new approach achieves comparable performance at lower complexity. In order to proof the suitability of the algorithm for hardware integration, a corresponding VLSI architecture has been realized. The heart of the implementation is the butter-fly processing (BPU) unit, that sequentially computes the (Inverse) Fast Fourier Transform as required for the new algorithm. Excessive resource sharing allows the silicon area of the design to be minimized. The corresponding hardware implementation in 130 nm CMOS achieves a 5 x improvement of area-timing (AT-)product when compared to prior art.

Top: Block diagram of implemented pre-filter coefficients computation architecture comprising butterfly processing unit (BPU), logarithm computation (LOG) and CORDIC for polar-cartesian transformations.

Personnel: Johannes Widmer; Assistants: Christian Benkeser, Stefan Zwicky

Thesis: Semester Project

Partners: KTI, ACP

References: ISCAS 2012

Time division synchronous code division multiple access (TD-SCDMA) is a 3G standard currently emerging from China. It employs a combination of TDMA, FDMA and CDMA, where up to 16 users are simultaneously active during the same time slot. Its TDD nature allows it to han-dle asymmetric traffic effectively, which is a key advan-tage since the data traffic becomes more and more asym-metric as mobile internet applications gain popularity.One challenging part of any TD-SCDMA receiver is the equalizer. The fading channels introduce severe inter-symbol interference, which has to be removed prior to channel decoding. High performance channel equaliza-tion is therefore crucial for a successful receiver.Since the base station can assign multiple CDMA-codes to each specific user in order to achieve a flexible through-put, interference cancellation schemes are promising. These iterative algorithms first decode the most reliable codes and use this information to enhance the estimation of the remaining codes.The goal of this thesis was to investigate, evaluate, simu-late and compare equalizer algorithms for the TD-SCDMA downlink and to implement the most promising candidate. In a first step a TD-SCDMA compliant MATLAB frame-work was developed in order to compare the performance of different algorithms. After the evaluation the most suit-able algorithm, a successive interference cancellation equalizer, was implemented in VHDL and synthesized.

Block Diagram of the successive interference cancellation (SIC) equalizer implementation.

Channel Equalization for TD-SCDMA

Personnel: Sandro Belfanti; Assistants: Christian Benkeser, Schekeb Fateh, Karim Badawi

Thesis: Master Thesis

Partners: Hasler

73

Joint Multiuser Equalization and Detec-tion for 3GPP TD-SCDMA

TD-SCDMA is a part of the UMTS 3GPP standard, rep-resenting the 1.28 Mcps low chip-rate option. The real-ization of the Maximum Likelihood Sequence Estimator (MLSE) algorithm in an environment such as that of the TD-HSPA standard (deploying higher order modulation up-to 64-QAM and multiplexing of up-to 16 users over the same physical channel in a multipath propagation condi-tions) is not feasible due to prohibitive complexity. Therefore, this project’s focus was on suboptimal ap-proaches for the MLSE design problem providing a power-efficient implementation, while still maintaining the superior performance of MLSE algorithms. A staged grouping-based reduced-state MLSE algorithm has been implemented and investigated.Design-specific parameters such as the number of sur-viving symbols at each stage, the number of users to be grouped at each stage and the final number of states con-stituting the trellis that is fed to the Viterbi algorithm were evaluated and optimized. Finally, a recommendation for a power and performance efficient implementation of the new algorithm providing an optimal and feasible solution for CDMA systems with large system dimensions has been proposed and defended.The simulation results showed a performance superior to linear and interference cancellation based algorithms. The performance exhibited small loss compared to the optimal MLSE with manageable complexity.

Block Diagram of the MLSGD Algorithm

Personnel: Tigist Mulatu Gebeyehu; Assistants: Karim Badawi, Christoph Roth

Thesis: Master Thesis

Partners: Hasler

Co-Channel Interference Cancellation-with RX Diversity

Modern cellular networks in urban areas are interference-limited rather than noise-limited. In order to address this limitation, advanced interference cancellation technolo-gies are applied in the receiver path of mobile phones. Co-channel interference is caused by users operating in the same frequency band as the desired user in a neigh-boring cell. In order to distinguish co-channel interference from the desired signal the training sequence code is used. In the receiver co-channel interference cancellation is particularly challenging due to power consumption and other design reasons.Three different methods for co-channel interference cancellation using RX diversity have been studied, the algorithms are simulated and their computational com-plexity is analyzed. A complexity index, which assesses the hardware implementation complexity in terms of arith-metical operations is provided. The methods have been implemented and tested in a Evolved EDGE simulation framework using MATLAB. The simulations show that all methods provide a significant gain over a system with no diversity in the interference limited case. In particular the space time filter achieves the largest gain compared to interference ratio combining, albeit at a higher complexity.

Block diagram of the analyzed space time filter.

Personnel: Simone Baffelli; Assistants: Harald Kröll, Sandro Belfanti

Thesis: Semester Project

Partners: KTI, ACP

74

Adjacent Channel Interference Detec-tion and Filtering

Modern cellular networks in urban areas are interference-limited rather than noise-limited. In order to address this limitation, advanced interference cancellation technolo-gies are applied in the receiver path of mobile phones. Adjacent channel interference arises from other users in the same cell and can be significantly stronger than the wanted signal. In addition, the variety of supported modu-lation types in the latest GSM specifications demand high sensitivity regarding the choice of filter types. In con-trast to static low pass filtering approaches, techniques in which filters are adapted on the characteristics of the adjacent channel are required in order to meet the tight performance constraints.In this semester project algorithm evaluation and imple-mentation of adjacent channel detection and filtering is covered. A configurable FIR filter approach proved to be the most promising filter type for hardware implementa-tion. Different approaches for the generation of the FIR coefficients were implemented and compared. The per-formance of the adjacent channel detection and filter-ing algorithm for the 5 modulation types (GMSK, QPSK, 8 PSK, 16 QAM and 32 QAM) was investigated in detail. A bit-true VLSI implementation for adjacent channel de-tection and filtering was achieved and synthesis results were presented.

System model of the implemented adjacent channel detec-tor and filter.

Personnel: Chenming Zhang; Assistants: Harald Kröll, Stefan Zwicky

Thesis: Semester Project

Partners: KTI, ACP

Cell Search & Synchronization Con-cepts for 3GPP TD-HSPA

TD-HSPA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD nature allows to master asymmetric services more efficiently than other 3G standards. Up- and downlink resources are flexibly assigned according to traffic needs, and a flexible data rate up-to 2.8 Mbit/s is provided.This flexibility is helpful in an environment with increasing data traffic, which tends to be asymmetric (mobile Inter-net). In order to meet these promises, a highly synchro-nized power-controlled transmission is eminent. Hence, TD-HSPA utilizes a multi-level synchronization in time (sample, chip, slot and frame levels). Moreover, an efficient frequency synchronization tech-nique is required to secure a maximum frequency-offset specified by the 3GPP UMTS standard. This process is synonymous with the term ’cell search’ in TDD communi-cation systems. In this project, fast synchronization techniques have been investigated focusing on their performance-complexity tradeoff and their convergence speed. Therefore, Matlab blocks have been implemented and integrated within our TD-HSPA simulation chain, ready for implementation in VHDL code for further testing on an FPGA.

TD-HSPA Frame Structure showing the Synchronization Pi-lot Channels DwPTS and UpPTS.

Personnel: Filip Gospodinov; Assistants: Karim Badawi, Sandro Belfanti

Thesis: Master Thesis

Partners: Hasler

75

Embedded Control System for Wireless ECG Monitoring Device

The goal of this project was to design and build an em-bedded control system for a wireless electrocardiography (ECG) monitoring device. The main functional blocks of the ECG system are - ECG capture device, wireless GSM module and control block. The latter must control and ini-tialize system modules, perform data exchange with ECG capture device and GSM module. The system should pro-cess the sampled data from the ECG capture device in real-time (500 samples per second), perform filtering and send the filtered data via the GSM module. The wireless GSM module is used to establish a connection to a host PC, that runs software to receive and display the ECG data.The assembled ECG system is shown in the figure be-low. It includes GSM module for data sending (on top), and the ECG acquisition board (not shown), The FPGA board that contains the embedded control system is at the bottom. An additional interface device with level shift-ers is required to connect GSM module to FPGA board. The system contains two large data buffers for intermedi-ate storage of samples and continuous transmission of a buffer at a time. With GPRS data transmission it can provide a maximum data rate of 10 kbps, enough for the ECG application.

Assembled test system with GSM module (on top) and FP-GA-board with the embedded controller

Personnel: Dmitry Lukyantsev; Assistants: , Thomas Burger, Tom Kleier, Roger Ulrich,

Thesis: Semester Project

Physical Layer Interface Development for GSM Protocol Stack

During the past years, considerable amount of work has been performed at IIS on the development of hardware IP realizations for GSM receivers. So far, the focus has been on problems at physical layer (PHY), i.e., digital base-band signal processing including the digital front-end, channel equalization, channel coding or interference can-cellation. Other basic PHY functionalities like power mea-surements, monitoring of the surrounding base-stations or synchronization tasks have not been treated so far, and are still missing for building a working GSM receiver pro-totype/demonstrator. Meanwhile, the open source com-munity has discovered the GSM system. For example, the GSM protocol stack (layer 2/3) has been implemented in open-source software by the OsmocomBB project.The aim of this project was to close the missing link be-tween existing PHY hardware implementations and layer 2/3 by developing and implementing a proper interface. To this end the OsmocomBB open source project was analyzed. In particular compatibility with the L1CTL pro-tocol, used to communicate with the physical layer was ensured.The entire setup as shown in the Figure below, with the OsmocomBB software is able to act as a MS. A base sta-tion from the OpenBTS project was used as counterpart. The state of camping on a cell and reading out the cells system information messages has been achieved. The GSM frames were encapsulated in UDP packets and vi-sualized with the Wireshark protocol analyzer.

System setup of PHY hardware interface with OpenBTS base station on transmit side and OsmocomBB layer 2/3 and Wireshark on receive side.

Personnel: Benjamin Weber; Assistants: Harald Kröll, Christian Benkeser

Thesis: Semester Project

76

Medium- to high-resolution successive approximation reg-ister (SAR) analog-to-digital converters (ADCs) are wide-ly used in today’s low-power CMOS applications such as wireless communication receivers, sensor networks, and medical instrumentation. Modern CMOS technologies make the SAR ADC suitable to cover bandwidths up to some tens of MHz with resolutions of more than 10 bits. SAR ADCs employ a charge-redistribution digital-to-analog converter (DAC) and a comparator in the analog domain to convert the sampled input in successive steps. No subcircuits consume static power since no operational amplifiers are used. The SAR ADC is thus the preferred converter choice for low power applications. The linearity of the converter is limited by the mismatch of the charge-redistribution capacitor array and the offset of the corresponding comparator. To correct the resulting static distortion, a calibration circuit is required in practical implemenentations. In this work, a 13-bit SAR ADC has been implemented in a 130 nm CMOS technology. The ADC is designed to cover a signal bandwidth of up to 5 MHz. The architecture includes a start-up calibration circuit to compensate the capacitor mismatch in the charge-redistribution array and the offset of the comparator. A resolution of 10.57 ENOB at Nyquist frequency is achieved in simulations.

Overview of the SAR ADC showing it’s main subcircuits and a simulated spectrum for a Nyquist frequency input signal.

Successive Approximation Register Analog-to-Digital Converter

Personnel: Philipp Schönle; Assistants: Schekeb Fateh, Luca Bettini, Jürg Treichler

Thesis: Master Thesis

OTA Design for a 2 MSample/s Algorith-mic ADC in 130 nm CMOS

Modern deep-submicron CMOS technologies have re-cently reinvigorated the popularity of successive-approxi-mation-register (SAR) and algorithmic A/D converters for all kinds of applications requiring medium resolutions and moderate bandwidths, such as sensors, measurement systems, and potentially also communications. Small silicon areas and very low power consumption can be achieved at the price of a limited accuracy. Algorithmic ADCs are Nyquist rate converters built with a single OTA which is iteratively re-used in different configurations. Similarly to the SAR converter, it performs a binary search to digitize the input. However, the input signal is multiplied by a factor of two at each step while the reference is held constant. In the SAR ADC on the contrary, the reference voltage is divided by two, while the input signal is kept unmodified. The main advantage of this approach is that no huge capacitor array is required. The price to pay, on the other hand, is that one active element, i.e. an OTA, is needed to implement the multiply by two operation. The goal of this project was the investigation of different OTA topologies with application to a low-power algorith-mic ADC. A regulated folded cascode topology has been identified as the best choice and was implemented in a 130 nm CMOS technology. It achieved more than 90 dB of DC gain with a gain-bandwidth-product of 300 MHz. Transient simulations of the entire converter employing the designed OTA have shown an effective resolution of more than 11 bits for a 1 MHz signal bandwidth.

Simulated spectrum at the output of the algorithmic ADC running at a sampling rate of 2 MHz. An effective resolution of 11.3 bits is observed.

Personnel: Federico Polli; Assistants: Thomas Burger, Luca Bettini, Schekeb Fateh

Thesis: Semester Project

77

Optimization of a Comparator in a Level-Crossing ADC

In the last years a new type of Analog Digital Converter (ADC) has come up which is called continuous time ADC (also called asynchronous ADC or level-crossing ADC). These ADC basically need less power, have reduced electromagnetic interferences and are faster than the conventional ones. In a continuous time ADC the sampling rate depends on the input signal. The input is only been sampled, if it crosses a certain level. This means there has to be a certain activity of the input signal in order to get it sam-pled. The advantage of this method is, that if the input signal has a period of silence, there is no power wasted in sampling the input. One of the major field of usage for this technology are biomedical applications because such systems often operate with low duty cycle signals to be power efficient. The circuits in biomedical applications must be able to perform their application specific task while running with small portable energy sources. In this thesis a level-crossing ADC based on an asyn-chronous delta-modulator is investigated. This topol-ogy has the advantage that only two comparators are needed. When the system is sufficiently oversampled the comparator levels can be dynamically adjusted to follow the input. The comparator is the most important building block for this converter. So the thesis concentrates on its optimization.

Investigated delta-modulator topology for the level-crossing ADC. The control logic implements a tracking algorithm such that the input signal stays within the VLOW to VHIGH interval.

Personnel: Fabian Hilti; Prof. Ana Rusu (KTH); Assistant: Thomas Burger

Thesis: Semester Project

Partners: KTH

High Speed Serial Interface Circuits for DigRF 4G

This thesis investigates two different topologies of a fre-quency synthesizer, the integer-N charge pump PLL and the all-digital PLL, focusing on area and power consump-tion. Both synthesizers, implemented in a 130 nm CMOS process, are designed to match the requirements of the DigRFSM v4 standard. DigRFSM v4 is a high-speed serial link between the baseband chip and a radio-frequency chip of a mobile radio. The serial link and therefore also its synthesizer have to meet the common requirements of mobile radios such as low chip area (and hence a low manufacturing price) and low power consumption due to the battery operation.The difference in the two topologies under investigation is mainly the detection and processing of the phase er-ror between external reference clock and the internally generated clock. In the charge pump PLL the phase dif-ference is converted and processed to an analog control voltage while in the all-digital PLL it is converted and pro-cessed to a digital control word.The main effort has been made to design a controllable oscillator that can be used as part of both PLLs. For the all-digital PLL a novel time-to-digital converter approach has been designed. For the given technology node and performance requirements it can be shown that both fre-quency synthesizer topologies are comparable regarding size and power consumption. The all-digital PLL circuit-ry will profit more from technology scaling and is hence preferable in smaller technologies.

Top: Block diagram all-digital PLL.Bottom: Block diagram of conventional integer-N charge pump PLL.

Personnel: Benjamin Sporrer; Assistants: Thomas Burger, Jürg Treichler

Thesis: Master Thesis

78

In a former student IC design project, an application-spe-cific integrated circuit (ASIC) has been developed which imitates “famous” analog music synthesizers as “Moog” or “Sequential Prophet-10”. These machines consist of a multitude of analog components that can be interconnect-ed to realize an almost infinite variety of different systems. The main components are voltage-controlled oscillators (VCO), voltage-controlled filters (VCF), and voltage-con-trolled amplifiers (VCA). The VCOs are controlled to gen-erate the frequency of the note including strong harmon-ics. Therefor, pulse trains, triangular or saw-tooth waves are made available. The VCFs then form the harmonic spectral behavior while VCAs in conjunction with enve-lope generators start and end the tone comparable to mu-sical instruments.The goal of this semester project was the design of the synthesizer system, supporting up to eight synthesizer ASICS. A printed circuit board has been developed to carry the direct-bonded ASIC dies. It provides also the interface to a digital signal processor (DSP) board with analog and digital audio ports. The DSP controls the syn-thesizer chips and combines the collected sounds of the synthesizer chips. A MIDI interface will serve to connect the keyboard. The DSP firmware will take care of the user interface to pro-gram and configure the synthesizer for generating the typical sound. The synthesizer firmware and the MIDI in-terface are still missing.

The photograph shows the synthesizer daughter board mounted on the DSP board. Two of the eight possible chips are directly bonded to the daughter board and covered with protective resin.

Personnel: Andreas Romer; Assistants: Norbert Felber, Andreas Looser

Thesis: Semester Project

Virtual Analog Synthesizer by Digital Signal Processing

Tube Amplifier Emulation on Digital Signal Processor

This semester project was a first step towards the simula-tion of a guitar tube amplifier with the goal of a later emu-lation on a digital signal processing system. Since it is the complex combination of non-idealities of a guitar amplifier which makes the instrument “sound”, it is no trivial task to find a simulation model which covers all relevant dynami-cally varying non-linear effects.The attempt followed in this work is to play a sine wave at several frequencies and amplitudes. As illustrated in the figure, one period of the distorted response is recorded and the time-domain transfer curves for both the ascen-dent and descendent signal portions are derived. The waveform is then reconstructed with the aid of polynomial approximations of the transfer curves. A filter bank as shown at the bottom of the figure is used to separate the frequency content of the guitar output. The RMS amplitude is measured and selects the suitable transfer curve pair in each frequency band. After recom-bination of all filter outputs, the result can be analyzed. Although the simulated sound is not identical to the real one, it resembles it quite well, but it lacks in presence. More work needs to be done to enhance the simulation of this significantly non-linear problem.

Top: a) Input wave, b) Output wave, c) Transfer curves (green: ascending, orange: descending). Bottom: Block diagram of the simulated non-linear guitar amplifier.

Personnel: Federico Polli; Assistant: Norbert Felber

Thesis: Semester Project

79

High-Efficiency Low-Power DC-DC Converter for Optical-Additives-Sup-ported Light Power

The Swiss startup company Optical Additives GmbH’s product ZeoFRET® is a new additive for transparent polymers. These polymers serve as a light harvester. The harvested light is concentrated onto a solar cell and trans-formed into electricity. The aim of this semester project was a demonstration of this functionality on a commer-cially available wireless optical mouse.Several power converter principles have been investi-gated with the goal of efficient conversion of the energy delivered by the solar cell. This requires optimal-power- point tracking due to the strongly varying current-voltage characteristics of solar cells. Based on use cases, the en-ergy requirement of the mouse has been put in relation to the available energy from the working-place illumination. The investigations showed that the ZeoFRET coating should provide a power gain of 10 with the given mouse. A low-power ASIC replacing the electronics of the mouse would allow to replace the rechargeable battery cells by a gold cap and to use a smaller solar cell (or less optical gain).

Wireless optical mouse prototype with a DC-DC converter in the battery cabinet and external solar cells. On the transpar-ent case, optical additives will be deposited to concentrate the light onto the solar cells to be cemented to the surface.

Personnel: Samuel Schöb; Assistants: Norbert Felber, Andy Kunzmann (Optical Additives GmbH)

Thesis: Semester Project

Partners: Optical Additives

Performance Improvement of Auto-matic Target Recognition Algorithm in Laser Trackers

Laser trackers are instruments which measure the posi-tion of a so called T-probe by forcing a laser beam onto a reflector. Movements of the probe are tracked such that the laser beam always stays on the reflector. Using a combination of 3-dimensional angular sensing and dis-tance measurement, the position of the tip of the T-probe can be calculated at all times.A camera mounted on a laser tracker is kept constantly pointed at the T-probe. The spots produced by the LEDs on the camera’s image sensor allow the use of photo-grammetry to calculate the yaw, pitch and roll orientation of the probe. Together with angles of the laser beam and the distance, all six degrees of freedom of the probe, and therefore the position of the tip, are known.The goal of this master project was to develop and imple-ment algorithms to speed up the measurement rate of a Leica Laser tracker. The bottle neck was the frame rate of the camera which can only be sped up by reading restrict-ed parts of the image, the so called regions of interest (ROI). The implemented algorithm dynamically defines these ROI and instructs the camera to use them. In the image below, the black bars containing spots shows an example. The algorithm has been implemented on a microproces-sor and has been demonstrated to reach the expected speed up of the tracking.

Image with the spots (marked yellow) of the LEDs of the T-Probe shown on the left side. The black background areas indicate regions of interest to be transmitted, while the grey areas will be suppressed in order to save bandwidth.

Personnel: Michael Meier; Assistants: Norbert Felber; Adrian Renold, Tomasz Kwiatkowski (Leica)

Thesis: Master Thesis

Partners: Leica

80

Fabrication of Through-Silicon Vias with RF Capability by Magnetic Assem-bly of Nickel Wires

The goal of this master thesis was a novel Through-Sili-con Via (TSV) fabrication technology for TSVs with good RF quality. The major focus was put on the design and the construc-tion of a fully automated fabrication tool for the assembly of Nickel TSV cores. The utilisation of the ferromagnetic properties of Ni enabled a highly parallelized self-assem-bly process for the automated fabrication. As shown in the figure, the Ni wires are brought into vertical position by a magnetic filed. This “brush” is moved over the silicon wafer, where the wires fall in into the holes. The develop-ment of the tool required the implementation of a com-munication interface between a computer and the robot, as well as the programming of a control software for the assembly process. In order to increase the low conductivity of Ni, a novel type of metal conductor was devised and fabricated. Tak-ing the skin effect into account, the deposition of a thin gold layer on the perimeter of the conductor lowers the resistivity at high frequencies and therefore enhances the RF performance. The developed assembly process was then used to build RF test structures. Various configurations of micro-strip transmission lines with integrated TSVs along their paths have been implemented.

Top: Behavior of Nickel wires in a magnetic field. Middle: Process to slide the Ni wires into the silicon holes. Bottom: Assembly robot with the custom-built TSV assem-bly stage on the right side.

Personnel: Simon Bleiker; Assistants: Norbert Felber, Andreas Fischer (KTH)

Thesis: Master Thesis

Partners: KTH

References: ECTC 2012, IMM (submitted)

Wireless ECG Monitoring System

Electrocardiography (ECG) is widely used in medicine to detect heart arrhythmia. The goal of this project was to evolve the fundamentals for a portable ECG system which transmits the recorded data wirelessly using the cellular phone network, i.e., GSM or UMTS. Such a de-vice allows to observe the heartbeat over a long time and distance, which is interesting for ergometry. Using the mobile phone network allows to use the ECG system out-door, e.g., during sporting activities.In this project, a FPGA evaluation board was used to pro-vide a central control unit. This control unit reads the data delivered by the sensor front-end, does some signal pro-cessing, and controls the cellular modem. The collected data is sent using GPRS to a PC.The software necessary to read the received data on the PC consists of a communication interface written in C and a MATLAB GUI. The interface reads the streamed data and forwards it to the GUI. The latter controls the interface and presents the measured signals in an animated plot.

The wireless ECG monitoring system consists of a sensor front-end, a control and signal processing unit and a cellular modem. The measured signal is transmitted by GPRS to a PC.

Personnel: Fiona Huang, Chris Fougner, Adit Jain, Assistants: Thomas Burger, Thomas Kleier, Roger Ulrich

Thesis: Group Project

81

PhD Theses – Abstracts

The dissertation describes the simulation of the high-energy charge transport in single photon avalanche di-odes by means of the full-band Monte Carlo technique. A computationally efficient formulation of the scattering rates, while keeping the main physical features, renders the CPU-intensive calculation of the breakdown charac-teristics of single photon avalanche diodes feasible on standard computer clusters. CarloS, a novel full-band Monte Carlo simulator is applied to the high-field charge dynamics of the multiplication process. Compared to pre-

vious works employing simple charge transport models, the solution of the Boltzmann transport equation and the incorporation of the full-band structure puts the evalua-tion of the breakdown probability, the time to avalanche breakdown and its jitter on deeper theoretical grounds. Additionally, this thesis presents an impact ionization model for the scattering rates and the secondary carrier energies based on the random-k approximation

Prof. Dr. A. Schenk, ETH Zürich, examinerProf. Dr. M. Luisier, ETH Zürich, co-examiner

Diss. ETH-Nr. 20121

With respect to light absorption, this doctoral thesis re-veals how the electromagnetic eigenvalue problem can be used to understand and design optimum light absorp-tion in nanowire array solar cells. The proposed model yields good quantitative agreement for the geometries of interest. It provides some new physical insight. The results are original. Based on the comprehensive under-standing of the absorption process, I discuss the effect

of the projected local density of photon states (PLDOS) that is altered by the nanostructure in the context of a detailed balance efficiency calculation. I propose a hybrid discrete/continuous modeling of carrier transport that is verified and discussed against industry strength drift/dif-fusion simulations. This hybrid approach constitutes an extension of similar models discussed in contemporary scientific literature.

Prof. Dr. U. Keller, ETH Zürich, examinerProf. Dr. B. Witzigmann, Uni Kassel, co-examiner

Diss. ETH-Nr. 19864

Full-band Monte Carlo simulation of single photon avalanche diodes

Denis Dolgos

Modeling nanostructured solar cellsJan Kupec

Present thesis deals with four major developments.The first development is aimed to improve the procedures to control the defectivity of gate oxide in LDMOS transis-tors. The scope of the second development is to screen out defects in the shallow trench insulation of LDMOS transistors. With the third development a novel approach

to screen out defective Vertical Parallel Plates (VPP) ca-pacitors used in SAR (Successive Approximation Regis-ter) Analog-to-Digital converters (ADC) is proposed. Fi-nally, the fourth development deals with a novel built-in ΔIDDQ testing technique for the screening of Low Voltage transistors of the SAR logic.

Prof. Dr. W. Fichtner, ETH Zürich, examinerProf. Dr. Enrico Zanoni, Uni Padova, co-examiner

Diss. ETH-Nr. 19678

In situ screening techniques for automotive devices

Vezio Malandruccolo

82

Two mesa InAlAs/InGaAs separated absorption, charge and multiplication (SACM) avalanche photodiodes (APDs) for next generation 10~Gbit/s fiber-to-the-home (FTTH) passive optical networks (PON) are designed, characterized and analyzed. Furthermore, a 25~Gbit/s APD prototype is presented.The analysis of the device performance is supported by the simulation of carrier transport within the APD in pres-ence of fast changing, high electric fields and transport across hetero-junction band diagram energy offsets. For

this purpose, a transport simulator based on the Monte Carlo (MC) method is implemented. The band structure is represented by a spherical, non-parabolic approxima-tion with three conduction band and three valence band valleys. The simulation results show good agreement with measurements and give insight to performance critical physics, such as carrier velocity overshoots and non-local impact ionization. The simulator allows a quantitative de-sign optimization of future APD devices.

Prof. Dr. W. Fichtner, ETH Zürich, examinerProf. Dr. B. Witzigmann, Uni Kassel, co-examiner

Diss. ETH-Nr. 19519

Design, Characterization and Simulation of Avalanche Photodiodes

Hektor Meier

83

Halbleiterbauelemente 4th Sem.Semiconductor Devices Bachelor in EE

A. Schenk

This lecture gives an introduction to the basics of modern semiconductor devices for micro-, opto-, and power-electronics. It bases on semiconductor physics and covers band structures, band models, dispersion relations, statistics, transport equations, macroscopic models, and the characteristics of silicon and other semiconductors. An overview on device fami-lies is presented.

The part on technologies covers the properties of materials, and introduces the steps of modern process technologies as well as packaging. To understand the basic principles of devices, ohmic and rectifying contacts, physical and electrical characteristics of pn junctions, and types of diodes are explained. The lecture continues with the bipolar transistor’s func-tion, working regions, characteristic diagrams, and its simulation. MOS devices are treated based on band diagrams, and the MOSFET behavior is deduced. Power devices, their working regions and static and dynamic behavior are followed by examples of optoelectronic devices as photo conductor, photodiode, LED, and fiber. Semiconductor measurement and characterization methods conclude the course.

Solid State Electronics Bachelor in EE, 5th Sem. Master in M&N

V. Wood

“Solid State Electronics” is an introductory condensed matter physics course for 5th semester students covering crystal structure, electron models, classification of metals, semiconductors, and insulators, band structure engineering, thermal and electronic transport in solids, magnetoresistance, and optical properties of solids.

VLSI I: Von Architektur zu hochintegrierter Schaltung und FPGA Bachelor in EE/CSE, 6th Sem.VLSI I: From Architectures to Very Large Scale Integration Circuits and FPGAs Masters in EE/CS/CSE

H. Kaeslin, N. Felber

As becomes clear from the subsequent list of topics, the first course in this series of three is mainly concerned with system-level issues of VLSI. Terminology, overview on design methodologies and fabrication avenues, levels of abstraction used for circuit description and simulation, VLSI design flow, dedicated VLSI architectures, how to obtain an architecture for a given processing algorithm, architectural transformations for meeting throughput, area, and power requirements. Hardware Description Languages (HDL) and their underlying concepts, VHDL for simulation and synthesis, the IEEE-1164 logic system, Register Transfer Level (RTL) synthesis. Timing models, Anceau diagrams, functional verification of digital circuits and systems, building blocks of digital VLSI circuits, case studies of actual circuits, comparison with microprocessors and DSPs.

During the exercises students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for ASICs and FPGAs.

VLSI II: Entwurf von hochintegrierten Schaltungen 7th Sem. VLSI II: Design of Very Large Scale Integration Circuits Masters in EE/CS/CSE

H. Kaeslin, N. Felber

The second course begins with a thorough discussion of various technical aspects at the circuit and layout level. It then moves on to economic issues of VLSI. Topics include: limitations of functional design verification, techniques for improving controllability and observability, design for test, block isolation, scan-path techniques, partial scan and its caveats. Evalu-ation of various synchronous clocking disciplines, skew margins, clock distribution techniques. Asynchronous inputs, data inconsistency and metastability problems, synchronization. Cell libraries, Process-Temperature-Voltage (PTV) variations, transistor models, characteristics of CMOS inverters, complex gates. Power estimation and low-power design. Layout parasitics, transport delay, switching currents, ground bounce, controlling noise problems, power distribution, floorplan-ning, chip assembly. Layout design at the mask level, symbolic layout. Timing verification, physical design verification. Cost structures of microelectronics design and fabrication, avenues to low-volume fabrication, management of VLSI projects.

Exercises are concerned with physical design and sound engineering practices for avoiding timing, testability, and layout parasitics problems. Industrial CAD tools are being used for place and route, clock tree generation, chip assembly, and physical design verification. Students that elect to carry through a term project at the laboratory are offered the opportunity to complete a full IC design cycle on a circuit of their own which gets actually fabricated.

Lectures

84

VLSI III: Test und Fabrikation von hochintegrierten Schaltungen Bachelor in CSE, 8th Sem. VLSI III: Test and Fabrication of Very Large Scale Integration Circuits Masters in EE/CS/CSE

N. Felber, H. Kaeslin

Whereas the preceding courses deal with design aspects of VLSI circuits, this one addresses manufacturing, testing, physi-cal analysis, and packaging issues, such as: Effects of fabrication defects, abstraction from physical to transistor- and gate-level fault models, fault grading of large ASICs. Generation of efficient test vector sets, enhancement of testability by built-in self-test techniques. Modern IC testers: Architectures and application. Deep-submicron CMOS fabrication processes with multi metal levels and the physical analysis of their devices. Packaging problems and solutions. Technology outlook.

Exercises teach students how to use CAE/CAD software and automatic test equipment for verifying ASICs after fabrication. Students that submitted a design for manufacturing at the end of the 7th semester do so on their own circuits. Physical analysis methods with professional equipment (AFM, DLTS) complement this training.

Analog Integrated Circuits Bachelor in EE, 5th Sem.

Q. Huang Masters in EE/BIO/M&N

This course provides a foundation in analog integrated circuit design: After a review of bipolar and MOS devices and their small-signal equivalent circuit models, building blocks in analog circuits such as current sources, active load, current mirrors, supply independent biasing are presented. Other topics are differential amplifiers, cascade amplifiers, high gain structures, and output stages, and comparators, gain bandwidth product and stability of op-amps. Second-order effects in analog circuits such as mismatch, noise, and offset are investigated. More complex circuits such as A/D and D/A convert-ers, analog multipliers and oscillators are analyzed. An introduction to switched-capacitor circuits from an IC designer’s point of view is given.

The exercise sessions aim to reinforce the lecture material by well-guided step-by-step design tasks. Cadence design tools are used to facilitate the tasks. There is also an experimental session on op-amp measurements.

Organic and Nanostructure Electronics Masters in EE/MPE/M&N

V. Wood

“Organic and Nanostructure Electronics” is a MSc level course providing students with the knowledge and practical experi-ence to begin research in organic or nanostructured materials and understand the key challenges in this rapidly emerging field. Organic molecules and colloidal quantum dots are presented as archetypical nanomaterials. Beginning with an over-view of solid state physics, the course outlines absorption, emission, and charge transport in amorphous thin films before exploring how the optical and electronic properties of these nanomaterials can be leveraged to create lasers, chemosen-sors, light emitting devices, solar cells, and transistors. In two laboratory sessions students gained hands-on experience by synthesizing colloidal quantum dots, performing experiments to investigate solvatochromic shifts and Förster energy transfer, and fabricating and characterizing organic LEDs..

Halbleiter-Bauelemente: Physikalische Grundlagen und Simulation 6th Sem. Semiconductor Devices: Physical Bases and Simulation Masters in EE/Math/Phys/M&N

A. Schenk

“This course aims at understanding the principles behind the physics of modern electronic silicon semiconductor devices and the foundations of physical modeling of transport and its numerical simulation. During the course basic knowledge on quantum mechanics, semiconductor physics, and device physics is also provided. The main topics are: Transport models for semiconductor devices (quantum transport, Boltzmann equation, drift-diffusion model, hydrodynamic model), physical characterization of silicon (intrinsic properties, band gap narrowing, scattering processes), mobility of cold and hot carriers, recombination (SRH statistics, lifetimes for tunnel-assisted transitions), interband tunneling (Zener diode), impact ioniza-tion, metal-semiconductor contact, MIS structure, and heterojunctions.The exercises focus on the theory and the basic understanding of special devices, such as pn-diodes, bipolar transistors, MOSFETs, and thyristors. Numerical simulations of these devices with an advanced simulation package are compared with corresponding measurements, which are also part of the exercises.

85

Halbleitertransporttheorie und Monte-Carlo Bauelementsimulation 8th Sem. Semiconductor Transport Theory and Monte-Carlo Device Simulation

Schenk Masters in EE/Phys/CSE/M&NThe aim of the course is, on the one hand, to establish the link between microscopic physics and its concrete application in device simulation and, on the other hand, to introduce the numerical techniques involved. The scope encompasses there-fore the basics of quantum mechanics, transport theory, and the Monte-Carlo method for the solution of the Boltzmann transport equation. The topics include second quantization, crystal symmetries, band structure calculation, phonons, Boltzmann equation, probability calculus, Monte-Carlo techniques, and device simulation.

The exercises comprise problems to illustrate the contents of the lecture, simple Monte-Carlo related programming tasks as well as the application of various professional tools for device simulation.

Schaltungs- und Leiterplattenentwicklung in der Praxis 5th-8th Sem.Applied Electrical Circuit and PCB-Design Bachelor in EE

M. Nussberger, D. Schöni

Participants learn how to design a predefined electronic circuit and how to lay out the pertaining circuit board. CAE and CAD activities are carried out with the aid of Spice and Altium Designer. The goal is to become acquainted with all those practical aspects of electronic circuit and PCB design by working through a modest but complete application example. This involves understanding specifications and datasheets, the evaluation of electronic parts, power supply and power distribu-tion, heat dissipation, electromagnetic compatibility (EMC), the usage of industrial CAE/CAD tools for circuit simulation and PCB layout, generating production data for the board manufacturer, board mounting, testing and start up.

The course is recommended to all students who plan to design an electronic circuit or a PCB in an upcoming term project or as part of their master thesis. Attending this course during the term before will ensure they are optimally prepared and will allow them to fully focus on their project.

Abbreviations:CS Computer ScienceCSE Computational Science and EngineeringBIO BioelectronicsEE Electrical EngineeringMPE Mechanical and Process EngineeringM&N Micro and NanosystemsMath MathematicsPhys Physics

86

PersonnelProf. Dr. H. Kaeslin (head, VLSI CAE), Dr. Gürkaynak (VLSI technology, VLSI CAE/CAD),B. Muheim (software operation, VLSI CAE/CAD), D. Schöni (PCB CAD).

A High-Performance Ciphering EngineCiphering essentially relies on two items: a secret key and a mathematical algorithm for encrypting (or decrypting) data with that key. In the context of an on-going Nano-Tera project, ID Quantique, a company based in Geneva, IIS, and other partners, strive to combine quantum key distribution with high-speed encryption where either subsystem is at the cutting edge in its own right.

A major contribution of ETHZ to the project is a secret key encryption engine with a target throughput of 100 Gb/s in each di-rection (see page 25). DZ was instrumental in building prototype hardware to investigate all relevant issues before the final construction of the challenging system would begin. To that end, a printed circuit board (PCB) 2.8 mm thick and comprising 24 conducting layers has been designed, manufactured, mounted and measured, see fig.1.

A first design challenge were the many high speed interconnections running at 10 Gb/s (dubbed 10G links) between the Stratix IV FPGA with its 1932 pins and the twenty optical transceivers. 5 out of the 24 board layers are occupied by imped-ance-controlled high speed wiring. Matching delays are obtained from meanders where necessary.

Another major difficulty was the complex power scheme made necessary by the seven independent supply voltages re-quired to power the various components and subcircuits. The FPGA core alone demands up to 48 A at 0.95 V. All voltages get produced on board from a single 12 V input with the aid of 11 buck converter modules, four of which work in parallel to feed the FPGA core. 15 out of the 24 layers are shaped as planes and devoted to power distribution, current return, refer-ence potential, and/or shielding.

Evaluation of SHA-3 Candidates The American National Institute of Standards and Technology (NIST) has launched a public competition to find a replace-ment of the ageing SHA-1 and SHA-2 secure hashing standards. This competition is currently in its final stage, from the initial 51 candidates, only five remain. These are Blake, Groestl, JH, Keccak, and Skein. In March 2012, the third and final SHA-3 candidate conference will be held in Washington D.C., the winner is expected to be announced in Summer of 2012.

DZ has taken an active role in evaluating the performance of the candidate algorithms in hardware. For the final round, together with the Integrated Systems Laboratory, a 65 nm ASIC was developed that includes two versions of all candidate algorithms, together with a reference SHA-2 implementation for comparison (see page 25).

For this study we have collaborated with the Crytographic Engineering Reserach Group (CERG) of the George Mason University (GMU). We have used VHDL code optimized for high throughput per area on FPGA developed by GMU on our test chip. Many hardware evaluation projects focus on a single corner of performance, like fastest algorithm, smallest implementation, or - as in the case of GMU - highest throughput/area ratio. In order to introduce more variation into the

Microelectronics Design Center (DZ)

Figure 1: Photograph of the assembled QCrypt testbed. The Stratix IV GT FPGA with its cooling fan can be seen near the center of the PCB. Nine power supply modules are placed to the left (mounting LGA packages is a delicate operation and one voltage converter module had actually to be bypassed on the laboratory sample depicted here). At the bottom edge from left to right are the optical interfaces: 100G CXP, two 10G XFP, four 10G SFP+ (four more mounted from bottom), and the 100G CFP with its cage removed. The top edge carries all interfaces and a row of test connectors for debugging and experiments.

87

evaluation, we have decided to further develop hardware implementations of the candidate algorithms targeted for a specific throughput ratio. For the purposes of this comparison we have elected to use 2.488 Gbit/s throughput, a value that can eas-ily be achieved by all candidate algorithms for the chosen 65 nm CMOS technology.

Fig.2 shows our cumulative results for the implementations. The graph is a variation of the AT-plot used for hardware implementation efficiency. The Y-axis gives the area in gate equivalents, where as the X-axis shows the time required to calculate the output (or 1/throughput). Curves show equal throughput-per-area lines. In this graph, points towards the left side of the graph represent faster implementations, and points towards the bottom of the graph are implementations with smaller circuit size.

There are two sets of results, GMU implementations are represented by ’plus’ signs +, and ETH Zurich implementations by circles ○. Furthermore, for every algorithm there are three datapoints. The first datapoint represents a standard synthesis result. The second data point is again a synthesis result, however using more precise estimations of the interconnection parasitics obtained through a preliminary placement and routing stage. Finally the third datapoint is the actual circuit as implemented on the ASIC. The graph clearly shows that there is a large discrepancy between simple synthesis results and actual ASIC implementations, at times exceeding 50%.

From the results, it can be seen that SHA-2 can be very efficiently implemented; in fact, none of the SHA-3 candidates can be implemented smaller. Of the new algorithms, Keccak is clearly the algorithm with the highest throughput, achieving over 20 Gbit/s under worst case PTV conditions. These results have been submitted to the third SHA-3 candidate conference.

Introducing a New 65 nm Fabrication TechnologyIn 2011, Europractice added UMC65, a 65 nm CMOS technology to their mini@sic program, creating a modern and afford-able alternative for MPW projects. A mini@sic run is being offered three times per year at a cost of 15 000 EUR per a die of 1.875 mm by 1.875 mm. The mini@sic uses 8 metal layers for interconnection, the top metal is 3.25 mm thick, and 2 fF/mm² MIM capacitors are supported, allowing a wide range of digital and analog projects.

We offer access to and support for the UMC65 technology and have already taped out a first ASIC in this technology. Our installation includes I/O cells, digital standard cells, and a memory compiler with full layouts. The I/O cell library uses Bond-ing over Active Circuit (BOAC). These pads are extremely area-efficient, allowing a net core area of 2.814 mm² (as compared to just 1.958 mm² for the 90 nm mini@sic with the same die size). In total, circuits with more than 1.25 million gate equivalents can be implemented on one 65 nm mini@sic, making it very attractive.

Supported Fabrication ProcessesDZ has installed and maintains design flows for a wide range of VLSI fabrication processes and cell libraries. As any list is per force outdated by the time it gets printed, we kindly ask prospective IC designers to refer to our documentation on the Intranet available at www.dz.ee.ethz.ch/en/information/ic-technologies.html for up-to-date and more complete informations on the resources available. Further be informed that DZ is willing to install most design kits supported by Europractice, Mosis, CMP and other MPW vendors. Please contact DZ staff as early as possible if you feel our current offerings do not meet your needs.

Figure 2: AT-plot showing the relative position in the solution space of the 12 SHA architectures studied along with how estimates have matured during the design process.

88

Design ActivitiesA statistical overview of all IC design activities conducted in 2011 with software installations operated by DZ and with sup-port by DZ staff is given in the table below along with the laboratory involved and with the target process. Only manufactured chips are listed, FPGA-based design projects and dry runs are not included in the numbers below.

IC Design Teaching Research TotalProcess family Foundry180 nm CMOS150 nm CMOS130 nm CMOS130 nm CMOS130 nm CMOS 65 nm CMOS

UMCLfoundrySMICSTMUMCUMC

52

1

1

41

1

624111

Total 8 7 15

89

ProfileThe IT’IS Foundation was established on November 17, 1999 through the initiative and support of the Swiss Fed-eral Institute of Technology in Zurich (ETHZ), the global wireless communications industry, and several govern-mental agencies. IT’IS stands for Information Technolo-gies in Society.The aim of the IT’IS Foundation is to create a flexible and dynamic research institution capable of addressing the research needs of society in the explosively expand-ing field of information technologies and the utilization of electromagnetic energies in general. Some of the areas encompassed are: • evaluation of the safety and risks related to current and

emerging information technologies• exploration of information technologies for medical, di-

agnostic, and life support systems• improvement of the accessibility of information tech-

nologies for all members of society including disabled persons.

The IT’IS Foundation is committed to the advancement of science for the benefit of society at large and to main-taining strict independence from any particular interest groups. These principles are reflected in the Founda-tion’s charter as well as in the balanced composition of its board, which includes distinguished personalities from science, medicine, the public sector, and the global wire-less communications industry. IT’IS Foundation is a non-profit tax-exempt research organization situated in down-town Zurich.

Infrastructure and CooperationThe IT’IS Foundation maintains the world’s finest near-field laboratories. It includes a large semi-anechoic cham-ber for general near-field and dosimetric measurements and new laboratories designed for accredited testing of body-mounted transmitters and implants. The IT’IS Foundation’s closest and most important co-operative tie is with the Integrated Systems Laboratory. Close cooperation has also been established with the Laboratories of Computer Vision and Biomedical Engi-neering as well as other laboratories of ETH Zurich. In addition, the IT’IS team has numerous multidisciplinary cooperation projects, resulting in an international network of over 100 academic and industrial research partners in Europe, the USA, and Asia.

Current Research FocusThe IT’IS Foundation’s mission to make a tangible differ-ence in people’s lives by enhancing the safety and quality of emerging electromagnetic technologies and improving the quality of life and adding healthy life years through personalized medicine, is achieved by performing re-search in two main areas 1) personalized medicine and 2) experimental and computational technologies for electro-magnetic analysis. In addition, the IT’IS Foundation offers various services to research partners, governments and industries, including antenna optimization, device optimi-zation for operation in EMF-hostile environments, expo-sure assessments, development of EM safety concepts,

testing of compliance with EM safety guidelines (wireless devices, implants, etc.), and exposure systems for bio-medical research.With its new research initiative IT’IS for Health, IT’IS aims to bridge the gap between bench and bedside by further developing multi-physics, multi-scale simulation approaches to optimize individual diagnostic, treatment planning, and therapeutic techniques, and to model inter-actions between physical agents and complex biological processes and structures. Specific areas of research in-clude EM-neuron interactions, focused ultrasound-based applications, blood flow modeling and cancer treatment modalities. Additionally, new and established virtual ana-tomical models of our world-renowned Virtual Population are continuously developed and refined for bioelectro-magnetic simulations.The second research initiative, Sensing and Computation-al Techniques, focuses on the development of new sensor technologies for electromagnetic compatibility and inter-ference measurements, new measurement procedures for testing the compliance of wireless devices and base stations with safety limits, and new numerical tools and solvers optimized for High-Performance Computing and operating in the frequency domain. These novel technolo-gies have been integrated and commercialized in prod-ucts such as DASY5, TDS, iSAR and SEMCAD X, while becoming the standard in the wireless and medical device industries for R&D, testing compliance and virtual proto-typing.Current research projects are publicly funded by NIH (USA), Framework Programs (EU), EUREKA (EU), CTI (CH), SNF (CH), health agencies such as BAG (CH) BfS (D), DSA (USA) as well as other governmental institutions (e.g., BAKOM (CH), TMC (CN)). Industry funding consists of support from major mobile communications manufac-turers, medical device companies, service providers and SME.

DirectorProf. Dr. Niels Kusterkuster@itis.ethz.ch

Main Office Address Mailing Address and LabsIT’IS Foundation IT’IS FoundationETH Zurich, ETZ Zeughausstrasse 43CH-8092 Zurich CH-8004 ZurichSwitzerland Switzerland

Phone: +41 44 245 9696 info@itis.ethz.chFax +41 44 245 9699

w w w. i t i s . e t h z . c h

Joint Research Cooperation with the IT’IS Foundation

90

Papers

IC and System Design and Test[D1.] P. Greisen, S. Heinzle, M. Gross, A. Burg

An FPGA-based processing pipeline for high-definition stereo video, EURASIP Journal on Image and Video Processing, vol. 2011, no. 18, Nov 2011

[D2.] L. Henzen, J. Aumasson, W. Meier, R. Phan VLSI Characterization of the Cryptographic Hash Function BLAKE, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 10, pp. 1746-1754, Oct 2011

[D3.] D. Stucki, M. Legré, F. Buntschu, B. Clausen, N. Felber, N. Gisin, L. Henzen, P. Junod, G. Litzistorf, P. Monbaron, L. Monat, J.B. Page, D. Perroud, G. Ribordy, A. Rochas, S. Robyr, J. Tavares, R. Thew, P. Trinkler, S. Ventura, R. Voirol, N. Walenta, H. Zbinden Long term performance of the SwissQuantum quantum key distribution network in a field environment, New Journal of Physics, vol. 13, pp. 1-18, Dec 2011

Nano Electronics and Nano Photonics[N1.] M. Duduta, B. Ho, V. Wood, P. Limthongkul, V.E. Brunini, W.C. Carter, Y.M. Chiang

Rechargeable Lithium Battery Using Flowable Semi-Solid Electrodes, Advanced Energy Materials, vol. 1, no. 4, pp. 511-516, Jul 2011

[N2.] V. Wood, M.J. Panzer, D. Bozyigit, Y. Shirasaki, I. Rousseau, S. Geyer, G.B. Moungi, V. Bulovic Electroluminescence from Nanoscale Materials via Field-Driven Ionization, Nano Letters, no. 11, pp. 2927-2932, Jun 2011

Analog and Mixed-Signal Design[A1.] C. Studer, C. Benkeser, S. Belfanti, Q. Huang

Design and Implementation of a Parallel Turbo Decoder ASIC for 3GPP-LTE, IEEE Journal of Solid-State Circuits, vol. 46, no. 1, pp. 8-17, Jan 2011

[A2.] C. Studer, S. Fateh, D. Seethaler ASIC Implementation of Soft-Input Soft-Output MIMO Detection Using Parallel Interference Cancellation, IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1754-1765, Jul 2011

Technology CAD[T1.] C.D. Bessire, M.T. Björk, H. Schmid, A. Schenk, K.B. Reuter, H. Riel

Trap-Assisted Tunneling in Si-InAs Nanowire Heterojunction Tunnel Diodes, Nano Letters, vol. 11, no. 10, pp. 4195-4199, Aug 2011

[T2.] D. Dolgos, H. Meier, A. Schenk, B. Witzigmann Full-band Monte Carlo simulation of high-energy carrier transport in single photon avalanche diodes: Computation of breakdown probability, time to avalanche breakdown, and jitter, Journal of Applied Physics, vol. 110, no. 8, pp. 084507, Oct 2011

[T3.] M. Frey, A. Esposito, A. Schenk Computational Comparison of Conductivity and Mobility Models for Silicon Nanowire Devices, Journal of Applied Physics, vol. 109, no. 8, pp. 083707, Apr 2011

[T4.] S.G. Kim, M. Luisier, T.B. Boykin, G. Klimeck Effects of Interface Roughness Scattering on Radio Frequency Performance of Silicon Nanowire Transistors, Applied Physics Letters, vol. 99, pp. 232107, Dec 2011

[T5.] J. Kupec, U. Akcakoca, B. Witzigmann Frequency domain analysis of guided resonances and polarization selectivity in photonic crystal membranes, J. Opt. Soc. Am. B, vol. 28, no. 2011, pp. 69-78, Jan 2011

[T6.] M. Luisier Investigation of Thermal Transport Degradation in Rough Si Nanowires, Journal of Applied Physics, vol. 110, pp. 074510, Oct 2011

[T7.] M. Luisier Performance Comparison of GaSb, Strained-Si, and InGaAs Double-Gate Ultra-Thin-Body n-FETs, IEEE Electron Device Letters, vol. 32, pp. 1686, Dec 2011

[T8.] S. Steingrube, O. Breitenstein, K. Ramspeck, S. Glunz, A. Schenk, P.P. Altermatt Explanation of Commonly Observed Shunt Currents in c-Si Solar Cells by Means of Recombination Statistics beyond the Shockley-Read-Hall Approximation, Journal of Applied Physics, vol. 110, no. 1, pp. 014515, Jul 2011

91

Physical Characterization[P1.] M. Ciappa, L. Mangiacapra, M. Stangoni, S. Ott

High resolution two-dimensional dose mapping of electron beam processed polymers, Journal of Radiation Physics and Chemistry, Dec 2011

[P2.] M. Ciappa, L. Mangiacapra, M. Stangoni, S. Ott, W. Fichtner A new process simulator for the optimization of electron beam crosslinking processes of polymer isolations in electrical cables, Journal of Radiation Physics and Chemistry, Dec 2011

[P3.] M. Ciappa, L. Mangiacapra, M. Stangoni, S. Ott, W. Fichtner Design of optimum electron beam irradiation processes for the reliability of electric cables used in critical applica-tions, Microelectronics Reliability, vol. 51, pp. 1479-1483, Oct 2011

[P4.] A. Esposito, M. Ciappa, W. Fichtner Synthesis of scanning electron microscopy images by high performance computing for the metrology of advanced CMOS processes, Microelectronics Reliability, vol. 51, pp. 1673-1678, Oct 2011

[P5.] V. Malandruccolo, M. Ciappa, H. Rothleitner, W. Fichtner A new built-in defect-based testing technique to achieve zero defects in the automotive environment, Journal of Electronic Testing, vol. 27, no. 1, pp. 19-30, Feb 2011

[P6.] V. Malandruccolo, M. Ciappa, H. Rothleitner, W. Fichtner Design and experimental characterization of a new built-in defect-based testing technique to achieve zero defects in the automotive environment, IEEE Transactions on Device and Materials Reliability, vol. 11, no. 2, pp. 349-357, Jun 2011

Bio-Electromagnetics and Electromagnetic Compatibility[B1.] J.F. Bakker, M.M. Paulides, E. Neufeld, A. Christ, N. Kuster, G.C. van Rhoon

Children and Adults Exposed to Electromagnetic Fields at the ICNIRP Reference Levels: Theoretical Assessment of the Induced Peak Temperature Increase, Physics in Medicine and Biology, vol. 56, pp. 4967-4990, Jul 2011

[B2.] M. Christen, O. Schenk, E. Neufeld, M. Paulides, H. Burkhart Manycore Stencil Computations in Hyperthermia Applications, Scientific Computing with Multicore and Accelerators, CRC Press, Taylor & Francis Group, 978-1-4398-2536-5, J. Kurzak , D. A . Bader and J. Dongarra, Boca Raton, FL, USA, pp. 255-277, 2011

[B3.] F.P. Costa, A.C. de Oliveira, R. Meirelles, M.C. Machado, T. Zanesco, R. Surjan, M.C. Chammas, M. de Souza Rocha, D. Morgan, A. Cantor, J. Zimmermann, I. Brezovich, N. Kuster, A. Barbault, B. Pasche Treatment of Advanced Hepatocellular Carcinoma With Very Low Levels of Amplitude-Modulated Electromagnetic Fields, British Journal of Cancer, vol. 105, pp. 640-648, Aug 2011

[B4.] P. Crespo-Valero, M. Christopoulou, M. Zefferer, A. Christ, P. Achermann, K.S. Nikita, N. Kuster Novel Methodology to Characterize Electromagnetic Exposure of the Brain, Physics in Medicine and Biology, vol. 56, pp. 383-396, Jan 2011

[B5.] T. Gohil, R. McGregor, D. Szczerba, K. Burckhardt, K. Muralidhar, G. Székely Simulation of Oscillatory Flow in an Aortic Bifurcation Using FVM and FEM: a Comparative Study of Implementa-tion Strategies, International Journal for Numerical Methods in Fluids, vol. 66, pp. 1037-1067, Jul 2011

[B6.] M.C. Gosselin, S. Kühn, P. Crespo-Valero, E. Cherubini, M. Zefferer, A. Christ, N. Kuster Estimation of Head-Tissue Specific Exposure from Mobile Phones Based on Measurements in the Homogeneous SAM Head, Bioelectromagnetics, vol. 32, pp. 493-505, Sep 2011

[B7.] M.C. Gosselin, G. Vermeeren, S. Kühn, V. Kellerman, S. Benkler, T. Uusitupa, W. Joseph, A. Gati, J. Wiart, F. Meyer, L. Martens, T. Nojima, T. Hikaje, Q. Balzano, A. Christ, N. Kuster Estimation Formulas for the Specific Absorption Rate in Humans Exposed to Base Station Antennas, IEEE Transactions on Electromagnetic Compatibility, vol. 53, no. 4, pp. 909-922, Nov 2011

[B8.] S. Hirsch, D. Szczerba, B. Lloyd, M. Bajka, N. Kuster, G. Székely Mechano-Chemical Simulation of a Solid Tumor Dynamics for Therapy Outcome Predictions, International Journal for Multiscale Computational Engineering, vol. 9, pp. 231-241, Aug 2011

[B9.] A. Kyriacou, A. Christ, E. Neufeld, N. Kuster Local tissue temperature increase of a generic implant compared to the basic restrictions defined in safety guide-lines, Bioelectromagnetics, Nov 2011

92

[B10.] H. Lehmann, L. Pollara, S. Spichtig, S. Kühn, M. Wolf Head Exposure System for a Human Provocation Study to Assess the Possible Influence of UMTS-Like Electro-magnetic Fields on Cerebral Blood Circulation Using Near Infrared Imaging, Bioelectromagnetics, Aug 2011

[B11.] C.H. Li, M. Douglas, E. Ofli, B. Derat, S. Gabriel, N. Chavannes, N. Kuster Influence of the Hand on the Specific Absorption Rate in the Head, IEEE Transactions on Antennas and Propagation, Oct 2011

[B12.] A. Lowden, T. Akerstedt, M. Ingre, C. Wiholm, L. Hillert, N. Kuster, J.P. Nilsson, B. Arnetz Sleep After Mobile Phone Exposure in Subjects With Mobile Phone-Related Symptoms, Bioelectromagnetics, vol. 32, pp. 4-14, Jan 2011

[B13.] Z. Malecha, L. Miroslaw, T. Tomczak, Z. Koza, M. Matyka, W. Tarnawski, D. Szczerba GPU-Based Simulation of 3D Blood Flow in Abdominal Aorta Using OpenFOAM, Archives of Mechanics, vol. 63, pp. 137-161, Apr 2011

[B14.] M. Murbach, E. Cabot, E. Neufeld, M.C. Gosselin, A. Christ, K.P. Pruessmann, N. Kuster Local SAR Enhancements in Anatomically Correct Children and Adult Models as a Function of Position Within 1.5T MR Body Coil, Progress in Biophysics and Molecular Biology, vol. 107, no. 3, pp. 428-433, Dec 2011

[B15.] J. Nadakuduti, M. Douglas, M. Capstick, S. Kühn, N. Kuster Application of an Induced Field Sensor for Assessment of Electromagnetic Exposure from Compact Fluorescent Lamps, Bioelectromagnetics, Aug 2011

[B16.] E. Neufeld, M.C. Gosselin, M. Murbach, A. Christ, E. Cabot, N. Kuster Analysis of the Local Worst-Case SAR Exposure Caused by MRI Multitransmit Coils in Anatomical Models of the Human Body, Physics in Medicine and Biology, vol. 56, pp. 4649-4659, Aug 2011

[B17.] M.R. Schmid, S.P. Loughran, S. Regel, M. Murbach, A.B. Grunauer, T. Rusterholz, A. Bersagliere, N. Kuster, P. Achermann Sleep EEG Alterations: Effects of Different Pulse-Modulated Radio Frequency Electromagnetic Fields, Journal of Sleep Research, Apr 2011

93

Conference Presentations

IC and System Design and Test[D4.] S. Heinzle, P. Greisen, D. Gallup, C. Chen, D. Saner, A. Smolic, A. Burg, W. Matusik, M. Gross

Computational Stereo Camera System with Programmable Control Loop, ACM SIGGRAPH 2011, 7-11 Aug 2011

[D5.] P. Maechler, N. Felber, A. Burg Random Sampling ADC for Sparse Spectrum Sensing, European Signal Processing Conference (EUSIPCO), Barcelona, Spain, 29 Aug - 2 Sep 2011

[D6.] A. Smolic, S. Poulakos, S. Heinzle, P. Greisen, M. Lang, A. Hornung, M. Farre, N. Stefanoski, O. Wang, L. Schny-der, R. Monroy, M. Gross Disparity-Aware Stereo 3D Production Tools, Conference for Visual Media Production (CVMP), 16-17 Nov 2011

Analog and Mixed-Signal Design[A3.] Q. Huang, C. Dehollain, C. Enz

Platform Circuit Technology Underlying Heterogeneous Nano and Tera Systems, nano-tera annual meeting, Bern, Switzerland, 12-13 May 2011

[A4.] Q. Huang, C. Dehollain, C. Enz, T. Burger A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative, IEEE Date 2011, Grenoble, France, 14-18 Mar 2011

[A5.] C. Roth, A. Cevrero, C. Studer, Y. Leblebici, A. Burg Area, Throughput, and Energy-Efficiency Trade-offs in the VLSI Implementation of LDPC Decoders, IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 15-18 May 2011

Technology CAD[T9.] F.M. Bufler

TCAD Simulation of FinFETs, 1st Seminar ETH Zurich-CEA Grenoble, Zurich, Switzerland, 8 Jun 2011

[T10.] F.M. Bufler State-of-the-Art in TCAD Device Simulation, Tutorial on Modeling for More Moore Application at the European Solid-State Device Research Conference (ES-SDERC), Helsinki, Finland, 12 Sep 2011

[T11.] F.M. Bufler State-of-the-Art in TCAD Device Simulation, Seminar of the Science & Technology Department at IBM Research Center Zurich, Rüschlikon, Switzerland, 23 Nov 2011

[T12.] M. Ciappa, L. Mangiacapra, M. Stangoni, S. Ott Experimental methods for high resolution two-dimensional dose mapping in electron beam crosslinked cables, 16th International Meeting on Radiation Processing (IMRP), Montreal, Canada, 13-16 Jun 2011

[T13.] M. Luisier, T.B. Boykin, G. Klimeck, W. Fichtner Atomistic Nanoelectronic Device Engineering with Sustained Performances up to 1.44 PFlop/s, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC),, Seattle, WA, USA, 12-18 Nov 2011

[T14.] M. Luisier, M. Lundstrom, D.A. Antoniadis, J. Bokor Ultimate Device Scaling: Intrinsic Performance Comparisons of Carbon-based, InGaAs, and Si Field-Effect Tran-sistors for 5 nm Gate Length, International Electron Devices Meeting (IEDM), Washington DC, USA, 5-7 Dec 2011

[T15.] V. Peikert, A. Schenk A Wavelet Method to Solve High-dimensional Transport Equations in Semiconductor Devices, 11th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Osaka, Japan, 8-10 Sep 2011

[T16.] R. Rhyner, C. Bessire, L. De Michielis, A. Biswas, A. Schenk, H. Riel, A.M. Ionescu Enabling Energy Efficient Tunnel FET-CMOS Co-Design by Compact Modeling and Simulation, Nano-Tera Annual Meeting (Nano-Tera), Bern, Switzerland, 12-13 May 2011

[T17.] R. Rhyner, C. Bessire, A. Schenk Atomistic Simulation of Nanowire Esaki Diodes and Tunnel FETs, 1st Seminar ETH Zurich-CEA Grenoble, Zurich, Switzerland, 8 Jun 2011

94

[T18.] A. Schenk, R. Rhyner, M. Luisier, C. Bessire Analysis of Si, InAs, and Si-InAs Tunnel Diodes and Tunnel FETs Using Different Transport Models, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Osaka, Japan, 8-10 Sep 2011

Physical Characterization[P7.] M. Ciappa

Synthesis of Scanning Electron Microscopy Images for the Metrology of Critical Dimensions, Raith/ETH Zurich Workshop on Electron Beam Lithography 2011, Zurich, Switzerland, 15 Nov 2011

[P8.] M. Ciappa, L. Mangiacapra, M. Stangoni, S. Ott, W. Fichtner Design of optimum electron beam irradiation processes for the reliability of electric cables used in critical applica-tions, 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, 3-7 Oct 2011

[P9.] A. Esposito, M. Ciappa, W. Fichtner Synthesis of scanning electron microscopy images by high performance computing for the metrology of advanced CMOS processes, 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, 3-7 Oct 2011

[P10.] V. Malandruccolo, M. Ciappa, W. Fichtner In situ screening techniques for defective oxides in devices for automotive applications, 2011 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 10-14 Apr 2011

Bio-Electromagnetics and Electromagnetic Compatibility[B18.] J.F. Bakker, A. Christ, E. Neufeld, M. Paulides, N. Kuster, G.C. van Rhoon

Interactions of electromagnetic fields and the human body: Tools for predicting induced absorption, currents and temperature rise, Poster Presentation at 3rd Dutch BioMedical Engineering Conference 2011 (BME '11), Egmond aan Zee, Nether-lands, 20-21 Jan 2011

[B19.] J.F. Bakker, A. Christ, E. Neufeld, M. Paulides, N. Kuster, G.C. van Rhoon Children exposed to radio frequency fields: Numerical assessment of induced absorption and temperature in-crease, 3rd Dutch BioMedical Engineering Conference 2011 (BME 2011), Egmond aan Zee, Netherlands, 20-21 Jan 2011

[B20.] J. Bakker, M. Paulides, E. Neufeld, A. Christ, N. Kuster, G. van Rhoon Assessment of the induced SAR and peak temperature increase in children exposed to electromagnetic fields at the ICNIRP reference levels, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B21.] E. Cabot, T. Lloyd, A. Christ, W. Kainz, M. Douglas, G. Stenzel, S. Wedan, N. Kuster MRI safety assessment of a generic deep brain stimulator, XXX General Assembly and Scientific Symposium of International Union of Radio Science (URSI GASS 2011), Istanbul, Turkey, 13-20 Aug 2011

[B22.] E. Cabot, T. Lloyd, A. Christ, G. Stenzel, W. Kainz, S. Wedan, N. Kuster RF safety assessment of a generic deep brain stimulator during 1.5T MRI exposure, Electronic Poster Presentation at 19th Annual Meeting of the International Society for Magnetic Resonance in Medicine (ISMRM 2011), Montreal, Canada, 7-13 May 2011

[B23.] M. Capstick, Y. Gong, N. Kuster, C. Dasenbrock Desktop reverberation chamber for small scale in-vivo radio frequency exposure experiments, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B24.] M. Capstick, Y. Gong, N. Kuster, P. Schär 2.45GHz in-vitro exposure system for use during live cell imaging, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B25.] X.L. Chen, S. Benkler, N. Chavannes, N. Kuster Numerical dosimetry for power frequency electric field exposure to the human body, 2011 IEEE International Symposium on Antennas and Propagation and USNC/URSI National Radio Science Meet-ing (AP-S/URSI 2011), Spokane, WA, USA, 3-9 Jul 2011

95

[B26.] X.L. Chen, N. Kuster, Y.C. Tan, N. Chavannes The design of a miniature antenna for wi-fi enabled memory card, 2011 IEEE International Symposium on Antennas and Propagation and USNC/URSI National Radio Science Meeting (AP-S/URSI 2011), Spokane, WA, USA, 3-9 Jul 2011

[B27.] A. Christ, M.G. Douglas, J. Roman, E.B. Cooper, A.P. Sample, J.R. Smith, N. Kuster Numerical electromagnetic analysis of human exposure for wireless power transfer systems, 10th International Conference of the European Bioelectromagnetics Association (EBEA 2011), Rome, Italy, 21-24 Feb 2011

[B28.] B. Derat, S. Gabriel, M.G. Douglas, N. Kuster A measurement interlab for investigating the hand effect on head SAR, Loughorough Antennas & Propagation Conference 2011 (LAPC 2011), Loughborough, UK, 15-17 Nov 2011

[B29.] M. Douglas, S. Gabriel, C. Bucher, D. Iliev, J. Kastrati, C. Leubler, M. Meili, K. Pokovic, N. Kuster Fast SAR methods for electromagnetic exposure evaluation of wireless devices, 5th European Conference on Antennas and Propagation (EuCAP 2011), Rome, Italy, 11-15 Apr 2011

[B30.] M. Douglas, S. Gabriel, C. Bucher, D. Iliev, J. Kastrati, C. Leubler, M. Meili, K. Pokovic, N. Kuster Specific absorption rate measurement of wireless devices using fast SAR methods, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B31.] M. Douglas, J. Nadakuduti, M. Wild, S. Kühn, M. Capstick, N. Kuster A european initiative to develop procedures and instrumentation for worker's electromagnetic safety WEMS, XXX General Assembly and Scientific Symposium of International Union of Radio Science (URSI GASS 2011), Istanbul, Turkey, 13-20 Aug 2011

[B32.] M. Douglas, J. Nadakuduti, M. Wild, S. Kühn, M. Capstick, N. Kuster Worker electromagnetic safety WEMS project: overview and results, EMC Europe 2011 Conference, York, UK, 26-30 Sep 2011

[B33.] Y. Gong, M. Capstick, N. Kuster An HF exposure system for mice with improved efficiency, Poster Presentation at 10th International Conference of the European Bioelectromagnetics Association (EBEA 2011), Rome, Italy, 21-24 Feb 2011

[B34.] M.C. Gosselin, A. Christ, S. Kühn, N. Kuster Magnitude & Distribution of Head & Brain Tissue-Specific Exposure from Mobile Phones, COST BM0704 workshop - Dosimetry Meet Epidemiology Program, Paris, France, 30 Nov - 1 Dec 2011

[B35.] M.C. Gosselin, P. Crespo-Valero, S. Kühn, N. Kuster Assessment of Brain Region Specific Exposure Using Standard SAR Test Systems, COST BM0704 workshop - Dosimetry Meet Epidemiology Program, Paris, France, 30 Nov - 1 Dec 2011

[B36.] M.C. Gosselin, P. Crespo-Valero, S. Kuehn, N. Kuster Implementation and experimental validation of a brain-region specific exposure estimation in SAR measurement systems, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B37.] M.C. Gosselin, E. Neufeld, M. Murbach, A. Christ, E. Cabot, N. Kuster Analysis of the SAR enhancement from a multitransmit coil, 10th International Conference of the European Bioelectromagnetics Association (EBEA 2011), Rome, Italy, 21-24 Feb 2011

[B38.] S. Kühn Novel approaches in exposure assessment and dosimetry of epidemiological and human laboratory studies, 10th International Conference of the European Bioelectromagnetics Association (EBEA 2011), Rome, Italy, 21-24 Feb 2011

[B39.] N. Kuster Possible Conclusions & Perspective for Future Research, 2011 International Scientific Conference on Electromagnetic Fields and Public Health, Brussels, Belgium, 16-17 Nov 2011

[B40.] N. Kuster ARIMMORA and IT'IS, Scientific Advisory Committee (SAC) meeting of the EMF and RF Health Assessment and Safety Program at the Electric Power Research Institute, Phoenix, Arizona, USA, 25-26 Oct 2011

[B41.] N. Kuster, M. Capstick Human exposure to induced fields from industrial and domestic induction cooker appliances, EMC Europe 2011 Conference, York, UK, 26-30 Sep 2011

96

[B42.] N. Kuster, S. Kuehn, G. Pedersen, T. Samaras, G. Vermeeren, L. Martens, J. Andersen Exposure from WiFi: Levels of exposure, challenges in exposure assessment and compliance testing, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B43.] A. Kyriacou, E. Neufeld, W. Wiedemair, B. Werner, V. Kurtcuoglu, N. Kuster Modeling tools for HIFU and induced in-vivo effects, 28th Annual Meeting of the Society for Thermal Medicine (STM 2011), New Orleans, LA, USA, 29 Apr - 2 May 2011

[B44.] A. Kyriacou, E. Neufeld, W. Wiedemair, B. Werner, V. Kurtcuoglu, N. Kuster Computational framework for HIFU/FUS modelling and induced in-vivo effects, 27th Annual Meeting of the European Society for Hyperthermic Oncology (ESHO 2011), Aarhus, Denmark, 26-28 May 2011

[B45.] C.H. Li, M. Douglas, E. Ofli, N. Chavannes, N. Kuster Absorption of radiofrequency electromagnetic fields in the hand due to partial-body resonances, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, N, Canada, 12-17 Jun 2011

[B46.] C.H. Li, M. Douglas, E. Ofli, B. Derat, N. Kuster User’s hand effect on the specific absorption rate in the head, 2011 IEEE International Symposium on Antennas and Propagation and USNC/URSI National Radio Science Meet-ing (AP-S/URSI 2011), Spokane, WA, USA, 3-9 Jul 2011

[B47.] S. Loughran, D. Benz, M. Schmid, M. Murbach, N. Kuster, P. Achermann Effects of pulse-modulated RF EMF on the human brain: Sensitivity in early adolescence, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B48.] M. Murbach, E. Neufeld, M.C. Gosselin, A. Christ, E. Cabot, N. Kuster Temperature, incident field and b1+ comparison in MR simulation and measurement, using a detailed anatomical model, 10th International Conference of the European Bioelectromagnetics Association (EBEA 2011), Rome, Italy, 21-24 Feb 2011

[B49.] J. Nadakuduti, M. Douglas, P. Crespo-Valero, N. Kuster Comparison of different safety standards in terms of human exposure to electric and magnetic fields at 100 kHz, Poster Presentation at 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B50.] J. Nadakuduti, M. Douglas, M. Wild, S. Kühn, M. Capstick, N. Kuster Exposure of railway workers to low frequency electromagnetic fields, EMC Europe 2011 Conference, York, UK, 26-30 Sep 2011

[B51.] J. Nadakuduti, M. Douglas, M. Wild, S. Kühn, M. Capstick, N. Kuster The development of novel sensors for assessment of human exposure to electromagnetic fields up to 10 MHz, EMC Europe 2011 Conference, York, UK, 26-30 Sep 2011

[B52.] J. Nadakuduti, M. Fehr, M. Douglas, S. Kühn, K. Pokovic, N. Kuster CCDF model for predicting the dosimetric probe response to complex modulation communication signals, Poster Presentation at 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B53.] E. Neufeld, M. Fuetterer, A. Kyriacou, M. Capstick, N. Kuster Fast estimation of SAR induced heating, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B54.] E. Neufeld, M. Fuetterer, A. Kyriacou, N. Chavannes, N. Kuster Fast SAR to temperature increase estimation, 2011 IEEE International Symposium on Antennas and Propagation and USNC/URSI National Radio Science Meet-ing (AP-S/URSI 2011), Spokane, WA, USA, 3-9 Jul 2011

[B55.] E. Neufeld, M.C. Gosselin, M. Murbach, A. Christ, E. Cabot, N. Chavannes, N. Kuster Analysis of the SAR enhancement from a multitransmit coil, 2011 IEEE International Symposium on Antennas and Propagation and USNC/URSI National Radio Science Meet-ing (AP-S/URSI 2011), Spokane, WA, USA, 3-9 Jul 2011

[B56.] E. Neufeld, D. Szczerba, B. Bühlmann, M. Zefferer, N. Kuster Fast interpolation based morphing of whole body human models, Poster Presentation at XXX General Assembly and Scientific Symposium of International Union of Radio Science (URSI GASS 2011), Istanbul, Turkey, 13-20 Aug 2011

[B57.] E. Neufeld, D. Szczerba, M. Zefferer, B. Buehlmann, M. Capstick, N. Kuster FEM and interpolation based morphing of whole body human models, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

97

[B58.] E. Neufeld, D. Szczerba, M. Zefferer, M.C. Gosselin, N. Kuster The 'Virtual Population': Latest developments and novel techniques, 3rd International Workshop on Computational Phantoms for Radiation Protection Imaging and Radiotherapy, Bei-jing, China, 8-9 Aug 2011

[B59.] R. Nylund, N. Kuster, D. Leszczynski Analysis of proteome in human endothelial cells exposed to the 1800 MHz mobile phone radiation, Poster Presentation at 10th International Conference of the European Bioelectromagnetics Association (EBEA 2011), Rome, Italy, 21-24 Feb 2011

[B60.] S. Schild, N. Chavannes, N. Kuster Advances in FDTD for dispersive and high frequency simulations, Poster Presentation at 5th European Conference on Antennas and Propagation (EuCAP 2011), Rome, Italy, 11-15 Apr 2011

[B61.] S. Schild, N. Chavannes, N. Kuster, E. Okoniewska, D. Pasalic, M. Okoniewski Advanced surface impedance boundary condition in EM-FDTD, Poster Presentation at 2011 IEEE International Symposium on Antennas and Propagation and USNC/URSI Na-tional Radio Science Meeting (AP-S/URSI 2011), Spokane, WA, USA, 3-9 Jul 2011

[B62.] M. Schmid, S. Loughran, M. Murbach, C. Lustenberger, N. Kuster, P. Achermann Effects of pulse-modulated RF EMF versus pulsed magnetic fields on the human sleep EEG, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B63.] T.P. Stefanski, N. Chavannes, N. Kuster Multi-GPU accelerated finite-difference time-domain solver in open computing language, 29th Progress In Electromagnetics Research Symposium (PIERS 2011), Marrakesh, Morocco, 20-23 Mar 2011

[B64.] T.P. Stefanski, N. Chavannes, N. Kuster Performance evaluation of the multi-device openCL FDTD solver, 5th European Conference on Antennas and Propagation (EuCAP 2011), Rome, Italy, 11-15 Apr 2011

[B65.] T. Stefanski, N. Chavannes, N. Kuster Multi-device openCL accelerated FDTD solver, Poster Presentation at 2011 IEEE International Symposium on Antennas and Propagation and USNC/URSI Na-tional Radio Science Meeting (AP-S/URSI 2011), Spokane, WA, USA, 3-9 Jul 2011

[B66.] D. Szczerba, E. Neufeld, M. Zefferer, B. Bühlmann, N. Kuster FEM based morphing of whole body human models, XXX General Assembly and Scientific Symposium of International Union of Radio Science (URSI GASS 2011), Istanbul, Turkey, 13-20 Aug 2011

[B67.] G. van Rhoon, T. Samaras, N. Kuster Advantages & disadvantages of CEM43 for EM safety; A new basis for EM standards?, 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Scotia, Canada, 12-17 Jun 2011

[B68.] E. Zastrow, E. Cabot, A. Christ, N. Kuster Experimental phantoms for the assessment of medical implant leads induced SAR under a linear-phase incident field condition, General Assembly and Scientific Symposium of International Union of Radio Science (URSI GASS 2011), Istanbul, Turkey, 13-20 Aug 2011

[B69.] J. Zimmerman, F. Costa, I. Brezovich, N. Kuster, M. Pennison, D. Absher, R. Myers, A. Barbault, B. Pasche Amplitude-modulated electromagnetic fields inhibit cell growth and cause molecular and structural changes in hepatocellular carcinoma HCC cells, Poster Presentation at 33rd Annual Meeting of the Bioelectromagnetics Society (BEMS2011), Halifax, Nova Sco-tia, Canada, 12-17 Jun 2011