Gianluigi De GeronimoMicroelectronics Team, Instrumentation Division Brookhaven National Laboratory

VMM ASIC―

Status Report - April 2013

Outline

• VMM1 - tested• architecture and results (brief)• issues

• VMM2 - in design• architecture• fixes (issues from VMM1)• new features• circuit details• pinout and packaging (tentative)• schedule (tentative)

2

3

CA shaper

logicor

neighbor

addr.channel (64x)

TGC out (ToT, TtP) x 16

ART (flag, parallel address)

logic

mux

mux

mux

analog ampl

analog time

parallel addr

mux clock

time

peak

Architecture of VMM1

• dual polarity, adj. gain (0.5-9 mV/fC), adj. peaktime (25-200 ns), DDF shaper• discriminator with sub-hysteresis and neighboring (channel and chip)• address of first event in real time at dedicated output (ART)• 16 direct timing outputs: time-over-threshold or time-to-peak• peak detector, time detector <1 ns• multiplexing with sparse readout and smart token passing (channel and chip)• threshold & pulse generator, analog monitor, mask, temperature sensor, 600mV BGR, 600mV LVDS• power 4.5 mW/ch, size 6 x 8.4 mm², process IBM CMOS 130nm 1.2V, test structures

_

+

Chold

• peak• timing at peak• analog memory • offsets cancel• high drive

out

Multi-Phase Peak Detector

4

timing

• charge resolution ENC < 5,000 e- at 25 ns, 200 pF• analog dynamic range Qmax / ENC > 12,000 → DDF

Charge

1p 10p 100p 200p 1n100

1k

5k

10k100ns, 9mV/fC50ns, 9mV/fC25ns, 9mV/fC

200ns, 9mV/fC200ns, 1mV/fC200ns, 0.5mV/fC

EN

C [e

lect

rons

]

Input capacitance [F]

lines: theoreticalsymbols: measured with actual gain

0.0 0.2 0.4 0.6 0.8 1.0100p

1n

10n

200pF, 200ns 200pF, 100ns 200pF, 50ns 200pF, 25ns 2pF, 25ns time walk

200pF, 25ns

Tim

ing

reso

lutio

n, ti

me

wal

k [s

]

Output pulse amplitude [V]

solid line: theor. 200pF, 25nssymbols: measurednominal gain 9mV/fCtiming ramp 125ns

Timing

σt ≈ENC τP

Q

• timing resolution < 1 ns (at peak-detect) λP

ρP

≈ 0.3-0.8

Resolution Measurements

5

Peak vs charge Linearity error

• discriminating few mV from baseline, in sub-hysteresis mode

0 200 400 600 800 10000.0

0.2

0.4

0.6

0.8

1.0

1.2Input capacitance ~10 pFPeaking time 50 nsGain 1 mV/fC

Out

put p

eak

[V]

Input charge [fC]

Signal baseline

• linearity error < 1% full 1V swing

1 10 100 1000-2

-1

0

1

2Input capacitance ~10 pFPeaking time 50 nsGain 1 mV/fC

Line

arity

err

or [%

]

Input charge [fC]

0 2 4 6 8 10 12 14 16 18 200.180

0.185

0.190

0.195

0.200

0.205

0.210

Threshold without sub-hysteresis

Noise floor

Signal baseline

Input capacitance ~10 pFPeaking time 50 nsGain 1 mV/fC

Out

put p

eak

[V]

Input charge [fC]

Peak Measurements

6

7

CA shaper

logicor

neighbor

addr.channel (64x)

• issues in VMM1 → fixes in VMM2

TGC out (ToT, TtP) x 16

ART (flag, parallel address)

logic

mux

mux

mux

analog ampl

analog time

parallel addr

mux clock

time

peak

Note: VMM2 will maintain all the functionalities of VMM1

Architecture of VMM2

8

• power distribution• voltage drop across power and ground wire-bonds

• front-end• stability at large capacitance (affects peaking time and gain)• saturation at high rate• leakage from ESD protection (disables positive charge operation)• test pulse linearity, settling time, range (needs optimization)• ESD protection (may need optimization)

• discrimination• digital pick-up in sub-hysteresis (affects low amplitudes)• threshold dispersion and trimming (needs optimization)

• signal processing• peak detector stability (affects low amplitudes)

• direct timing (TGC)• digital pick-up on pulse tail• delay and time walk (needs optimization)• possible locking in TtP mode

• test and readout• internal reset optimization• dedicated input for test-pulse strobe

Issues in VMM1 → Fixes in VMM2

9

CA shaper

logicor

neighbor

addr.channel (64x)

trigger

• fixes

6b ADC

TGC out (ToT, TtP, PtT, 6bADC) x 64TGC clock (160 MHz)TGC out (ToT, TtP) x 16

ART (flag, parallel address)

time

peak

• additional gain settings (TGC, MM) • external trigger• TGC: 64 outputs, 6-bit ADC 25ns serialized with dedicated clock

Note: VMM2 will maintain all the functionalities of VMM1

Architecture of VMM2

logic

mux

mux

mux

analog ampl

analog time

parallel addr

mux clock

ADC not fast enough for application:need a current-output peak stretcher

year 200764 channelsPDD 500ns, 6-bit

• voltage mode• clock-less• peak-detect• real-time• high power

comparators and logic

V1

V2

V3

Vn

quantization result(n-1 windows)

pulse (current signal I)

I

i1 i2 in-1

digital thermometer

• current mode• clock-less• peak-detect• real-time• low power

0 1 2 3 4 5 60.0

0.5

1.0

1.5

2.0

2.5

0

10

20

30

40

50

60

An

alo

g P

uls

e A

mp

litu

de

[V

]

Injected Charge [fC]

Baseline ~ 250 mV, Threshold ~ 360 mV

Peaking time 1 µsNo external capacitanceChannel 36

PD

AD

Co

un

ts (

Ave

rag

e)

Clock-Less PD-ADC

10

+_

Chold

Rhold

Iout

timing

• offsets still an issue• good for 6-bit resolution

Current-Output Peak Detector

11

12

25ns 50ns 75ns 100ns 125ns 150ns 175ns 200ns

CK

charge event

analog pulse

OUT

peak-found

end of conversion

end of encoding

reset end (ready for next event)

timing edge D5 - D0

• 160 MHz external clock• Conversion ends ~25ns after peak-found, programmable• Dead time from charge event <100ns• Amplitude data D5-D0 shifted at each clock edge

TGC ADC and Serializer

13

CA shaper

logicor

neighbor

addr.channel (64x)

trigger

• fixes

6b ADC

TGC out (ToT, TtP, PtT, 6bADC) x 64TGC clock (160 MHz)ART (flag, serial address)ART clock (160 MHz)ART (flag, parallel address)

time

peak

• additional gain settings • external trigger• TGC: 64 outputs, PtT, 6-bit ADC 25ns serial with dedicated clock• ART: flag and address serialized with dedicated clock

Note: VMM2 will maintain all the functionalities of VMM1

Architecture of VMM2

logic

mux

mux

mux

analog ampl

analog time

parallel addr

mux clock

14

25ns 50ns 75ns 100ns 125ns 150ns 175ns 200ns

CK

charge event

analog pulse

ART

peak-found

FL D5 - D0

reset

• 160 MHz external clock• Flag and address serialized• Address data D5-D0 shifted at each clock edge

ART Serializer

15

CA shaper

logicor

neighbor

addr.channel (64x)

trigger

• fixes

6b ADC

TGC out (ToT, TtP, PtT, 6bADC) x 64TGC clock (160 MHz)

spr 1-bitthr 1-bit

addr 6-bitampl 10-bittime 10-bitBC 12-bitL1A 8-bit

ART (flag, serial address)ART clock (160 MHz)

12b BC

Gray-code counters

DATA 48-bit2-bit

FIFO

10b ADC

10b ADC

DATA syncBC clock (40 MHz)L1A trigger

DATA clock (80 MHz)

8b L1A

logic

logic

mux

mux

mux

analog ampl

analog time

parallel addr

mux clock

time

peak

• 2-bit DATA output with dedicated sync and 80 MHz clock

• additional gain settings • external trigger• TGC: 64 outputs, PtT, 6-bit ADC 25ns serial with dedicated clock• ART: flag and address serialized with dedicated clock• 10-bit ADCs 200ns for amplitude and timing, digital

memories• Gray-code counters for BC-ID (12-bit) and L1A-ID (8-bit)Note: VMM2 will maintain all the functionalities of VMM1

Architecture of VMM2

+_

Rhold

Iout_low-resol.(6-7 bit)

Iout_high-resolution(10-11 bit)

• switch to buffer• offsets cancel• good for 10-bit resolution

Multi-Phase Current-Output Peak Detector

16

17

• front-end• additional gain settings to match signal sfrom TGC and MicroMegas• option to route monitors to PDO, TDO outputs for baseline acquisition

• signal processing• multi-phase current-output peak detector 1

• ADC 10-bit 200ns on PDO and TDO 1

• digital buffer, multiplexing, and logic for continuous acquisition 1

• counters and latches for BC-ID (12-bit) and L1A-ID (8-bit) 1

• ART (address in real time)• serialized flag and address

• trigger• external trigger for non-data-driven operation

• direct timing (TGC)• from 16 to 64 channels (initially packaging-limited to 32)• pulse at peak (like ART)• ADC 10-bit 25ns with serial output after flag 1

• fixed ramp discharge (PtT) 2

• layout and packaging• pads count from 176 to 208• dual-mode wire-bond (MM, TGC)

• radiation tolerance• off-ITAR switch circuit (CERN), optimization 2

1 Major developments2 If time allows

New Features

Current-Output Peak Detector - Schematics

Additional power dissipation ~ 150 µW

18

TGC 6-bit ADC - Schematics

19

Additional power dissipation ~ 600 µW (similar for 10-bit 200ns ADC)

COPD, 6b-ADC, Serialization - Simulation

20projected channel size (total) ~ 7mm (+1.5 mm) 6b 10b

• programmable conversion time (3-bit, 1 to 8 clocks from peak)

• programmable serialization (single or dual edge clock)• programmable baseline subtraction (3-bit)

MSB 1 0 0 0 1 1 LSB (dual edge mode)

5 ck from peak

~500mV amplitude

threshold

peak found

conversion current

reset160 MHz clock

LQFP208

Pinout and Packaging

21

projected die size ~ 9mm x 9mm

task statusfixes in progress ~50%external trigger completeART serializer in progress ~30%current-output PD complete6-bit ADC and serializer complete10-bit ADC and digital buffer in progress 70%counters and latches queuedanalog gain queuedphysical layout June-July 2013fabrication August 2013 (tentative)

Schedule and Status

Venetios Polychronakos (BNL)Neena Nambiar, Emerson Vernon, Alessio D’Andragora, Jack Fried (BNL)

Jessica Metcalfe (BNL & CERN), Ken A. Johns, Sarah L. Jones (University of Arizona, USA)Nachman Lupu, Lorne Levinson (Technion Haifa, Israel)Georgie Iakovidis (BNL, USA and NTU Athens, Grece),

ATLAS Collaboration, CERN

Acknowledgment

22