interconnect intermittency detection with sj bist™

Interconnect Intermittency Detection withSJ BIST™

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com 2

Agenda

What is SJ BIST? Interconnect Reliability – Background SJ BIST Basics SJ BIST Operation SJ BIST Application Summary & Conclusions


What is SJ BIST?

SJ BIST = Solder Joint Built-in Self-Test Original solution enabling the verification and

validation of solder joint interconnect reliability Originally developed for FPGA-BGA applications Can be applied to validate the integrity and reliability

of any type of interconnection


BGA – PCB Relationship: Die, package, wiring, pins


Defects: Location of Cracks/Fractures Corner pins likely to fail first

High stress areas, and corners of the BGA package and die


Solder Balls, Cracks and Fractures


Fatigue fractures (cracks) are caused by thermo-mechanical stress/strain

During periods of high stress, fractured bumps tend to momentarily open and cause intermittent faults of high resistance for periods of ns to µs

Over time, contamination and oxidation films occur on the fractured faces: the effective contact area becomes smaller and smaller

Transient opens can be detected by event detectors

Mechanisms of Failure

Oxide-covered

area


Mechanics of Failure

HALT results - Pulled FPGA – Damaged Solder Balls Undamaged

Damaged: Cracked Cracked, not detectable Fractured, detectable


Fractures and Intermittency


Defects: Fractures & Intermittency


Faults are intermittent: confirmed by CAVE, Auburn Univ., German automobile manufacturer, BAE Systems and other firms Occur during periods of increasing strain Multiple occurrences per cycle Industry standard: 200 ohms +, 200 ns +

Intermittent Faults


With present technology, reported electronic system problems in the field cannot be duplicated at the service point or in the lab

“Three/Four-letter” words (CND, NTF, RTOK) Could Not Duplicate (CND) No Trouble Found (NTF) Retest OK (RTOK)

50 to 80% of these CND/NTF/RTOK problem categories are reported by service personnel.

Major culprits – Solder joint intermittencies and NBTI effects in deep submicron ICs

Intermittencies


Objectives Detection of impending interconnect failures Unique in-situ testing in operating circuits Technology-independent

Feature and Benefits Detects ball fractures prior to catastrophic failure of

circuit Provides actionable maintenance data Independently tested and verified Endorsed by leading automotive and aerospace

customers

SJ BIST Objectives & Features


SJ BIST runs concurrently with host circuit SJ BIST requires dedicated I/0

SJ BIST Implementation

SJ BIST

Functional Circuitry

Functional I/O SJ BIST I/OSJ BIST Control




SJ BIST




Similar to a simple memory test: W0 – R0; W1 – R1 Runs concurrently with host circuit Verilog/VHDL core (patent pending)

Each core tests two I/O pins Pins are externally wired together Small capacitor connected to the two pins

SJ BIST™ Operation


SJ BIST Operation

Writes a “1” and reads a “1”

Healthy Solder Joint


SJ BIST Operation

Writes a “1” butreads a “0”

Faulty Solder Joint


Function of operating frequency & desired sensitivity

SJ BIST Capacitor

100 Ohm

300 Ohm

10 Ohm


SJ BIST Application

SJ BIST

Inte

rcon

nect

pat

h

On-chip interconnects

Die to substrate (incl. bumps)

Die to board (incl. bumps & balls)

Requirement:Interconnect path dedicated for SJ BIST


SJ BIST Application

Testing On-chip Interconnect

Need for dedicated on-chip path between SJ BIST™ Observation pins


SJ BIST Application

Testing Die to Substrate


SJ BIST ApplicationTesting Die to Board


LVTTL − Low Voltage TTL

SJ BIST Simulation Results

InputLow

≤0.8V

High≥2.0V

OutputLow

≤0.4VHigh

≥2.4V



Time

0s 20ns 40ns 60ns 80nsV(V1:+) V(C1:2)

0V

1.0V

2.0V

3.0V

Time

0s 20ns 40ns 60ns 80nsV(V1:+) V(C1:2)

0V

1.0V

2.0V

3.0V

Capacitor charging

Clock = 50 MHz Charge pulse t=20 ns C1=57 pF (47 pF capacitor)+(10 pF of the

I/O port and wires) The time constant =R1·C1 and t

determine the charge voltage In the prohibited zone (0.8 to 2.0 V) there

is guaranteed detection

R1=175Ω R1=700Ω

)( 1110CRt

eUUC



Voltage across the test capacitor

One bump is connected with a 700 Ω

resistor. So the time constant =R1·C1 increases and the test capacitor is charged with only 0.8 V.

A logical ‘0‘ instead of a ‘1‘ is read, a fault is detected.

700 Ω Fault: Same as electrical model and PSPICE simulation


SJ BIST specifications Sensitivity: as least as low as 100 Ω Resolution: guaranteed two clock periods Detectable intermittency: as short as ½ of a clock period 50 MHz clock

40-ns guaranteed detection 10-ns detection possible

SJ BIST Application Results

100 Ω fault1 MHz clock


Independent test results by German automotive firm Confirmed the same results as obtained by Ridgetop Group No false alarms

SJ BIST Application Results


Input (Control) Clock, Enable & Reset

Test Pins 2 bidirectional I/O pins: TP0 & TP1

Output (to host) Failure Flags (fault was detected on TP0/TP1) Active fault flags (fault is active on TP0/TP1 at the

moment of interrogation of SJ BIST) Failure counts (2 8-bit values related to number of

faults detected on TP0 and TP1 respectively)

SJ BIST I/O


Available as: Verilog/VHDL core Microcontroller code

Requires dedicated I/O + capacitor Runs concurrently Interconnect reliability verification

Process qualification Lifetime observation

SJ BIST Summary


SJ BIST HALT for Process Qualification


Contact Information

Hans ManhaeveOffice: +32 50 [email protected]

Ridgetop Group, Inc.

3580 West Ina Rd.Tucson, AZ 85741

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com34

Ridgetop Products and Services

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

Sentinel Silicon Prognostic CoresNBTITDDBHot CarrierRadiation Exposure

Ridgetop SPI Products & Services

InstaCell™ Mixed Signal CoresADC – Analog to Digital ConvertersDAC – Digital to Analog ConvertersOp Amps, References ,and

Comparators

nanoDFM Verification MonitorsPDKChek™ - Die-Level Process

MonitorsMismatch: ∆VT,∆I(on), ∆R, ∆C,

YieldMaxx™ - Die-Level Variation Visualization

InstaBIST™ Test CellsSJ-BIST BGA Solder Joint Built-in TestADC-BIST Self-testing Data Converters

ProChek Semiconductor Process Characterization System

- NBTI - PBTI- TDDB - Hot Carrier- Radiation - Stress Migration- VT Degradation - Electromigration

Q-Star Test™ Current MonitorsIDDQ

IDDT

ISSQ

On-chip & On-boardSingle- & multi-site

Design ServicesASICsCoresRadiation-hardeningMEMSCustom instruments

TopAct® Radiation TransportAnalysis Acceleration


Advantages of PDKChek

DLPM

Scribe LineTransistor

PDKChek Scribe Line Transistors

Uses test structure on the host die

Requires additional test fixture

Testing can occur pre- and post-packaging

Lost when wafers are sliced

Performs quick production test

Delicate probe measurement: inaccurate and time-consuming

Measures parameters that are useful to the designer

May not directly measure important parameters; needs additional characterization

Data is application-specific

DUTs are extracted from the host designPDK models may not provide accurate predictions

36


Example: Product Yield Analysis of 90nm Process

PDKChek embedded in the ADC

Example of GDSII Layout for the Ridgetop 14-bit Pipeline ADC

37


Chip-Level Prognostic Solutions and Applications

Products described herein are covered by U.S. patents:

7,239,163 7,196,294 7,271,608.

Other patents are pending.

Prognostic Cell Library Some Target Applications

NBTI Cell Flash memory, SRAM

HCI CellADCs, biasing circuits, analog, and slow-speed switching circuits

TDDB Cell Flash memory

Metal Migration Cell Damascene process stress, high current density application


What is ProChek?

ProChek is an innovative low-cost technique to very rapidly characterize the intrinsic reliability of deep submicron nanotechnology CMOS processes (bulk CMOS, SOI and SiGe)

39


Characteristics of ProChek

Targets bulk CMOS, SOI, SiGe reliability concerns NBTI / PBTI, TDDB, HC, EM, SM, TID

Test Coupon As little as 1 * 1 mm chip area MPW for lower cost 32 – 1024 devices can be tested in parallel for maximum throughput On-chip per transistor heaters to 325 °C, greatly reducing test time Synthesizable (except for on-chip heaters) to speed deployment

Benchtop Tester Fully programmable test conditions cover DC and AC stress cases Portable and compact ATE not needed

Host Controller Easy-to-use software GUI Rich suite of built-in reliability test templates Data processing capabilities

40


The cores provided by Ridgetop are "Silicon Proven" and have documented reports available. Ridgetop has designed cores for use in the IBM, TSMC, and AMI processes.

Analog-to-Digital Converter (ADC) Cores Digital-to-Analog Converter (DAC) Cores Bandgap Reference (BGR) Core Op-amp Core

InstaCell™ IP Core Library


Ridgetop maintains a complete Cadence design flow, and has designed circuitry down to the 45 nm process node. Ridgetop also has a line of predesigned and characterized IP blocks that can be used to accelerate the time-to-market for your systems. Examples include precision bandgap references, op-amps, comparators, ADCs, DACs and test structures.Our design services include:

Analog/mixed-signal and gate array integrated circuits with varying process nodes of 0.5 μm down to 45 nm

High-speed, high performance, high linearity ADC and DAC design Fuel Cell and Battery Management System components FPGA-based designs, from basic specification to gate level, with timing analysis and

programming IP blocks of specialized functionality Modeling and simulation Completion of back-end design from existing EDIF/SPICE to GDSII layout Rescaling “legacy” designs to smaller process geometries Radiation-hardened/foundry-specific designs

Design Services


Q-Star Test

IDDQ ,IDDT, ISSQ and other precision current measurement instruments for characterization and test

On-board modules and on-chip sensors

Test and DFT consulting and training services

70 semiconductor companies and 700 instruments installed

Developed by Ridgetop Europe


44

Q-Star Test Measurement Solutions

Static (Quiescent) Current Measurement Instruments (IDDQ/ISSQ) Standard and advanced IDDQ tests Stand-by current measurements Power-down current measurements Bias current measurements Average current measurements Analog DC and low frequency current measurements ….

Dynamic Current Measurement Instruments (IDDT) Dynamic and transient (IDDT) current tests Power profiling of circuits and systems Active current consumption E-fuse programming validation …


Why Ridgetop?

World Class Engineering Staff

(All project contributors PhD or advanced degree)

World Leaders in Electronic Prognostics(Awarded most gov’t

contracts)

Domain Expertise(Expansive portfolio

of electronic prognostic solutions)

IP Easily Configured to Target Applications (Seamless integration

and porting)

Customer Service(Dedicated service and support personnel for

on demand assistance)

Commitment to Innovation(Strive to

improve/upgrade existing IP)


For more information about Ridgetop’s products and capabilities please visit:

www.RidgetopGroup.com

interconnect intermittency detection with sj bist™

Documents

west ina road tucson

sj bist slide

type of interconnection

oxidecovered area slide

fractures intermittency

ball fractures

periods of high stress

ns intermittent faults