interconnect intro fpga

7/25/2019 Interconnect Intro FPGA

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CSET 4650CSET 4650Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan Solarek

Overview of FPGAOverview of FPGAInterconnectInterconnect


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Programmable InterconnectProgrammable Interconnect

In addition to programmable logic cells, FPGAs must haveIn addition to programmable logic cells, FPGAs must have

programmable interconnectprogrammable interconnect

Structure and complexity of the interconnect is determined byStructure and complexity of the interconnect is determined by

the programming technology and architecture of the logic cellthe programming technology and architecture of the logic cell

Interconnect is typically aluminum-based metal layersInterconnect is typically aluminum-based metal layers

esistance of approximately !" mesistance of approximately !" m#s$uare#s$uare

%ine capacitance of approximately "&2 pF#cm%ine capacitance of approximately "&2 pF#cm

'arly FPGAs had t(o metal interconnect layers, but current,'arly FPGAs had t(o metal interconnect layers, but current,high density parts may have three or more metal layershigh density parts may have three or more metal layers


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Field-Programmable ate !rra"sField-Programmable ate !rra"s

e$uires some form of programmable interconnecte$uires some form of programmable interconnect

at crossovers *at crossovers *

CLB CLB CLB CLBCLB CLB CLB







over sim#li$ied


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Tradeo$$s in FP! InterconnectTradeo$$s in FP! Interconnect

o( are logic blocs arranged.o( are logic blocs arranged.

o( /rich0 is interconnect bet(een channels.o( /rich0 is interconnect bet(een channels.

o( many (ires (ill be needed bet(een them.o( many (ires (ill be needed bet(een them.

Are (ires evenly distributed across chip.Are (ires evenly distributed across chip.

o( should (ires be segmented 1short, long.o( should (ires be segmented 1short, long.

o( long is the average (ire.o( long is the average (ire.

o( much buffering do (e add to (ires.o( much buffering do (e add to (ires.


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Tradeo$$s in FP! InterconnectTradeo$$s in FP! Interconnect

Programmability slo(s signals do(n *Programmability slo(s signals do(n *

are some (ires speciali3ed to long distances.are some (ires speciali3ed to long distances.

o( many inputs#outputs must be routed to#fromo( many inputs#outputs must be routed to#from

each configurable logic bloc.each configurable logic bloc.

4hat utili3ation are (e (illing to accept.4hat utili3ation are (e (illing to accept.

2"5. !"5. 6"5.2"5. !"5. 6"5.


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Interconnect Comes %it& a CostInterconnect Comes %it& a Cost


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'o(ting) C&oosing a Pat&'o(ting) C&oosing a Pat&

LE

LE

*iring c&annel

*ire

s*itc&

'o(ting is done b" a so$t*are tool+'o(ting is done b" a so$t*are tool+

LEs &old #revio(sl"

#laced $(nctions


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'o(ting Considerations'o(ting Considerations

Global routing:Global routing:

4hich combination of channels.4hich combination of channels.

%ocal routing:%ocal routing:

4hich (ire in each channel.4hich (ire in each channel.

outing metrics:outing metrics:

;et length;et length


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Programmable vs+ Fi,ed InterconnectProgrammable vs+ Fi,ed Interconnect

S(itch adds delayS(itch adds delay

=ransistor off-state is (orse in advanced=ransistor off-state is (orse in advanced

technologiestechnologies

FPGA interconnect has extra length > addedFPGA interconnect has extra length > added

capacitancecapacitance


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Interconnect StrategiesInterconnect Strategies

Some (ires (ill not be utili3edSome (ires (ill not be utili3ed

@ongestion (ill not be same throughout chip@ongestion (ill not be same throughout chip

=ypes of (ires:=ypes of (ires:

Short (ires: local %' connectionsShort (ires: local %' connections

Global (ires: long-distance, buffered communicationGlobal (ires: long-distance, buffered communication

Special (ires: clocs, etc&Special (ires: clocs, etc&


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Pat&s in InterconnectPat&s in Interconnect

@onnections may be long and complex@onnections may be long and complex

%ong (ires can help simplify%ong (ires can help simplify

%' %' %' %' %'

%' %' %' %' %'

%' %' %' %' %'

4iring channel

4iringchannel


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Interconnect arc&itect(reInterconnect arc&itect(re

@onnections from (iring channels to %'s&@onnections from (iring channels to %'s&

@onnections bet(een (ires in the (iring channels&@onnections bet(een (ires in the (iring channels&

%' %'

*iring c&annel

s*itc&es


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Interconnect 'ic&nessInterconnect 'ic&ness

4ithin a channel:4ithin a channel:

o( many (ireso( many (ires

%ength of segments%ength of segments

@onnections from@onnections from %'to interconnect channelto interconnect channelet(een channels:et(een channels:

;umber of connections bet(een channels;umber of connections bet(een channels

@hannel structure@hannel structure


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Segmented %iringSegmented %iring

%ength ?

%ength 2


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$$set Segments$$set Segments


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S*itc&bo,S*itc&bo,

channel channel

channel

channel

Bultiple s(itch pointsBultiple s(itch points

Increased flexibilityIncreased flexibility


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'o*s o$ #rogrammablelogic b(ilding blocks

.

ro*s o$ interconnect

!nti-$(se Tec&nolog")Program nce

/ in#(t single o(t#(t combinational logic blocks

FFs constr(cted $rom discrete cross co(#led gates

1se !nti-$(ses to b(ild(# long *iring r(ns $rom

s&ort segments

I/O Buffers, Programming and Test Logic

Logic Module Wiring Tracs

I/O Buffers, Programming and Test Logic

I/OBuffers,Programming

andTestLogic

I/OBuffers,ProgrammingandTestLogic

!ctel FP!s!ctel FP!s


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!ctel Programmable Interconnect!ctel Programmable Interconnect

Actel interconnect is similar to a channeled gate arrayActel interconnect is similar to a channeled gate array

ori3ontal routing channels bet(een ro(s of logic modulesori3ontal routing channels bet(een ro(s of logic modules

Certical routing channels on top of cellsCertical routing channels on top of cells

'ach channel has a fixed number of tracs each of (hich'ach channel has a fixed number of tracs each of (hich

holds one (ireholds one (ire

4ires are divided into segments of various lengths4ires are divided into segments of various lengths

segmented channel routingsegmented channel routing

%ong vertical tracs 1%C= extend the entire height of the%ong vertical tracs 1%C= extend the entire height of thechipchip


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'ach logic module has connections to its inputs and'ach logic module has connections to its inputs and

outputs called stubsoutputs called stubs

Input stubs extend vertically into routing channels above andInput stubs extend vertically into routing channels above and

belo( logic modulebelo( logic module

Dutput stub extends vertically 2 channels up and 2 channels do(nDutput stub extends vertically 2 channels up and 2 channels do(n

4ires are connected by antifuses4ires are connected by antifuses


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2"

Interconnection Fabric

Logic Module

!ori"ontal

Trac

#ertical

Trac

Anti$fuse

!ctel Interconnect!ctel Interconnect


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2ogs cross an anti-$(se

minimi3e t&e n(mber o$ 2ogs $or s#eed critical circ(its

- 2ogs $or most interconnections

Logic Module

Logic Module

Logic ModuleOut%ut

In%ut

In%ut

!ctel 'o(ting E,am#le!ctel 'o(ting E,am#le


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Betal to metal antifuse moved the antifuse out ofBetal to metal antifuse moved the antifuse out of

silicon maing the part denser and fastersilicon maing the part denser and faster

etal to etal !nti$(seetal to etal !nti$(se


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etal to etal !nti$(seetal to etal !nti$(se

TWO DIMENSIONAL

SEA OF MODULES

MODULES

TRACKS


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Detail o$ !CT7 C&annel !rc&itect(reDetail o$ !CT7 C&annel !rc&itect(re

!CT 7

&ori3ontal

and vertical

c&annel

arc&itect(re


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'o(ting 'eso(rces'o(ting 'eso(rces

A@= ? interconnection architectureA@= ? interconnection architecture

22 hori3ontal tracs per channel for signal routing (ith22 hori3ontal tracs per channel for signal routing (ith

) dedicated for C


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Elmore8s ConstantElmore8s Constant

Approximation of (aveform at nodeApproximation of (aveform at node ii::

(here (here -i-iis the resistance of the path to Cis the resistance of the path to C""shared by nodeshared by node kkand nodeand node ii

'xamples: 'xamples: 2+2+> > ??, , 2222> > ??22, and , and )?)?> > ??

If the s(itching points are assumed to be at the "&)! and "&7! points, theIf the s(itching points are assumed to be at the "&)! and "&7! points, the

delay at nodedelay at node iican be approximated bycan be approximated by


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Elmore8s ConstantElmore8s Constant


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'C Dela" in !nti$(se Connections'C Dela" in !nti$(se Connections

!ctel ro(ting model+ 9a: ! $o(r-anti$(se connection+ L0 is an o(t#(t st(b L7 and L are &ori3ontal

tracks L is a long vertical track 9L


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'C Dela" in !nti$(se Connections'C Dela" in !nti$(se Connections

nn- resistance of antifuse, @- resistance of antifuse, @nn- capacitance of (ire segment- capacitance of (ire segment

?+?+@@?? 2+2+@@22 )+)+@@)) ++++@@++ > 1> 1?? 22 )) ++@@++ 1 1?? 22 ))@@)) 1 1?? 22@@22 ??@@??

If all antifuse resistances are approximately e$ual and much larger thanIf all antifuse resistances are approximately e$ual and much larger than

the resistance of the (ire segment, then: ? > 2 > ) > +, and:the resistance of the (ire segment, then: ? > 2 > ) > +, and:

+@++ )@ )@)) 2@ 2@22 @ @??

A connection (ith t(o antifuses (ill generate a )@ time constant, aA connection (ith t(o antifuses (ill generate a )@ time constant, aconnection (ith three antifuses (ill generate a 7@ time constant, and aconnection (ith three antifuses (ill generate a 7@ time constant, and aconnection (ith + antifuses (ill generate a ?"@ time constantconnection (ith + antifuses (ill generate a ?"@ time constant

Interconnect delay gro(s $uadratically 1Interconnect delay gro(s $uadratically 1nn22 as the number of antifuses as the number of antifuses

nnincreasesincreases


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!ctel 'o(ting 'eso(rces!ctel 'o(ting 'eso(rces


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=ilin, LC! Interconnect=ilin, LC! Interconnect

ilinx %@A interconnect has a hierarchical architecture:ilinx %@A interconnect has a hierarchical architecture:

Vertical linesVertical linesandand horizontal lineshorizontal linesrun bet(een @%srun bet(een @%s

General-purpose interconnectGeneral-purpose interconnectJoinsJoinsswitch boxesswitch boxes1also no(n as1also no(n as magicmagic

boxesboxesororswitching matricesswitching matrices

Long linesLong linesrun across the entire chip - can be used to form internalrun across the entire chip - can be used to form internalbuses using the three-state buffers that are next to each @%buses using the three-state buffers that are next to each @%

Direct connectionsDirect connectionsbypass the s(itch matrices and directly connectbypass the s(itch matrices and directly connect

adJacent @%sadJacent @%s

Programmable Interconnect PointsProgrammable Interconnect Points1PIPs are programmable pass1PIPs are programmable pass

transistors the connect @% inputs and outputs to the routing net(ortransistors the connect @% inputs and outputs to the routing net(ori-directional interconnect bu!!ersi-directional interconnect bu!!ers 1I


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=ilin, FP! Internals=ilin, FP! Internals

Portion of a ilinxPortion of a ilinx

+""" FPGA+""" FPGA

Sho(s relativeSho(s relative

si3es of maJorsi3es of maJorelementselements

;eed more detail;eed more detail

about interconnectabout interconnect

architecturearchitecture


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=ilin, 4000 Interconnect=ilin, 4000 Interconnect

A closer looA closer loo

ProgrammableProgrammable

s(itch matricess(itch matrices

Single lengthSingle lengthlines bet(eenlines bet(een

adJacent PSBsadJacent PSBs


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S*itc& Detail and ScaleS*itc& Detail and Scale

@%s in a sea@%s in a seaof interconnectof interconnect

ProgrammableProgrammableS(itch BatrixS(itch Batrix1PSB1PSB

@onnections@onnectionsare controlledare controlled

by SAB bitsby SAB bits

%ong lines%ong lines

Global linesGlobal lines


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Programmable S*itc& atri,Programmable S*itc& atri,


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Pass Transistor ControlPass Transistor Control


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programmable switch element

turning the corner, etc.


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=ilin, LC! Interconnect 9cont+:=ilin, LC! Interconnect 9cont+:

=ilin, LC!

interconnect+

9a: T&e LC!

arc&itect(re

9notice t&e

matri, element

si3e is

larger t&an aCL>:+ 9b: !

sim#li$ied

re#resentation

o$ t&e

interconnect

reso(rces+

Eac& o$ t&elines is a b(s+


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=ilin, S*itc&ing atri, and=ilin, S*itc&ing atri, and

Com#onents o$ Interconnect Dela"Com#onents o$ Interconnect Dela"Com#onents o$ interconnectdela" in a =ilin, LC! arra"+ 9a: !#ortion o$ t&e interconnect

aro(nd t&e CL>s+ 9b: ! s*itc&ing

matri,+ 9c: ! detailed vie* inside

t&e s*itc&ing matri, s&o*ing t&e

#ass-transistor arrangement+ 9d:T&e e?(ivalent circ(it $or t&e

connection bet*een nets 6 and

0 (sing t&e matri,+ 9e: ! vie* o$

t&e interconnect at a

Programmable Interconnection

Point 9PIP+ 9$: and 9g: T&ee?(ivalent sc&ematic o$ a PIP

connection 9&: T&e com#lete 'C

dela" #at&+


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'o(ting Connections'o(ting Connections

A connection is reali3ed in an FPGA interconnect fabric by

enabling routing s(itches in the connection and s(itch boxes&


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=he parasitic contribution from the s(itches 1reali3ed as passtransistors and the metal trace constitute the total resistive and

capacitive components of the interconnect&


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ased on the s(itch and (ire parasitic, interconnect routes can bemodeled asRCnet(ors&

For typical parasitic values,Rwireis so negligible (hen compared to

Ron, and thus can be dropped&


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=he capacitance of a route segment is given by:

Cseg" ?"Cdi!! Cwire

=his can be used to model the energy of the route as

#nerg$1# !"Cdi!! +Cwire

=he delay of the route can be compute as follo(s:

Dela$1D ?"RonCwire ?2!RonCdi!!

=his modeling of the interconnect can be used to compute the cost

of the architectural modifications&


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=ilin, EPLD Interconnect=ilin, EPLD Interconnect

T&e =ilin, EPLD 1I 91niversal Interconnection od(le:+ 9a: ! sim#li$ied block diagram o$ t&e 1I+

T&e 1I b(s *idt& n varies $rom 6/ 9=C@6: to 7A/ 9=C@70/:+ 9b: T&e 1I is act(all" a large

#rogrammable !BD arra"+ 9c: T&e #arasitic ca#acitance o$ t&e EP' cell+

ilinx 'P%< family uses an interconnect bus called a Kniversalilinx 'P%< family uses an interconnect bus called a KniversalInterconnection Bodule 1KIBInterconnection Bodule 1KIB

KIB is a programmable A;< array (ith constant delay from any input toKIB is a programmable A;< array (ith constant delay from any input toany outputany output

@@GGis the fixed gateis the fixed gate

capacitance of thecapacitance of the

'PDB device'PDB device @@


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!ltera != 5 @ Interconnect!ltera != 5 @ Interconnect

! sim#li$ied block diagram o$ t&e !ltera != interconnect sc&eme+ 9a: T&e PI! 9Programmable

Interconnect !rra": is deterministic - dela" is inde#endent o$ t&e #at& lengt&+ 9b: Eac& L!> 9Logic

!rra" >lock: contains a #rogrammable !BD arra"+ 9c: Interconnect timing *it&in a L!> is also $i,ed+

Altera BA !""" and 8""" devices use a ProgrammableAltera BA !""" and 8""" devices use a ProgrammableInterconnect Array 1PIAInterconnect Array 1PIAPIA is also a programmable A;< array (ith constant delay from anyPIA is also a programmable A;< array (ith constant delay from anyinput to any outputinput to any output


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!ltera != A Interconnect !rc&itect(re!ltera != A Interconnect !rc&itect(re

T&e !ltera != A000 interconnect sc&eme+ 9a: ! 4 = 5 arra" o$ Logic !rra" >locks 9L!>s:

t&e same si3e as t&e EPA400 c&i#+ 9b: ! sim#li$ied block diagram o$ t&e interconnect

arc&itect(re s&o*ing t&e connection o$ t&e FastTrack b(ses to a L!>+

Altera BA 6""" devices use long ro( and column (ires 1Altera BA 6""" devices use long ro( and column (ires 1%ast&racks%ast&racksconnected by s(itchesconnected by s(itches


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!ltera Fle,!ltera Fle,

T&e !ltera FLE= interconnect sc&eme+ 9a: T&e ro* and col(mn FastTrack

interconnect+ 9b: ! sim#li$ied diagram o$ t&e interconnect arc&itect(re s&o*ing

t&e connections bet*een t&e FastTrack b(ses and a L!>+

Altera Flex devices also useAltera Flex devices also use%ast&racks%ast&racksconnected by s(itches, butconnected by s(itches, butthe (iring is more dense 1as are the logic modulesthe (iring is more dense 1as are the logic modules


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S(mmar"S(mmar"

Antifuse FPGA architectures are dense and regularAntifuse FPGA architectures are dense and regular

SAB architectures contain nested structures ofSAB architectures contain nested structures of

interconnect resourcesinterconnect resources

@omplex P%< architectures use long interconnect@omplex P%< architectures use long interconnectlines but achieve deterministic routinglines but achieve deterministic routing

interconnect intro fpga

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